EQ50F100 [TI]
1Gbps 至 6.25Gbps 背板均衡器;
| 型号： | EQ50F100 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1Gbps 至 6.25Gbps 背板均衡器 |
| 文件： | 总18页 (文件大小：5709K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EQ50F100
www.ti.com
SNOSAB8D –OCTOBER 2004–REVISED APRIL 2005
EQ50F100 1Gbps - 6.25 Gbps Backplane Equalizer
Check for Samples: EQ50F100
1
FEATURES
•
•
•
•
Equalize up to 20dB loss at 2.5 GHz
35 ps residual deterministic jitter at 5 Gbps
On-chip CML terminations
2
•
•
•
Recovers 6.25 Gbps signals after 30" of FR4
Single 1.8V power supply
Small 3 mm x 3 mm 6–pin leadless LLP
package
Low power consumption: 85mW
DESCRIPTION
The EQ50F100 is a equalizer designed to compensate transmission medium losses and reduce the medium-
induced deterministic jitter. It is optimized for operation from 1Gbps to 6.25Gbps, on printed circuit backplane for
up to 30" of FR4 striplines with backplane connectors at both ends. It is code independent, and functioning
equally well for short run length, balanced codes such as 8b/10b, commonly used in multiplexed 1.25 Gbps
Ethernet Systems.
The equalizer uses differential CML inputs and outputs with feed-through pin-outs, mounted in a 3 mm x 3 mm
6–pin leadless LLP package. It is powered from single 1.8V supply and consumes 85 mW.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2004–2005, Texas Instruments Incorporated
EQ50F100
SNOSAB8D –OCTOBER 2004–REVISED APRIL 2005
www.ti.com
Simplified Function Diagram
LVDS
Interface
CML
Interface
Channel 3, 4
Channel 1, 2
1.25/2.5/5 Gbps
EQ50F100
HT1
HT2
1.25 Gbps
T1[1-8]
T1_CLK
625 MHz
ASIC
Quad
SerDes
SCAN50C400
1.25 Gbps
625 MHz
OUT
IN
HR1
HR2
R1[1-8]
R1_CLK
Equalizer
EQ50F100
125 MHz
OUT
Equalizer
IN
SCLK
Clock
Distribution
Backplane
Sub-system
Switch Fabric Card
Line Card
Channel 3, 4
Channel 1, 2
1.25/2.5/5 Gbps
EQ50F100
HT1
HT2
1.25 Gbps
625 MHz
T1[1-8]
T1_CLK
ASIC
Quad
SerDes
SCAN50C400
1.25 Gbps
625 MHz
OUT
IN
HR1
HR2
R1[1-8]
R1_CLK
Equalizer
EQ50F100
125 MHz
OUT
Equalizer
IN
SCLK
Clock
Distribution
Note: Information contained in this datasheet is subject to change due to changes in design, specification and/or
process, before EQ50F100 is production released.
2
Submit Documentation Feedback
Copyright © 2004–2005, Texas Instruments Incorporated
Product Folder Links: EQ50F100
EQ50F100
www.ti.com
SNOSAB8D –OCTOBER 2004–REVISED APRIL 2005
Simplified Block Diagram
Offset
Cancellation
V
DD
50
50
IN+
IN-
OUT+
OUT-
Equalizer
Filter
Limiter
100
Pin Functions
Pin Descriptions
Pin Name
Pin Number
I/O, Type
Description
HIGH SPEED DIFFERENTIAL I/O
IN−
IN+
1
6
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN+ and IN−.
OUT−
OUT+
3
4
O, CML
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT+ to VDD and OUT− to VDD.
POWER
VDD
5
2
I, Power
I, Power
I, Power
VDD = 1.8V ± 5%. VDD pins should be tied to VDD plane through low inductance path. A 0.01
µF bypass capacitor should be connected between the VDD pin and the GND planes.
GND
Ground reference. GND should be tied to a solid ground plane through a low impedance
path.
Exposed Pad
PAD
Connect to GND. The exposed pad at the center of the package should be connected to
ground plane of the board to enhance thermal and electrical performance of the package.
Copyright © 2004–2005, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: EQ50F100
EQ50F100
SNOSAB8D –OCTOBER 2004–REVISED APRIL 2005
www.ti.com
Pin Diagram
OUT-
3
GND
2
IN-
1
EQ50F100
GND
4
5
6
OUT+
IN+
V
DD
Figure 1. Top View Shown
3 mm x 3 mm 6-Pin LLP Package
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
Absolute Maximum Ratings
Supply Voltage (VDD
)
−0.3V to +2.5V
-0.3V to (VDD + 0.3V)
+150°C
CML Input/Output Voltage
Junction Temperature
Storage Temperature
Lead Temp. (Soldering, 5 sec.)
ESD Rating
−65°C to +150°C
+260°C
HBM, 1.5 kΩ, 100 pF
EIAJ, 0Ω, 200 pF
>7 kV
>200V
Thermal Resistance
θJA, No Airflow
54°C/W
(1) “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply
that the device should be operated at these limits.
Recommended Operating Conditions
Min
Typ
Max
Units
Supply Voltage
(VDD to GND)
1.71
1.8
1.89
V
Ambient Temperature
−40
25
85
°C
4
Submit Documentation Feedback
Copyright © 2004–2005, Texas Instruments Incorporated
Product Folder Links: EQ50F100
EQ50F100
www.ti.com
SNOSAB8D –OCTOBER 2004–REVISED APRIL 2005
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified.
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(1)
POWER
P
N
Power Supply Consumption
85
106
mW
(2)
Supply Noise Tolerance
10 Hz–100 Hz
100 Hz–10 MHz
10 MHz–2.5 GHz
100
50
10
mVP-P
mVP-P
mVP-P
CML RECEIVER INPUTS (IN+, IN−)
VIN
RLI
RIN
Input Voltage Swing
Differential Input Return Loss
Input Resistance
Differential signal to equalizer,
measured before test channel
400
1600
mVP-P
100 MHz–2.5 GHz, with fixture's
effect de-embedded
15
dB
Differential across IN+ and IN−
85
100
115
800
Ω
CML OUTPUTS (OUT+, OUT−)
VO
Output Voltage Swing
Measured differentially with OUT+
and OUT− terminated by 50Ω to
GND through DC block(3) (4)
450
mVP-P
tR, tF
Transition Time
20% to 80% of differential output
voltage, measured with 1" from
output pins.
30
42
45
50
14
60
58
ps
Ω
(3) (4)
RO
Output Resistance
Single-ended to VDD
RLO
Differential Output Return Loss
100 MHz–2.5 GHz, with fixture's
effect de-embedded. IN+ = static
high.
dB
EQUALIZATION
(5) (6)
DJ1
Residual Deterministic Jitter at 6.25 Multiplexed K28.5 pattern,
Gb/s
,
0.25
0.13
0.09
0.4
0.35
0.2
UIP-P
UIP-P
UIP-P
(4)
30" Test channel, VIN = 1VP-P.
(7) (6)
DJ2
DJ3
Residual Deterministic Jitter at 5
Gb/s
Multiplexed K28.5 pattern,
,
(4)
30" Test channel. VIN = 1VP-P
.
(8) (6)
Residual Deterministic Jitter at 2.5 Multiplexed K28.5 pattern,
Gb/s
,
(4)
30" Test channel, VIN = 1VP-P.
(1) Typical parameters are measured at VDD = 1.8V, TA = 25°C. They are for reference purposes, and are not production-tested.
(2) Allowed supply noise (mVP-P sine wave) during jitter tests.
(3) Test pattern is clock-like 11111 00000 pattern.
(4) VO, tR, tF, tD, DJ1, DJ2, DJ3, DJ4 and RJ specifications are Guaranteed by Design using statistical analysis.
(5) Test pattern at 6.25 Gbps is a combination of K28.5± characters running at full bit rate and at half bit rate. It is intended to simulate the
multiplexing of two 3.125 Gb/s channels of a XAUI data stream.
Pattern in hex
0F FCCF 0033(quarter rate of K28.5+, half rate of K28.5−)
3 EB05(full rate K28.5±: 00 1111 1010 11 0000 0101)
(6) Deterministic jitter is measured at the differential outputs, minus the deterministic jitter before the test channel. Random jitter is removed
through the use of averaging or similar means.
(7) Test pattern at 5 Gbps is a combination of K28.5± characters running at full bit rate and at quarter bit rate. It is intended to simulate the
multiplexing of four 1.25 Gb/s Ethernet data streams.
Pattern in hex
00 FFFF F0F0 FF 0000 0F0F(quarter rate of K28.5+, quarter rate of K28.5−)
3 EB05(full rate K28.5±: 00 1111 1010 11 0000 0101)
(8) Test pattern at 2.5 Gbps is a combination of K28.5± characters running at full bit rate and at half bit rate. It is intended to simulate the
multiplexing of two 1.25 Gb/s Ethernet data streams.
Pattern in hex
0F FCCF 0033(half rate of K28.5+, half rate of K28.5−)
3 EB05(full rate K28.5±: 00 1111 1010 11 0000 0101)
Copyright © 2004–2005, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: EQ50F100
EQ50F100
SNOSAB8D –OCTOBER 2004–REVISED APRIL 2005
www.ti.com
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Typ
Symbol
DJ4
Parameter
Conditions
Min
Max
Units
(1)
(9) (6)
Residual Deterministic Jitter at 1.25 Multiplexed K28.5 pattern,
,
0.04
0.75
0.15
1.0
UIP-P
(4)
Gb/s
30" Test channel, VIN = 1VP-P.
(3) (10) (4)
RJ
Random Jitter
psrms
LATENCY
tD
Latency
Measured from input to output,
measured with multiplexed K28.5
pattern at 5Gb/s.
150
230
300
ps
(7) (4)
BIT RATE
BRMIN
Minimum Bit Rate
Maximum Bit Rate
1
Gbps
Gbps
BRMAX
6.25
(9) Test pattern at 1.25 Gbps is K28.5± characters running at full bit rate
Pattern in hex
3 EB05(full rate K28.5±: 00 1111 1010 11 0000 0101)
(10) Random jitter contributed by the equalizer is defined as sq rt (JOUT2 − JIN2). JOUT is the random jitter at equalizer outputs in ps-rms, JIN
in the random jitter at the input of the equalizer in ps-rms.
Test Setup Diagram
TEST CHANNEL USED IN PRODUCTION TEST, TYPICAL EYE DIAGRAMS
The test channel used in production test and typical eye diagram is a FR4 stripline test channel that can be
practically implemented in production load board environment, and yet with loss characteristics similar to a
backplane that intended to test the device's equalization span.
30 in
+
+
-
+
-
Digital Sampling
Scope
EQ50F100
Signal Source
-
Functional Description
The EQ50F100 6.25Gbps Backplane Equalizer is a fixed, receive-end backplane equalizer. It enables serial
transmission over FR-4 backplane with trace length of at least 30" at 6.25Gbps. It consists of an equalizer filter,
limiting amplifier, offset driver, and offset cancellation circuit. The equalizer block compensates for the high
frequency attenuation caused by the bandwidth-limited transmission channel found in backplane system. The
limiting amplifier boost the signal at the output of the equalizer block. The offset cancellation circuit corrects for
internal mis-match and offset from the previous stage to minimize duty-cycle distortion.
Input and Output
The input and output stage of the EQ50F100 is implemented using current mode logic (CML). The input stage
has an equivalent DC differential input resistance of 100Ω. The positive and negative output channels are
internally terminated with a 50Ω pull-up to VDD. AC coupling is recommended for both input and output.
6
Submit Documentation Feedback
Copyright © 2004–2005, Texas Instruments Incorporated
Product Folder Links: EQ50F100
EQ50F100
www.ti.com
SNOSAB8D –OCTOBER 2004–REVISED APRIL 2005
Application Information
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power / ground
sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance
parasitic. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF
capacitors may use values in the range of 0.1nF to 10nF. Tantalum capacitors may be in the 2.2uF to 10uF
range. Voltage rating of the tantalum capacitors should be at least 5X the power supply voltage being used.
It is a recommended practice to use two vias at each power pin as well as at all RF bypass capacitor terminals.
Dual vias reduce the interconnect inductance by up to half, thereby reducing interconnect inductance and
extending the effective frequency range of the bypass components. Locate RF capacitors as close as possible to
the supply pins, and use wide low impedance traces (not 50 Ohm traces). Surface mount capacitors are
recommended due to their smaller parasitics. It is recommended to connect power and ground pins directly to the
power and ground planes with bypass capacitors connected to the plane with via on both ends of the capacitor.
Connecting power or ground pins to an external bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603 or 0402, is recommended for external bypass. Its small body
size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz range. To provide effective bypassing,
multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of
interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
See AN-1187 for additional information on LLP package.
AC COUPLING
For multi-giga bit design, the smallest available package should be used for the AC coupling capacitor. This will
help minimize degradation of signal quality due to package parasitics. The most common used capacitor value
for the EQ50F100 interface is 0.1uF capacitor.
Copyright © 2004–2005, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: EQ50F100
EQ50F100
SNOSAB8D –OCTOBER 2004–REVISED APRIL 2005
www.ti.com
Typical Performance Characteristics
TYPICAL EYE DIAGRAM WITH 30" BACKPLANE CHARACTERISTICS
All typical eye diagrams are measured with a FR4 stripline test channel at VDD = 1.8V, TA = 25°C with PRBS-10
pattern at 1Vp-p at the source. They were acquired by an oscilloscope with 2k sampling hits, which includes
(1)
approximately 10ps of system jitter.
Figure 2. 1.25 Gb/s, PRBS-10 Input Signal to Equalizer after 30" of FR4
Figure 3. Typical 1.25 Gb/s Equalizer Output Signal, with Input as shown in Figure 2
Figure 4. 2.5 Gb/s, PRBS-10 Input Signal to Equalizer after 30" of FR4
(1) Typical parameters are measured at VDD = 1.8V, TA = 25°C. They are for reference purposes, and are not production-tested.
8
Submit Documentation Feedback
Copyright © 2004–2005, Texas Instruments Incorporated
Product Folder Links: EQ50F100
EQ50F100
www.ti.com
SNOSAB8D –OCTOBER 2004–REVISED APRIL 2005
Typical Performance Characteristics (continued)
Figure 5. Typical 2.5Gb/s Equalizer Output Signal, with Input as shown in Figure 4
Figure 6. 5 Gb/s, PRBS-10 Input Signal to Equalizer after 30" of FR4
Figure 7. Typical 5Gb/s Equalizer Output Signal, with Input as shown in Figure 6
Copyright © 2004–2005, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: EQ50F100
EQ50F100
SNOSAB8D –OCTOBER 2004–REVISED APRIL 2005
www.ti.com
Typical Performance Characteristics (continued)
Figure 8. 6.25 Gb/s, PRBS-10 Input Signal to Equalizer after 30" of FR4
Figure 9. Typical 6.25Gb/s Equalizer Output Signal, with Input as shown in Figure 8
10
Submit Documentation Feedback
Copyright © 2004–2005, Texas Instruments Incorporated
Product Folder Links: EQ50F100
EQ50F100
www.ti.com
SNOSAB8D –OCTOBER 2004–REVISED APRIL 2005
Typical Performance Characteristics (continued)
TYPICAL OPERATING CHARACTERISTICS
Typical performance are measured at VDD = 1.8V, TA = 25°C, unless otherwise noted. They are measured with a
FR4 stripline test channel and acquired by an oscilloscope with 2k sampling hits, which includes approximately
10ps of system jitter.
55
50
45
1.25 Gbps
2.5 Gbps
3.125 Gbps
5 Gbps
6.25 Gbps
40
35
30
25
20
15
5 Gbps
6.25 Gbps
2.5 Gbps
3.125 Gbps
30
BOARD LENGTH (in)
1.25 Gbps
10
15
20
25
35
40
Figure 10. Total Jitter vs Board Length (FR4)
(Input Level = 1VP-P, K28.5 Pattern)
55
50
1.25 Gbps
45
1.25 Gbps
2.5 Gbps
3.125 Gbps
5 Gbps
2.5 Gbps
40
35
30
25
20
15
6.25 Gbps
6.25 Gbps
5 Gbps
3.125 Gbps
400 600 800 1000 1200 1400 1600 1800
DIFFERENTIAL SIGNAL LEVEL (mVp-p)
Figure 11. Total Jitter vs Signal Level
(K28.5 Pattern, 30in FR4 Board)
55
50
45
K28.5
40
35
30
25
20
15
PRBS-7
PRBS-10
PRBS-15
PRBS-15
PRBS-10
K28.5
PRBS-7
1.25 2.25 3.25 4.25 5.25 6.25 7.25
DATA RATE (Gbps)
Figure 12. Total Jitter vs Data Rate
For 10in of FR4 Board
(Input Level = 1VP-P
)
Copyright © 2004–2005, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: EQ50F100
EQ50F100
SNOSAB8D –OCTOBER 2004–REVISED APRIL 2005
www.ti.com
Typical Performance Characteristics (continued)
55
50
45
40
35
30
25
20
15
PRBS-10
K28.5
PRBS-7
PRBS-10
PRBS-15
PRBS-15
PRBS-7
K28.5
1.25 2.25 3.25 4.25 5.25 6.25 7.25
DATA RATE (Gbps)
Figure 13. Total Jitter vs Data Rate
For 20in of FR4 Board
(Input Level = 1VP-P
)
55
50
45
40
35
30
25
20
15
PRBS-15
PRBS-10
K28.5
PRBS-7
PRBS-10
PRBS-15
PRBS-7
K28.5
1.25 2.25 3.25 4.25 5.25 6.25 7.25
DATA RATE (Gbps)
Figure 14. Total Jitter vs Data Rate
For 30in of FR4 Board
(Input Level = 1VP-P
)
75
65
55
45
35
25
15
PRBS-15
PRBS-10
K28.5
PRBS-7
PRBS-10
PRBS-15
PRBS-7
K28.5
1.25 2.25 3.25 4.25 5.25 6.25 7.25
DATA RATE (Gbps)
Figure 15. Total Jitter vs Data Rate
For 40in of FR4 Board
(Input Level = 1VP-P
)
12
Submit Documentation Feedback
Copyright © 2004–2005, Texas Instruments Incorporated
Product Folder Links: EQ50F100
EQ50F100
www.ti.com
SNOSAB8D –OCTOBER 2004–REVISED APRIL 2005
Typical Performance Characteristics (continued)
55
50
45
40
35
30
25
20
15
1.25 Gbps
2.5 Gbps
3.125 Gbps
5 Gbps
2.5 Gbps
6.25 Gbps
6.25 Gbps
3.125 Gbps
1.25 Gbps
5 Gbps
1.71 1.73 1.75 1.77 1.79 1.81 1.83 1.85 1.87 1.89
(V)
V
CC
Figure 16. Total Jitter vs Vcc
(Input Level = 1VP-P, K28.5 Pattern)
Copyright © 2004–2005, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: EQ50F100
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
EQ50F100LR/NOPB
ACTIVE
WSON
NGG
6
1000 RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
EQ50F
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
EQ50F100LR/NOPB
WSON
NGG
6
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WSON NGG
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
EQ50F100LR/NOPB
6
1000
Pack Materials-Page 2
MECHANICAL DATA
NGG0006A
SDE06A (Rev A)
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明