DSD1608 [TI]
SNR 为 108dB 的 8 通道音频 DAC;
| 型号： | DSD1608 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SNR 为 108dB 的 8 通道音频 DAC |
| 文件： | 总42页 (文件大小：461K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLES040 − JUNE 2002
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−
Digital Filter Rolloff: Sharp or Slow Soft
Mute
FEATURES
D
D
D
Supports DSD and PCM Formats
Supports TDMCA
−
Three Zero Flags
D
D
Dual Supply Operation:
5-V Analog, 3.3-V Digital
Package: 52-Pin TQFP
Accepts 16-, 18-, 20- and 24-Bit Audio Data for
PCM Format
−
D
Analog Performance (V
= 5 V):
CC
−
−
−
−
Dynamic Range: 108 dB, Typical
APPLICATIONS
SNR: 108 dB, Typical
D
D
D
D
Universal A/V Players
THD+N: 0.0012%, Typical
SACD Players
Full-Scale Output: 4 V , Typical
pp
Car Audio Systems
D
Includes 8× Oversampling Digital Filter for
PCM Format:
Other Applications Requiring 24-Bit Audio
−
−
Stopband Attenuation: –60 dB
Passband Ripple: 0.02 dB
DESCRIPTION
The DSD1608 is a CMOS, monolithic, 8-channel
digital-to-analog converter which supports both PCM
audio data format and direct stream digital (DSD) audio
data format. The device includes an 8× digital
interpolation filter and a digital DSD filter with three
selectable frequency-response curves, followed by
Texas Instruments’ enhanced multilevel delta-sigma
modulator, which employs 4th-order noise shaping and
8-level amplitude quantization to achieve excellent
dynamic performance and improved tolerance to clock
jitter. Sampling rates up to 192 kHz for the PCM mode
and 64 × 44.1 kHz for the DSD mode are supported. A
full set of user-programmable functions is accessible
through a 4-wire serial control port, which supports
register write and read functions. The DSD1608
supports the time-division-multiplexed command and
audio data (TDMCA) format. The DSD1608 is available
in a 52-pin TQFP package.
D
D
Includes Digital DSD FILTER for DSD Format:
Passband: 50 kHz, 70 kHz, 60 kHz at –3 dB
Sampling Frequency:
−
−
−
PCM Mode: 10 kHz to 200 kHz
DSD Mode: 64 × 44.1 kHz
D
D
System Clock:
128 f , 192 f , 256 f , 384 f , 512 f , 768 f
S
−
S
S
S
S
S
Data Formats:
2
−
Standard, I S, and Left-Justified for PCM
Direct Stream Digital
D
User-Programmable Mode Controls:
−
−
Digital Attenuation
Digital De-Emphasis
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢗꢔ ꢓ ꢀꢏ ꢇ ꢐꢑ ꢓꢊ ꢀ ꢉꢐꢉ ꢘꢙ ꢚꢛ ꢜ ꢝꢞ ꢟꢘꢛꢙ ꢘꢠ ꢡꢢ ꢜ ꢜ ꢣꢙꢟ ꢞꢠ ꢛꢚ ꢤꢢꢥ ꢦꢘꢡ ꢞꢟꢘ ꢛꢙ ꢧꢞ ꢟꢣꢨ ꢗꢜ ꢛꢧꢢ ꢡꢟꢠ
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ꢗꢜ ꢛ ꢧꢢꢡ ꢟ ꢘꢛ ꢙ ꢤꢜ ꢛ ꢡ ꢣ ꢠ ꢠ ꢘꢙ ꢭ ꢧꢛ ꢣ ꢠ ꢙꢛꢟ ꢙꢣ ꢡꢣ ꢠꢠ ꢞꢜ ꢘꢦ ꢬ ꢘꢙꢡ ꢦꢢꢧ ꢣ ꢟꢣ ꢠꢟꢘ ꢙꢭ ꢛꢚ ꢞꢦ ꢦ ꢤꢞ ꢜ ꢞꢝ ꢣꢟꢣ ꢜ ꢠꢨ
Copyright 2002, Texas Instruments Incorporated
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SLES040 − JUNE 2002
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
OPERATION
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
PRODUCT
PACKAGE
DSD1608PAH
Tube
DSD1608PAH
52-lead TQFP
PAH
−25°C to 85°C
DSD1608
DSD1608PAHR
Tape and reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
DSD1608
V
CC
V
DD
1–V
1, V
7
CC
2
DD
6.5 V
4 V
Supply voltage
Supply voltage differences: V 1–V 7, V 1, V
2
0.1 V
CC CC DD DD
Ground voltage differences: AGND1–6, DGND1, DGND2
0.1 V
Digital input voltage: PLRCK, PBCK, PDATA1–PDATA4, DSD1–DSD8, DBCK, DSCK, PSCK, RST
Digital input voltage: MC, MS, MDI, ZERO1, ZERO2, ZERO38, MDO
Analog input voltage
–0.3 V to 6.5 V
–0.3 V to (V
+ 0.3 V)
DD
–0.3 V to (V
+ 0.3 V)
CC
Input current (any pins except supplies)
Operating temperature
10 mA
–40°C to 85°C
–55°C to 150°C
150°C
Storage temperature
Junction temperature
Lead temperature (soldering)
260°C, 5 s
Package temperature (IR reflow, peak)
235°C, 10 s
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
at T = 25°C, V
= 3.3 V, V = 5 V; in PCM mode, f = 44.1 kHz, system clock = 256 f , 24-bit data; in DSD mode, f = 2.8224 MHz
A
DD
CC S S S
(= 64 × 44.1 kHz), system clock = 256 × 44.1 kHz, 1-bit data (unless otherwise noted)
PARAMETER TEST CONDITIONS
Resolution
MIN
TYP
24
MAX
UNIT
Bits
DATA FORMAT (PCM MODE)
Audio data interface format
Audio data bit length
2
Standard, I S, left justified
16-, 18-, 20-, 24-bit selectable
MSB first, 2s complement
Audio data format
f
S
Sampling frequency
f
S
= 44.1 kHz
10
200
kHz
128 f , 192 f , 256 f , 384 f ,
S
S
S
S
System clock frequency
512 f , 768 f
S
S
DATA FORMAT (DSD MODE)
Audio data interface format
Direct stream digital (DSD)
1 bit
Audio data bit length
Sampling frequency
System clock frequency
f
S
f
S
f
S
= 44.1 kHz
= 44.1 kHz
64 f
S
Hz
256 f , 384 f , 512 f , 768 f
S
kHz
S
S
S
(1)
(2)
(3)
(4)
(5)
Pins 50, 51, 34, 33, 37, 38–45, 46–49: PBCK, PLRCK, DSCK, PSCK, DBCK, DSD1–DSD8, PDATA1–PDATA4.
Pins 2, 3, 4, 36: MDI, MS, MC, RST.
Pins 5–8: MDO, ZERO1, ZERO2, ZERO38.
Analog performance specs are measured in the averaging mode using the System Twot audio measurement system by Audio Precisiont.
These specs are measured under the condition that the OVR1, OVR0 in mode registers are set to (0,1). (The oversampling rate of the modulator
is 64 f .) If the OVR1, OVR0 are (0,0) (32 f oversampling: default), the specs are the same as at f = 96 kHz.
S
S
S
2
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SLES040 − JUNE 2002
ELECTRICAL CHARACTERISTICS(continued)
at T = 25°C, V
= 3.3 V, V = 5 V; in PCM mode, f = 44.1 kHz, system clock = 256 f , 24-bit data; in DSD mode, f = 2.8224 MHz
A
DD
CC S S S
(= 64 × 44.1 kHz), system clock = 256 × 44.1 kHz, 1-bit data (unless otherwise noted)
PARAMETER
DIGITAL INPUT/OUTPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Logic family
TTL-compatible
V
V
2
IH
IL
(1)
Input logic level
Vdc
µA
0.8
10
I
I
I
I
V
V
V
V
= V
DD
= 0 V
IH
IN
IN
(1)
–10
100
–10
IL
Input logic current
Output logic level
(2)
= V
65
IH
IN
DD
(2)
= 0 V
IL
IN
(3)
(3)
V
V
I
I
= –2 mA
= +2 mA
2.4
OH
OH
OL
Vdc
1
OL
(4)
DYNAMIC PERFORMANCE (PCM MODE)
f
f
f
f
f
f
= 44.1 kHz
= 96 kHz
0.0012%
0.0015%
0.002%
S
S
S
S
S
S
THD+N at V
= 0 dB
OUT
OUT
(5)
= 192 kHz
= 44.1 kHz
= 96 kHz
0.0012% 0.0018%
0.0015%
0.002%
108
THD+N at V
= –3 dB
(5)
= 192 kHz
EIAJ, A-weighted, f = 44.1 kHz
S
EIAJ, A-weighted, f = 96 kHz
(5)
EIAJ, A-weighted, f = 192 kHz
104
104
101
108
Dynamic range
dB
dB
S
107
S
EIAJ, A-weighted, f = 44.1 kHz
S
EIAJ, A-weighted, f = 96 kHz
(5)
EIAJ, A-weighted, f = 192 kHz
108
108
Signal-to-noise ratio
S
107
S
f
S
f
S
f
S
= 44.1 kHz
= 96 kHz
(5)
= 192 kHz
104
104
Channel separation
Level linearity error
dB
dB
103
V
= –90 dB
0.5
OUT
(4)
DYNAMIC PERFORMANCE DSD MODE (at f = 64 × 44.1 kHz)
S
THD+N at V
OUT
Dynamic range
= 0 dB
0.0012%
108
EIAJ, A-weighted
EIAJ, A-weighted
dB
dB
dB
dB
Signal-to-noise ratio
Channel separation
Level linearity error
108
104
V
OUT
= −90 dB
0.5
DC ACCURACY
Gain error
1
1
6
3
% FSR
% FSR
mV
Gain mismatch, channel-to-channel
Bipolar zero error
V
= 0.5 V
CC
at BPZ
30
60
OUT
ANALOG OUTPUT
Output voltage
Center voltage
Load impedance
Full scale (0 dB)
80% of V
V
pp
Vdc
CC
CC
50% of V
AC load
4
kΩ
(1)
(2)
(3)
(4)
(5)
Pins 50, 51, 34, 33, 37, 38–45, 46–49: PBCK, PLRCK, DSCK, PSCK, DBCK, DSD1–DSD8, PDATA1–PDATA4.
Pins 2, 3, 4, 36: MDI, MS, MC, RST.
Pins 5–8: MDO, ZERO1, ZERO2, ZERO38.
Analog performance specs are measured in the averaging mode using the System Twot audio measurement system by Audio Precisiont.
These specs are measured under the condition that the OVR1, OVR0 in mode registers are set to (0,1). (The oversampling rate of the modulator
is 64 f .) If the OVR1, OVR0 are (0,0) (32 f oversampling: default), the specs are the same as at f = 96 kHz.
S
S
S
3
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SLES040 − JUNE 2002
ELECTRICAL CHARACTERISTICS(continued)
at T = 25°C, V
= 3.3 V, V = 5 V; in PCM mode, f = 44.1 kHz, system clock = 256 f , 24-bit data; in DSD mode, f = 2.8224 MHz
A
DD
CC S S S
(= 64 × 44.1 kHz), system clock = 256 × 44.1 kHz, 1-bit data (unless otherwise noted)
PARAMETER
DIGITAL FILTER PERFORMANCE
8× INTERPOLATION FILTER (SHARP ROLL OFF FILTER)
Pass band
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.02 dB
–3 dB
0.454 f
0.487 f
Hz
Hz
Hz
dB
dB
s
S
S
Pass band
Stop band
0.546 f
S
Pass-band ripple
0.02
Stop-band attenuation
Delay Time
Stop band = 0.546 f
–60
S
23/f
S
8× INTERPOLATION FILTER (SLOW ROLL OFF FILTER)
Pass band
–0.5 dB
–3 dB
0.308 f
Hz
Hz
Hz
dB
dB
s
S
S
Pass band
0.432 f
Stop band
0.832 f
S
Pass-band ripple
0.308 f
0.832 f
0.5
S
S
Stop-band attenuation
Delay time
–58
23/f
S
DE-EMPHASIS FILTER (PCM MODE ONLY)
De-emphasis error
At f = 32 kHz, 44.1 kHz or 48 kHz
S
0.1
dB
DSD FILTER (FILTER-1)
Pass band
At –3 dB
50
kHz
dB
Stop-band attenuation
DSD FILTER (FILTER-2)
Pass band
At 100 kHz
–18
At –3 dB
70
kHz
dB
Stop-band attenuation
DSD FILTER (FILTER-3)
Pass band
At 100 kHz
–9.8
At –3 dB
60
kHz
dB
Stop-band attenuation
INTERNAL ANALOG FILTER PERFORMANCE
At 100 kHz
–17
At 20 kHz
At 44 kHz
At 50 kHz
At 100 kHz
–0.02
–0.1
Frequency response
dB
–0.12
–0.5
POWER SUPPLY REQUIREMENTS
V
V
3
3.3
5.0
28
3.6
5.5
40
DD
CC
Voltage range
Vdc
mA
4.5
f
f
= 44.1 kHz
= 192 kHz
S
74
I
S
DD
DSD mode
45
Supply current
Power dissipation
f
S
f
S
f
S
f
S
= 44.1 kHz
= 192 kHz
= 44.1 kHz
= 192 kHz
36
50
I
CC
38
270
430
380
mW
(1)
(2)
(3)
(4)
(5)
Pins 50, 51, 34, 33, 37, 38–45, 46–49: PBCK, PLRCK, DSCK, PSCK, DBCK, DSD1–DSD8, PDATA1–PDATA4.
Pins 2, 3, 4, 36: MDI, MS, MC, RST.
Pins 5–8: MDO, ZERO1, ZERO2, ZERO38.
Analog performance specs are measured in the averaging mode using the System Twot audio measurement system by Audio Precisiont.
These specs are measured under the condition that the OVR1, OVR0 in mode registers are set to (0,1). (The oversampling rate of the modulator
is 64 f .) If the OVR1, OVR0 are (0,0) (32 f oversampling: default), the specs are the same as at f = 96 kHz.
S
S
S
4
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SLES040 − JUNE 2002
ELECTRICAL CHARACTERISTICS(continued)
at T = 25°C, V
= 3.3 V, V = 5 V; in PCM mode, f = 44.1 kHz, system clock = 256 f , 24-bit data; in DSD mode, f = 2.8224 MHz
A
DD
CC S S S
(= 64 × 44.1 kHz), system clock = 256 × 44.1 kHz, 1-bit data (unless otherwise noted)
PARAMETER TEST CONDITIONS
TEMPERATURE RANGE
MIN
TYP
MAX
UNIT
Operating temperature
Thermal resistance
–25
85
°C
θ
JA
52 TQFP
70
°C/W
(1)
(2)
(3)
(4)
(5)
Pins 50, 51, 34, 33, 37, 38–45, 46–49: PBCK, PLRCK, DSCK, PSCK, DBCK, DSD1–DSD8, PDATA1–PDATA4.
Pins 2, 3, 4, 36: MDI, MS, MC, RST.
Pins 5–8: MDO, ZERO1, ZERO2, ZERO38.
Analog performance specs are measured in the averaging mode using the System Twot audio measurement system by Audio Precisiont.
These specs are measured under the condition that the OVR1, OVR0 in mode registers are set to (0,1). (The oversampling rate of the modulator
is 64 f .) If the OVR1, OVR0 are (0,0) (32 f oversampling: default), the specs are the same as at f = 96 kHz.
S
S
S
PIN ASSIGNMENTS
PAH PACKAGE
(TOP VIEW)
DSD3
DSD4
DSD5
DSD6
DSD7
DSD8
PDATA1
PDATA2
PDATA3
PDATA4
PBCK
V
V
V
2
40
41
42
43
44
45
46
47
48
49
50
51
52
26
25
24
23
22
21
20
19
18
17
16
15
14
COM
7
CC
6
CC
AGND5
V
5
CC
AGND4
DSD1608
V
4
CC
AGND3
V
3
CC
AGND2
V
V
V
2
1
CC
PLRCK
CC
1
COM
V
1
DD
Audio Precision and System Two are trademarks of Audio Precision, Inc.
Other trademarks are the property of their respective owners.
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SLES040 − JUNE 2002
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
13
AGND1
AGND2
AGND3
AGND4
—
—
—
—
—
—
I
Analog ground
17
Analog ground
19
Analog ground
21
Analog ground
AGND5
AGND6
DBCK
DGND1
DGND2
DSCK
DSD1
DSD2
DSD3
DSD4
DSD5
DSD6
DSD7
DSD8
MC
23
27
37
1
Analog ground
Analog ground
(3)
DSD audio data bit clock input (DSD)
Digital ground
—
—
I
32
34
38
39
40
41
42
43
44
45
4
Digital ground
(3)
System clock input (DSD). Input frequency is 256, 384, 512 or 768 f
S
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
I
DSD audio data input for V
DSD audio data input for V
DSD audio data input for V
DSD audio data input for V
DSD audio data input for V
DSD audio data input for V
DSD audio data input for V
DSD audio data input for V
1 (DSD)
2 (DSD)
3 (DSD)
4 (DSD)
5 (DSD)
6 (DSD)
7 (DSD)
8 (DSD)
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I
I
I
I
I
I
I
(1)
I
Mode control clock input
(1)
MDI
2
I
Mode control data input
Mode control read back data output
(1)
(4)
MDO
5
O
I
MS
3
Chip select for mode control
Audio data bit clock input (PCM)
(3)
PBCK
PDATA1
PDATA2
PDATA3
PDATA4
PLRCK
PSCK
RST
50
46
47
48
49
51
33
36
15
16
18
20
22
24
25
14
I
(3)
(3)
(3)
(3)
I
Serial audio data input for V
Serial audio data input for V
Serial audio data input for V
Serial audio data input for V
1 and V
3 and V
5 and V
7 and V
2 (PCM)
4 (PCM)
6 (PCM)
8 (PCM)
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I
I
I
(3)
I
Audio data L/R clock input (PCM)
System clock input (PCM). Input frequency is 128, 192, 256, 384, 512 or 768 f
(3)
I
S
(2)
I
System reset, active LOW
Analog power supply, 5 V
Analog power supply, 5 V
Analog power supply, 5 V
Analog power supply, 5 V
Analog power supply, 5 V
Analog power supply, 5 V
Analog power supply, 5 V
V
V
V
V
V
V
V
V
1
2
3
4
5
6
7
—
—
—
—
—
—
—
O
CC
CC
CC
CC
CC
CC
CC
1
Common voltage output 1. This pin should be bypassed with a 10-µF capacitor to AGND.
COM
(1)
(2)
(3)
(4)
Schmitt-trigger input with internal pulldown.
Schmitt-trigger input with internal pulldown, 5-V tolerant.
Schmitt-trigger input, 5-V tolerant.
3-state output.
6
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TERMINAL
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SLES040 − JUNE 2002
Terminal Functions (continued)
I/O
DESCRIPTION
NAME
NO.
V
V
V
V
V
V
V
V
V
V
V
2
26
52
35
12
11
10
9
O
—
—
O
O
O
O
O
O
O
O
O
O
O
Common voltage output 2. This pin should be bypassed with a 10-µF capacitor to AGND.
Digital power supply, 3.3 V
COM
1
DD
DD
2
Digital power supply, 3.3 V
1
Voltage output for audio signal corresponding to L-channel on PDATA1 or DSD1
Voltage output for audio signal corresponding to R-channel on PDATA1 or DSD2
Voltage output for audio signal corresponding to L-channel on PDATA2 or DSD3
Voltage output for audio signal corresponding to R-channel on PDATA2 or DSD4
Voltage output for audio signal corresponding to L-channel on PDATA3 or DSD5
Voltage output for audio signal corresponding to R-channel on PDATA3 or DSD6
Voltage output for audio signal corresponding to L-channel on PDATA4 or DSD7
Voltage output for audio signal corresponding to R-channel on PDATA4 or DSD8
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
2
3
4
5
6
7
8
31
30
29
28
6
ZERO1
ZERO2
ZERO38
Zero data flag for V
Zero data flag for V
Zero data flag for V
1
OUT
OUT
OUT
7
2
8
3–V
8
OUT
(1)
(2)
(3)
(4)
Schmitt-trigger input with internal pulldown.
Schmitt-trigger input with internal pulldown, 5-V tolerant.
Schmitt-trigger input, 5-V tolerant.
3-state output.
7
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SLES040 − JUNE 2002
BLOCK DIAGRAM
V
1
2
Output Amp and
Low-Pass Filter
OUT
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DBCK
DSD1
DSD2
DSD3
DSD4
DSD5
DSD6
DSD7
DSD8
V
OUT
Output Amp and
Low-Pass Filter
DSD
I/F
DSD
Filter
V
V
1
COM
3
4
5
6
Output Amp and
Low-Pass Filter
OUT
OUT
OUT
OUT
V
V
V
Output Amp and
Low-Pass Filter
Enhanced
Multilevel
Delta-Sigma
Modulator
PSCK
DSCK
System
Clock
System Clock
Output Amp and
Low-Pass Filter
PBCK
Output Amp and
Low-Pass Filter
PLRCK
V
V
2
7
COM
OUT
PCM
Filter
(x8 DF)
PCM
I/F
Output Amp and
Low-Pass Filter
PDATA1
PDATA2
PDATA3
PDATA4
V
OUT
8
Output Amp and
Low-Pass Filter
MS
MC
Function
Control
MDI
MDO
Zero Detect
Power Supply
8
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TYPICAL PERFORMANCE CURVES
DIGITAL FILTER—PCM MODE
8× Interpolation Filter (De-Emphasis Off)
AMPLITUDE
vs
AMPLITUDE
vs
FREQUENCY
FREQUENCY
0
−20
0
−20
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
1
2
3
4
0
1
2
3
4
Frequency[x f ]
Frequency[x f ]
s
s
Figure 1. Frequency Response (Sharp Rolloff)
Figure 2. Frequency Response (Slow Rolloff)
AMPLITUDE
vs
AMPLITUDE
vs
FREQUENCY
FREQUENCY
0.05
0.04
2
1
0.03
0
0.02
0.01
−1
−2
−3
−4
−5
0.00
−0.01
−0.02
−0.03
−0.04
−0.05
0.0
0.1
0.2
0.3
0.4
0.5
0.0
0.1
0.2
0.3
0.4
0.5
Frequency[x f ]
Frequency[x f ]
s
s
Figure 3. Pass-Band Ripple (Sharp Rolloff)
Figure 4. Frequency Response (Slow Rolloff)
9
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De-Emphasis Curves
DE-EMPHASIS LEVEL
DE-EMPHASIS ERROR
vs
vs
FREQUENCY
FREQUENCY
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.5
0.4
0.3
0.2
0.1
V
= 5 V
V
= 5 V
CC
= 32 kHz
CC
f = 32 kHz
s
f
T
s
A
= 25°C
T
A
= 25°C
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
f − Frequency − kHz
f − Frequency − kHz
Figure 5
Figure 6
DE-EMPHASIS LEVEL
vs
DE-EMPHASIS ERROR
vs
FREQUENCY
FREQUENCY
0
0.5
0.4
0.3
0.2
0.1
V
= 5 V
V
= 5 V
CC
= 44.1 kHz
CC
f = 44.1 kHz
s
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
f
T
s
= 25°C
T
A
= 25°C
A
−
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
f − Frequency − kHz
f − Frequency − kHz
Figure 7
Figure 8
10
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SLES040 − JUNE 2002
De-Emphasis Curves (Continued)
DE-EMPHASIS LEVEL
DE-EMPHASIS ERROR
vs
vs
FREQUENCY
FREQUENCY
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.5
0.4
0.3
0.2
0.1
V
= 5 V
V
= 5 V
CC
= 48 kHz
CC
f = 48 kHz
s
f
T
s
A
= 25°C
T
A
= 25°C
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0
2
4
6
8
10 12 14 16 18 20 22
0
2
4
6
8
10 12 14 16 18 20 22
f − Frequency − kHz
f − Frequency − kHz
Figure 9
Figure 10
11
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SLES040 − JUNE 2002
ANALOG DYNAMIC PERFORMANCE
Supply Voltage Characteristics
DYNAMIC RANGE
vs
SUPPLY VOLTAGE
TOTAL HARMONIC DISTORTION + NOISE (−3 dB)
vs
SUPPLY VOLTAGE
110
109
108
107
106
105
0.0016
V
f
T
A
= 5 V
= 44.1 kHz
= 25°C
V
f
T
A
= 5 V
= 44.1 kHz
= 25°C
CC
s
CC
s
0.0014
192 kHz
96 kHz
0.0012
0.0010
0.0008
192 kHz
96 kHz
44.1 kHz
44.1 kHz
4.0
4.5
V
5.0
5.5
6.0
4.0
4.5
V
5.0
5.5
6.0
− Supply Voltage − V
− Supply Voltage − V
CC
CC
Figure 11
Figure 12
CHANNEL SEPARATION
vs
SNR
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
106
105
104
103
102
101
110
109
108
107
106
105
V
f
T
A
= 5 V
= 44.1 kHz
= 25°C
V
= 5 V
= 44.1 kHz
= 25°C
CC
s
CC
f
T
s
A
44.1 kHz
96 kHz
96 kHz
192 kHz
192 kHz
44.1 kHz
4.0
4.5
V
5.0
5.5
6.0
4.0
4.5
V
5.0
5.5
6.0
− Supply Voltage − V
− Supply Voltage − V
CC
CC
Figure 13
Figure 14
All specifications at T = +25°C, V
= 5.0 V, V = 3.3 V, f = 44.1 kHz, system clock = 384 f and 24-bit data, unless otherwise noted
DD S S
A
CC
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SLES040 − JUNE 2002
Temperature Characteristics
TOTAL HARMONIC DISTORTION + NOISE (−3 dB)
DYNAMIC RANGE
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0.0018
110
109
108
107
106
V
= 5 V
V
= 5 V
CC
= 44.1 kHz
CC
f = 44.1 kHz
s
f
s
0.0016
0.0014
44.1 kHz
192 kHz
96 kHz
0.0012
96 kHz
0.0010
192 kHz
44.1 kHz
0.0008
0.0006
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 15
Figure 16
SNR
vs
CHANNEL SEPARATION
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
106
105
104
103
102
101
110
109
108
107
106
V
= 5 V
= 44.1 kHz
V
= 5 V
CC
CC
f = 44.1 kHz
s
f
s
44.1 kHz
44.1 kHz
96 kHz
96 kHz
192 kHz
192 kHz
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 17
Figure 18
All specifications at T = +25°C, V
CC
= 5.0 V, V = 3.3 V, f = 44.1 kHz, system clock = 384 f and 24-bit data, unless otherwise noted
DD S S
A
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SLES040 − JUNE 2002
DIGITAL FILTER—DSD MODE
AMPLITUDE
vs
FREQUENCY
5
0
Filter 3
Filter 1
−5
Filter 2
−10
−15
−20
−25
−30
−35
1
10
100
1k
f − Frequency − kHz
Figure 19
SYSTEM CLOCK AND RESET FUNCTIONS
System clock input
The DSD1608 requires a system clock for operating the digital interpolation filter, digital DSD filter and multilevel
delta-sigma modulator. The system clock is applied to PSCK (pin 33) in the PCM mode and to DSCK (pin 34) in the
DSD mode. When CKCE (control register 10, B3) is not set to 1, the system clock is applied to PSCK in the DSD
mode. The DSD1608 has a system clock detection circuit. Table 1 shows examples of system clock frequencies for
common audio sampling rates.
Figure 20 shows the timing requirements for the system clock input. For optimal performance, it is important to use
a clock source with low phase jitter and noise. Texas Instruments’ PLL1700 multiclock generator is an excellent
choice for providing the DSD1608 system.
In the PCM mode, the oversampling rate of digital filter is 4× when a 128-f or 192-f system clock is applied to the
S
S
DSD1608. When a 256-f , 384-f , 512-f or 768-f system clock is applied, the oversampling rate is 8×.
S
S
S,
S
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SYSTEM CLOCK FREQUENCY (f
) (MHz)
SAMPLING
FREQUENCY
SCLK
MODE
128 f
192 f
256 f
384 f
512 f
768 f
S
S
S
S
S
S
16kHz
32kHz
2.0480
4.0960
5.6488
6.1440
11.2896
12.2880
24.5760
—
3.0720
6.1440
8.4672
9.2160
16.9344
18.4320
36.8640
—
4.0960
8.1920
6.1440
12.2880
16.9344
18.4320
33.8688
36.8640
See Note
16.9344
8.1920
16.3840
22.5792
24.5760
45.1584
49.1520
See Note
22.5792
12.2880
24.5760
33.8688
36.8640
67.7376
73.7280
See Note
33.8688
44.1kHz
48kHz
11.2896
12.2880
22.5792
24.5760
See Note
11.2896
PCM
DSD
88.2kHz
96kHz
192kHz
64×44.1kHz
:
NOTE This system clock is not supported for the given sampling frequency.
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SLES040 − JUNE 2002
t
(SCKH)
2 V
H
L
System Clock
(PSCK, DSCK)
0.8 V
t
t
(SCY)
(SCKL)
SYMBOL
PARAMETERS
MIN
MAX
UNIT
ns
t
System clock pulse cycle time
System clock pulse duration high
System clock pulse duration low
13
(SCY)
t
0.4 t
ns
(SCKH)
SCY
t
0.4 t
ns
(SCKL)
SCY
Figure 20. System Clock Input Timing
Power-On and External Reset Functions
The DSD1608 includes a power-on reset function. Figure 21 shows the operation of this function. With V
> 2 V,
DD
the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time V
DD
> 2 V. After the initialization period, the DSD1608 is set to its reset default state, as described in the mode control
register section of this data sheet. The DSD1608 also includes an external reset capability using the RST input (pin
36). This allows an external controller or master reset circuit to force the DSD1608 to initialize to its reset state.
Figure 22 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. When
the RST pin is set to a logic 0 state, the DSD1608 is initialized. The RST pin is then set to a logic 1 state, thus starting
the initialization sequence, which requires 1024 system clock periods.
V
DD
2.4 V
2 V
1.6 V
Reset
Reset Removal
Internal Reset
1024 System Clocks
System Clock
(PSCK)
Figure 21. Power-On Reset Timing
RST (Pin 36)
50% of V
DD
t
(RST)
Reset
Reset Removal
Internal Reset
System Clock
1024 System Clocks
SYMBOL
PARAMETERS
MIN
MAX
UNIT
t
Reset pulse duration low
20
ns
(RST)
Figure 22. External Reset Timing
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Audio Serial Interface
The DSD1608 has two audio serial interface ports: PCM audio interface port and DSD audio interface port.
In the PCM mode, the audio interface is a 3-wire serial port. It includes PLRCK (pin 51), PBCK (pin 50), and
PDATA1–PDATA4 (pins 46–49). PBCK is the serial audio bit clock, and it is used to clock the serial data present on
PDATA1–4 into the audio interface serial shift register. Serial data is clocked into the DSD1608 on the rising edge
of PBCK. PLRCK is the serial audio left/right word clock. It is used to latch serial data into the serial audio interface
internal registers.
The DSD1608 requires the synchronization of PLRCK to the system clock, but does not require a specific phase
relation between PLRCK and system clock.
If the relationship between PLRCK and system clock changes more than 6 PBCK, internal operation is initialized
within 1/f and analog outputs are forced to 0.5 V
until re-synchronization between PLRCK and the system clock
S
CC
is completed.
In the DSD mode, the audio interface is a 2-wire serial port. DBCK (pin 37) is the serial audio bit clock, and it is used
to clock the individual direct stream digital (DSD) audio data on DSD1–DSD8 (pins 38–45). DSD data is clocked into
the DSD1608 on the rising edge of DBCK. DBCK must be synchronous with the system clock, but does not require
a specific phase relation to the system clock. DBCK is operated at the sampling frequency f ; the f of DSD is
S
S
64 × 44.1 kHz, nominal.
Audio Data Formats and Timing
2
In the PCM mode, the DSD1608 supports industry-standard audio data formats, including standard, I S, and
left-justified. The data formats are shown in Figure 23. Data formats are selected using the format bits, FMT[2:0],
in control register 10. The default data format is 24-bit standard format. All formats require binary 2s complement,
MSB-first audio data. Figure 24 shows a detailed timing diagram for the serial audio interface.
In the DSD mode, the DSD1608 supports a DSD audio data format. The data formats are shown in Figure 25.
Figure 26 shows a detailed timing diagram for the DSD audio data interface.
Serial Control Interface
The serial control interface is a 4-wire serial port which operates completely asynchronously from the serial audio
interface and the system clock. The serial control interface is used to access the on-chip mode registers. The control
interface includes MDI (pin 2), MDO (pin 5), MC (pin 4), and MS (pin 3). MDI is the serial data input, used to program
the mode registers. MDO is the serial data output, used to read back the values of the mode registers. MC is the serial
bit clock, used to shift data into the control port, and MS is the chip select for the control port.
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(1) STD Format: L-Channel = H, R-Channel = L
1/f
S
PLRCK
R-Channel
L-Channel
PBCK
(a) Data Word = 16 Bit
14 15 16
1
2
15 16
LSB
1
2
15 16
17 18
PDATA1−4
MSB
(b) Data Word = 18 Bit
16 17 18
1
1
2
17 18
LSB
1
1
2
2
PDATA1−4
MSB
(c) Data Word = 20 Bit
18 19 20
2
19 20
LSB
19 20
23 24
PDATA1−4
MSB
(d) Data Word = 24 Bit
22 23 24
1
2
23 24
LSB
1
2
PDATA1−4
MSB
(2) IIS Format: L-Channel = L, R-Channel = H
1/f
S
PLRCK
PBCK
R-Channel
L-Channel
Data Word = 24 Bit
PDATA1−4
1
2
23 24
LSB
1
2
23 24
1
MSB
(3) Left Justified Format: L-Channel = H, R-Channel = L
1/f
S
PLRCK
PBCK
R-Channel
L-Channel
Data Word = 24 Bit
PDATA1−4
1
2
23 24
LSB
1
2
23 24
1
2
MSB
Figure 23. PCM Data Format
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50% of V
DD
PLRCK
t
t
t
(LB)
(BCH)
(BCL)
50% of V
DD
PBCK
t
t
(BL)
(BCY)
50% of V
DD
PDATA1−4
SYMBOL
t
t
su(D)
h(D)
PARAMETERS
MIN
70
30
30
10
10
10
10
MAX
UNIT
ns
t
PBCK pulse cycle time
PBCK high-level time
PBCK low-level time
(BCY)
t
ns
(BCH)
t
ns
(BCL)
t
PBCK rising edge to PLRCK edge
PLRCK edge to PBCK rising edge
PDATA1−4 setup time
ns
(BL)
(LB)
t
ns
t
ns
su(D)
t
PDATA1−4 hold time
ns
h(D)
Figure 24. Timing for PCM Audio Interface
t = 1/(64 x 44.1 kHz)
DBCK
D0
D1
D2
D3
D4
DSD1−8
Figure 25. Normal Data Output Form From DSD Decoder
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t
t
(BCL)
(BCH)
50% of V
DD
t
(BCY)
50% of V
DD
DSD1−8
t
t
su(D)
h(D)
SYMBOL
PARAMETERS
MIN
(1)
MAX
UNIT
ns
t
DBCK pulse cycle time
DBCK high-level time
DBCK low-level time
DSD1−8 setup time
DSD1−8 hold time
350
(BCY)
t
30
30
10
10
ns
(BCH)
t
ns
(BCL)
t
ns
su(D)
t
ns
h(D)
(1)
2.8224 MHz = 64 × 44.1 kHz; this value is specified as a sampling rate of DSD.
Figure 26. Timing for DSD Audio Interface
Register Read/Write Operation
All read/write operations for the serial control port use 16-bit data words. Figure 27 shows the control data word
format. The most significant bit is the read/write (R/W) bit. For write operations, the R/W bit must be set to 0. For
read operations, the R/W bit must be set to 1. There are seven bits, labeled IDX[6:0], that set the register index (or
address) for the read or write operations. The least significant eight bits, D[7:0], contain the data to be written to the
register specified by IDX[6:0] or to be read from the register specified by IDX[6:0].
Figure 28 shows the functional timing diagram for writing or reading the serial control port. MS is held at a logic 1
state until a register needs to be written or read. To start the register write or read cycle, MS is set to logic 0. Sixteen
clocks are then provided on MC, corresponding to the 16 bits of the control data word on MDI and read back data
on MDO. After the eighth clock cycle has completed, the data from indexed mode control register appears on MDO
in read operation. After the sixteenth clock cycle has completed, the data is latched into the indexed mode control
register in write operations. To write or read subsequent data, MS must be set to 1 once.
LSB
MSB
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
D7
D6
D5
D4
D3
D2
D1
D0
Register Index (or Address)
Register Data
Figure 27. Control Data Word Format for MDI
MS
MC
MDI
X
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0
X
X
R/W IDX6
MDO
High Impedance
D7 D6 D5 D4 D3 D2 D1 D0
When Read Mode is Instructed
High Impedance
Figure 28. Serial Control Format
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Control Interface Timing Requirements
Figure 29 shows a detailed timing diagram for the serial control interface. These timing parameters are critical for
proper control port operation.
t
(MHH)
MS
50% of V
DD
t
t
(MCL)
(MSS)
t
t
h(MS)
(MCH)
MC
50% of V
50% of V
50% of V
DD
DD
DD
t
(MCY)
LSB
MDI
t
t
su(MD)
t
(MOS)
h(MD)
MDO
SYMBOL
PARAMETERS
MIN MAX
UNIT
t
t
t
t
t
t
t
t
t
MC pulse cycle time
MC low level time
MC high level time
MS high level time
100
40
40
80
15
15
15
15
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
(MCY)
(MCL)
(MCH)
(MHH)
(MSS)
h(MS)
h(MD)
su(MD)
(MOS)
MS falling edge to MC rise edge
(1)
MS hold time
MDI hold time
MDI setup time
MC falling edge to MDO stable
(1)
MC rising edge for LSB-to-MS rising edge.
Figure 29. Control Interface Timing
MODE CONTROL REGISTERS
User-Programmable Mode Controls
The DSD1608 includes a number of user programmable functions which are accessed via control registers. The
registers are programmed using the serial control interface which was previously discussed in this data sheet. Table 2
lists the available mode control functions, along with their reset default conditions and associated register index.
Register Map
The mode control register map is shown in Table 3. Each register includes an index (or address) indicated by the
IDX[6:0] bits B[14:8].
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Table 2. User-Programmable Mode Controls
FUNCTION
RESET DEFAULT
0dB, no attenuation
Mute disabled
REGISTER
BIT(S)
AT1[7:0] to AT8[7:0]
MUT[8:1]
PCM
DSD
Digital attenuation control, 0 dB to –∞ in 0.5 dB steps
Soft mute control
0–7
8
√
√
√
√
√
√
√
DAC operation control
DAC1 to DAC8 enabled
24-bit standard format
Disabled
9
DAC[8:1]
Audio data format control
10
10
10
10
11
11
11
12
12
12
FMT[2:0]
Clock select control
CKCE
√
√
Attenuation rate select
8/f
S
ATS
√
√
√
√
√
√
√
√
Rolloff control for 8× digital filter
De-emphasis function control
De-emphasis sample rate control
Sharp rolloff
FLT
De-emphasis disabled
44.1kHz
DM12, -34, -56, -78
DMF[1:0]
Over sampling rate control (64 f or 128 f )
64 f oversampling
S
OVR[1:0]
S
S
Output phase select
Normal phase
High
DRV12, -34, -56, -78
ZREV
√
Zero flag polarity select
Zero flag output pin select
CH1/2 flags separately
selectable
AZRO
DSD mode control
System reset
PCM mode
Not operated
Filter 1
—
12
12
DSD
√
√
√
SRST
√
DSD filter select
13, 14
16
FS1[1:0] to FS8[1:0]
ZERO[8:1]
ID[4:0]
Zero flag status (read-only)
Device ID (at TDMCA)
√
√
—
17
√
Table 3. Mode Control Register Map
B15 B14 B13 B12 B11 B10 B9
B8
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
B7
B6
B5
B4
B3
B2
B1
B0
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12
Register 13
Register 14
Register 16
Register 17
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
AT17
AT27
AT37
AT47
AT57
AT67
AT77
AT87
MUT8
DAC8
RSV
AT16
AT26
AT36
AT46
AT56
AT66
AT76
AT86
MUT7
DAC7
FLT
AT15
AT25
AT35
AT45
AT55
AT65
AT75
AT85
MUT6
DAC6
ATS
AT14
AT24
AT34
AT44
AT54
AT64
AT74
AT84
MUT5
DAC5
RSV
AT13
AT23
AT33
AT43
AT53
AT63
AT73
AT83
MUT4
DAC4
CKCE
DM78
AT12
AT22
AT32
AT42
AT52
AT62
AT72
AT82
MUT3
DAC3
FMT2
DM56
AT11
AT21
AT31
AT41
AT51
AT61
AT71
AT81
MUT2
DAC2
FMT1
DM34
AT10
AT20
AT30
AT40
AT50
AT60
AT70
AT80
MUT1
DAC1
FMT0
DM12
OVR1
SRST
FS41
FS81
OVR0
DSD
DMF1
AZRO
FS31
FS71
DMF0
ZREV DRV78 DRV56 DRV34 DRV12
FS40
FS80
FS30
FS70
FS21
FS61
FS20
FS60
FS11
FS51
FS10
FS50
ZERO8 ZERO7 ZERO6 ZERO5 ZERO4 ZERO3 ZERO2 ZERO1
RSV RSV RSV ID4 ID3 ID2 ID1 ID0
R
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Register Definitions
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 0
:
R/W
0
0
0
0
0
0
0
AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10
Register 7
R/W
0
0
0
0
1
1
1
AT87 AT86 AT85 AT84 AT83 AT82 AT81 AT80
R/W
When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed.
ATxy Digital Attenuation Level Setting
Where x = register number + 1 and y = 1 to 8, corresponding to the DAC output V
Read/Write Mode Select
:PCM/DSD Mode
1 to V
8. In PCM mode, the
OUT
OUT
default value, 1111 1111b, represents 0 dB. Each DAC channel (V
1 to V
8) includes a digital attenuation
OUT
OUT
function. The attenuation level can be set from 0 dB to –119.5 dB in 0.5 dB steps or to –∞ in PCM mode, and from
6 dB to –113.5 dB or to –∞ in DSD mode. Alternatively, the attenuation level can be set to infinite attenuation (or mute).
The following table shows attenuation levels for various settings.
ATxy
DECIMAL VALUE
ATTENUATION LEVEL SETTING
PCM Mode
DSD Mode
1111 1111b
1111 1110b
1111 1101b
:
255
254
253
:
0 dB, no attenuation (default)
6 dB
–0.5 dB
5.5 dB
–1 dB
5 dB
:
–6 dB
–6.5 dB
:
:
1111 0011b
1111 0010b
:
243
242
:
0 dB
–0.5 dB
:
–56 dB
–56.5 dB
–57 dB
–57.5 dB
:
1000 0011b
1000 0010b
1000 0001b
1000 0000b
:
131
130
129
128
:
–62 dB
–62.5 dB
–63 dB
–63.5 dB
:
0111 0101b
:
117
:
–69 dB
:
–63 dB
:
0001 0000b
0000 1111b
:
16
15
:
–119.5 dB
–∞
–113.5 dB
–∞
:
:
0000 0000b
0
–∞
–∞
B15
R/W
B14
B13
0
B12
0
B11
1
B10
0
B9
0
B8
0
B7
B6
B5
B4
B3
B2
B1
B0
Register 8
0
MUT8
MUT7
MUT6 MUT5 MUT4 MUT3 MUT2 MUT1
R/W
When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed.
MUTx Soft Mute Control
Where x = 1 to 8, corresponding to the DAC output V
Read/Write Mode Select
:PCM/DSD Mode
1 to V
8. Default value: 0
OUT
OUT
MUTx = 0
MUTx = 1
Mute disabled (default)
Mute enabled
The mute bits, MUT1 to MUT8, are used to enable or disable the soft mute function for the corresponding DAC
outputs, V 1 to V 8. The soft mute function is incorporated into the digital attenuators. When mute is disabled
OUT
OUT
(MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the digital
attenuator for the corresponding output is decreased from the current setting to infinite attenuation, one attenuator
step (0.5 dB) at a time. This provides pop-free muting of the DAC output. By setting MUTx = 0, the attenuator is
incremented one step at a time to the previously programmed attenuation level.
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B15
R/W
B14
0
B13
0
B12
0
B11
1
B10
0
B9
0
B8
1
B7
B6
B5
B4
B3
B2
B1
B0
Register 9
DAC8
DAC7
DAC6
DAC5 DAC4 DAC3 DAC2 DAC1
R/W
When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed.
DACx DAC Operation Control
Where x = 1 to 8, corresponding to the DAC output V
Read/Write Mode Select
:PCM/DSD Mode
1 to V
8. Default value: 0
OUT
OUT
DACx = 0
DACx = 1
DAC operation enabled (default)
DAC operation disabled
The DAC operation controls are used to enable and disable the DAC outputs, V
the corresponding output generates the audio waveform dictated by the data present on the DATA pin. When DACx
1 to V
8. When DACx = 0,
OUT
OUT
= 1, the corresponding output is set to the bipolar zero level, or V
affected after the next PLRCK when the write operation occurs.
/ 2. In the TDMCA mode, the DACx bits are
CC
B15
R/W
B14
0
B13
0
B12
0
B11
1
B10
0
B9
1
B8
0
B7
B6
B5
B4
B3
B2
B1
B0
Register 10
RSV
FLT
ATS
RSV
CKCE FMT2
FMT1
FMT0
R/W
When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed.
RSV Reserved Bit
The RSV bit must be set to 0.
Read/Write Mode Select
FLT
Digital Filter Roll-Off Control
:PCM Mode
Default value: 0
FLT = 0
FLT = 1
Sharp rolloff (default)
Slow rolloff
The FLT bit allows the user to select the digital filter rolloff that is best suited to a particular application. Two filter rolloff
selections are available: sharp and slow. The filter responses for these selections are shown in the Typical
Performance Curves section of this data sheet.
ATS
Attenuation Rate Select
:PCM/DSD Mode
Default value: 0
ATS = 0
ATS = 1
8/f (default)
S
16/f
S
The ATS bit is used to select the rate at which the attenuator is decremented / incremented during level transitions.
CKCE
Clock Select Control
:DSD Mode
Default value: 0
CKCE = 0
CKCE = 1
System clock is applied to PSCK in the DSD mode (default).
System clock is applied to DSCK in the DSD mode.
The CKCE bit selects the system clock source in the DSD mode (PSCK or DSCK). The CKCE bit must be set before
the DSD bit in register 12 can be set to 1.
FMT[2:0]
Audio Interface Data Format
:PCM Mode
Default value: 000. The FMT[2:0] bits are used to select the data format for the serial audio interface. The table below
shows the available format options.
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FMT[2:0]
000
Audio Data Format Select
24-bit standard format, right-justified data (default)
20-bit standard format, right-justified data
18-bit standard format, right-justified data
16-bit standard format, right-justified data
001
010
011
2
100
I S format, 24 bits
101
Left-justified format, 24 bits
Reserved
110
111
Reserved
B15
B14
0
B13
0
B12
0
B11
1
B10
0
B9
1
B8
1
B7
B6
B5
B4
B3
B2
B1
B0
Register 11
R/W
OVR1 OVR0
DMF1 DMF0 DM78 DM56 DM34 DM12
R/W
Read/Write Mode Select
When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed.
OVR[1:0]
Delta-Sigma Oversampling Rate Select
Oversampling Rate Select
Default value: 0
OVR[1:0]
00
01
1x
64× f (default)
S
128× f
S
32× f
S
The OVR[1:0] bits are used to change the oversampling rate of delta-sigma modulation. This function makes it easy
to design a post-low-pass filter for any sampling rate.
DMF[1:0]
De-Emphasis Sampling Frequency Select
Default value: 0
DMF[1:0]
De-Emphasis Sampling Frequency Select
00
01
10
11
44.1 kHz (default)
48 kHz
32 kHz
Reserved
The DMF[1:0] bits are used to select the sampling frequency for the digital de-emphasis function when de-emphasis
is enabled.
DMxx
De-Emphasis Function Control
Default value: 0
DMxx = 0
DMxx = 1
De-emphasis function disabled (default)
De-emphasis function enabled
The DMxx bits are used to enable or disable the digital de-emphasis function of selected channel pairs. Suffix 12,
34, 56, 78 means Channel 1 and 2, 3 and 4, 5 and 6, and 7 and 8 respectively. See the plots shown in the Typical
Performance Curves section of this data sheet.
B15 B14 B13 B12
R/W
B11
1
B10
1
B9
0
B8
0
B7
B6
B5
B4
B3
B2
B1
B0
Register 12
24
0
0
0
SRST
DSD
AZRO ZREV DRV78 DRV56 DRV34 DRV12
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R/W
When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed.
SRST System Reset
Default value: 0. This bit is available only in the write mode.
Read/Write Mode Select
:PCM/DSD Mode
SRST = 1
DAC system is reset once.
The SRST bit allows the user to reset DAC system. This function is same as the power-on reset. When the SRST
is set to 1, one reset pulse is generated internally. It is not necessary to set SRST to 0.
DSD
DSD Mode Control
:PCM/DSD Mode
Default value: 0
DSD = 0
DSD = 1
PCM mode (default)
DSD mode
The DSD bit allows the user to select the operation mode, PCM mode or DSD mode.
AZRO
Zero Flag Output Pin Select
:PCM Mode
Default value: 0
AZRO = 0
AZRO = 1
When ZREV = 0 and either the channel 1 or channel 2 data is continuously zero, the
ZERO1 and ZERO2 pins go HIGH. When ZREV = 1 and either the channel 1 or
channel 2 data is continuously zero, the ZERO1 and ZERO2 pins go LOW (default).
When ZREV = 0 and both the channel 1 and channel 2 data is continuously zero, the
ZERO1 and ZERO2 pins go HIGH. ZERO2 pin stay in LOW. When ZREV = 1 and both
the channel 1 and channel 2 data is continuously zero, the ZERO1 and ZERO2 pins go
LOW.
The AZRO bit allows the user to select the output form of ZERO1 and ZERO2.
ZREV
Zero Flag Polarity Select
:PCM Mode
Default value: 0
ZREV = 0
ZREV = 1
Zero flag pins HIGH at a zero detect (default)
Zero flag pins LOW at a zero detect
The ZREV bit allows the user to select the polarity of zero flag pins.
DRVxx
Output Phase Select
:PCM/DSD Mode
Default value: 0
DRVxx = 0
DRVxx = 1
Normal output (default)
Inverted output
The DRVxx bits control output analog signal phase for channel pairs. The xx suffix in the register name designates
the channel pair: -12 indicates channels 1 and 2; -34 indicates channels 3 and 4; -56 indicates channels 5 and 6; and
-78 indicates channels 7 and 8.
B15 B14 B13 B12
B11
1
B10
1
B9
0
B8
1
B7
B6
B5
B4
B3
B2
B1
B0
Register 13
Register 14
R/W
0
0
0
FS41
FS40
FS31
FS30
FS21
FS20
FS11
FS10
R/W
0
0
0
1
1
1
0
FS81
FS80
FS71
FS70
FS61
FS60
FS51
FS50
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R/W
Read/Write Mode Select
When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed.
FSxy
DSD Filter Select
:DSD Mode
Default value: 00
FSxy
00
DSD Filter Select
Filter 1 (default)
Filter 2
01
10
Filter 3
11
Reserved
The FSxy bits allow selection of the DSD filter from three kind of filters for each channel. The x suffix in the register
name designates the channel, from 1 to 8, for which the filter is being selected. The y suffix in the register name
designates the high or low bit of the filter selection value.
B15 B14 B13 B12
B11
0
B10
0
B9
0
B8
0
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R
0
0
1
ZERO8 ZERO7 ZERO6 ZERO5 ZERO4 ZERO3 ZERO2 ZERO1
R
Read Only
Zero Flag
ZEROx
ZEROx = 0
ZEROx = 1
Not zero detected on indexed channel
Zero detected on indexed channel
The ZEROx bits indicate indexed the result of ZERO detection circuit of each channels.
B15 B14 B13 B12
B11
0
B10
0
B9
0
B8
1
B7
B6
B5
B4
B3
B2
B1
B0
Register 17
R
0
0
1
RSV
RSV
RSV
ID4
ID3
ID2
ID1
ID0
R
Read Only
RSV
Reserve Bit
The RSV bit is read as 0.
ID[4:0] Device ID
The ID[4:0] bits show a device ID in TDMCA mode.
ANALOG OUTPUTS
The DSD1608 includes eight independent output channels: V
capable of driving 4 Vp-p typical into a 10-kΩ ac-coupled load. The internal output amplifiers for V
biased to the dc common-mode (or bipolar zero) voltage, equal to V /2.
1 to V
8. These are unbalanced outputs, each
OUT
OUT
1 to V
8 are
OUT
OUT
CC
The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy
present at the DAC outputs due to the noise shaping characteristics of the DSD1608 delta-sigma D/A converters.
The frequency response of this filter is shown in Figure 30. By itself, this filter is not enough to attenuate the
out-of-band noise to an acceptable level for many applications. An external low-pass filter is required to provide
sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the Applications
Information section of this data sheet.
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RESPONSE
vs
FREQUENCY
10
0
−10
−20
−30
−40
−50
−60
100
1k
10k
100k
1M
10M
f − Frequency − Hz
Figure 30. Analog Output Filter Performance (100 Hz−10 MHz)
ZERO FLAGS
The DSD1608 includes circuitry for detecting an all-zero data condition for the audio data input pin and output pins
for indicating the result.
Zero Detect Condition
Zero detection for each channel or combination of channels is independent from any other.
In PCM mode, if the data for a given channel or channel combination remains at a 0 level for 1024 sample periods
(or PLRCK clock periods), a zero-detect condition exists for that channel or combination of channels.
In DSD mode, zero detection is not available.
Zero Output Flags
Given that a zero-detect condition exists for each channel or combination of channels, the zero flag pins for those
conditions will be set to a logic 1 state. There are three zero flag pins for channel 1, ZERO1 (pin 6), for channel 2,
ZERO2 (pin 7) and for a logical AND of channels 3 through 8, ZERO38 (pin 8). These pins can be used to operate
external mute circuits, or used as status indicators for a microcontroller, audio signal processor, or other digitally
controlled circuit.
The active polarity of the zero flag outputs can be inverted by setting the ZREV bit of control register 12 to 1. The
reset default is active-high output, or ZREV = 0.
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APPLICATION INFORMATION
CONNECTION DIAGRAMS
A basic connection diagram is shown in Figure 31, with the necessary power supply bypass and decoupling
components.
The use of series resistors (22 Ω to 100 Ω) is recommended for the xSCK, PLRCK, xBCK, PDATAX, and DSDx inputs.
The series resistor combines with the stray PCB and device input capacitance to form a low-pass filter which reduces
high-frequency noise emissions and helps to dampen glitches and ringing present on clock and data lines.
POWER SUPPLIES AND GROUNDING
The DSD1608 requires a 5-V analog supply and a 3.3-V digital supply. The 5-V supply is used to power the DAC
analog and output filter circuitry, while the 3.3-V supply is used to power the digital filter and serial interface circuitry.
For best performance, the 3.3-V digital supply should be derived from the 5-V supply by using a linear regulator. Texas
Instruments’ REG1117-3.3 is an ideal choice for this application.
Proper power supply bypassing is shown in Figure 31. The 10-µF capacitors should be tantalum or aluminum
electrolytic, while the 0.1-µF capacitors are ceramic (the X7R type is recommended for surface-mount applications).
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PLL1700
27 MHz Master Clock
5 V
GND
Analog
REG117
3.3 V
+
+
+
+
+
+
+
+
+
V
2
7
6
26
25
24
40 DSD3
41 DSD4
42 DSD5
43 DSD6
44 DSD7
45 DSD8
46 PDATA1
47 PDATA2
48 PDATA3
49 PDATA4
50 PBCK
51 PLRCK
COM
+
V
V
CC
CC
Audio DSP
or
Decoder
(DSD)
AGND5 23
V
5 22
CC
AGND4 21
Output
Low-Pass
Filter
DSD1608
V
4 20
CC
AGND3 19
Audio DSP
or
Decoder
(PCM)
V
3 18
CC
AGND2 17
V
V
2
1
1
16
15
14
CC
CC
V
52
V
1
DD
COM
+
+
µC/µP
+
+
+
+
Figure 31. Basic Connection Diagram
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D/A OUTPUT FILTER CIRCUITS: POST-LOW-PASS FILTER
The DSD1608 requires a third- or second-order analog low-pass filter to achieve the frequency response
recommended by the SACD standard and reduce the out-of-band noise produced by the delta-sigma modulator.
Figure 32 shows the recommended external low-pass filter circuit. This circuit is a third-order Butterworth filter using
the Sallen-Key circuit arrangement. The filter response and corner frequency are determined by the frequency
response recommended by the SACD standard. Figure 32 lists the standard values for resistors and capacitors
corresponding with the DSD digital filter on DSD1608. This filter can be used in either the PCM or the DSD modes.
C2
680 pF
R1
R2
R3
2.7 kΩ
6.8 kΩ
15 kΩ
+
−
C1
1500 pF
C3
100 pF
R4
10 kΩ
R5
10 kΩ
Figure 32. Post-Low-Pass Filter Circuit
TDMCA FORMAT
The DSD1608 supports the time division multiplexed command and audio data (TDMCA) format to reduce any host
control serial interface. The TDMCA format is designed for not only McBSP of TI DSPs but also any programmable
devices. The TDMCA format can transfer not only audio data but also command data so that it can be used with any
kind of device that supports the TDMCA format. The TDMCA frame consists of a command field, extended command
field, and some audio data fields. The audio data are transported to IN devices (such as DAC) and/or from OUT
devices (such as ADC). The DSD1608 is an IN device. PLRCK and PBCK are shared both IN and OUT devices so
that the sample frequency must be united in one system. The TDMCA mode supports a maximum of 30 device IDs.
The maximum number of audio channel depends on the PBCK frequency.
TDMCA Mode Determination
The DSD1608 recognizes the TDMCA mode by receiving PLRCK which pulse width is two PBCK clocks. The
DSD1608 goes into the TDMCA after two continuous TDMCA frames. Figure 33 shows the PLRCK and PBCK timing
required for the TDMCA mode. Any TDMCA commands can be issued the next TDMCA frame after entering the
TDMCA mode. If operation in the TDMCA mode operation is not required, PLRCK must be a 50%-duty-cycle square
wave.
Command
Accept
Pre TDMCA Frame
TDMCA Frame
PLRCK
PBCK
2PBCK
Figure 33. PLRCK and PBCK Timing for the TDMCA Mode
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TDMCA Terminals
TDMCA requires six signals, of which four are for command and audio data interface and two are for the daisy chain.
Signals that can be shared are as indicated in the following table. The host interface signals, MS, MC and MDO
change to DCI, DCO, and PDO respectively. The MDO signal is 3-state output so that it can be connected directly
to other PDO terminals.
TERMINAL (SIGNAL) NAME
PROPERTY
DESCRIPTION
PLRCK
Input
TDMCA frame-start signal. The frequency of PLRCK must be the same as the sampling
frequency.
PBCK
Input
TDMCA clock. The frequency of PBCK must be high enough to communicate the TDMCA
frame within a PLRCK clock cycle.
PDATA1/PDI
MDO/PDO
MS/DCI
Input
TDMCA command and audio data input signal
TDMCA command data three-state output signal
TDMCA daisy chain input signal
Output
Input
MC/DCO
Output
TDMCA daisy chain output signal
Device ID Determination
The TDMCA mode also supports a multi-chip implementation in one system. This means that the host controller
(DSP) can support several PCM devices and/or other devices simultaneously. The PCM devices are categorized as
IN device, OUT device, IN/OUT device, and NO device. The IN device has an input port to receive audio data. The
OUT device has a output port to provide audio data. The IN/OUT device has both input and output ports for audio
data. The NO device has no port for audio data but needs command data from the host. A DAC is an IN device, an
ADC is an OUT device, a CODEC is an IN/OUT device, and a PLL is a NO device. The DSD1608 is an IN device.
To distinguish devices from the host controller, each device is given its own device ID by the daisy chain. A device
gets its own device ID automatically by connecting its DCO to the DCI of the next device in the daisy chain. There
are actually two completely independent and equivalent daisy chains, which are categorized as the IN chain and the
OUT chain. Figure 34 shows the daisy chain connection. If a system needs to chain a DSD1608 and a NO device
in the same IN chain, the NO device should be chained at the back of the IN chain because it doesn’t require any
audio data. Figure 35 shows an example of a TDMCA system that includes an IN chain and an OUT chain with a
TI DSP. For chained devices to get their own device IDs, the DID signal should be set to 1 (the details are described
later) and PLRCK and PBCK should be driven to initiate the TDMCA mode for all devices which are chained. The
device at the top of the chain determines its device ID is 1 when DCI is fixed HIGH. Every other device determines
its position in the chain by counting PBCK pulses and observing its own DCI signal. Figure 36 shows the initialization
of each device ID. If all devices do not need separate device IDs, each DCI should be held high, causing the
corresponding device IDs to be 1.
IN Chain
IN Device
IN Device
IN
IN
NO Device
NO Device
NO Device
NO Device
INOUT
OUT
INOUT
OUT
OUT Device
OUT Device
OUT Chain
Figure 34. Daisy Chain Connection
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PLRCK
PBCK
PDI
DCI
IN Device
(DSD1608)
DCO
PDO
Device ID = 1
PLRCK
PBCK
PDI
DCI
NO Device
DCO
PDO
Device ID = 2
FSX
FSR
CLKX
CLKR
PLRCK
PBCK
PDI
DCI
OUT Device
DX
DCO
DR
PDO
Device ID = 1
TI DSP
PLRCK
PBCK
PDI
DCI
OUT Device
DCO
PDO
Device ID = 2
Figure 35. IN and OUT Daisy Chain Connection for Multichip System
PLRCK
PBCK
Command Field
PDI
DID
Device ID = 1
Device ID = 2
DCO1
DCO1
DCI2
Device ID = 3
DCO2
DCI3
58 BCKs
DCO29
DCI30
Device ID = 30
Figure 36. Device ID Determination Sequence
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TDMCA Frame
In general, the TDMCA frame consists of a command field, an extended command (EMD) field, and an audio data
field. All fields are 32 bits in length, but the LS byte has no meaning. The MSB is transferred first for each field. The
command field is always transferred as the first packet of the frame. The EMD field is transferred if the EMD flag of
the command field is high. If any EMD packets are transferred, no audio data follow after those EMD packets. This
frame is for quick initialization. All devices of the daisy chain should respond to the command field and extended
command field. The DSD1608 has eight audio channels that can be selected in register 41. If the corresponding flags
are preset low, those audio channels are transferred. Figure 37 shows a general TDMCA frame. If some DACs are
enabled although the corresponding audio data packets are not transferred, the analog outputs of those DACs are
unpredictable.
1/f
S
PLRCK
PBCK
[For Initialization]
Don’t
Care
PDI
EMD
CMD
CMD
EMD
EMD
CMD
EMD
EMD
32 Bits
PDO
CMD
CMD
CMD
CMD
CMD
CMD
[For Operation]
Don’t
Care
Ch(n)
Ch2
Ch2
Ch4
Ch4
CMD
Ch1
Ch1
Ch3
Ch3
PDI
PDO
CMD
Ch(m)
Figure 37. General TDMCA Frame
1/f (256 PBCK Clocks)
S
7 Packets x 32 Bits
PLRCK
PBCK
Don’t
Care
PDI
CMD
Ch4
IN and OUT Channel Orders are Completely Independent
Ch1 Ch2
Ch6
Ch7
Ch8
Ch3
CMD
Ch5
PDO
CMD
Figure 38. TDMCA Frame Example of 6-Ch DAC and 2-Ch ADC With Command Read
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Command Field
The command field is defined as follows. The DID field (MSB) has another meaning, that this frame is for device ID
determination.
31
30
29
28
24 23 22
R/W
21
20
16 15
8
7
0
command
DID
EMD DCS
Device ID
Register ID
Data
Not used
Bit 31: Device ID Enable Flag
The DSD1608 operates to get its own device ID if this bit is HIGH. This is for TDMCA initialization.
Bit 30: Extended Command Enable Flag
An EMD packet is transferred if this bit is HIGH, otherwise skipped. When the bit is HIGH, this frame does not contain
any audio data. This is for system initialization.
Bit 29: Daisy Chain Selection Flag
HIGH means OUT chain devices, LOW means IN chain devices. The DSD1608 is an IN device, so the DCS bit must
be set to LOW.
Bit [28:24]: Device ID
The device ID is 5 bits in length, and it can be defined. IDs of devices follow the order of an IN or OUT daisy chain.
The top device of the daisy chain has device ID 1 and the next device in the chain has device ID 2, etc. The ID for
any device that has its DCI set HIGH is also 1. The maximum device ID each in the IN or OUT chain is 30. If a device
ID is 0x1F, all devices are selected as broadcast when in the write mode. If any device ID is 0x00, no device is
selected.
Bit 23: Command Read/Write Flag
If it is HIGH, the command is a read operation.
Bit [22:16]: Register ID
The register ID is 7 bits in length. See Table 3.
Bit [15:18]: Command Data
The command data is 8 bits in length. Any valid data can be chosen for each register. See Table 3.
Bit [7:0]: Not used
These bits are never transported when a read operation is performed.
Extended Command Field
The extended command field is almost the same as the command field. The only difference is that it does not have
a DID flag.
31
30
29
28
24 23 22
R/W
21
20
16 15
8
7
0
Extended command RSVD EMD DCS
Device ID
Register ID
Data
Not Used
Audio Field
The audio field is 32 bits in length and the audio data is transferred MSB first. When transferring audio data of less
than 32 bits, the unused portion of the field must be padded with 0s, as the following figure shows.
31
16
12
8
7
0
Audio data
MSB
MSB
MSB
24 bits
20 bits
16 bits
LSB
All 0s
LSB
All 0s
LSB
All 0s
TDMCA Register Requirements
The TDMCA mode requires device ID and audio channel information, previously described. Register 9 indicates the
audio channels and register 17 indicates the device ID. Register 17 is used only in the TDMCA mode. See the Mode
Control Register Map, Table 3.
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Register Write/Read Operation
The command supports register write and read operations. If the command requests to read one register, the read
data is transferred on PDO during the data phase portion of the timing cycle. The PDI signal can be retrieved on the
positive edge of PBCK and the PDO signal is driven on the negative edge of PBCK. The PDO is activated one cycle
early due to compensate for the output delay caused by high impedance. Figure 39 shows the TDMCA write and read
timing.
Register ID Phase
Data Phase
PBCK
Read Mode and Proper Register ID
Write Data Retrieved, if Write Mode
PDI
Read Data Driven, if Read Mode
1 PBCK Early
PDO
PDOEN
(Internal)
Figure 39. TDMCA Write and Read Operation Timing
TDMCA Mode Operation
DCO specifies the owner of the next audio channel in TDMCA operation. When one device retrieves its own audio
channel data, the DCO becomes HIGH during last audio channel period. Figure 40 shows the DCO output timing
during a TDMCA-mode operation. The host controller is not affected by the behavior of DCI and DCO. DCO indicates
the last audio channel of each device. Therefore, DCI means that the next audio channel is allocated.
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1/f (384 PBCK Clocks)
S
9 Packets x 32 Bits
PLRCK
PBCK
IN Daisy Chain
Ch2 Ch3 Ch4 Ch5
CMD Ch1
Ch6 Ch7 Ch8
Don’t Care
CMD
PDI
DCI1
DID = 1
DID = 2
DCO1
DCI2
DCO2
DCI3
DID = 3
DID = 4
DCO3
DCI4
DCO4
IN Daisy Chain
PDI
CMD
CMD
Ch1
Ch2 Ch3 Ch4
Ch5
Ch6 Ch7 Ch8
DCI1
DID = 1
DID = 2
DID = 3
DID = 4
DCO1
DCI2
DCO2
DCI3
DCO3
DCI4
DCO4
Figure 40. DCO Output Timing in TDMCA-Mode Operation
1/f (768 PBCK Clocks)
S
17 Packets x 32 Bits
PLRCK
PBCK
IN Daisy Chain
Ch7 Ch8
Ch16
Ch15
PDI
Ch1
Ch9
Don’t Care
CMD
CMD
DCI1
DID = 1
DID = 2
DCO1
DCI2
DCO2
DCI3
DID = 3
Figure 41. DCO Output Timing Example for 16-Ch Audio Data of Two DSD1608s
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If some devices are skipped due to lack of an active audio channel, each skipped device must notify the next device
that the DCO will be passed through the next DCI. Figure 42 and Figure 43 show DCO timing with skip operation.
Figure 44 shows the ac timing of daisy chain signals.
1/f (256 PBCK Clocks)
S
5 Packets x 32 Bits
PRLCK
PBCK
PDI
DCI
CMD
Ch1
Ch2
Ch15
Ch16
Don’t Care
CMD
DID = 1
DID = 2
DCO
DCI
2 PBCK Delay
14 PBCK Delay
DCO
DCI
DID = 8
DCO
Figure 42. DCO Output Timing With Skip Operation
Command Packet
PLRCK
PBCK
PDI
DID EMD
DCO1
DCO2
Figure 43. DCO Output Timing With Skip Operation (for Command Packet 1)
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PLRCK
t
t
(BL)
(LB)
PBCK
PDI
t
t
t
(DH)
(BCY)
(DS)
t
(DOE)
PDO
DCI
t
t
(DH)
(DS)
t
(COE)
DCO
SYMBOL
PARAMETERS
PBCK pulse cycle time
PLRCK setup time
PLRCK hold time
PDI setup time
MIN MAX
UNIT
ns
t
t
t
t
t
t
t
t
t
20
0
(BCY)
ns
(LB)
3
ns
(BL)
0
ns
CDS)
(DH)
(DS)
PDI hold time
3
ns
DCI setup time
0
ns
DCI hold time
3
ns
(DH)
(DOE)
(COE)
(1)
PDO output delay
DCO output delay
8
ns
(1)
6
ns
(1)
Load capacitance is 10 pF.
Figure 44. AC Timing of Daisy Chain Signals
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HOST CONTROL FLOW
The host controller can control the TDMCA mode as follows:
1. Decides daisy chain to initialize PLRCK and PBCK signals generator
2. Generates TDMCA mode determination sequence
3. Sets DID flag in command to fix device ID automatically
4. Checks all device IDs if necessary
5. Initializes all devices
6. Communicates audio data and commands
No
Use TDMCA Mode?
Yes
Normal-Mode Operation
(1) Initialize Serial Port (McBSP)
Set FSX, CLKX Periods, Word,
Frame Length, ...
(2) Generates TDMCA Mode
Determination Timing With DID
Flag, Then Device ID Is
Determined Automatically
(3) Confirms Each Device ID
and Initialize All Devices Using
EMD Packet
(4)(5) Sends Command
and Audio Data
Figure 45. TDMCA Control Flow From Host
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MECHANICAL DATA
PAH (S-PQFP-G52)
PLASTIC QUAD FLATPACK
0,38
0,22
M
0,13
0,65
39
27
40
26
52
14
0,13 NOM
1
13
7,80 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
0,25
11,80
0,05 MIN
0°−ā7°
1,05
0,95
0,75
0,45
Seating Plane
0,10
1,20 MAX
4040281/C 11/96
NOTES:A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
40
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DSD1608PAH
ACTIVE
TQFP
PAH
52
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DSD1608
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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