DS92LV0412SQE/NOPB [TI]
具有 LVDS 并行接口的 5 - 50MHz Channel Link II 解串器 | RHS | 48 | -40 to 85;型号: | DS92LV0412SQE/NOPB |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 LVDS 并行接口的 5 - 50MHz Channel Link II 解串器 | RHS | 48 | -40 to 85 驱动 接口集成电路 |
文件: | 总53页 (文件大小:707K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DS92LV0411, DS92LV0412
www.ti.com
SNLS331B –MAY 2010–REVISED APRIL 2013
DS92LV0411 / DS92LV0412 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS
Parallel Interface
Check for Samples: DS92LV0411, DS92LV0412
1
FEATURES
DESCRIPTION
The DS92LV0411 (serializer) and DS92LV0412
(deserializer) chipset translates a Channel Link LVDS
video interface (4 LVDS Data + LVDS Clock) into a
high-speed serialized interface over a single CML
pair.
2
•
5-Channel (4 data + 1 clock) Channel Link
LVDS Parallel Interface Supports 24-bit Data
3-bit Control at 5 – 50 MHz
•
AC Coupled STP Interconnect up to 10 Meters
in Length
The DS92LV0411/DS92LV0412 enables applications
that currently use the popular Channel Link or
Channel Link style devices to seamlessly upgrade to
an embedded clock interface to reduce interconnect
cost or ease design challenges. The parallel LVDS
interface also reduces FPGA I/O pins, board trace
count and alleviates EMI issues, when compared to
traditional single-ended wide bus interfaces.
•
•
•
•
Integrated Serial CML Terminations
AT–SPEED BIST Mode and Status Pin
Optional I2C Compatible Serial Control Bus
Power Down Mode Minimizes Power
Dissipation
•
•
•
1.8V or 3.3V Compatible Control Pin Interface
>8 kV ESD (HBM) Protection
Programmable
transmit
de-emphasis,
receive
-40° to +85°C Temperature Range
SERIALIZER – DS92LV0411
equalization, on-chip scrambling and DC balancing
enables longer distance transmission over lossy
cables
and
backplanes.
The
Deserializer
•
•
•
Data Scrambler for Reduced EMI
DC–Balance Encoder for AC Coupling
automatically locks to incoming data without an
external reference clock or special sync patterns,
providing easy “plug-and-go” operation.
Selectable Output VOD and Adjustable De-
Emphasis
The
DS92LV0411
and
DS92LV0412
are
programmable though an I2C interface as well as by
pins. A built-in AT-SPEED BIST feature validates link
integrity and may be used for system diagnostics.
DESERIALIZER – DS92LV0412
•
Random Data Lock; No Reference Clock
Required
The DS92LV0411 and DS92LV0412 can be used
•
•
Adjustable Input Receiver Equalization
interchangeably
with
the
DS92LV2411
or
EMI Minimization on Output Parallel Bus
(Spread Spectrum Clock Generation and LVDS
VOD Select)
DS92LV2412. This allows designers the flexibility to
connect to the host device and receiving devices with
different interface types, LVDS or LVCMOS.
APPLICATIONS
•
•
Embedded Video and Display
Machine Vision, Industrial Imaging, Medical
Imaging
•
Office Automation — Printers, Scanners,
Copiers
•
•
Security and Video Surveillance
General purpose data communication
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
DS92LV0411, DS92LV0412
SNLS331B –MAY 2010–REVISED APRIL 2013
www.ti.com
Applications Diagram
Channel Link
Channel Link II
Channel Link
VDDIO
(1.8V or 3.3V)
VDDIO
(1.8V or 3.3V)
1.8V
1.8V 3.3V
RxIN3+/-
TxOUT3+/-
High-Speed Serial Link
1 Pair/AC Coupled
RxIN2+/-
TxOUT2+/-
Camera/AFE
Frame Grabber
Or
RGB Display
QVGA to XGA
24-bit Color Depth
DOUT+
DOUT-
RIN+
RIN-
Or
HOST
Graphics
Processor
RxIN1+/-
TxOUT1+/-
TxOUT0+/-
RxIN0+/-
100 ohm STP Cable
RxCLKIN+/-
TxCLKOUT+/-
CMF
DS92LV0411
DS92LV0412
LOCK
PASS
SSC[2:0]
PDB
BISTEN
VODSEL
De-Emph
LFMODE
CONFIG[1:0]
MAPSEL
MAPSEL
CONFIG[1:0]
PDB
BISTEN
OEN
OSSEL
VODSEL
SCL
SDA
ID[x]
SCL
SDA
ID[x]
Optional
Optional
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SNLS331B –MAY 2010–REVISED APRIL 2013
Block Diagrams
VODSEL
De-Emph
RxIN3+/-
RxIN2+/-
DOUT+
DOUT-
RxIN1+/-
RxIN0+/-
RxCLKIN+/-
Pattern
Generator
PLL
CONFIG[1:0]
MAPSEL
PDB
Timing and
Control
SCL
SCA
ID[x]
BISTEN
DS92LV0411
SSC[2:0]
OEN
VODSEL
SSCG
CMF
TxOUT[3]
TxOUT[2]
RIN+
RIN-
TxOUT[1]
TxOUT[0]
TxCLKOUT
EQ
Error
Detector
PASS
LOCK
PDB
SCL
SCA
Timing and
Control
ID[x]
PLL
BISTEN
OSS_SEL
LFMODE
DS92LV0412
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SNLS331B –MAY 2010–REVISED APRIL 2013
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DS92LV0411 Pin Diagram
RxIN0-
RxIN0+
RxIN1-
28
29
30
31
32
33
34
35
36
18
17
16
15
14
13
12
11
10
RES3
DAP = GND
VDDTX
DOUT+
DOUT-
VDDHS
RES2
RxIN1+
RxIN2-
DS92LV0411
(Top View)
RxIN2+
RxCLKIN-
RxCLKIN+
RES5
RES1
VDDP
CONFIG[1]
Figure 1. DS92LV0411 — Top View
4
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Pin Name
SNLS331B –MAY 2010–REVISED APRIL 2013
Table 1. DS92LV0411 PIN DESCRIPTIONS
Pin #
I/O, Type
Description
Channel Link Parallel Input Interface
RxIN[3:0]+
RxIN[3:0]-
RxCLKIN+
RxCLKIN-
2, 33, 31,
29
I, LVDS
I, LVDS
I, LVDS
I, LVDS
True LVDS Data Input
These inputs require an external 100 Ω differential termination for standard LVDS levels.
1, 34, 32,
30, 28
Inverting LVDS Data Input
These inputs require an external 100 Ω differential termination for standard LVDS levels.
35
True LVDS Clock Input
These inputs require an external 100 Ω differential termination for standard LVDS levels.
34
Inverting LVDS Clock Input
These inputs require an external 100 Ω differential termination for standard LVDS levels.
Control and Configuration
PDB
23
I, LVCMOS Power-down Mode Input
w/ pull-down PDB = 1, Device is enabled (normal operation).
Refer to POWER UP REQUIREMENTS AND PDB PIN in the Applications Information
Section.
PDB = 0, Device is powered down
When the Device is in the power-down state, the driver outputs (DOUT+/-) are both logic high,
the PLL is shutdown, IDD is minimized. Control Registers are RESET.
VODSEL
De-Emph
20
19
I, LVCMOS Differential Driver Output Voltage Select — Pin or Register Control
w/ pull-down VODSEL = 1, LVDS VOD is ±450 mV, 900 mVp-p (typ) — Long Cable / De-E Applications
VODSEL = 0, LVDS VOD is ±300 mV, 600 mVp-p (typ)
I, Analog
w/ pull-up
De-Emphasis Control — Pin or Register Control
De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to GND or control via register.
(See Table 5)
MAPSEL
26
I, LVCMOS Channel Link Map Select — Pin or Register Control
w/ pull-down MAPSEL = 1, MSB on RxIN3+/-. (SeeFigure 23)
MAPSEL = 0, LSB on RxIN3+/-. (See Figure 22)
CONFIG[1:0]
10, 9
I, LVCMOS Operating Modes
w/ pull-down Determines the device operating mode and interfacing device. (See Table 2)
CONFIG[1:0] = 00: Interfacing to DS92LV2412 or DS92LV0412, Control Signal Filter
DISABLED
CONFIG[1:0] = 01: Interfacing to DS92LV2412 or DS92LV0412, Control Signal Filter
ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR124, DS99R124
CONFIG [1:0] = 11: Interfacing to DS90C124
ID[x]
4
6
I, Analog
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. (See Table 11)
SCL
I, LVCMOS Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to 3.3V
SDA
7
I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor to 3.3V
BISTEN
21
I, LVCMOS BIST Mode — Optional
w/ pull-down BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
RES[7:0]
25, 3, 36,
I, LVCMOS Reserved - tie LOW
27, 18, 13, w/ pull-down
12, 8
Channel Link II Serial Interface
DOUT+
16
O, CML
True Output.
The output must be AC Coupled with a 0.1 μF capacitor.
DOUT-
15
O, CML
Inverting Output.
The output must be AC Coupled with a 0.1 μF capacitor.
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Table 1. DS92LV0411 PIN DESCRIPTIONS (continued)
Pin Name
Pin #
I/O, Type
Description
Power and Ground(1)
VDDL
5
11
Power
Power
Power
Power
Power
Power
Ground
Logic Power, 1.8 V ±5%
VDDP
VDDHS
VDDTX
VDDRX
VDDIO
GND
PLL Power, 1.8 V ±5%
14
TX High Speed Logic Power, 1.8 V ±5%
Output Driver Power, 1.8 V ±5%
RX Power, 1.8 V ±5%
17
24
22
LVCMOS I/O Power and Channel Link I/O Power 1.8 V ±5% OR 3.3 V ±10%
DAP
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
(1) 1= HIGH, 0 = LOW. The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms
then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
DS92LV0412 Pin Diagram
RES
VDDA
GND
TxOUT0-
TxOUT0+
TxOUT1-
TxOUT1+
TxOUT2-
TxOUT2+
TxCLKOUT-
TxCLKOUT+
TxOUT3-
TxOUT3+
GND
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
DAP = GND
RIN+
RIN-
DS92LV0412
CMF
(Top View)
VDDA
GND
GND
VDDSC
VDDSC
GND
VDDTX
Figure 2. DS92LV0412 — Top View
6
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Pin Name
SNLS331B –MAY 2010–REVISED APRIL 2013
DS92LV0412 PIN DESCRIPTIONS
Description
Pin #
I/O, Type
Channel Link II Serial Interface
RIN+
RIN-
CMF
40
41
42
I, CML
I, CML
True Input.
The output must be AC Coupled with a 0.1 μF capacitor.
Inverting Input.
The output must be AC Coupled with a 0.1 μF capacitor.
I, Analog
Common Mode Filter
VCM center tap is a virtual ground which can be AC-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7μF or higher.
Channel Link Parallel Output Interface
RxIN[3:0]+ 15, 19, 21, 23
RxIN[3:0]- 16, 20, 22, 24
O, LVDS
O, LVDS
O, LVDS
O, LVDS
True LVDS Data Output
Inverting LVDS Data Output
True LVDS Clock Output
Inverting LVDS Clock Output
RxCLKIN+
RxCLKIN-
17
18
LVCMOS Outputs
LOCK
27
O, LVCMOS LOCK Status Output
LOCK = 1, PLL is locked, output stated determined by OEN.
LOCK = 0, PLL is unlocked, output states determined by OSS_SEL and OEN.
(See Table 6)
Control and Configuration
PDB
1
I, LVCMOS Power-down Mode Input
w/ pull-down PDB = 1, Device is enabled (normal operation).
PDB = 0, Device is powered down and the outputs are Tri-State
Control Registers are RESET.
VODSEL
33
I, LVCMOS Parallel LVDS Driver Output Voltage Select — Pin or Register Control
w/ pull-down VODSEL = 1, LVDS VOD is ±400 mV, 800 mVp-p (typ) — Long Cable / De-E Applications
VODSEL = 0, LVDS VOD is ±250 mV, 500 mVp-p (typ)
OEN
30
35
36
I, LVCMOS Output Enable.
w/ pull-down (See Table 6)
OSS_SEL
LFMODE
I, LVCMOS Output Sleep State Select Input.
w/ pull-down (See Table 6)
I, LVCMOS SSCG Low Frequency Mode — Pin or Register Control
w/ pull-down LF_MODE = 1, low frequency mode (TxCLKOUT = 10–20 MHz)
LF_MODE = 0, high frequency mode (TxCLKOUT = 20–65 MHz)
SSCG not avaialble above 65 MHz.
MAPSEL
34
I, LVCMOS Channel Link Map Select — Pin or Register Control
w/ pull-down MAPSEL = 1, MSB on TxOUT3+/-. (See Figure 23)
MAPSEL = 0, LSB on TxOUT3+/-. (See Figure 22)
CONFIG[1
:0]
11, 10
I, LVCMOS Operating Modes
w/ pull-down Determine the device operating mode and interfacing device. (See Table 2)
CONFIG[1:0] = 00: Interfacing to DS92LV2411 or DS92LV0411, Control Signal Filter
DISABLED
CONFIG[1:0] = 01: Interfacing to DS92LV2411 or DS92LV0411, Control Signal Filter
ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR241, DS99R421
CONFIG [1:0] = 11: Interfacing to DS90C241
SSC[2:0]
RES
7, 2, 3
37
I, LVCMOS Spread Spectrum Clock Generation (SSCG) Range Select
w/ pull-down (See Table 9 and Table 10)
I, LVCMOS Reserved
w/ pull-down
Control and Configuration — STRAP PIN
EQ 28 [PASS] STRAP
EQ Gain Control of Channel Link II Serial Input
I, LVCMOS EQ = 1, EQ gain is enabled (~13 dB)
w/ pull-down EQ = 0, EQ gain is disabled (~ 1.625 dB)
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DS92LV0412 PIN DESCRIPTIONS (continued)
Pin Name
Pin #
I/O, Type
Description
Optional BIST Mode
BISTEN
PASS
29
28
I, LVCMOS BIST Mode — Optional
w/ pull-down BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
O, LVCMOS PASS Output (BIST Mode) — Optional
PASS =1, no errors detected
PASS = 0, errors detected
Leave open if unused. Route to a test point (pad) recommended.
Optional Serial Bus Control
ID[x]
SCL
SDA
12
I, Analog
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. (See Table 11)
5
I, LVCMOS Serial Control Bus Clock Input - Optional
Open Drain SCL requires an external pull-up resistor to 3.3V.
4
I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor 3.3V.
Power and Ground(1)
VDDL
VDDA
VDDP
VDDSC
6, 31
38, 43
8
Power
Power
Power
Power
Logic Power, 1.8 V ±5%
Analog Power, 1.8 V ±5%
PLL Power, 1.8 V ±5%
46, 47
SSC Generator Power, 1.8 V ±5%. Power must be connected to these pins regardless if the
SSCG feature is used or not.
VDDTX
VDDIO
GND
13
25
Power
Power
Ground
Channel Link LVDS Parallel Output Power, 3.3 V ±10%
LVCMOS I/O Power and Channel Link I/O Power 1.8 V ±5% OR 3.3 V ±10%
Ground
9, 14, 26, 32,
39, 44, 45, 48
DAP
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
(1) 1= HIGH, 0 = LOW. The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms
then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
8
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SNLS331B –MAY 2010–REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage – VDDn (1.8V)
−0.3V to +2.5V
−0.3V to +4.0V
Supply Voltage – VDDIO
Supply Voltage – VDDTX
(1.8V, Ser))
−0.3V to +2.5V
Supply Voltage – VDDTX
(3.3V, Des)
−0.3V to +4.0V
−0.3V to (VDDIO + 0.3V)
−0.3V to (VDDIO + 0.3V)
−0.3V to (VDDTX + 0.3V)
−0.3V to (VDDn + 0.3V)
−0.3V to (VDD + 0.3V)
+150°C
LVCMOS I/O Voltage
LVDS Input Voltage
LVDS Output Voltage
CML Driver Output Voltage
Receiver Input Voltage
Junction Temperature
Storage Temperature
−65°C to +150°C
36L WQFN Package
Maximum Power Dissipation Capacity at 25°C
Derate above 25°C
1/ θJA°C/W
27.4 °C/W
4.5 °C/W
θJA(with 9 thermal via)
θJC(with 9 thermal via)
48L WQFN Package
Maximum Power Dissipation Capacity at 25°C
Derate above 25°C
1/ θJA°C/W
27.7 °C/W
3.0 °C/W
θJA(with 9 thermal via)
θJC(with 9 thermal via)
ESD Rating (IEC, powered-up only), RD = 330Ω, CS = 150 pF
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
≥±30 kV
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
≥±8 kV
≥±8 kV
ESD Rating (HBM)
ESD Rating (CDM)
≥±1.25 kV
≥±250 V
ESD Rating (MM)
For soldering specifications: http://www.ti.com/lit/SNOA549
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
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Recommended Operating Conditions
Min
1.71
1.71
3.0
Nom
1.8
Max
1.89
1.89
3.6
Units
Supply Voltage (VDDn
Supply Voltage (VDDTX_Ser
Supply Voltage (VDDTX_Des
)
V
V
V
V
)
1.8
)
3.3
LVCMOS Supply Voltage (VDDIO
OR
)
)
1.71
1.8
1.89
LVCMOS Supply Voltage (VDDIO
3.0
3.3
3.6
V
Operating Free Air
Temperature (TA)
−40
+25
+85
50
°C
RxCLKIN/TxCLKOUT Clock Frequency
Supply Noise(1)
5
MHz
mVP-P
100
(1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with
amplitude = 100 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter
cable shows no error when the noise frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the
noise frequency is less than 400 kHz.
DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)(4)(5)
Uni
ts
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
DS92LV0411 LVCMOS INPUT DC SPECIFICATIONS
VDDIO = 3.0 to 3.6V
2.2
VDDIO
VDDIO
0.8
V
V
V
V
VIH
High Level Input Voltage
0.65*
VDDIO
VDDIO = 1.71 to 1.89V
VDDIO = 3.0 to 3.6V
VDDIO = 1.71 to 1.89V
PDB,
GND
VODSEL,
MAPSEL,
CONFIG[1:0],
BISTEN
VIL
Low Level Input Voltage
0.35*
VDDIO
GND
VDDIO = 3.0
to 3.6V
−15
−15
±1
±1
+15
+15
μA
μA
IIN
Input Current
VIN = 0V or VDDIO
VDDIO = 1.7
to 1.89V
DS92LV0412 LVCMOS I/O DC SPECIFICATIONS
VDDIO = 3.0 to 3.6V
VDDIO = 1.71 to 1.89V
VDDIO = 3.0 to 3.6V
VDDIO = 1.71 to 1.89V
2.2
VDDIO
VDDIO
0.8
V
V
V
V
VIH
High Level Input Voltage
Low Level Input Voltage
0.7*
VDDIO
PDB,
VODSEL,
OEN,
MAPSEL,
LFMODE,
SSC[2:0],
BISTEN
GND
VIL
0.3*
VDDIO
GND
VDDIO = 3.0
to 3.6V
−15
−10
±1
±1
+15
+10
μA
μA
IIN
Input Current
VIN = 0V or VDDIO
VDDIO = 1.7
to 1.89V
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at VDD = 1.8V, VDDIO = 3.3V, Ta = +25 °C, and at the Recommended Operation
Conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(4) Specification is ensured by characterization and is not tested in production.
(5) Specification is ensured by design and is not tested in production.
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SNLS331B –MAY 2010–REVISED APRIL 2013
DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)(4)(5)
Uni
ts
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
VDDIO = 3.3V
IOH = -2 mA
VDDIO
0.25
–
–
VDDIO
VDDIO
VOH
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
V
V
VDDIO = 1.8V
IOH = -2 mA
VDDIO
0.2
VDDIO = 3.3 V or 1.8V
IOL = +0.5 mA
VOL
GND
0.2
VDDIO = 3.0
to 3.6 V
LOCK,
PASS
-45
-13
IOS
VOUT = 0V
mA
VDDIO = 1.71
to 1.89V
VDDIO = 3.0
to 3.6 V
-10
-15
+10
+15
PDB = 0V, OSS_SEL
= 0V, VOUT = 0V or
VDDIO
IOZ
Tri-State Output Current(6)
μA
VDDIO = 1.71
to 1.89V
DS92LV0411 CHANNEL LINK PARALLEL LVDS RECEIVER DC SPECIFICATIONS
Differential Threshold High
Voltage
VTH
+100
mV
Differential Threshold Low
Voltage
VCM = 1.2V, (See Figure 3)
VTL
|VID
−100
RxIN[3:0]+/-,
RxCLKIN+/-,
|
Differential Input Voltage Swing
Common Mode Voltage
Input Current
200
0
600
2.4
mV
V
VDDIO = 3.3V
VDDIO = 1.8V
1.2
1.2
±1
VCM
0
1.55
+15
IIN
−15
μA
DS92LV0412 CHANNEL LINK PARALLEL LVDS DRIVER DC SPECIFICATIONS
VODSEL = L
100
200
250
400
400
600
mV
mV
|VOD
|
Differential Output Voltage
VODSEL = H
mV
p-p
VODSEL = L
500
800
Differential Output Voltage A –
B
VODp-p
mV
p-p
VODSEL = H
RL = 100Ω
TxCLKOUT-,
TxOUT[3:0]+,
TxOUT[3:0]-
ΔVOD
Output Voltage Unbalance
Offset Voltage
4
1.2
1.2
1
50
mV
V
VODSEL = L
VODSEL = H
1.0
-10
1.5
VOS
V
ΔVOS
Offset Voltage Unbalance
Output Short Circuit Current
50
mV
mA
IOS
VOUT = GND
-5
OEN = GND,
VOUT = VDDTX, or GND
IOZ
Output Tri-State Current(6)
+10
μA
(6) When the device output is at Tri-State the Deserializer will lose PLL lock. Resynchronization / Relock must occur before data transfer
require tPLD
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DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)(4)(5)
Uni
ts
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
DS92LV0411 Channel Link II CML DRIVER DC SPECIFICATIONS
VODSEL = 0
VODSEL = 1
±225
±350
±300
±450
±375
±550
VOD
Differential Output Voltage
mV
RL = 100Ω,
De-emph = disabled,
(SeeFigure 5)
mV
p-p
VODSEL = 0
VODSEL = 1
600
900
1
Differential Output Voltage
(DOUT+) – (DOUT-)
VODp-p
mV
p-p
RL = 100Ω, De-emph = disabled,
ΔVOD
Output Voltage Unbalance
50
mV
VODSEL = L
DOUT+,
DOUT-
VODSEL = 0
VODSEL = 1
1.65
V
V
Offset Voltage – Single-ended
At TP A & B, (SeeFigure 4)
RL = 100Ω,
De-emph = disabled
VOS
1.575
Offset Voltage Unbalance
Single-ended
ΔVOS
RL = 100Ω, De-emph = disabled
1
mV
At TP A & B, (SeeFigure 4)
DOUT+/- = 0V,
De-emph = disabled
IOS
RT
Output Short Circuit Current
VODSEL = 0
−35
mA
Internal Termination Resistor
80
120
Ω
DS92LV0412 CHANNEL LINK II CML RECEIVER DC SPECIFICATIONS
Differential Input Threshold
High Voltage
VTH
VTL
VCM = +1.2V (Internal VBIAS
)
+50
mV
mV
Differential Input Threshold Low
Voltage
-50
RIN+,
RIN-
Common mode Voltage,
Internal VBIAS
VCM
RT
1.2
V
Input Termination
80
100
120
Ω
DS92LV0411 SUPPLY CURRENT
IDDT1
Checker Board
Pattern,
De-emph = 3 kΩ,
VODSEL = H, (See
Figure 18)
VDD= 1.89V
All VDD pins
VDDIO
80
3
90
5
mA
mA
VDDIO= 1.89V
IDDIOT1
VDDIO = 3.6V
10
13
mA
Supply Current
(includes load current)
RL = 100Ω, f = 50 MHz
IDDT2
Checker Board
Pattern,
De-emph = 6 kΩ,
VODSEL = L, (See
Figure 18)
VDD= 1.89V
All VDD pins
VDDIO
75
3
85
5
mA
mA
VDDIO= 1.89V
IDDIOT2
IDDZ
VDDIO = 3.6V
10
13
mA
VDD= 1.89V
VDDIO= 1.89V
VDDIO = 3.6V
All VDD pins
VDDIO
60
0.5
1
1000
10
µA
µA
µA
PDB = 0V , (All other
LVCMOS Inputs = 0V)
Supply Current Power-down
IDDIOZ
30
DS92LV0412 SUPPLY CURRENT
IDD1
Supply Current
(Includes load current)
50 MHz Clock
Checker Board
Pattern,
VODSEL = H,
SSCG [2:0] = 000
VDDn = 1.89
V
All VDD(1:8)
pins
85
40
95
50
mA
mA
mA
mA
IDDTX1
IDDIO1
VDDTX = 3.6
V
VDDTX
VDDIO = 1.89 VDDIO
V
0.3
0.8
0.8
1.5
VDDIO = 3.6 V
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DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)(4)(5)
Uni
ts
Symbol
IDD2
IDDTX2
IDDIO2
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Supply Current
(Includes load current)
50 MHz Clock
Checker Board
VDDn = 1.89
V
All VDD(1:8)
pins
95
mA
mA
mA
Pattern,
VODSEL = H,
SSCG [2:0] = 111
VDDTX = 3.6
V
VDDTX
40
VDDIO = 1.89 VDDIO
V
0.3
VDDIO = 3.6 V
0.8
mA
mA
IDDZ
Supply Current Power Down
PDB = 0V,
VDD = 1.89 V All VDD(1:8)
pins
0.15
2
All other LVCMOS
Inputs = 0V
IDDTXZ
IDDIOZ
VDDTX = 3.6
V
VDDTX
0.01
0.01
0.01
0.1
mA
mA
mA
VDDIO = 1.89 VDDIO
V
0.08
0.08
VDDIO = 3.6V
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DS92LV0411 CHANNEL LINK PARALLEL LVDS INPUT
tRSP0
tRSP1
tRSP2
tRSP3
tRSP4
tRSP5
tRSP6
Receiver Strobe Position-bit 0
Receiver Strobe Position-bit 1
Receiver Strobe Position-bit 2
Receiver Strobe Position-bit 3
Receiver Strobe Position-bit 4
Receiver Strobe Position-bit 5
Receiver Strobe Position-bit 6
0.66
2.86
1.10
3.30
1.54
3.74
ns
ns
ns
ns
ns
ns
ns
5.05
5.50
5.93
RxCLKIN = 50 MHz,
RxIN[3:0]
(See Figure 7)
7.25
7.70
8.13
9.45
9.90
10.33
12.53
14.73
11.65
13.85
12.10
14.30
DS92LV0412 CHANNEL LINK PARALLEL LVDS OUTPUT
tLHT
Low to High Transition Time
High to Low Transition Time
Cycle-to-Cycle Output Jitter(1)
RL = 100Ω
0.3
0.3
900
75
1
0.6
0.6
ns
ns
ps
ps
UI(2)
UI
tTHLT
tDCCJ
TxCLKOUT± = 5 MHz
TxCLKOUT± = 50 MHz
5 – 50 MHz
2100
125
tTTP1
tTTP0
tTTP6
tTTP5
tTTP4
tTTP3
tTTP2
ΔtTTP
Transmitter Pulse Position for bit 1
Transmitter Pulse Position for bit 0
Transmitter Pulse Position for bit 6
Transmitter Pulse Position for bit 5
Transmitter Pulse Position for bit 4
Transmitter Pulse Position for bit 3
Transmitter Pulse Position for bit 2
2
3
UI
4
UI
5
UI
6
UI
7
UI
Offset Transmitter Pulse Position (bit 50 MHz
6— bit 0)
<+0.1
UI
tDD
Delay-Latency
142*T
7
143*T
12
ns
ns
tTPDD
Power Down Delay
Active to OFF
50 MHz
50 MHz
tTXZR
Enable Delay
OFF to Active
40
55
ns
(1) tDCCJ is the maximum amount of jitter between adjacent clock cycles.
(2) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*PCLK). The UI scales with PCLK frequency.
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Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DS92LV0411 Channel Link II CML OUTPUT
tHLT
tHLT
tXZD
Output Low-to-High Transition Time
(See Figure 5)
RL = 100Ω, De-emphasis = disabled,
VODSEL = 0
200
200
260
200
5
ps
ps
ps
ps
ns
RL = 100Ω, De-emphasis = disabled,
VODSEL = 1
Output High-to-Low Transition Time
(See Figure 6)
RL = 100Ω, De-emphasis = disabled,
VODSEL = 0
RL = 100Ω, De-emphasis = disabled,
VODSEL = 1
Ouput Active to OFF Delay (See
Figure 11)
15
tPLD
tSD
PLL Lock Time(3), (See Figure 9)
Delay - Latency, (See Figure 12)
Output Total Jitter (See Figure 14)
RL = 100Ω
RL = 100Ω
1.5
10
ms
ns
147*T
148*T
tDJIT
RL = 100Ω, De-Emph = disabled,
RANDOM pattern,
0.26
UI
RxCLKIN = 43 and 50 MHz
λSTXBW Jitter Transfer
Function -3 dB Bandwidth
RxCLKIN = 43 MHz
RxCLKIN = 50 MHz
RxCLKIN = 43 MHz
RxCLKIN = 50 MHz
2.2
2.6
1
MHz
dB
δSTX
Jitter Transfer
Function Peaking
1
DS92LV0412 CHANNEL LINK II CML INPUT
tDDLT
Lock Time
SSCG[2:0] = 000,
5 MHz
7
14
6
ms
ms
ms
ms
UI
SSCG[2:0] = 111,
5 MHz
SSCG[2:0] = 000,
50 MHz
SSCG[2:0] = 111,
50 MHz
8
tIJIT
Input Jitter Tolerance
EQ = OFF
>0.9
SSCG[2:0] = 000
TxCLKOUT± = 50 MHz
Input Jitter Frequency < 2 MHz
EQ = OFF
>0.5
UI
SSCG[2:0] = 000
TxCLKOUT± = 50 MHz
Input Jitter Frequency >6 MHz
DS92LV0412 LVCMOS OUTPUTS
tCLH
tCHL
Low to High Transition Time
High to Low Transition Time
CL = 8 pF
LOCK pin,
PASS pin
5
5
15
15
ns
ns
tPASS
BIST PASS Valid Time,
BISTEN = 1
PASS pin
5 MHz
570
50
580
65
ns
ns
50 MHz
DS92LV0412 SSCG MODE
tDEV
Spread Spectrum Clocking Deviation TxCLKOUT = 5 – 50 MHz,
±0.5
8
±2
%
Frequency
SSC[2:0] = ON
tMOD
Spread Spectrum Clocking
Modulation Frequency
TxCLKOUT = 5 – 50 MHz,
SSC[2:0] = ON
100
kHz
(3) tPLD is the time required by the device to obtain lock when exiting power-down state with an active RxCLKIN.
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Recommended Timing for the Serial Control Bus
Over recommended operating supply and temperature ranges unless otherwise specified. (Figure 20)
Symbol
Parameter
Conditions
Min
>0
Typ
Max
100
400
Units
kHz
kHz
μs
fSCL
SCL Clock Frequency
Standard Mode
Fast Mode
>0
tLOW
SCL Low Period
SCL High Period
Standard Mode
Fast Mode
4.7
1.3
4.0
0.6
4.0
0.6
4.7
0.6
0
μs
tHIGH
Standard Mode
Fast Mode
μs
μs
tHD:STA Hold time for a start or a
repeated start condition
Standard Mode
Fast Mode
μs
μs
tSU:STA Set Up time for a start or a
repeated start condition
Standard Mode
Fast Mode
μs
μs
tHD:DAT Data Hold Time
3.45
0.9
μs
Fast Mode
0
μs
tSU:DAT Data Set Up Time
Standard Mode
Fast Mode
250
100
4.0
0.6
4.7
1.3
μs
μs
tSU:STO Set Up Time for STOP
Condition
Standard Mode
Fast Mode
μs
μs
tBUF
Bus Free Time Between STOP Standard Mode
μs
and START
Fast Mode
μs
tr
SCL & SDA Rise Time
SCL & SDA Fall Time
Standard Mode
Fast Mode
1000
300
300
300
ns
ns
tf
Standard Mode
Fast Mode
ns
ns
DC and AC Serial Control Bus Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Input High Level
Conditions
Min
Typ
Max
Units
VIH
SDA and SCL
VDDIO = 3.3V
0.7*
VDDIO
VDDIO
V
VIL
Input Low Level Voltage
Input Hysteresis
SDA and SCL
VDDIO = 3.3V
0.3*
VDDIO
GND
V
mV
V
VHY
VOL
VDDIO = 3.3V
>50
SDA, IOL = 3mA
VDDIO = 3.3V
0
0.36
+10
Iin
tR
tF
SDA or SCL, Vin = 3.3V or GND
-10
µA
ns
ns
ns
ns
ns
pF
SDA RiseTime – READ
SDA Fall Time – READ
SDA, RPU = X, Cb ≤ 400pF, (See Figure 20)
430
20
tSU;DAT Set Up Time – READ
tHD;DAT Hold Up Time – READ
See Figure 20
See Figure 20
560
615
50
tSP
Cin
Input Filter
Input Capacitance
SDA or SCL
<5
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AC Timing Diagrams and Test Circuits
RxIN[3:0]+
RxCLKIN+
VTL
VCM=1.2V
VTH
RxIN[3:0]-
RxClkIN-
GND
Figure 3. Channel Link DC VTH/VTL Definition
A
B
A'
C
Scope
A
B
50W
50W
C
B'
50W
50W
Figure 4. DS92LV0411 Output Test Circuit
DOUT+
VOD-
VOD+
DOUT-
GND
VOS
VOD+
(DOUT+) - (DOUT+
)
0V
VODp-p
VOD-
Figure 5. Channel Link II Single-ended and Differential Waveforms
+VOD
80%
(DOUT+) - (DOUT-)
0V
20%
-VOD
t
t
LHLT
LLHT
Figure 6. DS92LV0411 Output Transition Times
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Figure 7. DS92LV0411 LVDS Receiver Strobe Positions
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Cycle N
TxCLKOUT±
TxOUT[3:0]±
bit 1 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
t
t
t
TTP1
TTP2
TTP3
1UI
2UI
3UI
4UI
5UI
6UI
7UI
t
t
TTP4
TTP5
t
t
TTP6
TTP7
Figure 8. DS92LV0412 LVDS Transmitter Pulse Positions
PDB
VIH
MIN
RxCLKIN
"X"
active
t
PLD
DOUT
(Diff.)
Driver On
Driver OFF, V
= 0V
OD
Figure 9. DS92LV0411 Lock Time
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PDB
VIH(min)
R ±
IN
tDDLT
LOCK
VOH(min)
TRI-STATE
Figure 10. DS92LV0412 Lock Time
VIL
PDB
X
MA
RxCLKIN
active
"X"
t
XZD
DOUT
(Diff.)
active
Driver OFF, V
= 0V
OD
Figure 11. DS92LV0411 Disable Time
RxIN[3:0]
RxCLKIN
N-1
N
N+1
N+2
t
SD
STOP START
BIT BIT
STOP START
BIT BIT
STOP START
STOP START
STOP
BIT
BIT BIT
BIT BIT
SYMBOL N-4
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
D
0-23
OUT
DCA, DCB
Figure 12. DS92LV0411 Latency Delay
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START
BIT
STOP
BIT
START
BIT
STOP
BIT
START
BIT
STOP
BIT
START STOP
BIT BIT
SYMBOLN+3
SYMBOLN
SYMBOLN+1
SYMBOLN+2
R
IN
+/-
t
RD
TxCLKOUT
TxOUT[3:0]
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
Figure 13. DS92LV0412 Latency Delay
t
t
DJIT
DJIT
VOD (+)
DOUT
(Diff.)
TxOUT_E_O
0V
VOD (-)
t
(1 UI)
BIT
Figure 14. DS92LV0411 Output Jitter
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PDB
RIN
(Diff.)
active serial stream
X
H
H
LOCK
TxOUT[3:0]
TxCLKOUT
L
L
L
Z
Z
Z
Z
Z
Z
f
f
Z
Z
PASS
OFF
Active
OSC Output
Active
OFF
OSC Output
CONDITIONS: OEN = H, OSS_SEL = H, and OSC_SEL not equal to 000.
Figure 15. DS92LV0412 Output State Diagram
PDB
RIN
VILmax
X
t
TPDD
LOCK
PASS
Z
Z
TxCLKOUT
TxOUT[3:0]
Z
Z
Figure 16. DS92LV0412 Power Down Delay
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PDB
LOCK
t
TXZR
OEN
VIHmin
Z
Z
TxCLKOUT
TxOUT[3:0]
Figure 17. DS92LV0412 Enable Delay
+V
OD
RxCLKIN
-V
OD
+V
OD
RxIN[odd]
-V
OD
+V
OD
RxIN[even]
-V
OD
Cycle N
Cycle N+1
Figure 18. Checkerboard Data Pattern
VIL
BISTEN
MAX
t
PASS
VOL
PASS
(w/ errors)
MAX
Prior BIST Result
Current BIST Test - Toggle on Error
Result Held
Figure 19. BIST PASS Waveform
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SDA
t
BUF
t
f
t
HD;STA
t
t
r
LOW
t
t
SP
t
f
r
SCL
t
t
SU;STA
t
SU;STO
HD;STA
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
START
REPEATED
START
Figure 20. Serial Control Bus Timing Diagram
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FUNCTIONAL DESCRIPTION
The DS92LV0411 / DS92LV0412 chipset transmits and receives 24-bits of data and 3 control signals, formatted
as Channel Link LVDS data, over a single serial CML pair operating at 140 Mbps to 1.4 Gbps serial line rate.
The serial stream contains an embedded clock, video control signals and is DC-balance to enhance signal
quality and supports AC coupling.
The Des can attain lock to a data stream without the use of a separate reference clock source, which simplifies
system complexity and overall cost. The Des also synchronizes to the Ser regardless of the data pattern,
delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without the need
of special training patterns or sync characters. The Des recovers the clock and data by extracting the embedded
clock information, validating and then deserializing the incoming data stream providing a parallel Channel Link
LVDS bus to the display, ASIC, or FPGA.
The DS92LV0411 / DS92LV0412 chipset can operate with up to 24 bits of raw data with three slower speed
control bits encoded within the serial data stream. For applications that require less the maximum 24 pclk speed
bit spaces, the user will need to ensure that all unused bit spaces or parallel LVDS channels are set to valid logic
states, as all parallel lanes and 27 bit spaces will always be sampled.
Block Diagrams for the chipset are shown at the beginning of this datasheet.
PARALLEL LVDS DATA TRANSFER
The DS92LV0411/DS92LV0412 can be configured to accept/transmit 24-bit data with 2 different mapping
schemes: The normal Channel Link LVDS format (MSBs on LVDS channel 3) can be selected by configuring the
MAPSEL pin to HIGH. See Figure 15 for the normal Channel Link LVDS mapping. An alternate mapping scheme
is available (LSBs on LVDS channel 3) by configuring the MAPSEL pin to LOW. See Figure 16 for the alternate
LVDS mapping. The mapping schemes can also be selected by register control.
The alternate mapping scheme is useful in some applications where the receiving system, typically a display,
requires that the LSBs for the 24-bit color data be sent on LVDS channel 3.
SERIAL DATA TRANSFER
The DS92LV0411 transmits a 24–bit word of data in the following format: C1 and C0 represent the embedded
clock in the serial stream. C1 is always HIGH and C0 is always LOW. b[23:0] contain the scrambled RGB data,
plus two additional bits for encoding overhead. The control signals (VS,HS,DE) are also encoded within these
two additional bits. This coding scheme is generated by the DS92LV0411 and decoded by the paring
deserializer, such as the DS92LV0412, automatically.
The DS92LV0412 receives a 24 bit word of data in the format as described above. It also synchronizes to the
serializer regardless of the data pattern, delivering true automatic “plug and lock” performance. it can lock to the
incoming serial stream without the need for special training patterns or sync characters. The DS92LV0412
recovers the clock and data by extracting the embedded clock information, validating and then deserializing the
incoming data stream.
Figure 21 illustrates the serial stream per PCLK cycle.
C
1
C
0
Figure 21. Channel Link II Serial Stream
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SNLS331B –MAY 2010–REVISED APRIL 2013
OPERATING MODES AND BACKWARD COMPATIBILITY (CONFIG[1:0])
The DS92LV0411 and DS92LV0412 are backward compatible with previous generations of Ser/Des.
Configuration modes are provided for backwards compatibility with the DS90C241/DS90C124 and also the
DS90UR241/DS90UR124 and DS99R241/DS99R124 by setting the respective mode with the CONFIG[1:0] pins
as shown in Table 2 and Table 3. The selection also determine whether the Video Control Signal filter feature is
enabled or disabled in Normal mode. Backward compatibility modes are selectable through the control pins only.
The Control Signal Filter can be selected by pin or through register programming.
Table 2. DS92LV0411 Configuration Modes
CON
FIG1
CON
FIG0
Mode
Des Device
L
L
H
L
Normal Mode, Control Signal Filter disabled
Normal Mode, Control Signal Filter enabled
Backwards Compatible
DS92LV0412,
DS92LV2412
L
DS92LV0412,
DS92LV2412
H
H
DS90UR124,
DS99R124
H
Backwards Compatible
DS90C124
Table 3. DS92LV0412 Configuration Modes
CON
FIG1
CON
FIG0
Mode
Des Device
L
L
H
L
Normal Mode, Control Signal Filter disabled
Normal Mode, Control Signal Filter enabled
Backwards Compatible
DS92LV0411,
DS92LV2411
L
DS92LV0411,
DS92LV2411
H
H
DS90UR241,
DS99R421
H
Backwards Compatible
DS90C241
BIT MAPPING SELECT
The DS92LV0411 and DS92LV0412 can be configured to accept the LVDS parallel data with 2 different mapping
schemes: LSBs on RxIN[3] shown in Figure 22 or MSBs on RxIN[3] shown in Figure 23. The user selects which
mapping scheme is controlled by MAPSEL pin or by Register.
NOTE
While the LVDS interface has 28 bits defined, only 27 bits are recovered by the Ser and
sent to the Des. This supports 24 bit RGB plus the three video control signals. The 28th
bit is not sampled, sent or recovered.
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RxCLKIN +/-
Previous cycle
Current cycle
R[1]
(bit 22)
R[0]
(bit 21)
B[1]
(bit 26)
B[0]
(bit 25)
G[1]
(bit 24)
G[0]
(bit 23)
RxIN3 +/-
DE
VS
HS
B[7]
B[6]
B[5]
B[4]
RxIN2 +/-
RxIN1 +/-
(bit 20)
(bit 19)
(bit 18)
(bit 17)
(bit 16)
(bit 15)
(bit 14)
B[3]
(bit 13)
B[2]
(bit 12)
G[7]
(bit 11)
G[6]
(bit 10)
G[5]
(bit 9)
G[4]
(bit 8)
G[3]
(bit 7)
G[2]
(bit 6)
R[7]
(bit 5)
R[6]
(bit 4)
R[5]
(bit 3)
R[4]
(bit 2)
R[3]
(bit 1)
R[2]
(bit 0)
RxIN0 +/-
Figure 22. 8–bit Channel Link Mapping: LSB's on RxIN3
RxCLKIN +/-
Previous cycle
Current cycle
R[7]
(bit 22)
R[6]
(bit 21)
B[6]
(bit 25)
G[7]
(bit 24)
G[6]
(bit 23)
B[7]
(bit 26)
RxIN3 +/-
RxIN2 +/-
DE
(bit 20)
VS
(bit 19)
HS
(bit 18)
B[5]
(bit 17)
B[4]
(bit 16)
B[3]
(bit 15)
B[2]
(bit 14)
G[3]
(bit 9)
G[2]
(bit 8)
G[1]
(bit 7)
B[1]
(bit 13)
B[0]
(bit 12)
G[5]
(bit 11)
G[4]
(bit 10)
RxIN1 +/-
RxIN0 +/-
G[0]
(bit 6)
R[5]
(bit 5)
R[4]
(bit 4)
R[3]
(bit 3)
R[2]
(bit 2)
R[1]
(bit 1)
R[0]
(bit 0)
Figure 23. 8–bit Channel Link Mapping: MSB's on RxIN3
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VIDEO CONTROL SIGNAL FILTER
The three control bits can be used to communicate any low speed signal. The most common use for these bits is
in the display or machine vision applications. In a display application these bits are typically assigned as: Bit 26 –
DE, Bit 24 – HS, Bit 25 – VS. In the machine vision standard, Camera Link, these bits are typically assigned: Bit
26 – DVAL, Bit 24 – LVAL, Bit 25 – FVAL.
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
•
•
•
Normal Mode with Control Signal Filter Enabled:
–
DE and HS — Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3
PCLK or longer.
Normal Mode with Control Signal Filter Disabled:
–
DE and HS — Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition
pulse.
VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency
noise on the control signals. See Figure 24.
PCLK
IN
HS/VS/DE
IN
Latency
PCLK
OUT
Pulses 1 or 2
PCLKs wide
Filetered OUT
HS/VS/DE
OUT
Figure 24. Video Control Signal Filter Wavefrom
SERIALIZER FUNCTIONAL DESCRIPTION
The Ser converts a Channel Link LVDS clock and data bus (4 LVDS data channels + 1 LVDS clock) to a single
serial output data stream, and also acts as a signal generator for the chipset Built In Self Test (BIST) mode. The
device can be configured via external pins or through the optional serial control bus. The Ser features enhanced
signal quality on the link by supporting: a selectable VOD level, a selectable de-emphasis signal conditioning and
also the Channel Link II data coding that provides randomization, scrambling, and DC Balanacing of the data.
The Ser includes multiple features to reduce EMI associated with display data transmission. This includes the
randomization and scrambling of the serial data and also the system spread spectrum clock support. The Ser
features power saving features with a sleep mode, auto stop clock feature, and optional 1.8 V or 3.3V I/O
compatibility.
See also the Functional Description of the chipset's serial control bus and BIST modes.
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EMI REDUCTION FEATURES
Data Randomization & Scrambling
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Channel Link II Ser / Des feature a 3 step encoding process which enables the use of AC coupled interconnects
and also helps to manage EMI. The serializer first passes the parallel data through a scrambler which
randomizes the data. The randomized data is then DC balanced. The DC balanced and randomized data then
goes through a bit shuffling circuit and is transmitted out on the serial line. This encoding process helps to
prevent static data patterns on the serial stream. The resulting frequency content of the serial stream ranges
from the parallel clock frequency to the nyquist rate. For example, if the Ser / Des chip set is operating at a
parallel clock frequency of 50 MHz, the resulting frequency content of serial stream ranges from 50 MHz to 700
MHz ( 50 MHz *28 bits = 1.4 Gbps / 2 = 700 MHz ).
Ser — Spread Spectrum Compatibility
The RxCLKIN of the Channel Link input is capable of tracking spread spectrum clocking (SSC) from a host
source. The RxCLKIN will accept spread spectrum tracking up to 35kHz modulation and ±0.5, ±1 or ±2%
deviations (center spread). The maximum conditions for the RxCLKIN input are: a modulation frequency of
35kHz and amplitude deviations of ±2% (4% total).
SER — INTEGRATED SIGNAL CONDITIONING FEATURES
Ser — VOD Select (VODSEL)
The DS92LV0411 differential output voltage may be increased by setting the VODSEL pin High. When VODSEL
is Low, the DC VOD is at the standard (default) level. When VODSEL is High, the DC VOD is increased in level.
The increased VOD is useful in extremely high noise environments and also on extra long cable length
applications. When using de-emphasis it is recommended to set VODSEL = H to avoid excessive signal
attenuation especially with the larger de-emphasis settings. This feature may be controlled by the external pin or
by register.
Table 4. Ser — Differential Output Voltage
Input
Effect
VOD
mV
VOD
mVp-p
VODSEL
H
L
±450
±300
900
600
Ser — De-Emphasis (De-Emph)
The De-Emph pin controls the amount of de-emphasis beginning one full bit time after a logic transition that the
device drives. This is useful to counteract loading effects of long or lossy cables. This pin should be left open for
standard switching currents (no de-emphasis) or if controlled by register. De-emphasis is selected by connecting
a resistor on this pin to ground, with R value between 0.5 kΩ to 1 MΩ, or by register setting. When using De-
Emphasis it is recommended to set VODSEL = H.
Table 5. De-Emphasis Resistor Value
Resistor Value (kΩ)
De-Emphasis Setting
Disabled
- 12 dB
Open
0.6
1.0
- 9 dB
2.0
- 6 dB
5.0
- 3 dB
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0.00
VDD = 1.8V,
= 25oC
T
A
-2.00
-4.00
-6.00
-8.00
-10.00
-12.00
-14.00
1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06
R VALUE - LOG SCALE (W)
Figure 25. De-Emph vs. R value
POWER SAVING FEATURES
Ser — Power Down Feature (PDB)
The DS92LV0411 has a PDB input pin to ENABLE or POWER DOWN the device. This pin is controlled by the
host and is used to save power, disabling the link when the display is not needed. In the POWER DOWN mode,
the high-speed driver outputs are both pulled to VDD and present a 0V VOD state. Note – in POWER DOWN,
the optional Serial Bus Control Registers are RESET.
Ser — Stop Clock Feature
The DS92LV0411 will enter a low power SLEEP state when the RxCLKIN is stopped. A STOP condition is
detected when the input clock frequency is less than 3 MHz. The clock should be held at a static Low or high
state. When the RxCLKIN starts again, the device will then lock to the valid input RxCLKIN and then transmits
the RGB data to the desializer. Note – in STOP CLOCK SLEEP, the optional Serial Bus Control Registers values
are RETAINED.
1.8V or 3.3V VDDIO Operation
The DS92LV0411 parallel control pin bus can operate with 1.8 V or 3.3 V levels (VDDIO) for host compatibility.
The 1.8 V levels will offer a system power savings.
OPTIONAL SERIAL BUS CONTROL
Please see the following section on the Optional Serial Bus Control Interface.
OPTIONAL BIST MODE
Please see the following section on the chipset BIST Mode for details.
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Deserializer Functional Description
The Des converts a single input serial data stream to a wide parallel output bus, and also provides a signal
check for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins and strap
pins or through the optional serial control bus. The Des features enhance signal quality on the link with an
integrated equalizer on the serial input and Channel Link II data encoding which provides randomization,
scrambling, and DC balanacing of the data. The Des includes multiple features to reduce EMI associated with
data transmission. This includes the randomization and scrambling of the data, the output spread spectrum clock
generation (SSCG) support. The Des features power saving features with a power down mode, and optional
LVCMOS (1.8 V) interface compatibility.
OSCILLATOR OUTPUT — OPTIONAL
The DS92LV0412 provides an optional TxCLKOUT when the input clock (serial stream) has been lost. This is
based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled
by the external pin or through the registers.
Clock-DATA RECOVERY STATUS FLAG (LOCK), OUTPUT ENABLE (OEN) and OUTPUT STATE SELECT
(OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input, LOCK is LOW and the Channel Link
interface state is determined by the state of the OSS_SEL pin.
After the DS92LV0412 completes its lock sequence to the input serial data, the LOCK output is driven HIGH,
indicating valid data and clock recovered from the serial input is available on the Channel Link outputs. The
TxCLKOUT output is held at its current state at the change from OSC_CLK (if this is enabled via OSC_SEL) to
the recovered clock (or vice versa). Note that the Channel Link outputs may be held in an inactive state (Tri-
State®) through the use of the Output Enable pin (OEN).
If there is a loss of clock from the input serial stream, LOCK is driven LOW and the state of the outputs are
based on the OSS_SEL setting (configuration pin or register).
Table 6. Des Output State Table
INPUTS
PDB
L
OUTPUTS
LOCK
X
OEN
OSS_SEL
OTHER OUTPUTS
X
X
TxCLKOUT is Tri-State
TxOUT[3:0] are Tri-State
PASS is Tri-State
L
X
L
L
L
TxCLKOUT is Tri-State
TxOUT[3:0] are Tri-State
PASS is HIGH
H
H
H
H
H
H
X
X
L
TxCLKOUT is Tri-State
TxOUT[3:0] are Tri-State
PASS is Tri-State
H
L
L
TxCLKOUT is Tri-State or OSC Output through Register bit
TxOUT[3:0] are Tri-State
PASS is Tri-State
H
H
TxCLKOUT is Tri-State
TxOUT[3:0] are Tri-State
PASS is HIGH
H
TxCLKOUT is Active
TxOUT[3:0] are Active
PASS is Active
(Normal operating mode)
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DES — INTEGRATED SIGNAL CONDITIONING FEATURES — DES
Des — Common Mode Filter Pin (CMF) — Optional
The Des provides access to the center tap of the internal termination. A capacitor may be placed on this pin for
additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 0.1μF capacitor may be connected to this pin to Ground.
Des — Input Equalizer Gain (EQ)
The Des can enable receiver input equalization of the serial stream to increase the eye opening to the Des input.
Note this function cannot be seen at the RxIN+/- input. The equalization feature may be controlled by the
external pin or by register.
Table 7. Receiver Equalization Configuration Table
EQ (Strap Option)
Effect
L
~1.5 dB
~13 dB
H
EMI REDUCTION FEATURES
Des — VOD Select (VODSEL)
The differential output voltage of the Channel Link interface is controlled by the VODSEL input.
Table 8. Des — Differential Output Voltage Table
VODSEL
Result
L
VOD is 250 mV TYP (500 mVp-p)
VOD is 400 mV TYP (800 mVp-p)
H
Des — SSCG Generation — Optional
The Des provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and
data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2% (4% total) at up
to 100 kHz modulations is available. See Switching Characteristics Table. This feature may be controlled by
external STRAP pins or by register. The LFMODE setting should be set appropriately if the SSCG is being used.
Set LFMODE HIGH if the clock frequency is between 5 MHz and 20 MHz. Set LFMODE LOW if teh clock
frequency is between 20 MHz and 50 MHz.
Table 9. SSCG Configuration (LF_MODE = L) — Des Output
SSC[2:0] Inputs
Result
LF_MODE = L (20 — 55 MHz)
SSC2
SSC1
SSC0
fdev (%)
OFF
±0.9
fmod (kHz)
OFF
L
L
L
L
L
H
L
CLK/2168
L
H
H
L
±1.2
L
H
L
±1.9
H
H
H
H
±2.3
L
H
L
±0.7
CLK/1300
H
H
±1.3
H
±1.7
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Table 10. SSCG Configuration (LF_MODE = H) — Des Output
SSC[2:0] Inputs
LF_MODE = H (5 — 20
MHz)
Result
SSC2
SSC1
SSC0
fdev (%)
OFF
±0.7
fmod (kHz)
OFF
L
L
L
L
L
H
L
CLK/625
L
H
H
L
±1.3
L
H
L
±1.8
H
H
H
H
±2.2
L
H
L
±0.7
CLK/385
H
H
±1.2
H
±1.7
Frequency
fdev(max)
F
F
PCLK+
F
PCLK
fdev(min)
Time
PCLK-
1/fmod
Figure 26. SSCG Waveform
Power Saving Features
Des — Power Down Feature (PDB)
The DS92LV0412 has a PDB input pin to ENABLE or POWER DOWN the device. This pin is controlled by the
host and is used to save power, disabling the Des when the display is not needed. An auto detect mode is also
available. In this mode, the PDB pin is tied HIGH and the Des will enter POWER DOWN when the serial stream
stops. When the serial stream starts up again, the Des will lock to the input stream and assert the LOCK pin and
output valid data. In the POWER DOWN mode, the LVDS data and clock output states are determined by the
OSS_SEL status. Note – in POWER DOWN, the optional Serial Bus Control Registers are RESET.
Des — Stop Stream SLEEPFeature
The DS92LV0412 will enter a low power SLEEP state when the input serial stream is stopped. A STOP condition
is detected when the embedded clock bits are not present. When the serial stream starts again, the Des will then
lock to the incoming signal and recover the data. Note – in STOP CLOCK SLEEP, the optional Serial Bus
Control Registers values are RETAINED.
1.8V or 3.3V VDDIO Operation
The DS92LV0412 parallel control bus can operate with 1.8 V or 3.3 V levels (VDDIO) for host compatibility. The
1.8 V levels will offer a system power savings.
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Built In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is
useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST
mode only a input clock is required along with control to the Ser and Des BISTEN input pins. The Ser outputs a
test pattern (PRBS7) and drives the link at speed. The Des detects the PRBS7 pattern and monitors it for errors.
A PASS output pin toggles to flag any payloads that are received with 1 to 24 errors. Upon completion of the
test, the result of the test is held on the PASS output until reset (new BIST test or Power Down). A high on PASS
indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration
of the test is controlled by the pulse width applied to the Des BISTEN pin.
Inter-operability is supported between this Channel Link II device and all reverse compatible devices— see
respective datasheets for details on entering BIST mode and control.
Sample BIST Sequence
See Figure 27 for the BIST mode flow diagram.
Step 1: Place the serializer in BIST Mode by setting Ser BISTEN = H. The BIST Mode is enabled via the
BISTEN pin. An RxCLKIN is required for all the Ser options. When the deserializer detects the BIST mode
pattern and command the parallel data and control signal outputs are shut off.
Step 2: Place the deserializer in BIST mode by setting the BISTEN = H. The Des is now in the BIST mode and
checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS pin will
switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted
to determine the payload error rate.
Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the
data and the final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If
there was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new
BIST is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the
BISTEN signal.
Step 4: To return the link to normal operation, the ser and des BISTEN input are set Low. The Link returns to
normal operation.
Figure 28 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2
shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link
(differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting
the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or deserializer Equalization).
Normal
Step 1: SER in BIST
BIST
Wait
Step 2: Wait, DES in BIST
BIST
Start
Step 3: DES in Normal
Mode - check PASS
BIST
Stop
Step 4: SER in Normal
Figure 27. BIST Mode Flow Diagram
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BER Calculations
It is possible to calculate the approximate Bit Error Rate (BER). The following is required:
•
•
•
Pixel Clock Frequency (MHz)
BIST Duration (seconds)
BIST test Result (PASS)
The BER is less than or equal to one over the product of 24 times the RxCLKIN rate times the test duration. If we
assume a 65MHz RxCLKIN, a 10 minute (600 second) test, and a PASS, the BERT is ≤ 1.07 X 10E-12
The BIST mode runs a check on the data payload bits. The LOCK pin also provides a link status. It the recovery
of the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK pin will switch Low. The
combination of the LOCK and At-Speed BIST PASS pin provides a powerful tool for system evaluation and
performance monitoring.
BISTEN
(DS90UR907Q)
BISTEN
(Deserializer)
TxCLKOUT
(Diff.)
TxOUT[3:0]
(Diff.)
DATA
(internal)
PASS
Prior Result
Prior Result
PASS
FAIL
X = bit error(s)
DATA
(internal)
X
X
X
PASS
BIST
Result
Held
Normal
PRBS
Normal
BIST Test
BIST Duration
Figure 28. BIST Waveforms
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Optional Serial Bus Control
The DS92LV0411 and DS92LV0412 may be configured by the use of a serial control bus that is I2C protocol
compatible. By default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap pins. A write
of 01'h to reg_0x00'h will enable/allow configuration by registers; this will override the control/strap pins. Multiple
devices may share the serial control bus since multiple addresses are supported. See Figure 29.
The serial bus is comprised of three pins. The SCL is a Serial Bus Clock Input. The SDA is the Serial Bus Data
Input / Output signal. Both SCL and SDA signals require an external pull up resistor to VDDIO. For most
applications a 4.7 kΩ pull up resistor to 3.3V may be used. The resistor value may be adjusted for capacitive
loading and data rate requirements. The signals are either pulled High, or driven Low.
1.8V
10k
3.3V
ID[X]
4.7k
4.7k
R
ID
DS92LV0411/
DS92LV0412
SCL
HOST
SCL
SDA
SDA
To other
Devices
Figure 29. Serial Control Bus Connection
The third pin is the ID[X] pin. This pin sets one of four possible device addresses. Three different connections are
possible. The pin may be pulled to VDD (1.8V, NOT VDDIO)) with a 10 kΩ resistor. Or a 10 kΩ pull up resistor (to
VDD1.8V, NOT VDDIO)) and a pull down resistor of the recommended value to set other three possible addresses
may be used. See Table 11.
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See
Figure 30.
SDA
SCL
S
P
START condition, or
STOP condition
START repeat condition
Figure 30. START and STOP Conditions
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To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 31 and a WRITE is shown in Figure 32.
If the Serial Bus is not required, the three pins may be left open (NC).
Table 11. ID[x] Resistor Value – DS92LV0411
Resistor
RID kΩ
Address
7'b
Address
8'b
0 appended
(WRITE)
0.47
2.7
7b' 110 1001 (h'69)
7b' 110 1010 (h'6A)
7b' 110 1011 (h'6B)
7b' 110 1110 (h'6E)
8b' 1101 0010 (h'D2)
8b' 1101 0100 (h'D4)
8b' 1101 0110 (h'D6)
8b' 1101 1100 (h'DC)
8.2
Open
Table 12. ID[x] Resistor Value – DS92LV0412
Resistor
RID kΩ
Address
7'b
Address
8'b
0 appended
(WRITE)
0.47
2.7
7b' 111 0001 (h'71)
7b' 111 0010 (h'72)
7b' 111 0011 (h'73)
7b' 111 0110 (h'76)
8b' 1110 0010 (h'E2)
8b' 1110 0100 (h'E4)
8b' 1110 0110 (h'E6)
8b' 1110 1100 (h'EC)
8.2
Open
Register Address
Slave Address
Slave Address
Data
a
c
k
a
c
k
a
c
k
a
c
k
A
2
A
1
A
0
A
2
A
1
A
0
0
S
S
1
P
Figure 31. Serial Control Bus — READ
Register Address
Slave Address
Data
a
c
a
c
k
a
c
k
A
2
A
1
A
0
0
S
P
k
Figure 32. Serial Control Bus — WRITE
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Table 13. DS92LV0411 SERIALIZER — Serial Bus Control Registers
ADD ADD Register Name
(dec) (hex)
Bit(s)
R/W Defau Function
Description
lt
(bin)
0
0
Ser Config 1
7
6
R/W
R/W
0
0
Reserved
Reserved
MAPSEL
0: LSB on RxIN3
1: MSB on RxIN3
5
R/W
R/W
0
VODSEL
0: Low
1: High
4
0
Reserved
Reserved
3:2
00
CONFIG
00: Control Signal Filter Disabled
01: Control Signal Filter Enabled
10: Reserved
11: Reserved
1
R/W
0
SLEEP
Note – not the same function as PowerDown (PDB)
0: normal mode
1: Sleep Mode – Register settings retained.
0
7
R/W
R/W
0
0
REG
0: Configurations set from control pins
1: Configuration set from registers (except I2C_ID)
1
2
1
2
Device ID
REG ID
0: Address from ID[X] Pin
1: Address from Register
6:0
R/W 11010 ID[X]
00
Serial Bus Device ID, IDs are:
7b '1101 001 (h'69)
7b '1101 010 (h'6A)
7b '1101 011 (h'6B)
7b '1101 110 (h'6E)
All other addresses are Reserved.
De-Emphasis
Control
7:5
R/W
000 De-E Setting
000: set by external Resistor
001: -1 dB
010: -2 dB
011: -3.3 dB
100: -5 dB
101: -6.7 dB
110: -9 dB
111: -12 dB
4
R/W
R/W
0
De-E EN
0: De-Emphasis Enabled
1: De-Emphasis Disabled
3:0
000 Reserved
Reserved
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Table 14. DS92LV0412 DESERIALIZER — Serial Bus Control Registers
ADD ADD Register Name
(dec) (hex)
Bit(s)
R/W Defau Function
Description
lt
(bin)
0
0
Des Config 1
7
6
R/W
R/W
0
LFMODE
MAPSEL
SSCG Mode — low frequency support
0: 20 to 65 MHz Operation
1: 10 to 20 MHz Operation
0
Channel Link Map Select
0: LSB on TxOUT3+/-
1: MSB on TxOUT3+/-
5
4
R/W
R/W
R/W
0
0
Reserved
Reserved
CONFIG
Reserved
Reserved
3:2
00
00: Control Signal Filter Disabled
01: Control Signal Filter Enabled
10: Reserved
11: Reserved
1
R/W
0
SLEEP
Note – not the same function as PowerDown (PDB)
0: normal mode
1: Sleep Mode – Register settings retained.
0
7
R/W
R/W
0
0
REG Control
REG ID
0: Configurations set from control pins
1: Configuration set from registers (except I2C_ID)
1
2
1
2
Device ID
0: Address from ID[X] Pin
1: Address from Register
6:0
R/W 11100 ID[X]
00
Serial Bus Device ID, IDs are:
7b' 111 0001 (h'71)
7b' 111 0010 (h'72)
7b' 111 0011 (h'73)
7b' 111 0110 (h'76)
All other addresses are Reserved.
Des Features 1
7
6
R/W
R/W
0
0
OEN
Output Enable Input
(See Table 6)
OSS_SEL
Output Sleep State Select
(See Table 6)
5:4
3
R/W
R/W
00
0
Reserved
Reserved
VODSEL
LVDS Driver Output Voltage Select
0: LVDS VOD is ±250 mV, 500 mVp-p (typ)
1: LVDS VOD is ±400 mV, 800 mVp-p (typ)
2:0
R/W
000 OSC_SEL
000: OFF
001:RESERVED
010: 25 MHz ±40%
011: 16.7 MHz ±40%
100: 12.5 MHz ±40%
101: 10 MHz ±40%
110: 8.3 MHz ±40%
111: 6.3MHz ±40%
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Table 14. DS92LV0412 DESERIALIZER — Serial Bus Control Registers (continued)
ADD ADD Register Name
(dec) (hex)
Bit(s)
R/W Defau Function
Description
lt
(bin)
3
3
Des Features 2
7:5
R/W
000 EQ Gain
000: ~1.625 dB
001: ~3.25 dB
010: ~4.87 dB
011: ~6.5 dB
100: ~8.125 dB
101: ~9.75 dB
110: 11.375 dB
111: 13 dB
4
R/W
0
0
EQ Enable
0: EQ = disabled
1: EQ = enabled
3
R/W
R/W
Reserved
Reserved
2:0
000 SSC
IF LFMODE = 0 then:
000: SSCG OFF
001: fdev = ±0.9%, fmod = CLK/2168
010: fdev = ±1.2%, fmod = CLK/2168
011: fdev = ±1.9%, fmod = CLK/2168
100: fdev = ±2.3%, fmod = CLK/2168
101: fdev = ±0.7%, fmod = CLK/21300
110: fdev = ±1.3%, fmod = CLK/1300
111: fdev = ±1.57%, fmod = CLK/1300
IF LFMODE = 1, then:
001: fdev = ±0.7%, fmod = CLK/625
010: fdev = ±1.3%, fmod = CLK/625
011: fdev = ±1.8%, fmod = CLK/625
100: fdev = ±2.2%, fmod = CLK/625
101: fdev = ±0.7%, fmod = CLK/385
110: fdev = ±1.2%, fmod = CLK/385
111: fdev = ±1.7%, fmod = CLK/385
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APPLICATIONS INFORMATION
DISPLAY APPLICATION
The DS92LV0411 and DS92LV0412 chipset is intended for interface between a host (graphics processor) and a
Display. It supports an 24-bit color depth (RGB888) and up to 1024 X 768 display formats. In a RGB888
application, 24 color bits (R[7:0], G[7:0], B[7:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are
supported across the serial link with PCLK rates from 5 to 50 MHz. The chipset may also be used in 18-bit color
applications. In this application three to six general purpose signals may also be sent from host to display.
DS92LV0411 TYPICAL APPLICATION CONNECTION
Figure 33 shows a typical application of the DS92LV0411 for a 50 MHz 24-bit Color Display Application. The
LVDS inputs require external 100 ohm differential termination resistors. The CML outputs require 0.1 μF AC
coupling capacitors to the line. The line driver includes internal termination. Bypass capacitors are placed near
the power supply pins. At a minimum, four 0.1 µF capacitors and a 4.7 µF capacitor should be used for local
device bypassing. System GPO (General Purpose Output) signals control the PDB and BISTEN pins. The
application assumes the companion deserializer (DS92LV0412) therefore the configuration pins are also both
tied Low. In this example the cable is long, therefore the VODSEL pin is tied High and a De-Emphasis value is
selected by the resistor R1. The interface to the host is with 1.8 V LVCMOS levels, thus the VDDIO pin is
connected also to the 1.8V rail. The Optional Serial Bus Control is not used in this example, thus the SCL, SDA
and ID[x] pins are left open. A delay cap is placed on the PDB signal to delay the enabling of the device until
power is stable. Bypass capacitors are placed near the power supply pins. Ferrite beads are placed on the power
lines for effective noise suppression.
DS92LV0411
1.8V
VDDIO
VDDIO
VDDTX
VDDHS
C10 C8
C9
C11
FB1
C3
C4
FB2
VDDP
VDDL
C12
C5
C6
FB3
FB4
RxCLKIN-
RxCLKIN+
RxIN3-
RxIN3+
VDDRX
Channel Link
Interface
RxIN2-
RxIN2+
C7
FB5
LVDS
100W Terminations
DOUT+
DOUT-
RxIN1-
RxIN1+
RxIN0-
RxIN0+
C1
C2
Serial
Channel Link II
Interface
1.8V
10k
RID
ID[X]
SCL
SDA
VDDIO
VODSEL
De-Emph
R1
Host
Control
BISTEN
PDB
NOTE:
R
C1-C2 = 0.1 mF (50 WV)
C3-C9 = 0.1 mF
C10-C12 = 4.7 mF
C13 = >10 mF
RES7
RES6
RES5
RES4
RES3
RES2
C13
CONFIG1
CONFIG0
MAPSEL
R = 10 kW
R1 (cable insertion loss specific)
RID (see ID[x] Resistor Value Table)
FB1-FB5: Impedance = 1 kW,
low DC resistance (<1W)
RES1
RES0
DAP (GND)
Figure 33. DS92LV0411 Typical Connection Diagram
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DS92LV0412 TYPICAL APPLICATION CONNECTION
Figure 34 shows a typical application of the DS92LV0412 for a 50 MHz 24-bit Color Display Application. The
CML inputs require 0.1 μF AC coupling capacitors to the line. The line driver includes internal termination.
Bypass capacitors are placed near the power supply pins. At a minimum, four 0.1 µF capacitors and a 4.7 µF
capacitor should be used for local device bypassing. System GPO (General Purpose Output) signals control the
PDB and BISTEN pins. The application assumes the companion deserializer (DS92LV0412) therefore the
configuration pins are also both tied Low. The interface to the host is with 1.8 V LVCMOS levels, thus the VDDIO
pin is connected also to the 1.8V rail. The Optional Serial Bus Control is not used in this example, thus the SCL,
SDA and ID[x] pins are left open. A delay cap is placed on the PDB signal to delay the enabling of the device
until power is stable. Bypass capacitors are placed near the power supply pins. Ferrite beads are placed on the
power lines for effective noise suppression.
DS92LV0412
3.3V
1.8V
FB1
FB4
VDDL
VDDTX
C6
C11
C3
C4
C8
C12
C9
VDDL
FB2
VDDIO
FB5
VDDA
VDDA
VDDIO
C7
C13
C10
FB3
VDDP
C5
VDDSC
VDDSC
TxCLKOUT+
TxCLKOUT-
C1
C2
TxOUT3+
TxOUT3-
TxOUT2+
TxOUT2-
TxOUT1+
TxOUT1-
TxOUT0+
TxOUT0-
RIN+
Serial
Channel Link II
Interface
Channel
Link
Interface
RIN-
CMF
C15
BISTEN
PDB
Host
Control
LOCK
PASS
R
C14
1.8V
OEN
OSS_SEL
LFMODE
VODSEL
MAPSEL
10k
RID
ID[X]
SCL
SDA
C1 - C2 = 0.1 mF (50 WV)
C3 œ C10, C15 = 0.1 mF
C11 - C13 = 4.7 mF
C14 = >10 mF
CONFIG1
CONFIG0
RES
GND
8
SSC[2]
SSC[1]
SSC[0]
DAP (GND)
R = 10 kW
RID (See ID[x] Resistor Value Table)
FB1 - FB5: Impedance = 1 kW
Low DC resistance ( <1W)
Figure 34. DS92LV0412 Typical Connection Diagram
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POWER UP REQUIREMENTS AND PDB PIN
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms
then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the
recommended operating voltage. When PDB pin is pulled to VDDIO, it is recommended to use a 10 kΩ pull-up and
a 22 uF cap to GND to delay the PDB input signal.
TRANSMISSION MEDIA
The DS92LV0411 / DS92LV0412 and their companion deserializer/serializer chipset is intended to be used in a
point-to-point configuration, through a PCB trace, twisted pair or coaxial cables. The DS92LV0411 requires
external parallel LVDS termination, but provides internal serial lane terminations to provide a clean signaling
environment. The interconnect for LVDS should present a differential impedance of 100 Ohms. The interconnect
for the Channel Link II interface should present a differential impedance of 100 Ohms or when configured for
coaxial cables the interconnect should present an impedance of 50 Ohms. Use cables and connectors that have
matched impedance to minimize impedance discontinuities. Shielded or un-shielded cables may be used
depending upon the noise environment and application requirements.
LIVE LINK INSERTION
The serializer and deserializer devices support live link or cable hot plug applications. The automatic receiver
lock to random data “plug & go” hot insertion capability allows the DS92LV0412 to attain lock to the active data
stream during a live cable insertion event.
ALTERNATE COLOR / DATA MAPPING
Color Mapped data Pin names are provided to specify a recommended mapping for 24-bit and 18-bit
Applications. When connecting to earlier generations of Channel Link II deserializer devices, a color mapping
review is recommended to ensure the correct connectivity is obtained. Table 15 provides examples for interfacing
between DS92LV0411 and different deserializers.
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Table 15. Serializer Alternate Color / Data Mapping
Channel Link
Bit Number
RGB (LSB
Example)
DS92LV2412
DS90UR124
DS99R124Q
DS90C124
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
B1
B0
G1
G0
R1
R0
DE
VS
HS
B7
B6
B5
B4
B3
B2
G7
G6
G5
G4
G3
G2
R7
R6
R5
R4
R3
R2
B1
B0
G1
RxIN3
N/A
G0
R1
R0
DE
VS
ROUT20
ROUT19
ROUT18
ROUT17
ROUT16
ROUT15
ROUT14
ROUT13
ROUT12
ROUT11
ROUT10
ROUT9
ROUT8
ROUT7
ROUT6
ROUT5
ROUT4
ROUT3
ROUT2
ROUT1
ROUT0
ROUT23
ROUT22
ROUT21
ROUT20
ROUT19
ROUT18
ROUT17
ROUT16
ROUT15
ROUT14
ROUT13
ROUT12
ROUT11
ROUT10
ROUT9
ROUT8
ROUT7
ROUT6
ROUT5
ROUT4
ROUT3
ROUT2
ROUT1
ROUT0
ROUT23
ROUT22
ROUT21
HS
B7
RxIN2
TxOUT2
TxOUT1
TxOUT0
B6ROUT10
B5
B4
B3
B2
G7
RxIN1
G6
G5
Bit 8
G4
Bit 7
G3
Bit 6
G2
Bit 5
R7
Bit 4
R6
RxIN0
Bit 3
R5
Bit 2
R4
Bit 1
R3
Bit 0
R2
OS2
OS1
OS0
N/A
N/A
DS92LV0411
Settings
CONFIG [1:0] =
00
CONFIG [1:0] =
11
MAPSEL = 0
CONFIG [1:0] = 10
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Table 16. Deserializer Alternate Color / Data Mapping
Channel Link
Bit Number
RGB (LSB
Example)
DS92LV2411
DS90UR241
DS99R421Q
DS90C241
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
B1
B0
G1
G0
R1
R0
DE
VS
HS
B7
B6
B5
B4
B3
B2
G7
G6
G5
G4
G3
G2
R7
R6
R5
R4
R3
R2
B1
B0
G1
TxOUT3
N/A
G0
R1
R0
DE
VS
DIN20
DIN19
DIN18
DIN17
DIN16
DIN15
DIN14
DIN13
DIN12
DIN11
DIN10
DIN9
DIN20
DIN19
DIN18
DIN17
DIN16
DIN15
DIN14
DIN13
DIN12
DIN11
DIN10
DIN9
HS
B7
TxOUT2
TxOUT1
TxOUT0
RxIN2
RxIN1
RxIN0
B6ROUT10
B5
B4
B3
B2
G7
G6
G5
Bit 8
G4
DIN8
DIN8
Bit 7
G3
DIN7
DIN7
Bit 6
G2
DIN6
DIN6
Bit 5
R7
DIN5
DIN5
Bit 4
R6
DIN4
DIN4
Bit 3
R5
DIN3
DIN3
Bit 2
R4
DIN2
DIN2
Bit 1
R3
DIN1
DIN1
Bit 0
R2
DIN0
DIN0
DIN923
DIN922
DIN921
OS2
OS1
OS0
DIN923
DIN922
DIN921
N/A
N/A
DS92LV0412
Settings
CONFIG [1:0] =
00
CONFIG [1:0] =
11
MAPSEL = 0
CONFIG [1:0] = 10
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PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitics, which has proven especially effective at high
frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. PIN DESCRIPTIONS tables typically provide guidance on which circuit blocks are connected to which
power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such
as PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100
Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled
noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also
radiate less.
Information on the WQFN style package is provided in Application Note: AN-1187 (SNOA401).
LVDS INTERCONNECT GUIDELINES
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
•
•
Use 100Ω coupled differential pairs
Use the S/2S/3S rule in spacings
–
–
–
S = space between the pair
2S = space between pairs
3S = space to LVCMOS signal
•
•
Minimize the number of vias
If vias are used, be sure to place vias to ground adjacent to the signal vias to ensure a constant return path
for the signal
•
•
•
•
Use differential connectors when operating above 500Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Terminate as close to the TX outputs and RX inputs as possible
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REVISION HISTORY
Changes from Revision A (April 2013) to Revision B
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 45
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS92LV0411SQ/NOPB
DS92LV0411SQE/NOPB
DS92LV0411SQX/NOPB
DS92LV0412SQ/NOPB
DS92LV0412SQE/NOPB
DS92LV0412SQX/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
NJK
NJK
NJK
RHS
RHS
RHS
36
36
36
48
48
48
1000 RoHS & Green
250 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
LV0411SQ
SN
SN
SN
SN
SN
LV0411SQ
LV0411SQ
LV0412SQ
LV0412SQ
LV0412SQ
2500 RoHS & Green
1000 RoHS & Green
250
RoHS & Green
2500 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS92LV0411SQ/NOPB
WQFN
NJK
NJK
NJK
RHS
RHS
RHS
36
36
36
48
48
48
1000
250
330.0
178.0
330.0
330.0
178.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
6.3
6.3
6.3
7.3
7.3
7.3
6.3
6.3
6.3
7.3
7.3
7.3
1.5
1.5
1.5
1.3
1.3
1.3
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
DS92LV0411SQE/NOPB WQFN
DS92LV0411SQX/NOPB WQFN
2500
1000
250
DS92LV0412SQ/NOPB
WQFN
DS92LV0412SQE/NOPB WQFN
DS92LV0412SQX/NOPB WQFN
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS92LV0411SQ/NOPB
DS92LV0411SQE/NOPB
DS92LV0411SQX/NOPB
DS92LV0412SQ/NOPB
DS92LV0412SQE/NOPB
DS92LV0412SQX/NOPB
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
NJK
NJK
NJK
RHS
RHS
RHS
36
36
36
48
48
48
1000
250
356.0
208.0
356.0
356.0
208.0
356.0
356.0
191.0
356.0
356.0
191.0
356.0
35.0
35.0
35.0
35.0
35.0
35.0
2500
1000
250
2500
Pack Materials-Page 2
MECHANICAL DATA
NJK0036A
SQA36A (Rev A)
www.ti.com
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