DS91M125 [TI]
具有 LVDS 输入的 125MHz 1:4 M-LVDS 中继器;
| 型号： | DS91M125 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 LVDS 输入的 125MHz 1:4 M-LVDS 中继器 中继器 |
| 文件： | 总19页 (文件大小：877K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS91M125
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SNLS290C –AUGUST 2008–REVISED APRIL 2013
DS91M125 125 MHz 1:4 M-LVDS Repeater with LVDS Input
Check for Samples: DS91M125
1
FEATURES
DESCRIPTION
The DS91M125 is a 1:4 M-LVDS repeater designed
for driving and distributing clock or data signals to up
to four multipoint networks.
2
•
DC - 125 MHz / 250 Mbps Low Jitter, Low
Skew, Low Power Operation
•
•
Independent Driver Enable Pins
M-LVDS (Multipoint LVDS) is a new family of bus
interface devices based on LVDS technology
specifically designed for multipoint and multidrop
cable and backplane applications. It differs from
standard LVDS in providing increased drive current to
handle double terminations that are required in multi-
point applications. Controlled transition times
minimize reflections that are common in multipoint
configurations due to unterminated stubs.
Outputs Conform to TIA/EIA-899 M-LVDS
Standard
•
•
•
Controlled Transition Times Minimize
Reflections
Inputs Conform to TIA/EIA-644-A LVDS
Standard
8 kV ESD on M-LVDS Output Pins Protects
Adjoining Components
A single DS91M125 channel is a 1:4 repeater that
accepts M-LVDS/LVDS/CML/LVPECL signals and
converts them to M-LVDS signal levels. Each output
has an associated independent driver enable pin. The
DS91M125 input conforms to the LVDS standard.
•
•
Flow-Through Pinout Simplifies PCB Layout
Industrial Operating Temperature Range
(−40°C to +85°C)
•
Available in a Space Saving SOIC-16 Package
The DS91M125 has a flow-through pinout for easy
PCB layout. It provides a new alternative for high
speed multipoint interface applications. It is packaged
in a space saving SOIC-16 package.
APPLICATIONS
•
•
•
Multidrop / Multipoint Clock and Data
Distribution
High-Speed, Low Power, Short-Reach
Alternative to TIA/EIA-485/422
Clock Distribution in AdvancedTCA (ATCA)
and MicroTCA (μTCA, uTCA) Backplanes
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
DS91M125
SNLS290C –AUGUST 2008–REVISED APRIL 2013
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Typical Application
Line Card in SLOT 1
DS91M125
Line Card in SLOT N-1
M-LVDS Receivers
Line Card in SLOT N
M-LVDS Receivers
R
T
R
T
R
T
R
T
Z
Z
Z
Z
R
R
R
R
0
0
0
0
T
T
T
T
R
T
= Z
LOADED
BACKPLANE
Connection Diagram
DE0
1
2
3
4
5
6
7
8
16
B0
A0
A1
B1
B2
A2
A3
B3
DE1
DE2
VDD
15
14
13
12
11
10
9
GND
DI+
DI-
DE3
Figure 1. 16-Lead (0.150″ Wide) Molded Small Outline Package, JEDEC
See Package Number D
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SNLS290C –AUGUST 2008–REVISED APRIL 2013
Logic Diagram
DE0
DE1
B0
A0
B1
A1
DI+
DI-
B2
A2
DE2
DE3
B3
A3
PIN DESCRIPTIONS
Number
Name
I/O, Type
Description
1, 2, 3, 8
DE
I, LVCMOS
Driver enable pins: When DE is low, the driver is disabled. When DE is high,
the driver is enabled. There is a 300 kΩ pulldown resistor on each pin.
6
DI+
DI-
GND
A
I, LVDS
I, LVDS
Non-inverting receiver input pin.
Inverting receiver input pin.
Ground pin.
7
5
Power
10, 11, 14, 15
9, 12, 13, 16
4
O, M-LVDS
O, M-LVDS
Power
Non-inverting driver output pin.
Inverting driver output pin.
Power supply pin, +3.3V ± 0.3V
B
VDD
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Supply Voltage
−0.3V to +4V
−0.3V to (VDD + 0.3V)
−1.9V to +5.5V
−0.3V to (VDD + 0.3V)
2.21W
LVCMOS Input Voltages
M-LVDS Output Voltages
LVDS Input Voltages
Maximum Package Power Dissipation at +25°C
SOIC Package
Derate SOIC Package
19.2 mW/°C above +25°C
52°C/W
Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)
θJA
θJC
19°C/W
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 4 seconds)
ESD Susceptibility
140°C
−65°C to +150°C
260°C
HBM(3)
MM(4)
≥ 8 kV
≥ 250V
CDM(5)
≥ 1250V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) Human Body Model, applicable std. JESD22-A114C
(4) Machine Model, applicable std. JESD22-A115-A
(5) Field Induced Charge Device Model, applicable std. JESD22-C101-C
RECOMMENDED OPERATING CONDITIONS
Min
3.0
−1.4
0
Typ
Max
3.6
Units
V
Supply Voltage, VDD
3.3
Voltage at M-LVDS Outputs
Voltage at LVDS Inputs
+3.8
VDD
VDD
0.8
V
V
LVCMOS Input Voltage High VIH
LVCMOS Input Voltage Low VIL
Operating Free Air Temperature TA
2.0
0
V
V
−40
+25
+85
°C
4
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SNLS290C –AUGUST 2008–REVISED APRIL 2013
ELECTRICAL CHARACTERISTICS
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)(4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC Specifications
VIH
VIL
IIH
High-Level Input Voltage
Low-Level Input Voltage
2.0
GND
-15
VDD
0.8
15
V
V
High-Level Input Current
Low-Level Input Current
Input Clamp Voltage
VIH = 3.6V
VIL = 0V
±1
±1
μA
μA
V
IIL
-15
15
VCL
IIN = -18 mA
-1.5
M-LVDS Driver DC Specifications
|VAB
|
Differential output voltage magnitude
RL = 50Ω, CL = 5pF
480
−50
0.3
0
650
+50
2.1
mV
mV
V
ΔVAB
Change in differential output voltage magnitude
between logic states
See Figure 2and Figure 4
0
VOS(SS)
Steady-state common-mode output voltage
RL = 50Ω, CL = 5pF
1.6
|ΔVOS(SS)
|
Change in steady-state common-mode output voltage
between logic states
See Figure 2
and Figure 3
+50
mV
VA(OC)
VB(OC)
VP(H)
Maximum steady-state open-circuit output voltage
Maximum steady-state open-circuit output voltage
Voltage overshoot, low-to-high level output
See Figure 5
0
0
2.4
2.4
V
V
RL = 50Ω, CL = 5pF,CD = 0.5pF
See Figure 7 and Figure 8
1.2VSS
V
(5)
VP(L)
Voltage overshoot, high-to-low level output
−0.2V
SS
V
(6)
IOS
IA
Differential short-circuit output current
Driver output current
See Figure 6
-43
43
32
mA
µA
µA
µA
µA
µA
µA
µA
VA = 3.8V, VB = 1.2V
VA = 0V or 2.4V, VB = 1.2V
VA = −1.4V, VB = 1.2V
VB = 3.8V, VA = 1.2V
−20
−32
+20
IB
Driver output current
32
VB = 0V or 2.4V, VA = 1.2V
VB = −1.4V, VA = 1.2V
VA = VB, −1.4V ≤ V ≤ 3.8V
−20
−32
−4
+20
IAB
Driver output differential current (IA − IB)
+4
32
IA(OFF)
Driver output power-off current
VA = 3.8V, VB = 1.2V,
DE = 0V
0V ≤ VDD ≤ 1.5V
µA
µA
µA
VA = 0V or 2.4V, VB = 1.2V,
DE = 0V
0V ≤ VDD ≤ 1.5V
−20
−32
+20
VA = −1.4V, VB = 1.2V,
DE = 0V
0V ≤ VDD ≤ 1.5V
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD
.
(3) Typical values represent most likely parametric norms for VDD = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
(4) CL includes fixture capacitance and CD includes probe capacitance.
(5) Specification is ensured by characterization and is not tested in production.
(6) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)(4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
IB(OFF)
Driver output power-off current
VB = 3.8V, VA = 1.2V,
DE = 0V
32
µA
0V ≤ VDD ≤ 1.5V
VB = 0V or 2.4V, VA = 1.2V,
DE = 0V
0V ≤ VDD ≤ 1.5V
−20
−32
−4
+20
µA
µA
µA
VB = −1.4V, VA = 1.2V,
DE = 0V
0V ≤ VDD ≤ 1.5V
IAB(OFF)
Driver output power-off differential current (IA(OFF)
−
VA = VB, −1.4V ≤ V ≤ 3.8V,
DE = 0V
IB(OFF)
)
+4
0V ≤ VDD ≤ 1.5V
CA
Driver output capacitance
VDD = OPEN
7.8
7.8
3
pF
pF
pF
CB
Driver output capacitance
CAB
CA/B
Driver output differential capacitance
Driver output capacitance balance (CA/CB)
1
LVDS Receiver DC Specifications
VIT+
Positive-going differential input voltage threshold
-5
-5
100
mV
mV
V
VIT−
Negative-going differential input voltage threshold
Common mode voltage range
−100
VCMR
VID = 100 mV
0.05
VDD-
0.05
IIN
Input current
VIN = 3.6V, VDD = 3.6V
VIN = 0V, VDD = 3.6V
VDD = OPEN
±1
±1
5
±10
±10
µA
µA
pF
CIN
Input capacitance
POWER SUPPLY CURRENT
ICCD
ICCZ
Driver Supply Current
RL = 50Ω, DE = VDD
67
21
78
26
mA
mA
TRI-STATE Supply Current
DE = GND
6
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SNLS290C –AUGUST 2008–REVISED APRIL 2013
SWITCHING CHARACTERISTICS
Over recommended operating supply and temperature ranges unless otherwise specified.
(1) (2) (3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRIVER AC SPECIFICATION
tPLH
Differential Propagation Delay Low to High
RL = 50Ω, CL = 5 pF,
3.0
3.0
5.5
5.5
65
8.5
8.5
350
400
2.5
5.5
3.0
3.0
11
ns
ns
tPHL
Differential Propagation Delay High to Low
CD = 0.5 pF
(4)(5)
tSKD1 (tsk(p)
tSKD2
tSKD3
tSKD4
tTLH (tr)
tTHL (tf)
tPZH
)
Pulse Skew |tPLHD − tPHLD
|
See Figure 7 and Figure 8
ps
Channel-to-Channel Skew(6)(5)
Part-to-Part Skew(7)(5)
Part-to-Part Skew(8)
Rise Time(5)
Fall Time(5)
65
ps
2.2
ns
ns
1.1
1.1
2.0
2.0
6
ns
ns
Enable Time (Z to Active High)
Enable Time (Z to Active Low )
Disable Time (Active Low to Z)
Disable Time (Active High to Z)
Maximum Operating Frequency(5)
RL = 50Ω, CL = 5 pF,
CD = 0.5 pF
ns
tPZL
6
11
ns
tPLZ
See Figure 9 and Figure 10
6
11
ns
tPHZ
6
11
ns
fMAX
125
MHz
(1) The ELECTRICAL CHARACTERISTICS tables list ensured specifications under the listed Recommended Operating Conditions except
as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes.
(2) Typical values represent most likely parametric norms for VDD = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
(3) CL includes fixture capacitance and CD includes probe capacitance.
(4) tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(5) Specification is ensured by characterization and is not tested in production.
(6) tSKD2, Channel-to-Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels.
(7) tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same VDD and within 5°C of each other within the operating temperature range.
(8) tSKD4, Part-to-Part Skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min|
differential propagation delay.
TEST CIRCUITS AND WAVEFORMS
C
L
A
R /2
DI+
DI-
L
Power Supply
Power Supply
D
V
OS
V
AB
C
C
L
L
R /2
L
B
Driver ENABLED
Figure 2. Differential Driver Test Circuit
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A
B
~ 1.9V
~ 1.3V
DV
OS(SS)
V
OS
V
OS(PP)
Figure 3. Differential Driver Waveforms
A
3.32 kW
DI+
Power Supply
Power Supply
V
TEST
D
V
AB
R
L
DI-
3.32 kW
B
Vary V
TEST
œ 1.0V to 3.4V
Figure 4. Differential Driver Full Load Test Circuit
DI+
DI-
A
B
Power Supply
Power Supply
D
V = V or V
A
B
V
1.62 kW
Figure 5. Differential Driver DC Open Test Circuit
DI+
DI-
A
B
Power Supply
Power Supply
D
I
OS
V
TEST
Vary V
TEST
œ 1.0V to 3.4V
Figure 6. Differential Driver Short-Circuit Test Circuit
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SNLS290C –AUGUST 2008–REVISED APRIL 2013
C
L
A
DI+
DI-
C
D
D
Signal Generator
R
L
B
Driver ENABLED
50W
50W
C
L
Figure 7. Driver Propagation Delay and Transition Time Test Circuit
1.3V
DI+
1.2V
1.2V
DI-
B
1.1V
t
t
PHL
PLH
V
V
OH
0V (Differential)
0V
A
OL
V
SS
90%
90%
0V
V
P(H)
V
DIFF
0V
10%
V
P(L)
V
= A - B
DIFF
10%
0 V
SS
t
t
THL
TLH
Figure 8. Driver Propagation Delays and Transition Time Waveforms
C
L
A
R /2
L
DI+
DI-
Power Supply
Power Supply
C
D
D
V
TYP
OS(SS)
R /2
L
B
DE
Generator
C
L
50W
Figure 9. Driver TRI-STATE Delay Test Circuit
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V
DD
V
DD
2
/
DE
V
DD
/2
0V
t
t
PZH
PHZ
~ 0.6V
0V
A-B WHEN DIN = L
A-B WHEN DIN = H
50%
50%
50%
50%
0V
~ 0.6V
t
t
PZL
PLZ
Figure 10. Driver TRI-STATE Delay Waveforms
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SNLS290C –AUGUST 2008–REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS
3.4
3.4
f = 125 MHz
f = 125 MHz
3.0
2.6
3.0
2.6
V = 3.0 V
CC
V
CC
= 3.0 V
2.2
2.2
1.8
1.4
1.8
1.4
V
= 3.6 V
110
CC
V
= 3.3 V
CC
V
= 3.6 V
110
CC
V
= 3.3 V
30
CC
1.0
-50
1.0
-50
-10
30
70
150
-10
70
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Driver Rise Time as a Function of Temperature
Figure 12. Driver Fall Time as a Function of Temperature
900
8.0
f = 125 MHz
V
CC
= 3.0 V
750
600
7.0
6.0
450
5.0
V
CC
= 3.6 V
300
4.0
3.0
V
CC
= 3.3 V
f = 1 MHz
V
= 3.3V
CC
150
0
T
= 25°C
A
2.0
-50
0
25
50
75
100
125
-10
30
70
110
150
RESISTIVE LOAD (W)
TEMPERATURE (°C)
Figure 13. Driver Output Signal Amplitude as a Function of
Resistive Load
Figure 14. Driver Propagation Delay (tPLHD) as a Function
of Temperature
8.0
180
V
= 3.3V
CC
f = 125 MHz
V
= 3.0 V
CC
T
A
= 25°C
7.0
6.0
150
120
R
= 50W (On all CH)
L
4OutputsON
3 Outputs ON
2 Outputs ON
1 Output ON
5.0
90
V
CC
= 3.6 V
V
= 3.3 V
CC
4.0
3.0
60
30
2.0
-50
0
-10
30
70
110
150
0
25
50
75
100
125
TEMPERATURE (°C)
FREQUENCY (MHz)
Figure 15. Driver Propagation Delay (tPHLD) as a Function
of Temperature
Figure 16. Driver Power Supply Current as a Function of
Frequency
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REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS91M125TMA/NOPB
DS91M125TMAX/NOPB
ACTIVE
SOIC
SOIC
D
D
16
16
48
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
DS91M125
TMA
ACTIVE
2500 RoHS & Green
SN
DS91M125
TMA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS91M125TMAX/NOPB
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.3
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
DS91M125TMAX/NOPB
D
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DS91M125TMA/NOPB
D
16
48
495
8
4064
3.05
Pack Materials-Page 3
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