DS90UH949ATRGCRQ1 [TI]

支持 HDCP 的 2K DSI 转 FPD-Link III 串行器 | RGC | 64 | -40 to 105;


型号：	DS90UH949ATRGCRQ1
厂家：	TEXAS INSTRUMENTS
描述：	支持 HDCP 的 2K DSI 转 FPD-Link III 串行器 \| RGC \| 64 \| -40 to 105 光电二极管
文件：	总88页 (文件大小：2185K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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DS90UH949A-Q1

ZHCSIO8 –AUGUST 2018

支持 HDCP 的 DS90UH949A-Q1 2K HDMI 转 FPD-Link III 桥接器串行器

1 特性

3 说明

•

符合面向汽车应用的 AEC-Q100 标准：

DS90UH949A-Q1 是一款 HDMI 转 FPD-Link III 桥接

器件，与 FPD-Link III DS90UH940A-

–

器件温度等级 2：-40°C 至 105°C 的环境运行

温度范围

Q1/DS90UH948A-Q1 解串器配合使用，可通过经济高

效的 50Ω 单端同轴电缆或 100Ω 差分屏蔽双绞线

(STP) 和屏蔽四路绞线 (STQ) 电缆提供单通道或双通

道高速串行流。该器件可对 HDMI v1.4b 输入进行序列

化，从而支持高达 2K 的视频分辨率和 24 位色深。

–

器件 HBM ESD 分类等级 2

器件 CDM ESD 分类等级 C5

•

支持高达 210MHz 的 TMDS 时钟，支持 2K

(2880x1080) 分辨率（24 位色深）

单路和双路 FPD-Link III 输出，支持 STP 或 STQ

电缆

FPD-Link III 接口支持通过同一条差分链路进行视频和

音频数据传输以及全双工控制（包括 I2C 通信）。通

过两个差分对实现视频数据和控制的整合可减小互连线

尺寸和重量，并简化系统设计。通过使用低压差分信

令、数据换序和随机生成最大限度地减少了电磁干扰

(EMI)。在向后兼容模式中，该器件通过一条差分链路

针对 94x 解串器支持高达 1080p 分辨率，针对 92x 解

串器支持 720p 分辨率，并具有 24 位色深。

•

高清多媒体 (HDMI) v1.4b 兼容输入

HDMI 模式 DisplayPort (DP++) 输入

支持片上密钥存储的集成型 HDCP v1.4 密码引擎

最多支持 8 通道的 HDMI 音频提取

高速反向通道，支持速率高达 2Mbps 的 GPIO

可跟踪扩频输入时钟以降低 EMI

具有 1Mbps 快速模式增强版的 I2C（主/从）

SPI 直通接口

DS90UH949A-Q1 支持 HDCP 中继器应用，在这些

应用中，无需外部控制器即可实现所有身份验证和加密

功能。在输入端对 HDMI 音频和视频数据进行解密，

并在将数据发送给 FPD-Link III 接口前重新加密。

向后兼容 DS90UH926Q-Q1 和 DS90UH928Q-Q1

FPD-Link III 解串器

2 应用

DS90UH949A-Q1 支持通过外部 I2S 接口接收多通道

音频。该器件还具有可选的辅助音频接口。

•

汽车信息娱乐：

–

车载信息娱乐 (IVI) 主机和人机交互界面 (HMI)

模块

器件信息⁽¹⁾

–

后座娱乐系统

数字仪表板

器件型号

封装

VQFN (64)

封装尺寸（标称值）

DS90UH949A-Q1

9.00mm x 9.00mm

•

安全和监控摄像机

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

消费类输入 HDMI 端口

应用图

VDDIO

(3.3 V / 1.8 V)

VDDIO

1.8 V

3.3 V

1.25 V

1.8 V

1.1 V

FPD-Link

(Open LDI)

HDMI

FPD-Link III

2 Lane

CLK+/-

D0+/-

IN_CLK-/+

RIN0+

RIN0-

DOUT0+

DOUT0-

IN_D0-/+

IN_D1-/+

D1+/-

D2+/-

D3+/-

Graphics

DOUT1+

DOUT1-

RIN1+

RIN1-

Processor

LVDS Display

(2880x1080)

or Graphic

IN_D2-/+

DS90UH949A-Q1

Serializer

DS90UH948-Q1

Deserializer

Processor

CLK2+/-

CEC

DDC

HPD

D4+/-

D5+/-

I2C

IDx

I2C

IDx

D6+/-

D7+/-

D_GPIO

(SPI)

D_GPIO

(SPI)

HDCP œ High-Bandwidth Content Protection

HDMI œ High Definition Multimedia Interface

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNLS543

DS90UH949A-Q1

ZHCSIO8 –AUGUST 2018

www.ti.com.cn

7.3 Feature Description................................................. 16

7.4 Device Functional Modes........................................ 30

7.5 Programming........................................................... 33

7.6 Register Maps......................................................... 37

Application and Implementation ........................ 72

8.1 Applications Information.......................................... 72

8.2 Typical Applications ................................................ 72

Power Supply Recommendations...................... 78

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 7

6.1 Absolute Maximum Ratings ..................................... 7

6.2 ESD Ratings ............................................................ 7

6.3 Recommended Operating Conditions....................... 7

6.4 Thermal Information.................................................. 8

6.5 DC Electrical Characteristics .................................... 8

6.6 AC Electrical Characteristics..................................... 9

6.7 DC and AC Serial Control Bus Characteristics....... 11

6.8 Recommended Timing for the Serial Control Bus .. 11

6.9 Timing Diagrams..................................................... 12

6.10 Typical Characteristics.......................................... 14

Detailed Description ............................................ 15

7.1 Overview ................................................................. 15

7.2 Functional Block Diagram ....................................... 15

10 Layout................................................................... 79

10.1 Layout Guidelines ................................................. 79

10.2 Layout Example .................................................... 79

11 器件和文档支持 ..................................................... 80

11.1 文档支持 ............................................................... 80

11.2 接收文档更新通知 ................................................. 80

11.3 社区资源................................................................ 80

11.4 商标....................................................................... 80

11.5 静电放电警告......................................................... 80

11.6 术语表 ................................................................... 80

12 机械、封装和可订购信息....................................... 80

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

2018 年 8 月

最初发布版本

DS90UH949A-Q1

www.ti.com.cn

ZHCSIO8 –AUGUST 2018

5 Pin Configuration and Functions

RGC Package

64-Pin VQFN

Top View

MODE_SEL1

PDB

IN_CLK-

IN_CLK+

VDD18

RES2

VDDHA11

NC2

RES1

VDDHS11

DOUT0+

VDDHA11

IN_D0-

DOUT0-

DS90UH949A-Q1

IN_D0+

VTERM

VDDHA11

IN_D1-

VDDS11

VDD18

64 VQFN

Top View

DOUT1+

DOUT1-

VDDHS11

IN_D1+

VDDHA11

IN_D2-

LFT

IDx

DAP = GND

MODE_SEL0

VDDP11

IN_D2+

VDD18

Pin Functions

I/O, TYPE

DESCRIPTION

NAME

NO.

HDMI TMDS INPUT

IN_CLK-

IN_CLK+

I, TMDS

TMDS Clock Differential Input

IN_D0-

IN_D0+

TMDS Data Channel 0 Differential Input

TMDS Data Channel 1 Differential Input

TMDS Data Channel 2 Differential Input

IN_D1-

IN_D1+

IN_D2-

IN_D2+

OTHER HDMI

HPD

O, Open-

Drain

Hot Plug Detect Output. Pull up to RX_5V with a 1-kΩ resistor

RX_5V

HDMI 5-V Detect Input

DDC_SDA

IO, Open-

Drain

DDC Slave Serial Data

Pull up to RX_5V with a 47-kΩ resistor

DS90UH949A-Q1

ZHCSIO8 –AUGUST 2018

www.ti.com.cn

Pin Functions (continued)

I/O, TYPE

DESCRIPTION

NAME

NO.

DDC_SCL

I, Open-Drain DDC Slave Serial Clock

Pull up to RX_5V with a 47-kΩ resistor

CEC

IO, Open-

Drain

Consumer Electronic Control Channel Input/Output Interface.

Pullup with a 27-kΩ resistor to 3.3 V

I, LVCMOS Optional Oscillator Input: This pin is the optional reference clock for CEC. It must be

connected to a 25 MHz 0.1% (1000ppm), 45-55% duty cycle clock source at CMOS-level

1.8 V. Leave it open if unused.

FPD-LINK III SERIAL

DOUT0-

FPD-Link III Inverting Output 0

The output must be AC-coupled with a 0.1-μF capacitor for interfacing with 92x deserializers

and 0.1-μF or 33-nF capacitor for 94x deserializers

DOUT0+

DOUT1-

DOUT1+

LFT

FPD-Link III True Output 0

The output must be AC-coupled with a 0.1-µF capacitor for interfacing with 92x deserializers

and 0.1-μF or 33-nF capacitor for 94x deserializers

FPD-Link III Inverting Output 1

The output must be AC-coupled with a 0.1-µF capacitor for interfacing with 92x deserializers

and 0.1-μF or 33-nF capacitor for 94x deserializers

FPD-Link III True Output 1

The output must be AC-coupled with a 0.1-µF capacitor for interfacing with 92x deserializers

and 0.1-μF or 33-nF capacitor for 94x deserializers

Analog

FPD-Link III Loop Filter

Connect to a 10-nF capacitor to GND

CONTROL

SDA

IO, Open-

Drain

I2C Data Input / Output Interface

Open-drain. Must have an external pullup to resistor to 1.8 V or 3.3 V. See I2CSEL pin. DO

NOT FLOAT.

Recommended pullup: 4.7 kΩ.

SCL

IO, Open-

Drain

I2C Clock Input / Output Interface

Open-drain. Must have an external pullup resistor to 1.8 V or 3.3 V. See I2CSEL pin. DO

NOT FLOAT.

Recommended pullup: 4.7 kΩ.

I2CSEL

I, LVCMOS I2C Voltage Level Strap Option

Tie to V_DDIOwith a 10-kΩ resistor for 1.8-V I2C operation.

Leave floating for 3.3-V I2C operation.

This pin is read as an input at power up.

IDx

Analog

I2C Serial Control Bus Device ID Address Select

Mode Select 0. See 表 6.

MODE_SEL0

MODE_SEL1

PDB

Mode Select 1. See 表 6.

I, LVCMOS Power-Down Mode Input Pin

INTB

O, Open-

Drain

Open-Drain. Remote interrupt. Active LOW.

Pull up to VDDIO with a 4.7-kΩ resistor.

REM_INTB

O, Open-

Drain

Remote interrupt. Mirrors status of INTB_IN from the deserializer.

Note: External pull-up to 1.8 V required. Recommended pullup: 4.7 kΩ.

INTB = H, Normal Operation

INTB = L, Interrupt Request

SPI PINS (DUAL LINK MODE ONLY)

MOSI

MISO

SPLK

IO, LVCMOS SPI Master Out Slave In. Shared with D_GPIO0

IO, LVCMOS SPI Master In Slave Out. Shared with D_GPIO1

IO, LVCMOS SPI Clock. Shared with D_GPIO2

IO, LVCMOS SPI Slave Select. Shared with D_GPIO3

HIGH-SPEED (HS) BIDIRECTIONAL CONTROL CHANNEL GPIO PINS (DUAL LINK MODE ONLY)

D_GPIO0

D_GPIO1

D_GPIO2

IO, LVCMOS HS GPIO0. Shared with MOSI

IO, LVCMOS HS GPIO1. Shared with MISO

IO, LVCMOS HS GPIO2. Shared with SPLK

DS90UH949A-Q1

www.ti.com.cn

ZHCSIO8 –AUGUST 2018

Pin Functions (continued)

I/O, TYPE

DESCRIPTION

NAME

NO.

D_GPIO3

IO, LVCMOS HS GPIO3. Shared with SS

BIDIRECTIONAL CONTROL CHANNEL (BCC) GPIO PINS

GPIO0

GPIO1

GPIO2

GPIO3

IO, LVCMOS BCC GPIO0. Shared with SDIN

IO, LVCMOS BCC GPIO1. Shared with SWC

IO, LVCMOS BCC GPIO2. Shared with I2S_DC

IO, LVCMOS BCC GPIO3. Shared with I2S_DD

GPIO5_REG

GPIO6_REG

GPIO7_REG

GPIO8_REG

IO, LVCMOS General-Purpose Input/Output 5

Local register control only. Shared with I2S_DB

IO, LVCMOS General-Purpose Input/Output 6

Local register control only. Shared with I2S_DA

IO, LVCMOS General-Purpose Input/Output 7

Local register control only. Shared with I2S_WC

IO, LVCMOS General-Purpose Input/Output 8

Local register control only. Shared with I2S_CLK

SLAVE MODE LOCAL I2S CHANNEL PINS

I2S_WC

I2S_CLK

I2S_DA

I2S_DB

I2S_DC

I2S_DD

I, LVCMOS Slave Mode I2S Word Clock Input. Shared with GPIO7_REG

I, LVCMOS Slave Mode I2S Clock Input. Shared with GPIO8_REG

I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO6_REG

I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO5_REG

I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO2

I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO3

AUXILIARY I2S CHANNEL PINS

SWC

O, LVCMOS Master Mode I2S Word Clock Ouput. Shared with GPIO1

SCLK

O, LVCMOS Master Mode I2S Clock Ouput. Shared with I2CSEL. This pin is sampled following power-up

as I2CSEL, then it will switch to SCLK operation as an output.

SDIN

I, LVCMOS Master Mode I2S Data Input. Shared with GPIO0

IO, LVCMOS Master Mode I2S System Clock Input/Output

MCLK

POWER and GROUND

VTERM

Power

3.3-V (±5%) Supply for DC-coupled internal termination OR

1.8-V (±5%) Supply for AC-coupled internal termination

Refer to 图 25 or 图 26.

VDD18

1.8-V (±5%) Analog supply. Refer to 图 25 or 图 26.

VDDA11

Power

1.1-V (±5%) Analog supply. Refer to 图 25 or 图 26.

1.1-V (±5%) TMDS supply. Refer to 图 25 or 图 26.

VDDHA11

VDDHS11

VDDL11

Power

1.1-V (±5%) supply. Refer to 图 25 or 图 26.

1.1-V (±5%) Digital supply. Refer to 图 25 or 图 26.

VDDP11

VDDS11

VDDIO

Power

1.1-V (±5%) PLL supply. Refer to 图 25 or 图 26.

1.1-V (±5%) Serializer supply. Refer to 图 25 or 图 26.

1.8-V (±5%) IO supply. Refer to 图 25 or 图 26.

GND

Thermal

Pad

GND

Ground. Connect to Ground plane with at least 9 vias.

OTHER

DS90UH949A-Q1

ZHCSIO8 –AUGUST 2018

www.ti.com.cn

Pin Functions (continued)

I/O, TYPE

DESCRIPTION

NAME

NO.

RES0

RES1

—

Reserved. Tie to GND.

RES2

—

Reserved. Connect with 50 Ω to GND.

NC0

NC1

NC2

No connect. Leave floating. Do not connect to VDD or GND.

DS90UH949A-Q1

www.ti.com.cn

ZHCSIO8 –AUGUST 2018

6 Specifications

6.1 Absolute Maximum Ratings

(1)

See

MIN

–0.3

MAX

1.7

UNIT

V_DD11

V_DD18

V_DDIO

Supply voltage

2.5

Supply voltage

2.5

OpenLDI inputs

2.75

LVCMOS I/O voltage

1.8-V tolerant I/O

3.3-V tolerant I/O

5-V tolerant I/O

–0.3 V_DDIO+ 0.3

–0.3

−0.3

2.5

5.3

1.7

150

FPD-Link III output voltage

Junction temperature

Storage temperature

°C

T_stg

–65

(1) For soldering specifications, see product folder at www.ti.com and Absolute Maximum Ratings for Soldering (SNOA549).

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

±2000

±750

Air Discharge (Pins 22, 23, 26,

and 27)

±15000

±8000

(IEC 61000-4-2)

Electrostatic

discharge

R_D= 330 Ω, C_S= 150 pF

Contact Discharge (Pins 22, 23,

26, and 27)

V_(ESD)

Air Discharge (Pins 22, 23, 26,

and 27)

±15000

±8000

(ISO10605)

R_D= 330 Ω, C_S= 150 pF

R_D= 2 kΩ, C_S= 150 pF or 330 pF

Contact Discharge (Pins 22, 23,

26, and 27)

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

1.045

1.71

NOM

1.1

1.8

3.3

1.8

MAX

UNIT

V_DD11

V_DD18

V_DDIO

Supply voltage

1.155

1.89

3.465

1.89

105

Supply voltage

LVCMOS supply voltage

V_DDI2C, 1.8-V operation

1.71

V_DDI2C, 3.3-V operation

3.135

1.71

HDMI termination (V_TERM), DC-coupled

HDMI termination (V_TERM), AC-coupled

Operating free air temperature

T_A

–40

°C

Allowable ending ambient temperature for continuous PLL lock

when ambient temperature is rising under following condition:

-40C ≤ starting ambient temperature (Ts) < 0C.⁽¹⁾

T_CLH1

°C

Allowable ending ambient temperature for continuous PLL lock

when ambient temperature is rising under following condition:

0C ≤ starting ambient temperature (Ts) ≤ 105C.⁽¹⁾

T_CLH2

105

(1) The input and output PLLs are calibrated at the ambient start up temperature (Ts) when the device is powered on or when reset using

the PDB pin. The PLLs will stay locked up to the specified ending temperature.

DS90UH949A-Q1

ZHCSIO8 –AUGUST 2018

www.ti.com.cn

Recommended Operating Conditions (continued)

Over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

Allowable ending ambient temperature for continuous PLL lock

T_CHL1

when ambient temperature is falling under following condition:

°C

45C < starting ambient temperature (Ts) ≤ 105C.⁽¹⁾

Allowable ending ambient temperature for continuous PLL lock

when ambient temperature is falling under following condition:

-20C ≤ starting ambient temperature (Ts) ≤ 45C.⁽¹⁾

T_CHL2

Ts-20

°C

TMDS frequency

Supply noise⁽²⁾(DC-50 MHz)

210

MHz

mV_P-P

(2) Supply noise testing was done without any capacitors or ferrite beads connected. A sinusoidal signal is AC-coupled to the V_DD11supply

of the serializer until the deserializer loses lock.

6.4 Thermal Information

DS90UB949A

THERMAL METRIC⁽¹⁾

RGC (VQFN)

64 PINS

25.8

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

11.4

5.1

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

5.1

R_θJC(bot)

0.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 DC Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

1.8-V LVCMOS I/O

TEST CONDITIONS

PIN/FREQ.

MIN

TYP

MAX UNIT

0.65 ×

V_DDIO

SCLK/I2CSEL, PDB,

D_GPIO0/MOSI,

V_IH

High level input voltage

D_GPIO1/MISO,

D_GPIO2/SPLK,

D_GPIO3/SS,

SDIN/GPIO0,

0.35 ×

V_IL

I_IN

Low level input voltage

Input current

V_DDIO

V_IN= 0 V or 1.89 V

−10

μA

SWC/GPIO1, MCLK

I2S_DC/GPIO2,

I2S_DD/GPIO3,

I2S_DB/GPIO5_REG,

I2S_DA/GPIO6_REG,

I2S_CLK/GPIO8_REG,

I2S_WC/GPIO7_REG

0.7 ×

V_DDIO

V_OH

High level output voltage

I_OH= –4 mA

I_OL= 4 mA

V_DDIO

0.26 ×

V_DDIO

V_OL

Low level output voltage

GND

–10

I_OS

I_OZ

Output short-circuit current

TRI-STATE output current

V_OUT= 0 V

–50

V_OUT= 0 V or V_DDIO, PDB = L

μA

TMDS INPUTS -- FROM HDMI v1.4b SECTION 4.2.5

V_TERM

–

V_TERM

–

V_ICM1

Input common-mode voltage IN_CLK ≤ 210 MHz

IN_D[2:0]+, IN_D[2:0]–

IN_CLK+, IN_CLK–

V_TERM= 1.8 V (±5%) or

VTERM = 3.3 V (±5%)

400

37.5

V_TERM

–

V_TERM

+ 10

V_ICM2

V_IDIFF

R_TMDS

Input common-mode voltage IN_CLK ≤ 210 MHz

Input differential voltage level IN_CLK ≤ 210 MHz

150

1200 mV_P-P

IN_D[2:0]+, IN_D[2:0]–

IN_CLK+, IN_CLK–

Termination resistance

Differential

100

110

5.3

HDMI IO -- FROM HDMI v1.4b SECTION 4.2.7 to 4.2.9

V_{RX_5V}

I_{5V_Sink}

5-V power signal

5-V input current

4.8

RX_5V

DS90UH949A-Q1

www.ti.com.cn

ZHCSIO8 –AUGUST 2018

DC Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

PIN/FREQ.

MIN

TYP

MAX UNIT

High level output voltage,

HPD

V_OH,HPD

V_OL,HPD

I_IZ,HPD

I_OH= –4 mA

2.4

5.3

0.4

HPD, R_PU= 1 kΩ

Low level output voltage,

HPD

I_OL= 4 mA

PDB = L

GND

–10

Power-down input current,

HPD

0.3 ×

V_DD,DDC

V_IL,DDC

V_IH,DDC

I_IZ,DDC

Low level input voltage, DDC

High level input voltage,

DDC

DDC_SCL, DDC_SDA

2.7

Power-down input current,

DDC

PDB = L

–10

µA

V_IH,CEC

V_IL,CEC

V_HY,CEC

High level input voltage, CEC

Low level input voltage, CEC

Input hysteresis, CEC

0.8

0.4

Low level output voltage,

CEC

V_OL,CEC

V_OH,CEC

I_{OFF_CEC}

GND

2.5

0.6

3.63

1.8

CEC

High level output voltage,

CEC

Power-down input current,

CEC

PDB = L

–1.8

µA

FPD-LINK III DIFFERENTIAL DRIVER

V_ODp-p

Output differential voltage

Output voltage unbalance

900

1200 mV_p-p

ΔV_OD

Output differential offset

voltage

V_OS

550

DOUT[1:0]+,

DOUT[1:0]–

ΔV_OS

I_OS

Offset voltage unbalance

Output short-circuit current

–50

Ω

FPD-Link III outputs = 0 V

Single-ended

R_T

Termination resistance

(1)

SUPPLY CURRENT

Supply current, normal

operation

I_DD11

300

510

Supply current, normal

operation

I_DD18

Colorbar pattern

V_TERMcurrent, normal

operation

I_DD,VTERM

I_DDZ11

Supply current, power-down

mode

Supply current, power-down

mode

I_DDZ18

PDB = L

V_TERMcurrent, power-down

mode

I_DDZ,VTERM

(1) Specification is ensured by bench characterization.

6.6 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER

TEST CONDITIONS

PIN/FREQ.

MIN

TYP

MAX

UNIT

(1)

GPIO FREQUENCY

(1) Back channel rates are available on the companion deserializer datasheet.

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AC Electrical Characteristics (continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER

TEST CONDITIONS

PIN/FREQ.

MIN

TYP

MAX

UNIT

Single-lane, IN_CLK = 25

MHz – 105 MHz

0.25 ×

IN_CLK

Forward channel GPIO

frequency

GPIO[3:0],

D_GPIO[3:0]

R_b,FC

MHz

Dual-lane, IN_CLK/2 = 25

MHz – 105 MHz

0.125 ×

IN_CLK

Single-lane, IN_CLK = 25

MHz – 105 MHz

>2 /

IN_CLK

GPIO pulse width,

forward channel

GPIO[3:0],

D_GPIO[3:0]

t_GPIO,FC

Dual-lane, IN_CLK/2 = 25

MHz – 105 MHz

>2 /

(IN_CLK/2)

TMDS INPUT

Skew-

Intra

Maximum intra-pair

skew

(2)

0.4

UI_TMDS

IN_CLK±,

IN_D[2:0]±

(3)

Skew-

Inter

Maximum inter-pair

skew

0.2 × T_char

+ 1.78

Per HDMI CTS ver 1.4b⁽⁴⁾

Per Test ID 8-7: TMDS - Jitter

Tolerance

(2)

I_TJIT

Input total jitter tolerance

IN_CLK±

0.3

UI_TMDS

FPD-LINK III OUTPUT

Low voltage differential

t_LHT

low-to-high transition

time

Low voltage differential

high-to-low transition

time

t_HLT

Output active to OFF

delay

t_XZD

PDB = L

100

t_PLD

t_SD

Lock time (HDMI Rx)

Delay — latency

IN_CLK±

145 × T⁽²⁾

Single-lane:

measured

with CDR

loop BW =

f/15 (7MHz)

Output total jitter (see

图 5)

(5)

t_DJIT

Random Pattern

0.3

UI_FPD3

Dual-lane:

measured

with CDR

loop BW =

f/30 (7MHz)

Jitter transfer function

(-3-dB bandwidth)

λ_STXBW

δ_STX

960

0.1

kHz

Jitter transfer function

peaking

(2) One bit period of the TMDS input.

(3) Ten bit periods of the TMDS input.

(4) Per Test ID 8-7: TMDS - Jitter Tolerance:

1) D_JITTER = 500kHz, C_JITTER = 10MHz

Set C_JITTER component to 0.25*T_BITat TP1

Set D_JITTER component to 0.3*TBIT at TP1

2) Set C_JITTER component to 0.25*T_BITat TP1

Set D_JITTER component to 0.3TBIT at TP1D_JITTER = 1MHz, C_JITTER = 7MHz

Set C_JITTER component to 0.25*T_BITat TP1

Set D_JITTER component to 0.3*TBIT at TP1

Note: TP1 is the edges of eye diagram shown in the HDMI specification

A CDR filter is applied at 4MHz with BER ≤1 E-10

(5) One bit period of the serializer output.

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6.7 DC and AC Serial Control Bus Characteristics

Over V_DDI2Csupply and temperature ranges unless otherwise specified. V_DDI2Ccan be 1.8 V (±5%) or 3.3 V (±5%) (refer to

I2CSEL pin description for 1.8-V or 3.3-V operation).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

0.7 ×

V_DDI2C

SDA and SCL, V_DDI2C= 1.8 V

V_IH,I2C

Input high level, I2C

0.7 ×

V_DDI2C

SDA and SCL, V_DDI2C= 3.3 V

SDA and SCL, V_DDI2C= 1.8 V

0.3 ×

V_DDI2C

V_IL,I2C

Input low level voltage, I2C

0.3 ×

SDA and SCL, V_DDI2C= 3.3 V

V_DDI2C

V_HY

Input hysteresis, I2C

Output low level, I2C

SDA and SCL, V_DDI2C= 1.8 V or 3.3 V

>50

SDA and SCL, V_DDI2C= 1.8-V, fast-mode, 3-mA sink

current

0.2 ×

GND

V_DDI2C

V_OL,I2C

SDA and SCL, V_DDI2C= 3.3-V, 3-mA sink current

SDA and SCL, V_DDI2C= 0 V

GND

–800

–10

0.4

–600

µA

I_IN,I2C

Input current, I2C

SDA and SCL, V_DDI2C= V_DD18or V_DD33

SDA and SCL

C_IN,I2C

Input capacitance, I2C

6.8 Recommended Timing for the Serial Control Bus

Over I2C supply and temperature ranges unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

100 kHz

400 kHz

Standard-mode

Fast-mode

f_SCL

SCL clock frequency

Fast-mode plus

Standard-mode

Fast-mode

MHz

µs

4.7

1.3

0.5

t_LOW

SCL low period

SCL high period

Fast-mode plus

Standard-mode

Fast-mode

t_HIGH

0.6

0.26

Fast-mode plus

Standard-mode

Fast-mode

Hold time for a start or a

repeated start condition

t_HD;STA

t_SU;STA

t_HD;DAT

t_SU;DAT

t_SU;STO

t_BUF

0.6

0.26

4.7

0.6

0.26

Fast-mode plus

Standard-mode

Fast-mode

Setup time for a start or a

repeated start condition

Fast-mode plus

Standard-mode

Fast-mode

Data hold time

Data setup time

Fast-mode plus

Standard-mode

Fast-mode

250

100

Fast-mode plus

Standard-mode

Setup time for STOP condition Fast-mode

Fast-mode plus

0.6

0.26

4.7

1.3

0.5

Standard-mode

Fast-mode

Bus free time

between STOP and START

Fast-mode plus

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MAX UNIT

Recommended Timing for the Serial Control Bus (continued)

Over I2C supply and temperature ranges unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

Standard-mode

Fast-mode

1000

300

120

300

120

t_r

SCL and SDA rise time

Fast-mode plus

Standard-mode

Fast-mode

t_f

SCL and SDA fall time

Input filter

Fast-mode plus

Fast-mode

t_SP

Fast-mode plus

6.9 Timing Diagrams

DOUT+

DOUT-

100 nF

Differential probe

SCOPE

BW û 4GHz

IN_CLK±

IN_D[2:0]±

Input Impedance û 100 kW

ú 0.5 pf

100W

BW û 3.5 GHz

100 nF

OUT

OD/2

Single Ended

OD/2

OUT

+) - (D

OUT

Differential

OUT

图 1. Serializer V_ODOutput

80%

20%

(DOUT+) - (DOUT-)

VOD

HLT

LHT

图 2. Output Transition Times

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Timing Diagrams (接下页)

VDD

VDDIO

PDB

RX_5V

IN_CLK

(Diff.)

PLD

DOUT

(Diff.)

Driver On

Driver OFF, V

= 0V

图 3. Serializer Lock Time

N-1

N+1

N+2

IN_D[2:0]

IN_CLK

STOP START

STOP

BIT

START

BIT

STOP

BIT

START

STOP

BIT

START

BIT

STOP

BIT

SYMBOL N

BIT BIT

BIT

SYMBOL N-4

SYMBOL N-3

SYMBOL N-2

SYMBOL N-1

DOUT

图 4. Latency Delay

DJIT

DOUT

(Diff.)

EYE OPENING

(1 UI)

BIT

图 5. Serializer Output Jitter

SDA

t_BUF

t_f

t_HD;STA

t_SP

t_LOW

t_r

t_f

t_r

SCL

t_SU;STA

t_HD;STA

t_HD;DAT

t_SU;STO

t_HIGH

t_SU;DAT

STOP

START

REPEATED

START

图 6. Serial Control Bus Timing Diagram

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Timing Diagrams (接下页)

t_LC

t_HC

V_IH

V_IL

I2S_CLK

t_sr

t_hr

I2S_WC

I2S_D[A,B,C,D]

图 7. I2S Timing Diagram

6.10 Typical Characteristics

图 8. DOUT0 Eye at 3.675 Gbps

图 9. DOUT1 Eye at 3.675 Gbps

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7 Detailed Description

7.1 Overview

The DS90UH949A-Q1 converts an HDMI interface (3 TMDS data channels + 1 TMDS Clock) to an FPD-Link III

interface. This device transmits a 35-bit symbol operating at up to 3.675-Gbps line rate over either a single serial

pair or two serial pairs. The serial stream contains an embedded clock, video control signals, RGB video data,

and audio data. The payload is DC-balanced to enhance signal quality and support AC coupling.

The DS90UH949A-Q1 serializer is intended for use with a DS90UH926Q-Q1, DS90UH928Q-Q1, DS90UH940A-

Q1, and DS90UH948A-Q1 deserializer.

The DS90UH949A-Q1 serializer and companion deserializer can incorporate an I²C-compatible interface. The

I²C-compatible interface supports the programming of serializer or deserializer devices from a local host

controller. The devices can also incorporate a bidirectional control channel (BCC) that allows communication

between the serializer and deserializer as well as between remote I2C slave devices.

The bidirectional control channel (BCC) is implemented through embedded signaling in the high-speed forward

channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to

serializer). Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial

link from one I2C bus to another. The implementation allows for arbitration with other I2C-compatible masters at

either side of the serial link.

7.2 Functional Block Diagram

KSV

FIFO

Packet

FIFO

Audio

PLL

Audio

FIFO

HDCP

Key

NVM

FPD-Link

III TX

Digital

FPD3 TX

Analog

Video

FPD-Link III

Digital

TMDS

Interface

PAT

GEN

TMDS

I2S Audio

HDMI Controller

Digital

HDMI RX

PHY

FPD-Link III Digital

HPA

FPD-Link

III TX

Digital

FPD3 TX

Analog

RX_5V

DDC

Bridge Control

Digital

EDID

I/F

EDID/

Config

NVM

Optional

Secondary

I2S

I2C

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7.3 Feature Description

7.3.1 High-Definition Multimedia Interface (HDMI)

HDMI is a leading interface standard used to transmit digital video and audio from sources (such as a DVD

player) to sinks (such as an LCD display). The interface is capable of transmitting high-definition video, audio,

and also supports HDCP. Other HDMI signals consist of various control and status data that travel bidirectionally.

7.3.1.1 HDMI Receive Controller

The HDMI Receiver is an HDMI version 1.4b compliant receiver. The HDMI receiver is capable of operation at

greater than 2K resolutions. The configuration used in the DS90UH949A-Q1 does not include version 1.4b

features such as the ethernet channel (HEC) or Audio Return Channel (ARC).

7.3.2 Transition Minimized Differential Signaling

HDMI uses Transition Minimized Differential Signaling (TMDS) over four differential pairs (3 TMDS channels and

1 TMDS clock) to transmit video and audio data. TMDS is widely used to transmit high-speed serial data. The

technology incorporates a form of 8b/10b encoding, and the differential signaling allows the device to reduce

electromagnetic interference (EMI) and achieve high skew tolerance.

7.3.3 Enhanced Display Data Channel

The Display Data Channel (DDC) is a collection of digital communication protocols between a computer display

and a graphics adapter that enables the display to send the supported display modes to the adapter. The DDC

also allows the computer host to adjust monitor parameters, such as brightness and contrast.

7.3.4 Extended Display Identification Data (EDID)

EDID is a data structure provided by a digital display to describe the display capabilities to a video source. By

providing this information, the video source can then send video data with the proper timing and resolution that

the display supports. The DS90UH949A-Q1 supports several options for delivering display identification (EDID)

information to the HDMI graphics source. The EDID information is accessible through the DDC interface and

comply with the DDC and EDID requirements given in the HDMI v1.4b specification.

The EDID configurations supported are as follows:

•

External local EDID (EEPROM)

Internal EDID loaded into device memory

Remote EDID connected to I2C bus at deserializer side

Internal pre-programmed EDID

The EDID mode selected should be configurable from the MODE_SEL pins or from internal control registers. For

all modes, the EDID information should be accessible at the default address of 0xA0.

7.3.4.1 External Local EDID (EEPROM)

The DS90UH949A-Q1 can be configured to allow a local EEPROM EDID device. The local EDID device may

implement any EDID configuration allowable by the HDMI v1.4b and DVI 1.0 standards, including multiple

extension blocks up to 32KB.

7.3.4.2 Internal EDID (SRAM)

The DS90UH949A-Q1 also allows the internal loading of an EDID profile up to 256 bytes. This SRAM storage is

volatile and requires loading from an external I2C master (local or remote). The internal EDID is reloadable and

readable (local/remote) from control registers during normal operation.

7.3.4.3 External Remote EDID

The serializer copies the remote EDID connected to the I2C bus of the remote deserializer into its internal

SRAM. The remote EDID device can be a standalone I2C EEPROM, or integrated into the digital display panel.

In this mode, the serializer automatically accesses the Bidirectional Control Channel to search for the EDID

information at the default address 0xA0. Once found, the serializer copies the remote EDID into local SRAM.

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Feature Description (接下页)

7.3.4.4 Internal Pre-Programmed EDID

The serializer also has an internal eFuse that is loaded into the internal SRAM with pre-programmed 256-byte

EDID data at start-up. This EDID profile supports several generic video (480p, 720p) and audio (2-channel audio)

timing profiles within the single-link operating range of the device (25-MHz to 105-MHz pixel clock). In this mode,

the internal EDID SRAM data is readable from the DDC interface. The EDID contents are below:

0x00 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x53 0x0E 0x49 0x09 0x01 0x00 0x00 0x00

0x1C 0x18 0x01 0x03 0x80 0x34 0x20 0x78 0x0A 0xEC 0x18 0xA3 0x54 0x46 0x98 0x25

0x0F 0x48 0x4C 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01

0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x1D 0x00 0x72 0x51 0xD0 0x1E 0x20 0x6E 0x50

0x55 0x00 0x00 0x20 0x21 0x00 0x00 0x18 0x00 0x00 0x00 0xFD 0x00 0x3B 0x3D 0x62

0x64 0x08 0x00 0x0A 0x20 0x20 0x20 0x20 0x20 0x20 0x00 0x00 0x00 0xFC 0x00 0x54

0x49 0x2D 0x44 0x53 0x39 0x30 0x55 0x78 0x39 0x34 0x39 0x0A 0x00 0x00 0x00 0x10

0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x57

0x02 0x03 0x15 0x40 0x41 0x84 0x23 0x09 0x7F 0x05 0x83 0x01 0x00 0x00 0x66 0x03

0x0C 0x00 0x10 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x28

7.3.5 Consumer Electronics Control (CEC)

Consumer Electronics Control (CEC) is designed to allow the system user to command and control up to ten

CEC-enabled devices connected through HDMI using only one of their remote controls (for example, controlling

a television set, set-top box, and DVD player using only the remote control of the TV). CEC also allows for

individual CEC-enabled devices to command and control each other without user intervention. CEC is a one-

wire, open-drain bus with an external 27-kΩ (±10%) resistor pullup to 3.3 V.

CEC protocol can be implemented using an external clock reference or the 25-MHz internal oscillator inside the

DS90UH949A-Q1.

7.3.6 +5-V Power Signal

5 V is asserted by the HDMI source through the HDMI interface. The 5-V signal propagates through the

connector and cable until it reaches the sink. The 5-V supply is used for various HDMI functions, such as HPD

and DDC signals.

7.3.7 Hot Plug Detect (HPD)

The HPD pin is asserted by the sink to let the source know that it is ready to receive the HDMI signal. The

source initiates the connection by first providing the 5-V power signal through the HDMI interface. The sink holds

HPD low until it is ready to receive signals from the source, at which point it will release HPD to be pulled up to 5

7.3.8 High-Speed Forward Channel Data Transfer

The High-Speed Forward Channel is composed of 35 bits of data containing RGB data, sync signals, HDCP,

I2C, GPIOs, and I2S audio transmitted from serializer to deserializer. 图 10 shows the serial stream per clock

cycle. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized,

balanced, and scrambled.

图 10. FPD-Link III Serial Stream

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Feature Description (接下页)

The device supports TMDS clocks in the range of 25 MHz to 105 MHz over one lane, or 50 MHz to 210 MHz

over two lanes. The FPD-Link III serial stream rate is 3.675 Gbps maximum (875 Mbps minimum) when

transmitting either over one lane or both lanes.

7.3.9 Back Channel Data Transfer

The Backward Channel provides bidirectional communication between the display and host processor. The

information is carried from the deserializer to the serializer as serial frames. The back channel control data is

transferred over both serial links along with the high-speed forward data, DC balance coding, and embedded

clock information. This architecture provides a backward path across the serial link together with a high-speed

forward channel. The back channel contains the I2C, HDCP, CRC, and 4 bits of standard GPIO information with

a line rate of 5, 10, or 20 Mbps (configured by the compatible deserializer).

7.3.10 FPD-Link III Port Register Access

The DS90UH949A-Q1 contains two downstream ports, therefore some registers must be duplicated to allow

control and monitoring of the two ports. To facilitate this, a TX_PORT_SEL register controls access to the two

sets of registers. Registers that are shared between ports (not duplicated) will be available independent of the

settings in the TX_PORT_SEL register.

Setting the TX_PORT0_SEL or TX_PORT1_SEL bit will allow a read of the register for the selected port. If both

bits are set, port1 registers will be returned. Writes will occur to ports for which the select bit is set, allowing

simultaneous writes to both ports if both select bits are set.

Setting the PORT1_I2C_EN bit will enable a second I2C slave address, allowing access to the second port

registers through the second I2C address. If this bit is set, the TX_PORT0_SEL and TX_PORT1_SEL bits will be

ignored.

7.3.11 Power Down (PDB)

The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin may be controlled by an

external device, or through V_DDIO, where V_DDIO= 1.71 V to 1.89 V. To save power, disable the link when the

display is not required (PDB = LOW). Ensure that this pin is not driven HIGH before all power supplies have

reached final levels. When PDB is driven low, ensure that the pin is driven to 0 V for at least 3 ms before

releasing or driving high. In the case where PDB is pulled up to V_DDIOdirectly, a 10-kΩ pullup resistor and a >10-

µF capacitor to ground are required (see ).

Toggling PDB low will POWER DOWN the device and RESET all control registers to default. During this time,

PDB must be held low for a minimum of 3 ms before going high again.

7.3.12 Serial Link Fault Detect

The DS90UH949A-Q1 can detect fault conditions in the FPD-Link III interconnect. If a fault condition occurs, the

Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x0C (Table 10). The DS90UH949A-Q1 will

detect any of the following conditions:

1. Cable open

2. “+” to “-” short

3. ”+” to GND short

4. ”–” to GND short

5. ”+” to battery short

6. ”–” to battery short

7. Cable is linked incorrectly (DOUT+/DOUT– connections reversed)

注

The device will detect any of the above conditions, but does not report specifically which

one has occurred.

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Feature Description (接下页)

7.3.13 Interrupt Pin (INTB)

The INTB pin is an active low interrupt output pin that acts as an interrupt for various local and remote interrupt

conditions (see registers 0xC6 and 0xC7 of Register Maps). For the remote interrupt condition, the INTB pin

works in conjunction with the INTB_IN pin on the deserializer. This interrupt signal, when configured, will

propagate from the deserializer to the serializer.

1. On the Serializer, set register 0xC6[5] = 1 and 0xC6[0] = 1

2. Deserializer INTB_IN pin is set LOW by some downstream device.

3. Serializer pulls INTB pin LOW. The signal is active LOW, so a LOW indicates an interrupt condition.

4. External controller detects INTB = LOW; to determine interrupt source, read the HDCP_ISR register.

5. A read to HDCP_ISR will clear the interrupt at the Serializer, releasing INTB.

6. The external controller typically must then access the remote device to determine downstream interrupt

source and clear the interrupt driving the Deserializer INTB_IN. This would be when the downstream device

releases the INTB_IN pin on the Deserializer. The system is now ready to return to step (2) at next falling

edge of INTB_IN.

7.3.14 Remote Interrupt Pin (REM_INTB)

REM_INTB will mirror the status of INTB_IN pin on the deserializer and does not need to be cleared. If the

serializer is not linked to the deserializer, REM_INTB will be high.

7.3.15 General-Purpose I/O

7.3.15.1 GPIO[3:0] and D_GPIO[3:0] Configuration

In normal operation, GPIO[3:0] may be used as general-purpose I/Os in either forward channel (outputs) or back

channel (inputs) mode. GPIO and D_GPIO modes may be configured from the registers. The same registers

configure either GPIO or D_GPIO, depending on the status of PORT1_SEL and PORT0_SEL bits (0x1E[1:0]).

D_GPIO operation requires 2-lane FPD-Link III mode. See 表 1 for GPIO enable and configuration.

表 1. GPIO Enable and Configuration

DESCRIPTION

DEVICE

Serializer

FORWARD CHANNEL

0x0F[3:0] = 0x3

0x1F[3:0] = 0x5

0x0E[7:4] = 0x3

0x1E[7:4] = 0x5

0x0E[3:0] = 0x3

0x1E[3:0] = 0x5

0x0D[3:0] = 0x3

0x1D[3:0] = 0x5

BACK CHANNEL

0x0F[3:0] = 0x5

0x1F[3:0] = 0x3

0x0E[7:4] = 0x5

0x1E[7:4] = 0x3

0x0E[3:0] = 0x5

0x1E[3:0] = 0x3

0x0D[3:0] = 0x5

0x1D[3:0] = 0x3

GPIO3 / D_GPIO3

Deserializer

Serializer

GPIO2 / D_GPIO2

GPIO1 / D_GPIO1

GPIO0 / D_GPIO0

Deserializer

Serializer

Deserializer

Serializer

Deserializer

7.3.15.2 Back Channel Configuration

The D_GPIO[3:0] pins can be configured to obtain different sampling rates depending on the mode as well as

back channel frequency. These different modes are controlled by a compatible deserializer. Consult the

appropriate deserializer datasheet for details on how to configure the back channel frequency. See 表 2 for

details about D_GPIOs in various modes.

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表 2. Back Channel D_GPIO Effective Frequency

D_GPIO EFFECTIVE FREQUENCY⁽¹⁾(kHz)

5-Mbps BC⁽²⁾10-Mbps BC⁽³⁾20-Mbps BC⁽⁴⁾

HSCC_MODE

(ON DES)

NUMBER OF

D_GPIOs

SAMPLES

PER FRAME

D_GPIOs

ALLOWED

MODE

000

011

010

001

Normal

Fast

400

666

1000

133

800

D_GPIO[3:0]

D_GPIO[1:0]

D_GPIO0

200

333

500

Fast

1333

2000

Fast

(1) The effective frequency assumes the worst-case back channel frequency (–20%) and a 4X sampling rate.

(2) 5 Mbps corresponds to BC FREQ SELECT = 0 and BC_HS_CTL = 0 on deserializer.

(3) 10 Mbps corresponds to BC FREQ SELECT = 1 and BC_HS_CTL = 0 on deserializer.

(4) 20 Mbps corresponds to BC FREQ SELECT = X and BC_HS_CTL = 1 on deserializer.

7.3.15.3 GPIO_REG[8:5] Configuration

GPIO_REG[8:5] are register-only GPIOs and may be programmed as outputs or read as inputs through local

GPIO_REG mode. See 表 3 for GPIO enable and configuration.

注

Local GPIO value may be configured and read either through local register access, or

remote register access through the Bidirectional Control Channel. Configuration and state

of these pins are not transported from serializer to deserializer as is the case for

GPIO[3:0].

表 3. GPIO_REG and GPIO Local Enable and Configuration

DESCRIPTION

0x11[7:4] = 0x01

0x11[7:4] = 0x09

0x11[7:4] = 0x03

0x11[3:0] = 0x1

0x11[3:0] = 0x9

0x11[3:0] = 0x3

0x10[7:4] = 0x1

0x10[7:4] = 0x9

0x10[7:4] = 0x3

0x10[3:0] = 0x1

0x10[3:0] = 0x9

0x10[3:0] = 0x3

0x0F[3:0] = 0x1

0x0F[3:0] = 0x9

0x0F[3:0] = 0x3

0x0E[7:4] = 0x1

0x0E[7:4] = 0x9

0x0E[7:4] = 0x3

0x0E[3:0] = 0x1

0x0E[3:0] = 0x9

0x0E[3:0] = 0x3

0x0D[3:0] = 0x1

0x0D[3:0] = 0x9

0x0D[3:0] = 0x3

FUNCTION

Output, L

GPIO_REG8

Output, H

Input, Read: 0x1D[0]

Output, L

GPIO_REG7

GPIO_REG6

GPIO_REG5

GPIO3

Output, H

Input, Read: 0x1C[7]

Output, L

Output, H

Input, Read: 0x1C[6]

Output, L

Output, H

Input, Read: 0x1C[5]

Output, L

Output, H

Input, Read: 0x1C[3]

Output, L

GPIO2

Output, H

Input, Read: 0x1C[2]

Output, L

GPIO1

Output, H

Input, Read: 0x1C[1]

Output, L

GPIO0

Output, H

Input, Read: 0x1C[0]

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7.3.16 SPI Communication

The SPI Control Channel uses the secondary link in a 2-lane FPD-Link III implementation. Two possible modes

are available: Forward Channel and Reverse Channel modes. In Forward Channel mode, the SPI Master is

located at the Serializer, such that the direction of sending SPI data is in the same direction as the video data. In

Reverse Channel mode, the SPI Master is located at the Deserializer, such that the direction of sending SPI data

is in the opposite direction as the video data.

The SPI Control Channel can operate in a high-speed mode when writing data, but must operate at lower

frequencies when reading data. During SPI reads, data is clocked from the slave to the master on the SPI clock

falling edge. Thus, the SPI read must operate with a clock period that is greater than the round-trip data latency.

On the other hand, data for SPI writes can be sent at much higher frequencies where the MISO pin can be

ignored by the master.

SPI data rates are not symmetrical for the two modes of operation. Data over the forward channel can be sent

much faster than data over the reverse channel.

注

SPI cannot be used to access Serializer / Deserializer registers.

7.3.16.1 SPI Mode Configuration

SPI is configured over the I2C using the High-Speed Control Channel Configuration (HSCC_CONTROL) register

0x43 on the deserializer. HSCC_MODE (0x43[2:0]) must be configured for either High-Speed, Forward Channel

SPI mode (110) or High-Speed, Reverse Channel SPI mode (111).

7.3.16.2 Forward Channel SPI Operation

In Forward Channel SPI operation, the SPI master located at the Serializer generates the SPI Clock (SPLK),

Master Out / Slave In data (MOSI), and active low Slave Select (SS). The Serializer oversamples the SPI signals

directly using the video pixel clock. The three sampled values for SPLK, MOSI, and SS are each sent on data

bits in the forward channel frame. At the Deserializer, the SPI signals are regenerated using the pixel clock. To

preserve setup and hold time, the Deserializer will hold MOSI data while the SPLK signal is high. The

Deserializer can also delay the SPLK by one pixel clock relative to the MOSI data, increasing the setup by one

pixel clock.

SERIALIZER

SPLK

MOSI

DESERIALIZER

SPLK

MOSI

图 11. Forward Channel SPI Write

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SERIALIZER

SPLK

MOSI

MISO

RD0

RD1

DESERIALIZER

SPLK

MOSI

MISO

RD0

RD1

图 12. Forward Channel SPI Read

7.3.16.3 Reverse Channel SPI Operation

In Reverse Channel SPI operation, the Deserializer samples the Slave Select (SS) and the SPI clock (SCLK) in

the internal oscillator clock domain. Upon detection of the active SPI clock edge, the Deserializer can also

sample the SPI data (MOSI). The SPI data samples are stored in a buffer to be passed to the Serializer over the

back channel. The Deserializer sends SPI information in a back channel frame to the Serializer. In each back

channel frame, the Deserializer sends an indication of the Slave Select value. The Slave Select should be

inactive (high) for at least one back-channel frame period to ensure propagation to the Serializer.

Because data is delivered in separate back channel frames and then buffered, the data may be regenerated in

bursts. 图 13 shows an example of the SPI data regeneration when the data arrives in three back channel

frames. The first frame delivered the SS active indication, the second frame delivered the first three data bits,

and the third frame delivers the additional data bits.

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DESERIALIZER

SPLK

MOSI

SPLK

SERIALIZER

MOSI

图 13. Reverse Channel SPI Write

For Reverse Channel SPI reads, the SPI master must wait for a round-trip response before the master can

generate the sampling edge of the SPI clock. This is similar to operation in Forward channel mode. Note that at

most one data/clock sample will be sent per back channel frame.

DESERIALIZER

SPLK

MOSI

MISO

RD0

RD1

SERIALIZER

SPLK

MOSI

MISO

RD0

RD1

图 14. Reverse Channel SPI Read

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For both Reverse Channel SPI writes and reads, the SPI_SS signal should be deasserted for at least one back

channel frame period.

表 4. SPI SS Deassertion Requirement

BACK CHANNEL FREQUENCY

DEASSERTION REQUIREMENT

5 Mbps

10 Mbps

20 Mbps

7.5 µs

3.75 µs

1.875 µs

7.3.17 Backward Compatibility

This FPD-Link III serializer is backward compatible to the DS90UH926Q-Q1 and DS90UH928Q-Q1 for TMDS

clock frequencies ranging from 25 MHz to 85 MHz. Enabling backward compatibility is not required. When paired

with a backward-compatible device, the serializer will auto-detect to 1-lane FPD-Link III on the primary channel

(DOUT0±).

7.3.18 Audio Modes

The DS90UH949A-Q1 supports several audio modes and functions:

•

HDMI Mode

DVI Mode

AUX Audio Channel

When using with the DS90UH926Q-Q1 because the default audio mode is I2S Surround Sound and

DS90UH926Q-Q1 can't receive more than 2 channels of audio while in 24-bit mode, the DS90UH949A-Q1 will

automatically transmit 18-bit video to a DS90UH926Q-Q1. To transmit 24-bit video to a DS90UH926Q-Q1, I2S

Surround must be disabled by writing to register 0x1A[0]=0.

7.3.18.1 HDMI Audio

The DS90UH949A-Q1 allows embedded audio in the HDMI interface to be transported over the FPD-Link III

serial link and output on the compatible deserializer. Depending on the number of channels, HDMI audio can be

output on several I2S pins on the deserializer, or it can be converted to TDM to output on one audio output pin

on the deserializer.

7.3.18.2 DVI I2S Audio Interface

The DS90UH949A-Q1 serializer features six I2S input pins that, when paired with a compatible deserializer,

supports 7.1 High-Definition (HD) Surround Sound audio applications. The bit clock (I2S_CLK) supports

frequencies between 1 MHz and the lesser of IN_CLK/2 or 13 MHz. Four I²S data inputs transport two channels

of I2S-formatted digital audio each, with each channel delineated by the word select (I2S_WC) input. Refer to 图

15 and 图 16 for I2S connection diagram and timing information.

Serializer

Bit Clock

I2S_CLK

I2S

Transmitter

Word Select

I2S_WC

I2S_Dx

Data

图 15. I2S Connection Diagram

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I2S_CLK

MSB

LSB MSB

LSB

I2S_Dx

图 16. I2S Frame Timing Diagram

表 5 covers several common I²S sample rates:

表 5. Audio Interface Frequencies

SAMPLE RATE (kHz)

I²S DATA WORD SIZE (BITS)

I²S CLK (MHz)

44.1

1.024

1.411

1.536

3.072

6.144

1.536

2.117

2.304

4.608

9.216

2.048

2.822

3.072

6.144

12.288

192

44.1

192

44.1

192

7.3.18.2.1 I2S Transport Modes

By default, audio is packetized and transmitted during video blanking periods in dedicated Data Island Transport

frames. Data Island frames may be disabled from control registers if Forward Channel Frame Transport of I2S

data is desired. In this mode, only I2S_DA is transmitted to a DS90UH928Q-Q1, DS90UH940A-Q1, or

DS90UH948A-Q1 deserializer. If connected to a DS90UH926Q-Q1 deserializer, I2S_DA and I2S_DB are

transmitted. Surround Sound Mode, which transmits all four I2S data inputs (I2S_D[A..D]), may only be operated

in Data Island Transport mode. This mode is only available when connected to a DS90UH928Q-Q1,

DS90UH940A-Q1, or DS90UH948A-Q1 deserializer.

7.3.18.2.2 I2S Repeater

I2S audio may be fanned-out and propagated in the repeater application. By default, data is propagated through

Data Island Transport during the video blanking periods. If frame transport is desired, then the I2S pins should be

connected from the deserializer to all serializers. Activating surround sound at the top-level deserializer

automatically configures downstream serializers and deserializers for surround sound transport using the Data

Island Transport. If 4-channel operation using the I2S_DA and I2S_DB only is desired, this mode must be

explicitly set in each serializer and deserializer control register throughout the repeater tree (see Table 10).

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7.3.18.3 AUX Audio Channel

The AUX Audio Channel is a single separate I2S audio data channel that may be transported independently of

the main audio stream received in either HDMI Mode or DVI Mode. This channel is shared with the GPIO[1:0]

interface and is supported by the DS90UH940A-Q1 and DS90UH948A-Q1 deserializers.

7.3.18.4 TDM Audio Interface

In addition to the I2S audio interface, the DS90UH949A-Q1 serializer also supports TDM format. A number of

specifications for TDM format are in common use, so the DS90UH949A-Q1 offers flexible support for word

length, bit clock, number of channels to be multiplexed, and so forth. For example, assume that the word clock

signal (I2S_WC) period = 256 × bit clock (I2S_CLK) time period. In this case, the DS90UH949A-Q1 can multiplex

4 channels with maximum word length of 64 bits each, or 8 channels with a maximum word length of 32 bits

each. 图 17 shows the multiplexing of 8 channels with 24-bit word length in a format similar to I2S.

t1/f_S(256 BCKs at Single Rate, 128 BCKs at Dual Rate)t

I2S_WC

I2S_CLK

Ch 1

Ch 2

Ch 3

Ch 4

Ch 5

Ch 6

Ch 7

Ch 8

t32 BCKst

I²S Mode

DIN1

23 22

(Single)

图 17. TDM Format

7.3.19 HDCP

The HDCP Cipher function is implemented in the serializer per HDCP v1.4 specification. The serializer provides

HDCP encryption of audiovisual content when connected to an HDCP capable source. HDCP authentication and

shared key generation is performed using the HDCP Control Channel, which is embedded in the forward and

backward channels of the serial link. On-chip Non-Volatile Memory (NVM) is used to store the HDCP keys. The

confidential HDCP keys are loaded by TI during the manufacturing process and are not accessible external to the

device.

7.3.19.1 HDCP I2S Audio Encryption

Depending on the quality and specifications of the audiovisual source, HDCP encryption of digital audio may be

required. When HDCP is active, packetized Data Island Transport audio is also encrypted along with the video

data per HDCP v.1.4. I2S audio transmitted in Forward Channel Frame Transport mode is not encrypted. System

designers should consult the specific HDCP specifications to determine if encryption of digital audio is required

by the specific application audiovisual source.

7.3.20 Built-In Self Test (BIST)

An optional At-Speed Built-In Self Test (BIST) feature supports testing of the high-speed serial link and back

channel without external data connections. This is useful in the prototype stage, equipment production, in-system

test, and system diagnostics.

7.3.20.1 BIST Configuration and Status

The BIST mode is enabled at the deserializer by either the BISTEN pin or the BIST configuration register. The

test may select either an external TMDS clock or the internal Oscillator clock (OSC) frequency. In the absence of

the TMDS clock, the user can select the internal OSC frequency at the deserializer through the BISTC pin or

BIST configuration register.

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When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer through the Back

Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test

pattern and monitors it for errors. The deserializer PASS output pin toggles to flag each frame received that

contained one or more errors. The serializer also tracks errors indicated by the CRC fields in each back channel

frame.

The BIST status can be monitored real time on the deserializer PASS pin, with each detected error resulting in a

half pixel clock period toggled LOW. After BIST is deactivated, the result of the last test is held on the PASS

output until a reset (through either a new BIST test or Power Down). A high on PASS indicates NO ERRORS

were detected. A Low on PASS indicates one or more errors were detected. The duration of the test is controlled

by the pulse width applied to the deserializer BISTEN pin. LOCK is valid throughout the entire duration of BIST.

See 图 18 for the BIST mode flow diagram.

Step 1: The Serializer is paired with another FPD-Link III Deserializer and BIST Mode is enabled through the

BISTEN pin or through the register on the Deserializer. Right after BIST is enabled, part of the BIST sequence

requires that bit 0x04[5] is toggled locally on the Serializer (set 0x04[5]=1, then set 0x04[5]=0). The desired clock

source is selected either through the deserializer BISTC pin or through register on the Deserializer.

Step 2: An all-zeros pattern is balanced, scrambled, randomized, and sent through the FPD-Link III interface to

the deserializer. Once the serializer and the deserializer are in BIST mode and the deserializer acquires Lock,

the PASS pin of the deserializer goes high and BIST starts checking the data stream. If an error in the payload (1

to 35) is detected, the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS

output can be monitored and counted to determine the payload error rate.

Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the

data. The final test result is held on the PASS pin. If the test ran error-free, the PASS output will remain HIGH. If

one or more errors were detected, the PASS output will output constant LOW. The PASS output state is held

until a new BIST is run, the device is RESET, or the device is powered down. The BIST duration is user-

controlled by the duration of the BISTEN signal.

Step 4: The link returns to normal operation after the deserializer BISTEN pin is low. 图 19 shows the waveform

diagram of a typical BIST test for two cases: Case 1 is error-free, and Case 2 shows one with multiple errors. In

most cases, it is difficult to generate errors due to the robustness of the link (differential data transmission and so

forth), thus they may be introduced by greatly extending the cable length, faulting the interconnect medium, or

reducing signal condition enhancements (Rx Equalization).

For more information on using BIST, refer to white paper: Using BIST on 94x.

Normal

Step 1: DES in BIST

BIST

Wait

Step 2: Wait, SER in BIST

BIST

start

Step 3: DES in Normal Mode -

check PASS

BIST

stop

Step 4: DES/SER in Normal

图 18. BIST Mode Flow Diagram

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7.3.20.2 Forward Channel and Back Channel Error Checking

While in BIST mode, the serializer stops sampling the FPD-Link input pins and switches over to an internal all

zeroes pattern. The internal all zeroes pattern goes through the scrambler, DC-balancing, and so forth, and is

transmitted over the serial link to the deserializer. The deserializer, on locking to the serial stream, compares the

recovered serial stream with all zeroes and records any errors in status registers. Errors are also dynamically

reported on the PASS pin of the deserializer.

The back channel data is checked for CRC errors once the serializer locks onto the back channel serial stream,

as indicated by link detect status (register bit 0x0C[0] - Table 10). CRC errors are recorded in an 8-bit register in

the deserializer. The register is cleared when the serializer enters BIST mode. As soon as the serializer enters

BIST mode, the functional mode CRC register starts recording any back channel CRC errors. The BIST mode

CRC error register is active in BIST mode only and keeps a record of the last BIST run until the register is

cleared or the serializer enters BIST mode again.

BISTEN

(DES)

TxCLKOUT±

TxOUT[3:0]±

DATA

(internal)

PASS

Prior Result

PASS

FAIL

X = bit error(s)

DATA

(internal)

PASS

BIST

Result

Held

Normal

PRBS

Normal

BIST Test

BIST Duration

图 19. BIST Waveforms in Conjunction With Deserializer Signals

7.3.21 Internal Pattern Generation

The DS90UH949A-Q1 serializer provides an internal pattern generation feature. It allows basic testing and

debugging of an integrated panel. The test patterns are simple and repetitive and allow for a quick visual

verification of panel operation. As long as the device is not in power down mode, the test pattern will be

displayed even if no input is applied. If no clock is received, the test pattern can be configured to use a

programmed oscillator frequency. For detailed information, refer to AN-2198 Exploring Int Test Patt Gen Feat of

720p FPD-Link III Devices (SNLA132).

7.3.21.1 Pattern Options

The DS90UH949A-Q1 serializer pattern generator is capable of generating 17 default patterns for use in basic

testing and debugging of panels. Each can be inverted using register bits (Table 10) shown below:

1. White/Black (default/inverted)

2. Black/White

3. Red/Cyan

4. Green/Magenta

5. Blue/Yellow

6. Horizontally Scaled Black to White/White to Black

7. Horizontally Scaled Black to Red/Cyan to White

8. Horizontally Scaled Black to Green/Magenta to White

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9. Horizontally Scaled Black to Blue/Yellow to White

10. Vertically Scaled Black to White/White to Black

11. Vertically Scaled Black to Red/Cyan to White

12. Vertically Scaled Black to Green/Magenta to White

13. Vertically Scaled Black to Blue/Yellow to White

14. Custom Color (or its inversion) configured in PGRS

15. Black-White/White-Black Checkerboard (or custom checkerboard color, configured in PGCTL)

16. YCBR/RBCY VCOM pattern, orientation is configurable from PGCTL

17. Color Bars (White, Yellow, Cyan, Green, Magenta, Red, Blue, Black) – Note: not included in the auto-

scrolling feature

Additionally, the Pattern Generator incorporates one user-configurable, full-screen, 24-bit color controlled by the

PGRS, PGGS, and PGBS registers. This is pattern #14. One of the pattern options is statically selected in the

PGCTL register when Auto-Scrolling is disabled. The PGTSC and PGTSO1-8 registers control the pattern

selection and order when Auto-Scrolling is enabled.

7.3.21.2 Color Modes

By default, the Pattern Generator operates in 24-bit color mode where all bits of the Red, Green, and Blue

outputs are enabled. 18-bit color mode can be activated from the configuration registers (Table 10). In 18-bit

mode, the 6 most significant bits (bits 7-2) of the Red, Green, and Blue outputs are enabled. The 2 least

significant bits will be 0.

7.3.21.3 Video Timing Modes

The Pattern Generator has two video timing modes – external and internal. In external timing mode, the Pattern

Generator detects the video frame timing present on the DE and VS inputs. If Vertical Sync signaling is not

present on VS, the Pattern Generator determines Vertical Blank by detecting when the number of inactive pixel

clocks (DE = 0) exceeds twice the detected active line length. In internal timing mode, the Pattern Generator

uses custom video timing as configured in the control registers. The internal timing generation may also be

driven by an external clock. By default, external timing mode is enabled. Internal timing or Internal timing with

External Clock are enabled by the control registers (Table 10).

7.3.21.4 External Timing

In external timing mode, the Pattern Generator passes the incoming DE, HS, and VS signals unmodified to the

video control outputs after a two pixel clock delay. The Pattern Generator extracts the active frame dimensions

from the incoming signals to properly scale the brightness patterns. If the incoming video stream does not use

the VS signal, the Pattern Generator determines the Vertical Blank time by detecting a long period of pixel clocks

without DE asserted.

7.3.21.5 Pattern Inversion

The Pattern Generator also incorporates a global inversion control, located in the PGCFG register, which causes

the output pattern to be bitwise-inverted. For example, the full screen Red pattern becomes full-screen cyan, and

the Vertically Scaled Black to Green pattern becomes Vertically Scaled White to Magenta.

7.3.21.6 Auto Scrolling

The Pattern Generator supports an Auto-Scrolling mode, in which the output pattern cycles through a list of

enabled pattern types. A sequence of up to 16 patterns may be defined in the registers. The patterns may

appear in any order in the sequence and may also appear more than once.

7.3.21.7 Additional Features

Additional pattern generator features can be accessed through the Pattern Generator Indirect Register Map. It

consists of the Pattern Generator Indirect Address (PGIA reg_0x66 — Table 10) and the Pattern Generator

Indirect Data (PGID reg_0x67 — Table 10). See AN-2198 Exploring Int Test Patt Gen Feat of 720p FPD-Link III

Devices (SNLA132).

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7.3.22 Spread Spectrum Clock Tolerance

The DS90UH949A-Q1 (for DVI mode) tolerates a spread spectrum input clock to help reduce EMI. The following

triangular SSC profile is supported:

•

Frequency deviation ≤ 2.5%

Modulation rate ≤ 100 kHz

Note: Maximum frequency deviation and maximum modulation rate are not supported simultaneously. Some

typical examples:

•

Frequency deviation: 2.5%, modulation rate: 50 kHz

Frequency deviation: 1.25%, modulation rate: 100 kHz

7.4 Device Functional Modes

7.4.1 Mode Select Configuration Settings (MODE_SEL[1:0])

Configuration of the device may be done through the MODE_SEL[1:0] input pins, or through the configuration

the MODE_SEL[1:0] inputs. See 表 7 and 表 8. These values will be latched into register location during power-

up:

表 6. MODE_SEL[1:0] Settings

MODE

SETTING

FUNCTION

Look for remote EDID, if none found, use internal SRAM EDID. Can be overridden

from register. Remote EDID address may be overridden from default 0xA0.

EDID_SEL: Display ID Select

Use external local EDID.

HDMI audio.

AUX_I2S: AUX Audio Channel

HDMI + AUX audio channel.

Internal HDCP/HDMI control.

EXT_CTL: External Controller

Override

External HDCP/HDMI control from I2C interface pins.

Enable FPD-Link III for twisted pair cabling.

Enable FPD-Link III for coaxial cabling.

Use internal SRAM EDID.

COAX: Cable Type

REM_EDID_LOAD: Remote

EDID Load

If available, remote EDID is copied into internal SRAM EDID.

1.8 V

R₃

R₄

V_R4

MODE_SEL0

MODE_SEL1

1.8 V

Serializer

R₅

V_R6

R₆

图 20. MODE_SEL[1:0] Connection Diagram

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表 7. Configuration Select (MODE_SEL0)

SUGGESTED

RATIO

V_R4/V_DD18

TARGET V_R4

(V)

RESISTOR

NO.

RESISTOR PULLUP

PULLDOWN R4 kΩ

R3 kΩ (1% tol)

EDID_SEL

AUX_I2S

(1% tol)

OPEN

Any value less than

100⁽¹⁾

0.208

0.553

0.668

0.374

0.995

1.202

118

82.5

68.1

30.9

102

137

(1) This resistor does not need to be 1% tolerance. 5% is acceptable.

表 8. Configuration Select (MODE_SEL1)

SUGGESTED

RESISTOR

PULLUP R5

kΩ (1% tol)

SUGGESTED

RESISTOR

PULLDOWN R6

kΩ (1% tol)

RATIO

V_R6/V_DD18

TARGET V_R6

(V)

REM_EDID_LO

NO.

EXT_CTL

COAX

Any value less than

100⁽¹⁾

OPEN

0.208

0.323

0.440

0.553

0.668

0.789

0.374

0.582

0.792

0.995

1.202

1.420

118

107

113

82.5

68.1

56.2

30.9

51.1

88.7

102

137

210

Any value less

than 100⁽¹⁾

1.8

OPEN

(1) This resistor does not need to be 1% tolerance. 5% is acceptable.

The strapped values can be viewed and/or modified in the following locations:

•

EDID_SEL : Latched into BRIDGE_CTL[0], EDID_DISABLE (0x4F[0]).

AUX_I2S : Latched into BRIDGE_CFG[1], AUDIO_MODE[1] (0x54[1]).

EXT_CTL: Latched into BRIDGE_CFG[7], EXT_CONTROL (0x54[7]).

COAX : Latched into DUAL_CTL1[7], COAX_MODE (0x5B[7]).

REM_EDID_LOAD : Latched into BRIDGE_CFG[5] (0x54[5]).

7.4.2 FPD-Link III Modes of Operation

The FPD-Link III transmit logic supports several modes of operation, dependent on the downstream receiver as

well as the video being delivered. The following modes are supported:

7.4.2.1 Single Link Operation

Single Link mode transmits the video over a single FPD-Link III to a single receiver. Single link mode supports

frequencies up to 105 MHz for 24-bit video when paired with the DS90UH940A-Q1/DS90UH948A-Q1. This mode

is compatible with the DS90UH926Q-Q1/DS90UH928Q-Q1 when operating below 85 MHz. If the downstream

device is capable, the secondary FPD-Link III link could be used for high-speed control.

In Forced Single mode (set through DUAL_CTL1 register), the secondary TX Phy and back channel are

disabled.

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7.4.2.2 Dual Link Operation

In Dual Link mode, the FPD-Link III TX splits a single video stream and sends alternating pixels on two

downstream links. If HDCP is enabled, a single HDCP connection is created for the video that is sent on the two

links. The receiver must be a DS90UH948A-Q1 or DS90UH940A-Q1, capable of receiving the dual-stream video.

Dual link mode is capable of supporting an HDMI clock frequency of up to 210 MHz, with each FPD-Link III TX

port running at one-half the frequency. This allows support for full 2K video. The secondary FPD-Link III link

could be used for high-speed control.

Dual Link mode may be automatically configured when connected to a DS90UH948A-Q1/DS90UH940A-Q1, if

the video meets minimum frequency requirements. Dual Link mode may also be forced using the DUAL_CTL1

For dual lane operation, if the High-Speed Control Channel (HSCC) is desired, force the back channel

capabilities for Port 1.

•

Force the backchannel capability for Port1:

–

Set Reg0x1E=0x02 (Select Port1 in Port Select register)

Set Reg0x20=0x8F (Make Port1 Dual link capable in Deserializer Capabilities register)

Set Reg0x1E=0x01 (Select Port0 in Port Select register to restore the register default value)

•

For forcing Dual Lane mode, use the following configuration:

Set Reg0x5B[2:0]=011b (Disable Auto-detect and Force Dual Link mode in DUAL_CTL1 register)

–

Any device configuration including this one should be written as a part of the 949A Init A sequence as shown in

7.4.2.3 Replicate Mode

In this mode, the FPD-Link III TX operates as a 1:2 HDCP Repeater. A second HDCP core is implemented to

support HDCP authentication and encryption to independent HDCP-capable receivers. The same video (up to

105 MHz, 24-bit color) is delivered to each receiver.

Replicate mode may be automatically configured when connected to two independent Deserializers.

7.4.2.4 Auto-Detection of FPD-Link III Modes

The DS90UH949A-Q1 automatically detects the capabilities of downstream links and can resolve whether a

single device, dual-capable device, or multiple single link devices are connected.

In addition to the downstream device capabilities, the DS90UH949A-Q1 will be able to detect the HDMI pixel

clock frequency to select the proper operating mode.

If the DS90UH949A-Q1 detects two independent devices, it will operate in Replicate mode, sending the single

channel video on both connections. If the device detects a device on the secondary link, but not the first, it can

send the video only on the second link.

Auto-detection can be disabled to allow forced modes of operation using the Dual Link Control Register

(DUAL_CTL1).

The frequency detection circuit may cause change in Single / Dual mode during a temperature ramp. When the

ambient temperature around the DS90UH949A-Q1 changes by more than 40°C and when PCLK is between 60

MHz and 78 MHz, the auto-detect feature can switch device configuration from Single-lane to Dual-lane mode (or

vice-versa) even though the input PCLK has not changed. This causes a configuration change in Deserializer

resulting in a momentary loss of lock that may result in display flicker. It is recommended to configure the device

to force Single or Dual Lane mode of operation.

•

For forcing Single Lane mode, use the following configuration:

–

If the Deserializer is set in HSCC mode prior to forcing Single Lane mode, force the backchannel

capability for Port1:

–

Set Reg0x1E=0x02 (Select Port1 in Port Select register)

Set Reg0x20=0x8F (Make Port1 Dual link capable in Deserializer Capabilities register)

Set Reg0x1E=0x01 (Select Port0 in Port Select register to restore the register default value)

–

Set Reg0x5B[2:0]=100b (Enable Auto-detect and disable Dual Link mode in DUAL_CTL1 register)

•

For forcing Dual Lane mode, use the following configuration:

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–

If the Deserializer is set in HSCC mode prior to forcing Dual Lane mode, force the backchannel capability

for Port1:

–

Set Reg0x1E=0x02 (Select Port1 in Port Select register)

Set Reg0x20=0x8F (Make Port1 Dual link capable in Deserializer Capabilities register)

–

Set Reg0x5B[2:0]=011b (Disable Auto-detect and Force Dual Link mode in DUAL_CTL1 register)

Any device configuration including this one should be written as a part of the 949A Init A sequence as shown in

7.4.2.5 Frequency detection circuit may reset the FPD-Link III PLL during a temperature ramp

When ambient temperature around the DS90UH949A-Q1 changes by more than 40°C, the frequency detection

logic in the device can RESET the FPD-Link III PLL even though the input PCLK has not changed. This behavior

may result in a loss of lock in the Deserializer and flicker on the system display.

The following programming sequence is required for all systems. This should be written after the user register

configuration of the DS90UH949A-Q1 and downstream Deserializer configuration.

•

Disable the “Reset FPD-Link III PLL on Frequency Change” feature after the DS90UH949A-Q1 power-up

–

Set Reg0x5B[5]=0b (Disable PLL reset feature via RST_PLL_FREQ field in DUAL_CTL1 register)

Any device configuration including this one should be written as a part of the 949A Init A sequence as shown in

7.5 Programming

7.5.1 Serial Control Bus

This serializer may also be configured by the use of a I2C-compatible serial control bus. Multiple devices may

share the serial control bus (up to 8 device addresses supported). The device address is set through a resistor

divider (R1 and R2 — see 图 21) connected to the IDx pin.

V_DD18

V_DDI2C

R₁

R₂

VR2

4.7 k

IDx

4.7 k

HOST

SER

SCL

SDA

SCL

SDA

To other

Devices

图 21. Serial Control Bus Connection

The serial control bus consists of two signals, SCL and SDA. SCL is a Serial Bus Clock Input. SDA is the Serial

Bus Data Input / Output signal. Both SCL and SDA signals require an external pullup resistor to V_DD18or V_DD33

For most applications, a 4.7-kΩ pullup resistor is recommended. However, the pullup resistor value may be

adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven Low.

The IDx pin configures the control interface to one of 8 possible device addresses. A pullup resistor and a

pulldown resistor may be used to set the appropriate voltage on the IDx input pin. See Table 10 for more

information. 1% or 5% resistors can be used.

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Programming (接下页)

表 9. Serial Control Bus Addresses for IDx

SUGGESTED

RESISTOR R1 kΩ

(1% tol)

SUGGESTED

RESISTOR R2 kΩ

(1% tol)

RATIO

NO.

IDEAL V_R2

(V)

7-BIT ADDRESS

8-BIT ADDRESS

V_R2/ V_DD18

OPEN

Any value less than

100⁽¹⁾

0x0C

0x18

0.208

0.323

0.440

0.553

0.668

0.789

0.374

0.582

0.792

0.995

1.202

1.420

1.8

118

107

113

82.5

68.1

56.2

30.9

51.1

88.7

102

0x0E

0x10

0x12

0x14

0x16

0x18

0x1A

0x1C

0x20

0x24

0x28

0x2C

0x30

0x34

137

210

Any value less than

100⁽¹⁾

OPEN

(1) This resistor does not need to be 1% tolerance. 5% is acceptable.

The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when

SCL transitions Low while SDA is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See

图 22.

SDA

SCL

START condition, or

START repeat condition

STOP condition

图 22. Start and Stop Conditions

To communicate with an I2C slave, the host controller (master) sends the slave address and listens for a

response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is

addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address does not

match a slave address of the device, it Not-acknowledges (NACKs) the master by letting SDA be pulled High.

ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs

after every data byte is successfully received. When the master is reading data, the master ACKs after every

data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop

reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus

begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop

condition. A READ is shown in 图 23 and a WRITE is shown in 图 24.

Slave Address

Data

图 23. Serial Control Bus — Read

Slave Address

Data

图 24. Serial Control Bus — Write

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The I2C Master located at the serializer must support I2C clock stretching. For more information on I2C interface

requirements and throughput considerations, refer to the TI Application Note I2C Communication Over FPD-Link

III With Bidirectional Control Channel (SNLA131).

7.5.2 Multi-Master Arbitration Support

The Bidirectional Control Channel in the FPD-Link III devices implements I2C-compatible bus arbitration in the

proxy I2C master implementation. When sending a data bit, each I2C master senses the value on the SDA line.

If the master is sending a logic 1 but senses a logic 0, the master has lost arbitration. It will stop driving SDA and

retry the transaction when the bus becomes idle. Thus, multiple I2C masters may be implemented in the system.

Ensure that all I2C masters on the bus support multi-master arbitration.

Assign I2C addresses with more than a single bit set to 1 for all devices on the I2C bus. 0x6A, 0x7B, and 0x37

are examples of good choices for an I2C address. 0x40 and 0x20 are examples of bad choices for an I2C

address.

If the system does require master-slave operation in both directions across the BCC, some method of

communication must be used to ensure only one direction of operation occurs at any time. The communication

method could include using available read/write registers in the deserializer to allow masters to communicate

with each other to pass control between the two masters. An example would be to use register 0x18 or 0x19 in

the deserializer as a mailbox register to pass control of the channel from one master to another.

7.5.3 I2C Restrictions on Multi-Master Operation

The I2C specification does not provide for arbitration between masters under certain conditions. The system

should make sure the following conditions cannot occur to prevent undefined conditions on the I2C bus:

•

One master generates a repeated Start while another master is sending a data bit.

One master generates a Stop while another master is sending a data bit.

One master generates a repeated Start while another master sends a Stop.

Note that these restrictions mainly apply to accessing the same register offsets within a specific I2C slave.

7.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices

When using the latest generation of FPD-Link III devices, DS90UH949A-Q1 or DS90UH940A-Q1/DS90UH948A-

Q1 registers may be accessed simultaneously from both local and remote I2C masters. These devices have

internal logic to properly arbitrate between sources to allow proper read and write access without risk of

corruption.

Access to remote I2C slaves would still be allowed in only one direction at a time.

7.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices

When using older FPD-Link III devices, simultaneous access to serializer or deserializer registers from both local

and remote I2C masters may cause incorrect operation, thus restrictions should be imposed on accessing of

serializer and deserializer registers. The likelihood of an error occurrence is relatively small, but it is possible for

collision on reads and writes to occur, resulting in an read or write error.

Two basic options are recommended. The first is to allow device register access only from one controller. This

would allow only the Host controller to access the serializer registers (local) and the deserializer registers

(remote). A controller at the deserializer would not be allowed to access the deserializer or serializer registers.

The second basic option is to allow local register access only with no access to remote serializer or deserializer

registers. The Host controller would be allowed to access the serializer registers while a controller at the

deserializer could access those register only. Access to remote I2C slaves would still be allowed in one direction.

In a very limited case, remote and local access could be allowed to the deserializer registers at the same time.

deserializer register. This allows a simple method of passing control of the Bidirectional Control Channel from

one master to another.

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7.5.6 Restrictions on Control Channel Direction for Multi-Master Operation

Only one direction should be active at any time across the Bidirectional Control Channel. If both directions are

required, some method of transferring control between I2C masters should be implemented.

7.5.7 Prevention of I2C Faults During Abrupt System Faults

In rare instances, FPD-Link III back-channel data errors caused by system fault conditions (e.g. abrupt power

downs of the remote deserializer or cable disconnects) may result in the DS90UH949A-Q1 sending inadvertent

I2C transactions on the local I2C bus prior to determining loss of valid back channel signal. For minimizing

impact of these types of events:

•

Set DS90UH949A-Q1 register 0x16 = 0x02 to minimize the duration of inadvertent I2C events. Any device

configuration including this one should be written as a part of the 949A Init A sequence as shown in

•

Ensure all I2C masters on the bus support multi-master arbitration

–

0x6A, 0x7B, and 0x37 are examples of good choices for an I2C address

0x40 and 0x20 are examples of bad choices for an I2C address

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7.6 Register Maps

Table 10. Serial Control Bus Registers

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

FUNCTION

(hex)

BIT(S)

DESCRIPTION

0x00

I2C Device ID

7:1

Strap

0x00

DEVICE_ID

ID Setting

7-bit address of Serializer. Defaults to address configured by the IDx strap pin.

I2C ID setting.

0: Device I2C address is from IDx strap pin (default).

1: Device I2C address is from 0x00[7:1].

0x01

Reset

7:5

0x00

Reserved.

A software I2C

reset command

issued by writing

to register 0x01

is supported only

when operating

I2C in the 3.3V

mode.

HDMI Reset

HDMI Digital Reset.

Resets the HDMI digital block. This bit is self-clearing.

0: Normal operation.

1: Reset.

3:2

Reserved.

Digital

RESET1

Reset the entire digital block including registers. This bit is self-clearing.

0: Normal operation (default).

1: Reset.

Following setting of this bit, software should also set bit 0x4F[1] (BRIDGE_CTL register).

This will restore register values that are initially loaded from Non- Volatile Memory to their

default state.

Digital

RESET0

Reset the entire digital block except registers. This bit is self-clearing.

0: Normal operation (default).

1: Reset.

Registers which are loaded by pin strap will be restored to their original strap value when

this bit is set. These registers show 'Strap' as their default value in this table.

Registers which are loaded by pin strap will be restored to their original strap value when

this bit is set. These registers show 'Strap' as their default value in this table. Registers

0x015, 0x18, 0x19, 0x1A, 0x48-0x55, 0xC0, 0xC2, 0xC3, 0xC6, 0xC8, and 0xCE are also

restored to their default value when this bit is set.

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Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x03

General

0xD2

Back channel

Enable/disable back channel CRC Checker.

Configuration

CRC Checker 0: Disable.

Enable

1: Enable (default).

Reserved.

I2C Remote

Write Auto

Acknowledge

Port0/Port1

Automatically acknowledge I2C remote writes. When enabled, I2C writes to the

Deserializer (or any remote I2C Slave, if I2C PASS ALL is enabled) are immediately

acknowledged without waiting for the Deserializer to acknowledge the write. This allows

higher throughput on the I2C bus. Note: this mode will prevent any NACK from a remote

device from reaching the I2C master.

0: Disable (default).

1: Enable.

If PORT1_SEL is set, this register controls Port1 operation.

Filter Enable

HS, VS, DE two-clock filter. When enabled, pulses less than two full TMDS clock cycles

on the DE, HS, and VS inputs will be rejected.

0: Filtering disable.

1: Filtering enable (default).

I2C Pass-

through

Port0/Port1

I2C pass-through mode. Read/Write transactions matching any entry in the Slave Alias

registers will be passed through to the remote Deserializer.

0: Pass-through disabled (default).

1: Pass-through enabled.

If PORT1_SEL is set, this register controls Port1 operation.

Reserved.

TMDS Clock

Auto

Switch over to internal oscillator in the absence of TMDS Clock.

0: Disable auto-switch.

1: Enable auto-switch (default).

Reserved.

0x04

Mode Select

0x80

Failsafe State Input failsafe state.

0: Failsafe to High.

1: Failsafe to Low (default).

Reserved.

CRC Error

Reset

Clear back channel CRC Error counters. This bit is NOT self-clearing.

0: Normal operation (default).

1: Clear counters.

Video gate

Set to 1. This prevents video from being set during the blanking interval.

Reserved.

3:0

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Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x05

I2C Control

7:5

4:3

0x00

Reserved.

SDA Output

Delay

Configures output delay on the SDA output. Setting this value will increase output delay

in units of 40ns.

Nominal output delay values for SCL to SDA are:

00: 240ns (default).

01: 280ns.

10: 320ns.

11: 360ns.

Local Write

Disable

Disable remote writes to local registers. Setting this bit to 1 will prevent remote writes to

local device registers from across the control channel. This prevents writes to the

Serializer registers from an I2C master attached to the Deserializer. Setting this bit does

not affect remote access to I2C slaves at the Serializer.

0: Enable (default).

1: Disable.

I2C Bus Timer Speed up I2C bus Watchdog Timer.

Speedup 0: Watchdog Timer expires after approximately 1s (default).

1: Watchdog Timer expires after approximately 50µs.

I2C Bus Timer Disable I2C bus Watchdog Timer. The I2C Watchdog Timer may be used to detect when

Disable

the I2C bus is free or hung up following an invalid termination of a transaction. If SDA is

high and no signaling occurs for approximately 1s, the I2C bus will be assumed to be

free. If SDA is low and no signaling occurs, the device will attempt to clear the bus by

driving 9 clocks on SCL.

0: Enable (default).

1: Disable.

0x06

DES ID

7:1

0x00

DES Device ID 7-bit I2C address of the remote Deserializer. A value of 0 in this field disables I2C access

Port0/Port1

to the remote Deserializer. This field is automatically configured by the Bidirectional

Control Channel once RX Lock has been detected. Software may overwrite this value,

but should also assert the FREEZE DEVICE ID bit to prevent overwriting by the

Bidirectional Control Channel.

If PORT1_SEL is set, this register indicates the Deserializer Device ID for the

Deserializer attached to Port1.

Freeze Device Freeze Deserializer Device ID.

1: Prevents auto-loading of the Deserializer Device ID by the Bidirectional Control

Port0/Port1

Channel. The ID will be frozen at the value written.

0: Allows auto-loading of the Deserializer Device ID from the Bidirectional Control

Channel.

If PORT1_SEL is set, this register is with reference to Port1.

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Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x07

Slave ID[0]

7:1

0x00

Slave ID 0

Port0/Port1

7-bit I2C address of the remote Slave 0 attached to the remote Deserializer. If an I2C

transaction is addressed to Slave Alias ID 0, the transaction will be remapped to this

address before passing the transaction across the Bidirectional Control Channel to the

Deserializer. A value of 0 in this field disables access to the remote Slave 0.

If PORT1_SEL is set, this register is with reference to Port1.

Reserved.

0x08

Slave Alias[0]

CRC Errors

7:1

0x00

Slave Alias ID 7-bit Slave Alias ID of the remote Slave 0 attached to the remote Deserializer. The

transaction will be remapped to the address specified in the Slave ID 0 register. A value

of 0 in this field disables access to the remote Slave 0.

Port0/Port1

If PORT1_SEL is set, this register is with reference to Port1.

Reserved.

0x0A

0x0B

0x0C

7:0

0x00

CRC Error

LSB

Number of back channel CRC errors – 8 least significant bits. Cleared by 0x04[5].

If PORT1_SEL is set, this register is with reference to Port1.

Port0/Port1

7:0

CRC Error

MSB

Number of back channel CRC errors – 8 most significant bits. Cleared by 0x04[5].

If PORT1_SEL is set, this register is with reference to Port1.

Port0/Port1

General Status

7:5

Reserved.

0x00

Link Lost

Link lost flag for selected port:

Port0/Port1

This bit indicates that loss of link has been detected. This register bit will stay high until

cleared using the CRC Error Reset in register 0x04.

If PORT1_SEL is set, this register is with reference to Port1.

BIST CRC

Error

Port0/Port1

Back channel CRC error(s) during BIST communication with Deserializer. This bit is

cleared upon loss of link, restart of BIST, or assertion of CRC Error Reset bit in 0x04[5].

0: No CRC errors detected during BIST.

1: CRC error(s) detected during BIST.

If PORT1_SEL is set, this register is with reference to Port1.

TMDS Clock

Detect

Pixel clock status:

0: Valid clock not detected at HDMI input.

1: Valid clock detected at HDMI input.

DES Error

Port0/Port1

CRC error(s) during normal communication with Deserializer. This bit is cleared upon

loss of link or assertion of 0x04[5].

0: No CRC errors detected.

1: CRC error(s) detected.

If PORT1_SEL is set, this register is with reference to Port1.

Link Detect

Port0/Port1

Link detect status:

0: Cable link not detected.

1: Cable link detected.

If PORT1_SEL is set, this register is with reference to Port1.

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Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x0D

GPIO0

Configuration

7:4

Revision ID

Revision ID.

0x00

GPIO0 Output Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function

Value

D_GPIO0

Output Value

is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled.

0: Output LOW (default).

1: Output HIGH.

If PORT1_SEL is set, this register controls the D_GPIO0 pin.

2:0

GPIO0 Mode

D_GPIO0

Mode

Determines operating mode for the GPIO pin:

x00: Functional input mode.

x10: TRI-STATE™.

001: GPIO mode, output.

011: GPIO mode, input.

101: Remote-hold mode. The GPIO pin will be an output, and the value is received from

the remote Deserializer. In remote-hold mode, data is maintained on link loss.

111: Remote-default mode. The GPIO pin will be an output, and the value is received

from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output

on link loss.

If PORT1_SEL is set, this register controls the D_GPIO0 pin.

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Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x0E

GPIO1 and

GPIO2

ConfigurationD_

GPIO1 and

D_GPIO2

0x00

GPIO2 Output Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function

Value

D_GPIO2

Output Value

is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled.

0: Output LOW (default).

1: Output HIGH.

If PORT1_SEL is set, this register controls the D_GPIO2 pin.

Configuration

6:4

GPIO2 Mode

D_GPIO2

Mode

Determines operating mode for the GPIO pin:

x00: Functional input mode.

x10: TRI-STATE™.

001: GPIO mode, output.

011: GPIO mode, input.

101: Remote-hold mode. The GPIO pin will be an output, and the value is received from

the remote Deserializer. In remote-hold mode, data is maintained on link loss.

111: Remote-default mode. The GPIO pin will be an output, and the value is received

from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output

on link loss.

If PORT1_SEL is set, this register controls the D_GPIO2 pin.

GPIO1 Output Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function

Value

D_GPIO1

Output Value

is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled.

0: Output LOW (default).

1: Output HIGH.

If PORT1_SEL is set, this register controls the D_GPIO1 pin.

2:0

GPIO1 Mode

D_GPIO1

Mode

Determines operating mode for the GPIO pin:

x00: Functional input mode.

x10: TRI-STATE™.

001: GPIO mode, output.

011: GPIO mode, input.

101: Remote-hold mode. The GPIO pin will be an output, and the value is received from

the remote Deserializer. In remote-hold mode, data is maintained on link loss.

111: Remote-default mode. The GPIO pin will be an output, and the value is received

from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output

on link loss.

If PORT1_SEL is set, this register controls the D_GPIO1 pin.

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Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x0F

GPIO3

Configuration

D_GPIO3

7:4

0x00

Reserved.

GPIO3 Output Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function

Value

D_GPIO3

Output Value

is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled.

0: Output LOW (default).

Configuration

1: Output HIGH.

If PORT1_SEL is set, this register controls the D_GPIO3 pin.

2:0

GPIO3 Mode

D_GPIO3

Mode

Determines operating mode for the GPIO pin:

x00: Functional input mode.

x10: TRI-STATE™.

001: GPIO mode, output.

011: GPIO mode, input.

101: Remote-hold mode. The GPIO pin will be an output, and the value is received from

the remote Deserializer. In remote-hold mode, data is maintained on link loss.

111: Remote-default mode. The GPIO pin will be an output, and the value is received

from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output

on link loss.

If PORT1_SEL is set, this register controls the D_GPIO3 pin.

0x10

GPIO5_REG

and

GPIO6_REG

Configuration

0x00

GPIO6_REG

Output Value

Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function

is enabled and the local GPIO direction is set to output.

0: Output LOW (default).

1: Output HIGH.

Reserved.

5:4

GPIO6_REG

Mode

Determines operating mode for the GPIO pin:

00: Functional input mode.

10: TRI-STATE™.

01: GPIO mode, output.

11: GPIO mode; input.

GPIO5_REG

Output Value

Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function

is enabled and the local GPIO direction is set to output.

0: Output LOW (default).

1: Output HIGH.

Reserved.

1:0

GPIO5_REG

Mode

Determines operating mode for the GPIO pin:

00: Functional input mode.

10: TRI-STATE™.

01: GPIO mode, output.

11: GPIO mode; input.

DS90UH949A-Q1

ZHCSIO8 –AUGUST 2018

www.ti.com.cn

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x11

GPIO7_REG

and

GPIO8_REG

Configuration

0x00

GPIO8_REG

Output Value

Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function

is enabled and the local GPIO direction is set to output.

0: Output LOW (default).

1: Output HIGH.

Reserved.

5:4

GPIO8_REG

Mode

Determines operating mode for the GPIO pin:

00: Functional input mode.

10: TRI-STATE.

01: GPIO mode, output.

11: GPIO mode; input.

GPIO7_REG

Output Value

Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function

is enabled and the local GPIO direction is set to output.

0: Output LOW (default).

1: Output HIGH.

Reserved.

1:0

GPIO7_REG

Mode

Determines operating mode for the GPIO pin:

00: Functional input mode.

10: TRI-STATE.

01: GPIO mode, output.

11: GPIO mode; input.

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ZHCSIO8 –AUGUST 2018

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x12

Data Path

Control

0x00

Reserved.

Pass RGB

Setting this bit causes RGB data to be sent independent of DE. However, setting this bit

prevents HDCP operation and blocks packetized audio.

0: Normal operation.

1: Pass RGB independent of DE.

DE Polarity

This bit indicates the polarity of the DE (Data Enable) signal.

0: DE is positive (active high, idle low).

1: DE is inverted (active low, idle high).

I2S Repeater

Regen

Regenerate I2S data from Repeater I2S pins.

0: Repeater pass through I2S from video pins (default).

1: Repeater regenerate I2S from I2S pins.

I2S Channel B I2S Channel B Enable Override.

Enable

0: Disable I2S Channel B override.

Override

1: Set I2S Channel B Enable from 0x12[0].

18-Bit Video

Select

0: Select 24-bit video mode.

1: Select 18-bit video mode.

I2S Transport

Select

Select I2S transport mode:

0: Enable I2S Data Island transport (default).

1: Enable I2S Data Forward Channel Frame transport.

I2S Channel B I2S Channel B Enable.

Enable

0: I2S Channel B disabled.

1: Enable I2S Channel B on B1 input.

Note that in a repeater, this bit may be overridden by the in-band I2S mode detection.

0x13

General Purpose

Control

6:4

0x88

MODE_SEL1

Done

Indicates MODE_SEL1 value has stabilized and has been latched.

MODE_SEL1

Decode

Returns the 3-bit decode of the MODE_SEL1 pin.

MODE_SEL0

Done

Indicates MODE_SEL0 value has stabilized and has been latched.

Returns the 3-bit decode of the MODE_SEL0 pin.

2:0

MODE_SEL0

Decode

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www.ti.com.cn

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x14

BIST Control

7:3

2:1

0x00

Reserved.

Allows choosing different OSC clock frequencies for forward channel frame.

OSC clock frequency in functional mode when TMDS clock is not present and 0x03[2]=1:

OSC Clock

Source

00: 50 MHz oscillator.

01: 50 MHz oscillator.

10: 100 MHz oscillator.

11: 25 MHz oscillator.

Clock source in BIST mode i.e. when 0x14[0]=1:

00: External pixel clock.

01: 33 MHz oscillator.

1x: 100 MHz oscillator.

BIST Enable

BIST control:

0: Disabled (default).

1: Enabled.

0x15

I2C Voltage

Select

7:0

0x01

I2C Voltage

Select

Selects 1.8 or 3.3 V for the I2C_SDA and I2C_SCL pins. This register is loaded from the

I2C_VSEL strap option from the SCLK pin at power-up. At power-up, a logic LOW will

select 3.3 V operation, while a logic HIGH (pull-up resistor attached) will select 1.8 V

signaling. Issuing either of the digital resets via register 0x01 will cause the I2C_VSEL

value to be reset to 3.3V operation.

Reads of this register return the status of the I2C_VSEL control:

0: Select 1.8 V signaling.

1: Select 3.3 V signaling.

This bit may be overwritten via register access or via eFuse program by writing an 8-bit

value to this register:

Write 0xb5 to set I2C_VSEL.

Write 0xb6 to clear I2C_VSEL.

0x16

BCC Watchdog

Control

7:1

0xFE

Timer Value

The watchdog timer allows termination of a control channel transaction if it fails to

complete within a programmed amount of time. This field sets the Bidirectional Control

Channel Watchdog Timeout value in units of 2 milliseconds. This field should not be set

to 0. Set to 0x01.

Timer Control

Disable Bidirectional Control Channel (BCC) Watchdog Timer:

0: Enable BCC Watchdog Timer operation (default).

1: Disable BCC Watchdog Timer operation.

DS90UH949A-Q1

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ZHCSIO8 –AUGUST 2018

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x17

I2C Control

0x1E

I2C Pass All

Port0/Port1

0: Enable Forward Control Channel pass-through only of I2C accesses to I2C Slave IDs

matching either the remote Deserializer Slave ID or the remote Slave ID (default).

1: Enable Forward Control Channel pass-through of all I2C accesses to I2C Slave IDs

that do not match the Serializer I2C Slave ID.

If PORT1_SEL is set, this bit controls Port1 operation.

6:4

SDA Hold

Time

Internal SDA hold time:

Configures the amount of internal hold time provided for the SDA input relative to the

SCL input. Units are 40 nanoseconds.

3:0

7:0

I2C Filter

Depth

Configures the maximum width of glitch pulses on the SCL and SDA inputs that will be

rejected. Units are 5 nanoseconds.

0x18

0x19

SCL High Time

SCL Low Time

0x7F

TX_SCL_HIGH I2C Master SCL high time:

This field configures the high pulse width of the SCL output when the Serializer is the

Master on the local I2C bus. Units are 40 ns for the nominal oscillator clock frequency.

The default value is set to provide a minimum 5us SCL high time with the internal

oscillator clock running at 26.25 MHz rather than the nominal 25 MHz. Delay includes 5

additional oscillator clock periods.

Min_delay = 38.0952ns * (TX_SCL_HIGH + 5).

7:0

TX_SCL_LOW I2C Master SCL low time:

This field configures the low pulse width of the SCL output when the Serializer is the

Master on the local I2C bus. This value is also used as the SDA setup time by the I2C

Slave for providing data prior to releasing SCL during accesses over the Bidirectional

Control Channel. Units are 40 ns for the nominal oscillator clock frequency. The default

value is set to provide a minimum 5us SCL low time with the internal oscillator clock

running at 26.25 MHz rather than the nominal 25 MHz. Delay includes 5 additional clock

periods.

Min_delay = 38.0952ns * (TX_SCL_LOW + 5).

0x1A

Data Path

Control 2

7:4

Reserved.

Strap

0x01

SECONDARY Enable Secondary Audio.

_AUDIO

This register indicates that the AUX audio channel is enabled. The control for this

function is via the AUX_AUDIO bit in the BRIDGE_CFG register register offset 0x54).

The AUX_AUDIO control is strapped from the MODE_SEL0 pin at power-up.

Reserved.

MODE_28B

Enable 28-bit Serializer Mode.

0: 24-bit high-speed data + 3 low-speed control (DE, HS, VS).

1: 28-bit high-speed data mode.

I2S Surround

Enable 5.1- or 7.1-channel I2S audio transport:

0: 2-channel or 4-channel I2S audio is enabled as configured in register 0x12 bits 3 and

1: 5.1- or 7.1-channel audio is enabled.

Note that I2S Data Island Transport is the only option for surround audio. Also note that

in a repeater, this bit may be overridden by the in-band I2S mode detection (default).

DS90UH949A-Q1

ZHCSIO8 –AUGUST 2018

www.ti.com.cn

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x1B

BIST BC Error

Count

7:0

0x00

BIST BC Error BIST back channel CRC error counter.

Port0/Port1

This register stores the back channel CRC error count during BIST Mode (saturates at

255 errors). Clears when a new BIST is initiated or by 0x04[5].

If PORT1_SEL is set, this register indicates Port1 status.

0x1C

GPIO Pin Status

0x00

GPIO7_REG

Pin Status

GPIO7_REG input pin status.

Note: status valid only if pin is set to GPI (input) mode.

GPIO6_REG

Pin Status

GPIO6_REG input pin status.

Note: status valid only if pin is set to GPI (input) mode.

GPIO5_REG

Pin Status

GPIO5_REG input pin status.

Note: status valid only if pin is set to GPI (input) mode.

Reserved.

GPIO3 Pin

Status

D_GPIO3 Pin

Status

GPIO3 input pin status.

Note: status valid only if pin is set to GPI (input) mode.

If PORT1_SEL is set, this register indicates D_GPIO3 input pin status.

GPIO2 Pin

Status

D_GPIO2 Pin

Status

GPIO2 input pin status.

Note: status valid only if pin is set to GPI (input) mode.

If PORT1_SEL is set, this register indicates D_GPIO2 input pin status.

GPIO1 Pin

Status

D_GPIO1 Pin

Status

GPIO1 input pin status.

Note: status valid only if pin is set to GPI (input) mode.

If PORT1_SEL is set, this register indicates D_GPIO1 input pin status.

GPIO0 Pin

Status

D_GPIO0 Pin

Status

GPIO0 input pin status.

Note: status valid only if pin is set to GPI (input) mode.

If PORT1_SEL is set, this register indicates D_GPIO0 input pin status.

0x1D

GPIO Pin Status

7:1

0x00

Reserved

GPIO8_REG

Pin Status

GPIO8_REG input pin status.

Note: status valid only if pin is set to GPI (input) mode.

DS90UH949A-Q1

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ZHCSIO8 –AUGUST 2018

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x1E

Transmitter Port

Select

7:3

Reserved.

PORT1_I2C_E Port1 I2C Enable.

0x01

Enables secondary I2C address. The second I2C address provides access to Port1

registers as well as registers that are shared between Port0 and Port1. The second I2C

address value will be set to DeviceID + 1 (7-bit format). The PORT1_I2C_EN bit must

also be set to allow accessing remote devices over the second link when the device is in

Replicate mode.

PORT1_SEL

PORT0_SEL

Selects Port1 for register access from primary I2C address.

For writes, Port1 registers and shared registers will both be written.

For reads, Port1 registers and shared registers will be read. This bit must be cleared to

read Port0 registers.

This bit is ignored if PORT1_I2C_EN is set.

Selects Port0 for register access from primary I2C address.

For writes, Port0 registers and shared registers will both be written.

For reads, Port0 registers and shared registers will be read. Note that if PORT1_SEL is

also set, then Port1 registers will be read.

This bit is ignored if PORT1_I2C_EN is set.

0x1F

Frequency

Counter

7:0

0x00

Frequency

Count

Frequency counter control.

A write to this register will enable a frequency counter to count the number of pixel clock

during a specified time interval. The time interval is equal to the value written multiplied

by the oscillator clock period (nominally 40ns). A read of the register returns the number

of pixel clock edges seen during the enabled interval. The frequency counter will freeze

at 0xff if it reaches the maximum value. The frequency counter will provide a rough

estimate of the pixel clock period. If the pixel clock frequency is known, the frequency

counter may be used to determine the actual oscillator clock frequency.

DS90UH949A-Q1

ZHCSIO8 –AUGUST 2018

www.ti.com.cn

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x20

Deserializer

0x00

FREEZE_DES Freeze Deserializer Capabilities.

Capabilities 1

_CAP

Port0/Port1

Prevent auto-loading of the Deserializer Capabilities by the Bidirectional Control Channel.

The Capabilities will be frozen at the values written in registers 0x20 and 0x21.

If PORT1_SEL is set, this register indicates Port1 capabilities.

0x00

HSCC_MODE[ High-Speed Control Channel bit 0.

Lowest bit of the 3-bit HSCC indication. The other 2 bits are contained in Deserializer

Port0/Port1

Capabilities 2. This field is automatically configured by the Bidirectional Control Channel

once RX Lock has been detected. Software may overwrite this value, but must also set

the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel.

If PORT1_SEL is set, this register indicates Port1 capabilities.

SEND_FREQ

Port0/Port1

Send Frequency Training Pattern.

Indicates the DS90UH949A-Q1 should send the Frequency Training Pattern. This field is

automatically configured by the Bidirectional Control Channel once RX Lock has been

detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit

to prevent overwriting by the Bidirectional Control Channel.

If PORT1_SEL is set, this register indicates Port1 capabilities.

0x00

SEND_EQ

Port0/Port1

Send Equalization Training Pattern.

Indicates the DS90UH949A-Q1 should send the Equalization Training Pattern. This field

is automatically configured by the Bidirectional Control Channel once RX Lock has been

detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit

to prevent overwriting by the Bidirectional Control Channel.

If PORT1_SEL is set, this register indicates Port1 capabilities.

DUAL_LINK_C Dual link Capabilities.

Indicates if the Deserializer is capable of dual link operation. This field is automatically

Port0/Port1

configured by the Bidirectional Control Channel once RX Lock has been detected.

Software may overwrite this value, but must also set the FREEZE DES CAP bit to

prevent overwriting by the Bidirectional Control Channel.

If PORT1_SEL is set, this register indicates Port1 capabilities.

DUAL_CHANN Dual Channel 0/1 Indication.

In a dual-link capable device, indicates if this is the primary or secondary channel.

Port0/Port1

0: Primary channel (channel 0).

1: Secondary channel (channel 1).

This field is automatically configured by the Bidirectional Control Channel once RX Lock

has been detected. Software may overwrite this value, but must also set the FREEZE

DES CAP bit to prevent overwriting by the Bidirectional Control Channel.

If PORT1_SEL is set, this register indicates Port1 capabilities.

DS90UH949A-Q1

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ZHCSIO8 –AUGUST 2018

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x20

Deserializer

0x00

VID_24B_HD_ Deserializer supports 24-bit video concurrently with HD audio.

Capabilities 1

AUD

Port0/Port1

This field is automatically configured by the Bidirectional Control Channel once RX Lock

has been detected. Software may overwrite this value, but must also set the FREEZE

DES CAP bit to prevent overwriting by the Bidirectional Control Channel.

If PORT1_SEL is set, this register indicates Port1 capabilities.

DES_CAP_FC Deserializer supports GPIO in the Forward Channel Frame.

_GPIO

Port0/Port1

This field is automatically configured by the Bidirectional Control Channel once RX Lock

has been detected. Software may overwrite this value, but must also set the FREEZE

DES CAP bit to prevent overwriting by the Bidirectional Control Channel.

If PORT1_SEL is set, this register indicates Port1 capabilities.

0x21

Deserializer

7:2

1:0

Reserved.

Capabilities 2

0x00

HSCC_MODE[ High-Speed Control Channel bits [2:1].

2:1]

Upper bits of the 3-bit HSCC indication. The lowest bit is contained in Deserializer

Port0/Port1

Capabilities 1.

000: Normal back channel frame, GPIO mode.

001: High Speed GPIO mode, 1 GPIO.

010: High Speed GPIO mode, 2 GPIOs.

011: High Speed GPIO mode: 4 GPIOs.

100: Reserved.

101: Reserved.

110: High Speed, Forward Channel SPI mode.

111: High Speed, Reverse Channel SPI mode. In Single Link devices, only Normal back

channel frame modes are supported.

If PORT1_SEL is set, this register indicates Port1 capabilities.

0x26

Link Detect

Control

7:3

2:0

Reserved.

0x00

LINK DETECT Bidirectional Control Channel Link Detect Timer.

TIMER This field configures the link detection timeout period. If the timer expires without valid

communication over the reverse channel, link detect will be deasserted.

000: 162 microseconds.

001: 325 microseconds.

010: 650 microseconds.

011: 1.3 milliseconds.

100: 10.25 microseconds.

101: 20.5 microseconds.

110: 41 microseconds.

111: 82 microseconds.

DS90UH949A-Q1

ZHCSIO8 –AUGUST 2018

www.ti.com.cn

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x30

SCLK_CTRL

0x00

SCLK/WS

SCLK to Word Select Ratio.

0 : 64.

1 : 32.

6:5

4:3

2:1

MCLK/SCLK

MCLK to SCLK Select Ratio.

00 : 4.

01 : 2.

10 : 1.

11 : 8.

CLEAN

CLOCK_DIV

Clock Cleaner divider.

00 : FPD_VCO_CLOCK/8.

01 : FPD_VCO_CLOCK/4.

10 : FPD_VCO_CLOCK/2.

11 : AON_OSC.

CLEAN Mode If non-zero, the SCLK Input or HDMI N/CTS generated Audio Clock is cleaned digitally

before being used.

00 : Off.

01 : ratio of 1.

10 : ratio of 2.

11 : ratio of 4.

MASTER

If set, the SCLK I/O and the WS_IO are used as an output and the Clock Generation

Circuits are enabled, otherwise they are inputs.

0x31

0x32

0x33

0x34

0x35

0x36

AUDIO_CTS0

AUDIO_CTS1

AUDIO_CTS2

AUDIO_N0

7:0

7:4

3:0

7:6

5:3

2:0

0x00

CTS[7:0]

CTS[15:8]

CTS[23:16]

N[7:0]

If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.

Selects the LPF_COEFF in the Clock Cleaner (Feedback is divided by 2^COEFF).

If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.

Reserved.

AUDIO_N1

N[15:8]

AUDIO_N2_CO

EFF

COEFF[3:0]

N[19:16]

0x37

CLK_CLEAN_ST

0x00

IN_FIFO_LVL Clock Cleaner Input FIFO Level.

OUT_FIFO_LV Clock Cleaner Output FIFO Level.

DS90UH949A-Q1

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ZHCSIO8 –AUGUST 2018

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x40

ANA_IA_CTL

7:5

4:2

Reserved

0x00

ANA_IA_SEL

(Analog

Analog Register Select:

Selects target for register access

Indirect Select) 000 : Disabled 001 : HDMI Channel 0 Registers

010 : HDMI Channel 1 Registers

011 : HDMI Channel 2 Registers

100 : HDMI Share Registers

101 : FPD3 TX Registers

110 : Simultaneous access to HDMI Channel 0-2 registers

ANA_AUTO_I Analog Register Auto Increment:

Enables auto-increment mode. Upon completion of a read or write, the register address

will automatically be incremented by 1

(Analog

Indirect

Increment)

ANA_IA_REA Start Analog Register Read:

Setting this allows generation of a read strobe to the analog block upon setting of the

ANA_IA_ADDR register. In auto-increment mode, read strobes will also be asserted

(Analog

Indirect Read) following a read of the ANA_IA_DATA register. This function is only required for analog

blocks that need to pre-fetch register data.

0x41

0x42

0x48

ANA_IA_ADDR

ANA_IA_DATA

APB_CTL

7:0

0x00

ANA_IA_ADD Analog Register Offset:

This register contains the 8-bit register offset for the indirect access.

Analog Indirect

Address)

ANA_IA_DATA Analog Register Data:

(Analog

Writing this register will cause an indirect write of the ANA_IA_DATA value to the

Indirect Data)

selected analog block register. Reading this register will return the value of the selected

analog block register

7:5

4:3

Reserved.

0x00

APB_SELECT APB Select: Selects target for register access.

00 : HDMI APB interface.

01 : EDID SRAM.

10 : Configuration Data (read only).

11 : Die ID (read only).

APB_AUTO_I APB Auto Increment: Enables auto-increment mode. Upon completion of an APB read or

write, the APB address will automatically be incremented by 0x4 for HDMI registers or by

0x1 for others.

APB_READ

Start APB Read: Setting this bit to a 1 will begin an APB read. Read data will be available

in the APB_DATAx registers. The APB_ADRx registers should be programmed prior to

setting this bit. This bit will be cleared when the read is complete.

APB_ENABLE APB Interface Enable: Set to a 1 to enable the APB interface. The APB_SELECT bits

indicate what device is selected.

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ZHCSIO8 –AUGUST 2018

www.ti.com.cn

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

TYPE

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

APB_ADR0

APB_ADR1

APB_DATA0

APB_DATA1

APB_DATA2

APB_DATA3

BRIDGE_CTL

7:0

7:5

0x00

APB_ADR0

APB_ADR1

APB_DATA0

APB_DATA1

APB_DATA2

APB_DATA3

APB Address byte 0 (LSB).

APB Address byte 1 (MSB).

Byte 0 (LSB) of the APB Interface Data.

Byte 1 of the APB Interface Data.

Byte 2 of the APB Interface Data.

Byte 3 (MSB) of the APB Interface Data.

Reserved.

0x00

CEC_CLK_SR CEC Clock Source Select: Selects clock source for generating the 32.768 KHz clock for

CEC operations in the HDMI Receive Controller.

0 : Selects internal generated clock.

1 : Selects external 25 MHz oscillator clock.

CEC_CLK_EN CEC Clock Enable: Enable CEC clock generation. Enables generation of the 32.768 KHz

clock for the HDMI Receive controller. This bit should be set prior to enabling CEC

operation via the HDMI controller registers.

EDID_CLEAR Clear EDID SRAM: Set to 1 to enable clearing the EDID SRAM. The EDID_INIT bit must

be set at the same time for the clear to occur. This bit will be cleared when the

initialization is complete.

EDID_INIT

Initialize EDID SRAM from EEPROM: Causes a reload of the EDID SRAM from the non-

volatile EDID EEPROM. This bit will be cleared when the initialization is complete.

Strap

EDID_DISABL Disable EDID access via DDC/I2C: Disables access to the EDID SRAM via the HDMI

DDC interface. This value is loaded from the MODE_SEL0 pin at power-up.

DS90UH949A-Q1

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ZHCSIO8 –AUGUST 2018

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x50

BRIDGE_STS

0x03

RX5V_DETEC RX +5V detect: Indicates status of the RX_5V pin. When asserted, indicates the HDMI

interface has detected valid voltage on the RX_5V input.

HDMI_INT

HDMI Interrupt Status: Indicates an HDMI Interrupt is pending. HDMI interrupts are

serviced through the HDMI Registers via the APB Interface.

HDCP_INT

INIT_DONE

HDCP Interrupt Status: Indicates an HDCP Transmitter Interrupt is pending. HDCP

Transmit interrupts are serviced through the HDCP Interrupt Control and Status registers.

Initialization Done: Initialization sequence has completed. This step will complete after

configuration complete (CFG_DONE).

REM_EDID_L Remote EDID Loaded: Indicates EDID SRAM has been loaded from a remote EDID

OAD

EEPROM device over the Bidirectional Control Channel. The EDID_CKSUM value

indicates if the EDID load was successful.

CFG_DONE

Configuration Complete: Indicates automatic configuration has completed. This step will

complete prior to initialization complete (INIT_DONE).

CFG_CKSUM Configuration checksum status: Indicates result of Configuration checksum during

initialization. The device verifies the 2’s complement checksum in the last 128 bytes of

the EEPROM. A value of 1 indicates the checksum passed.

7:1

EDID_CKSUM EDID checksum Status: Indicates result of EDID checksum during EDID initialization. The

device verifies the 2’s complement checksum in the first 256 bytes of the EEPROM. A

value of 1 indicates the checksum passed.

0x51

0x52

EDID_ID

0x50

EDID_ID

EDID I2C Slave Address: I2C address used for accessing the EDID information. These

are the upper 7 bits in 8-bit format addressing, where the lowest bit is the Read/Write

control.

EDID_RDONL EDID Read Only: Set to a 1 puts the EDID SRAM memory in read-only mode for access

via the HDMI DDC interface. Setting to a 0 allows writes to the EDID SRAM memory.

EDID_CFG0

Reserved.

6:4

0x01

EDID_SDA_H Internal SDA Hold Time: This field configures the amount of internal hold time provided

OLD

for the DDC_SDA input relative to the DDC_SCL input. Units are 40 nanoseconds. The

hold time is used to qualify the start detection to avoid false detection of Start or Stop

conditions.

3:0

0x0E

0x00

EDID_FLTR_D I2C Glitch Filter Depth: This field configures the maximum width of glitch pulses on the

PTH

DDC_SCL and DDC_SDA inputs that will be rejected. Units are 5 nanoseconds.

0x53

EDID_CFG1

7:2

1:0

Reserved.

EDID_SDA_DL SDA Output Delay: This field configures output delay on the DDC_SDA output when the

EDID memory is accessed. Setting this value will increase output delay in units of 40ns.

Nominal output delay values for DDC_SCL to DDC_SDA are:

00 : 240ns.

01 : 280ns.

10 : 320ns.

11 : 360ns.

DS90UH949A-Q1

ZHCSIO8 –AUGUST 2018

www.ti.com.cn

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x54

BRIDGE_CFG

Strap

EXT_CTL

External Control: When this bit Is set, the internal bridge control function is disabled. This

disables initialization of the HDMI Receiver as well as initiation of HDCP functions. These

operations must be controlled by an external controller attached to the I2C interface. This

value is loaded from the MODE_SEL1 pin at power-up.

0x00

HDMI_INT_EN HDMI Interrupt Enable: When this bit is set, Interrupts from the HDMI Receive controller

will be reported on the INTB pin. Software may check the BRIDGE_STS register to

determine if the interrupt is from the HDMI Receiver or the HDCP Transmitter.

Strap

DIS_REM_EDI Disable Remote EDID load: Disables automatic load of EDID SRAM from a remote EDID

EEPROM. By default, the device will check the remote I2C bus for an EEPROM with a

valid EDID, and load the EDID data to local EDID SRAM. If this bit is set to a 1, the

remote EDID load will be bypassed. This value is loaded from the MODE_SEL1 pin at

power-up.

0x00

AUTO_INIT_DI Disable Automatic initialization: The Bridge control will automatically initialize the HDMI

Receiver for operation. Setting this bit to a 1 will disable automatic initialization of the

HDMI Receiver. In this mode, initialization of the HDMI Receiver must be done through

EEPROM configuration or via external control.

AUTO_HDCP_ Disable Automatic HDCP_CTRL setting: By default the internal bridge control function will

DIS

configure the HDMI Receiver for HDCP operation using default settings for bits in the

HDCP_CTRL register. Setting this bit to a 1 will disable automatic control of the

HDCP_CTRL register in the HDMI Receiver.

AUDIO_TDM

Enable TDM Audio: Setting this bit to a 1 will enable TDM audio for the HDMI audio.

AUDIO_MODE Audio Mode: Selects source for audio to be sent over the FPD-Link III downstream link.

0 : HDMI audio.

1 : Local/DVI audio.

Local audio is sourced from the device I2S pins rather than from HDMI, and is useful in

modes such as DVI that do not include audio.

Strap

AUX_AUDIO_ AUX Audio Channel Enable: Setting this bit to a 1 will enable the AUX audio channel.

This allows sending additional 2-channel audio in addition to the HDMI or DVI audio. This

bit is loaded from the MODE_SEL0 pin at power-up.

DS90UH949A-Q1

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Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x55

AUDIO_CFG

0x00

TDM_2_PARA Enable I2S TDM to parallel audio conversion: When this bit is set, the I2S TDM to parallel

LLEL

conversion module is enabled. The clock output from the I2S TDM to parallel conversion

module is them used to send data to the deserializer.

HDMI_I2S_OU HDMI Audio Output Enable: When this bit is set, the HDMI I2S audio data will be output

on the I2S audio interface pins. This control is ignored if the

BRIDGE_CFG:AUDIO_MODE is not set to 00 (HDMI audio only).

5:4

Reserved.

0x0C

RST_ON_TYP Reset Audio FIFO on Type Change: When this bit is set, the internal bridge control

function will reset the HDMI Audio FIFO on a change in the Audio type.

RST_ON_AIF Reset Audio FIFO on Audio Infoframe: When this bit is set, the internal bridge control

function will reset the HDMI Audio FIFO on a change in the Audio Infoframe checksum.

RST_ON_AVI Reset Audio FIFO on Audio Video Information Infoframe: When this bit is set, the internal

bridge control function will reset the HDMI Audio FIFO on a change in the Audio Video

Information Infoframe checksum.

RST_ON_ACR Reset Audio FIFO on Audio Control Frame: When this bit is set, the internal bridge

control function will reset the HDMI Audio FIFO on a change in the Audio Control Frame

N or CTS fields.

0x5A

DUAL_STS

0x00

FPD3_LINK_R This bit indicates that the FPD-Link III has detected a valid downstream connection and

FPD3_TX_ST FPD-Link III transmit status:

This bit indicates that the FPD-Link III transmitter is active and the receiver is LOCKED to

determined capabilities for the downstream link.

the transmit clock. It is only asserted once a valid input has been detected, and the FPD-

Link III transmit connection has entered the correct mode (Single vs. Dual mode).

5:4

FPD3_PORT_ FPD3 Port Status: If FPD3_TX_STS is set to a 1, this field indicates the port mode status

STS

as follows:

00: Dual FPD-Link III Transmitter mode.

01: Single FPD-Link III Transmit on port 0.

10: Single FPD-Link III Transmit on port 1.

11: Replicate FPD-Link III Transmit on both ports.

TMDS_VALID HDMI TMDS Valid: This bit indicates the TMDS interface is recovering valid TMDS data

from HDMI.

HDMI_PLL_LO HDMI PLL lock status: Indicates the HDMI PLL has locked to the incoming HDMI clock.

NO_HDMI_CL No HDMI Clock Detected: This bit indicates the Frequency Detect circuit did not detect an

HDMI clock greater than the value specified in the FREQ_LOW register.

FREQ_STABL HDMI Frequency is Stable: Indicates the Frequency Detection circuit has detected a

stable HDMI clock frequency.

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ZHCSIO8 –AUGUST 2018

www.ti.com.cn

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x5B

DUAL_CTL1

Strap

FPD3_COAX_ FPD3 Coax Mode: Enables configuration for the FPD3 Interface cabling type.

MODE

0 : Twisted Pair.

1 : Coax This bit is loaded from the MODE_SEL1 pin at power-up.

DUAL_SWAP Dual Swap Control: Indicates current status of the Dual Swap control. If automatic

correction of Dual Swap is disabled via the DISABLE_DUAL_SWAP control, this bit may

be modified by software.

RST_PLL_FR Reset FPD3 PLL on Frequency Change: When set to a 1, frequency changes detected

by the Frequency Detect circuit will result in a reset of the FPD3 PLL. Set to 0.

FREQ_DET_P Frequency Detect Select PLL Clock: Determines the clock source for the Frequency

detection circuit:

0 : HDMI clock (prior to PLL).

1: HDMI PLL clock.

DUAL_ALIGN_ Dual align on DE (valid in dual-link mode):

DE 0: Data will be sent on alternating links without regard to odd/even pixel position.

1: Odd/Even data will be sent on the primary/secondary links, respectively, based on the

assertion of DE.

DISABLE_DU Disable Dual Mode: During Auto-detect operation, setting this bit to a 1 will disable Dual

FPD-Link III operation.

0: Normal Auto-detect operation.

1: Only Single or Replicate operation supported.

This bit will have no effect if FORCE_LINK is set.

FORCE_DUAL Force dual mode:

When FORCE_LINK bit is set, the value on this bit controls single versus dual operation:

0: Single FPD-Link III Transmitter mode.

1: Dual FPD-Link III Transmitter mode.

FORCE_LINK Force Link Mode: Forces link to dual or single mode, based on the FORCE_DUAL control

setting. If this bit is 0, mode setting will be automatically set based on downstream device

capabilities as well as the incoming data frequency.

0 : Auto-Detect FPD-Link III mode.

1 : Forced Single or Dual FPD-Link III mode.

DS90UH949A-Q1

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ZHCSIO8 –AUGUST 2018

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x5C

DUAL_CTL2

DISABLE_DU Disable Dual Swap: Prevents automatic correction of swapped Dual link connection.

AL_SWAP Setting this bit allows writes to the DUAL_SWAP control in the DUAL_CTL1 register.

0x00

FORCE_LINK_ Force Link Ready: Forces link ready indication, bypassing back channel link detection.

RDY

FORCE_CLK_ Force Clock Detect: Forces the HDMI/OpenLDI clock detect circuit to indicate presence

DET

of a valid input clock. This bypasses the clock detect circuit, allowing operation with an

input clock that does not meet frequency or stability requirements.

4:3

FREQ_STBL_ Frequency Stability Threshold: The Frequency detect circuit can be used to detect a

THR

stable clock frequency. The Stability Threshold determines the amount of time required

for the clock frequency to stay within the FREQ_HYST range to be considered stable:

00 : 40us.

01 : 80us.

10 : 320us.

11 : 1.28ms.

2:0

0x02

FREQ_HYST

Frequency Detect Hysteresis: The Frequency detect hysteresis setting allows ignoring

minor fluctuations in frequency. A new frequency measurement will be captured only if

the measured frequency differs from the current measured frequency by more than the

FREQ_HYST setting. The FREQ_HYST setting is in MHz.

0x5D

FREQ_LOW

Reserved.

HDMI_RST_M HDMI Phy Reset Mode:

ODE 0 : Reset HDMI Phy on change in mode or frequency.

1 : Don't reset HDMI Phy on change in mode or frequency if +5V is asserted.

5:0

FREQ_LO_TH Frequency Low Threshold: Sets the low threshold for the HDMI Clock frequency detect

circuit in MHz. This value is used to determine if the HDMI clock frequency is too low for

proper operation.

0x5E

0x5F

FREQ_HIGH

Reserved.

6:0

FREQ_HI_TH Frequency High Threshold: Sets the high threshold for the HDMI Clock frequency detect

circuit in MHz.

HDMI Frequency

7:0

0x00

HDMI_FREQ

HDMI frequency:

Returns the value of the HDMI frequency in MHz. A value of 0 indicates the HDMI

receiver is not detecting a valid signal.

DS90UH949A-Q1

ZHCSIO8 –AUGUST 2018

www.ti.com.cn

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0x60

SPI_TIMING1

7:4

0x02

SPI_HOLD

SPI Data Hold from SPI clock: These bits set the minimum hold time for SPI data

following the SPI clock sampling edge. In addition, this also sets the minimum active

pulse width for the SPI output clock.

0: Do not use.

0x1-0xF: Hold = (SPI_HOLD + 1) * 40ns.

For example, default setting of 2 will result in 120ns data hold time.

3:0

0x02

SPI_SETUP

SPI Data Setup to SPI Clock: These bits set the minimum setup time for SPI data to the

SPI clock active edge. In addition, this also sets the minimum inactive width for the SPI

output clock.

0: Do not use.

0x1-0xF: Hold = (SPI_SETUP + 1) * 40ns.

For example, default setting of 2 will result in 120ns data setup time.

0x61

0x62

SPI_TIMING2

SPI_CONFIG

7:4

3:0

Reserved.

0x00

SPI_SS_SETU SPI Slave Select Setup: This field controls the delay from assertion of the Slave Select

low to initial data timing. Delays are in units of 40ns.

Delay = (SPI_SS_SETUP + 1) * 40ns.

7:2

Reserved.

SPI_CPHA

SPI Clock Phase setting: Determines which phase of the SPI clock is used for sampling

data.

0: Data sampled on leading (first) clock edge.

1: Data sampled on trailing (second) clock edge.

This bit is read-only, with a value of 0. There is no support for CPHA of 1.

SPI_CPOL

SPI Clock Polarity setting: Determines the base (inactive) value of the SPI clock.

0: base value of the clock is 0.

1: base value of the clock is 1.

This bit affects both capture and propagation of SPI signals.

DS90UH949A-Q1

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ZHCSIO8 –AUGUST 2018

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

100

0x64

Pattern

7:4

0x10

Pattern

Fixed Pattern Select

Generator

Control

Generator

Select

Selects the pattern to output when in Fixed Pattern Mode. Scaled patterns are evenly

distributed across the horizontal or vertical active regions. This field is ignored when

Auto-Scrolling Mode is enabled.

xxxx: normal/inverted.

0000: Checkerboard.

0001: White/Black (default).

0010: Black/White.

0011: Red/Cyan.

0100: Green/Magenta.

0101: Blue/Yellow.

0110: Horizontal Black-White/White-Black.

0111: Horizontal Black-Red/White-Cyan.

1000: Horizontal Black-Green/White-Magenta.

1001: Horizontal Black-Blue/White-Yellow.

1010: Vertical Black-White/White-Black.

1011: Vertical Black-Red/White-Cyan.

1100: Vertical Black-Green/White-Magenta.

1101: Vertical Black-Blue/White-Yellow.

1110: Custom color (or its inversion) configured in PGRS, PGGS, PGBS registers.

1111: VCOM.

See TI App Note AN-2198.

Reserved.

Color Bars

Pattern

Enable color bars:

0: Color Bars disabled (default).

1: Color Bars enabled.

Overrides the selection from reg_0x64[7:4].

VCOM Pattern Reverse order of color bands in VCOM pattern:

Reverse

0: Color sequence from top left is (YCBR) (default).

1: Color sequence from top left is (RBCY).

Pattern

Pattern Generator enable:

Generator

Enable

0: Disable Pattern Generator (default).

1: Enable Pattern Generator.

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ZHCSIO8 –AUGUST 2018

www.ti.com.cn

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

101

0x65

Pattern

Generator

Configuration

0x00

Reserved.

Checkerboard Scale Checkered Patterns:

Scale

0: Normal operation (each square is 1x1 pixel) (default).

1: Scale checkered patterns (VCOM and checkerboard) by 8 (each square is 8x8 pixels).

Setting this bit gives better visibility of the checkered patterns.

Custom

Use Custom Checkerboard Color:

Checkerboard 0: Use white and black in the Checkerboard pattern (default).

1: Use the Custom Color and black in the Checkerboard pattern.

PG 18–bit

Mode

18-bit Mode Select:

0: Enable 24-bit pattern generation. Scaled patterns use 256 levels of brightness

(default).

1: Enable 18-bit color pattern generation. Scaled patterns will have 64 levels of

brightness and the R, G, and B outputs use the six most significant color bits.

External Clock Select External Clock Source:

0: Selects the internal divided clock when using internal timing (default).

1: Selects the external pixel clock when using internal timing.

This bit has no effect in external timing mode (PATGEN_TSEL = 0).

Timing Select

Timing Select Control:

0: The Pattern Generator uses external video timing from the pixel clock, Data Enable,

Horizontal Sync, and Vertical Sync signals (default).

1: The Pattern Generator creates its own video timing as configured in the Pattern

Generator Total Frame Size, Active Frame Size. Horizontal Sync Width, Vertical Sync

Width, Horizontal Back Porch, Vertical Back Porch, and Sync Configuration registers.

See TI App Note AN-2198.

Color Invert

Auto Scroll

Enable Inverted Color Patterns:

0: Do not invert the color output (default).

1: Invert the color output.

See TI App Note AN-2198.

Auto Scroll Enable:

0: The Pattern Generator retains the current pattern (default).

1: The Pattern Generator will automatically move to the next enabled pattern after the

number of frames specified in the Pattern Generator Frame Time (PGFT) register.

See TI App Note AN-2198.

102

103

0x66

0x67

PGIA

PGID

7:0

0x00

PG Indirect

Address

This 8-bit field sets the indirect address for accesses to indirectly-mapped registers. It

should be written prior to reading or writing the Pattern Generator Indirect Data register.

See TI App Note AN-2198

PG Indirect

Data

When writing to indirect registers, this register contains the data to be written. When

reading from indirect registers, this register contains the read back value.

See TI App Note AN-2198

DS90UH949A-Q1

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ZHCSIO8 –AUGUST 2018

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

112

113

114

115

116

117

0x70

0x71

0x72

0x73

0x74

0x75

Slave ID[1]

Slave ID[2]

Slave ID[3]

Slave ID[4]

Slave ID[5]

Slave ID[6]

7:1

0x00

Slave ID 1

Port0/Port1

7-bit I2C address of the remote Slave 1 attached to the remote Deserializer. If an I2C

transaction is addressed to Slave Alias ID 1, the transaction will be remapped to this

address before passing the transaction across the Bidirectional Control Channel to the

Deserializer. A value of 0 in this field disables access to the remote Slave 1.

If PORT1_SEL is set, this register controls Port 1 Slave ID.

Reserved.

7:1

Slave ID 2

Port0/Port1

7-bit I2C address of the remote Slave 2 attached to the remote Deserializer. If an I2C

transaction is addressed to Slave Alias ID 2, the transaction will be remapped to this

address before passing the transaction across the Bidirectional Control Channel to the

Deserializer. A value of 0 in this field disables access to the remote Slave 2.

If PORT1_SEL is set, this register controls Port 1 Slave ID.

Reserved.

7:1

Slave ID 3

Port0/Port1

7-bit I2C address of the remote Slave 3 attached to the remote Deserializer. If an I2C

transaction is addressed to Slave Alias ID 3, the transaction will be remapped to this

address before passing the transaction across the Bidirectional Control Channel to the

Deserializer. A value of 0 in this field disables access to the remote Slave 3.

If PORT1_SEL is set, this register controls Port 1 Slave ID.

Reserved.

7:1

Slave ID 4

Port0/Port1

7-bit I2C address of the remote Slave 4 attached to the remote Deserializer. If an I2C

transaction is addressed to Slave Alias ID 4, the transaction will be remapped to this

address before passing the transaction across the Bidirectional Control Channel to the

Deserializer. A value of 0 in this field disables access to the remote Slave 4.

If PORT1_SEL is set, this register controls Port 1 Slave ID.

Reserved.

7:1

Slave ID 5

Port0/Port1

7-bit I2C address of the remote Slave 5 attached to the remote Deserializer. If an I2C

transaction is addressed to Slave Alias ID 5, the transaction will be remapped to this

address before passing the transaction across the Bidirectional Control Channel to the

Deserializer. A value of 0 in this field disables access to the remote Slave 5.

If PORT1_SEL is set, this register controls Port 1 Slave ID.

Reserved.

7:1

Slave ID 6

Port0/Port1

7-bit I2C address of the remote Slave 6 attached to the remote Deserializer. If an I2C

transaction is addressed to Slave Alias ID 6, the transaction will be remapped to this

address before passing the transaction across the Bidirectional Control Channel to the

Deserializer. A value of 0 in this field disables access to the remote Slave 6.

If PORT1_SEL is set, this register controls Port 1 Slave ID.

Reserved.

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www.ti.com.cn

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

118

0x76

Slave ID[7]

7:1

0x00

Slave ID 7

Port0/Port1

7-bit I2C address of the remote Slave 7 attached to the remote Deserializer. If an I2C

transaction is addressed to Slave Alias ID 7, the transaction will be remapped to this

address before passing the transaction across the Bidirectional Control Channel to the

Deserializer. A value of 0 in this field disables access to the remote Slave 7.

If PORT1_SEL is set, this register controls Port 1 Slave ID.

Reserved.

119

120

121

122

123

124

0x77

0x78

0x79

0x7A

0x7B

0x7C

Slave Alias[1]

Slave Alias[2]

Slave Alias[3]

Slave Alias[4]

Slave Alias[5]

Slave Alias[6]

7:1

0x00

Slave Alias ID 7-bit Slave Alias ID of the remote Slave 1 attached to the remote Deserializer. The

transaction will be remapped to the address specified in the Slave ID 1 register. A value

of 0 in this field disables access to the remote Slave 1.

Port0/Port1

If PORT1_SEL is set, this register controls Port 1 Slave Alias.

Reserved.

7:1

Slave Alias ID 7-bit Slave Alias ID of the remote Slave 2 attached to the remote Deserializer. The

transaction will be remapped to the address specified in the Slave ID 2 register. A value

of 0 in this field disables access to the remote Slave 2.

Port0/Port1

If PORT1_SEL is set, this register controls Port 1 Slave Alias.

Reserved.

7:1

Slave Alias ID 7-bit Slave Alias ID of the remote Slave 3 attached to the remote Deserializer. The

transaction will be remapped to the address specified in the Slave ID 3 register. A value

of 0 in this field disables access to the remote Slave 3.

Port0/Port1

If PORT1_SEL is set, this register controls Port 1 Slave Alias.

Reserved.

7:1

Slave Alias ID 7-bit Slave Alias ID of the remote Slave 4 attached to the remote Deserializer. The

transaction will be remapped to the address specified in the Slave ID 4 register. A value

of 0 in this field disables access to the remote Slave 4.

Port0/Port1

If PORT1_SEL is set, this register controls Port 1 Slave Alias.

Reserved.

7:1

Slave Alias ID 7-bit Slave Alias ID of the remote Slave 5 attached to the remote Deserializer. The

transaction will be remapped to the address specified in the Slave ID 5 register. A value

of 0 in this field disables access to the remote Slave 5.

Port0/Port1

If PORT1_SEL is set, this register controls Port 1 Slave Alias.

Reserved.

7:1

Slave Alias ID 7-bit Slave Alias ID of the remote Slave 6 attached to the remote Deserializer. The

transaction will be remapped to the address specified in the Slave ID 6 register. A value

of 0 in this field disables access to the remote Slave 6.

Port0/Port1

If PORT1_SEL is set, this register controls Port 1 Slave Alias.

Reserved.

DS90UH949A-Q1

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ZHCSIO8 –AUGUST 2018

Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

125

0x7D

Slave Alias[7]

7:1

0x00

Slave Alias ID 7-bit Slave Alias ID of the remote Slave 7 attached to the remote Deserializer. The

transaction will be remapped to the address specified in the Slave ID 7 register. A value

of 0 in this field disables access to the remote Slave 7.

Port0/Port1

If PORT1_SEL is set, this register controls Port 1 Slave Alias.

Reserved.

128

129

130

131

132

144

145

146

147

148

160

0x80

0x81

0x82

0x83

0x84

0x90

0x91

0x92

0x93

0x94

0xA0

RX_BKSV0

RX_BKSV1

RX_BKSV2

RX_BKSV3

RX_BKSV4

TX_KSV0

7:0

0x00

RX_BKSV0

RX_BKSV1

RX_BKSV2

RX_BKSV3

RX_BKSV4

TX_KSV0

TX_KSV1

TX_KSV2

TX_KSV3

TX_KSV4

BKSV0: Value of byte0 of the Receiver KSV.

BKSV1: Value of byte1 of the Receiver KSV.

BKSV2: Value of byte2 of the Receiver KSV.

BKSV3: Value of byte3 of the Receiver KSV.

BKSV4: Value of byte4 of the Receiver KSV.

TX_KSV0: Value of byte0 of the Transmitter KSV.

TX_KSV1: Value of byte1 of the Transmitter KSV.

TX_KSV2: Value of byte2 of the Transmitter KSV.

TX_KSV3: Value of byte3 of the Transmitter KSV.

TX_KSV4: Value of byte4 of the Transmitter KSV.

Reserved.

TX_KSV1

TX_KSV2

TX_KSV3

TX_KSV4

RX_BCAPS

0x01

Repeater

Repeater: Indicates if the attached Receiver supports downstream connections. This bit

is valid once the Bksv is ready as indicated by the BKSV_RDY bit in the HDCP.

KSV_FIFO_RD KSV FIFO Ready: Indicates the receiver has built the list of attached KSVs and computed

the verification value V’.

FAST_I2C

Fast I2C: The HDCP Receiver supports fast I2C. Since the I2C is embedded in the serial

data, this bit is not relevant.

3:2

Reserved.

0x03

0x00

FEATURES_1 1.1_Features: The HDCP Receiver supports the Enhanced Encryption Status Signaling

_1 (EESS), Advance Cipher, and Enhanced Link Verification options.

FAST_REAUT Fast Reauthentication: The HDCP Receiver is capable of receiving (unencrypted) video

signal during the session re-authentication.

161

0xA1

RX_BSTATUS0

MAX_DEVS_E Maximum Devices Exceeded: Indicates a topology error was detected. Indicates the

XCEEDED number of downstream devices has exceeded the depth of the Repeater's KSV FIFO.

6:0

DEVICE_COU Device Count: Total number of attached downstream device. For a Repeater, this will

indicate the number of downstream devices, not including the Repeater. For an HDCP

Receiver that is not also a Repeater, this field will be 0.

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Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

162

0xA2

RX_BSTATUS1

7:4

Reserved.

MAX_CASC_E Maximum Cascade Exceeded: Indicates a topology error was detected. Indicates that

0x00

XCEEDED

more than seven levels of repeaters have been cascad-ed together.

2:0

7:0

Cascade

Depth

Cascade Depth: Indicates the number of attached levels of devices for the Repeater.

163

192

0xA3

0xC0

KSV_FIFO

0x00

KSV_FIFO

KSV FIFO: Each read of the KSV FIFO returns one byte of the KSV FIFO list composed

by the downstream Receiver.

HDCP_DBG

Reserved.

HDCP_I2C_T

O_DIS

HDCP I2C Timeout Disable: Setting this bit to a 1 will disable the bus timeout function in

the HDCP I2C master. When enabled, the bus timeout function allows the I2C master to

assume the bus is free if no signaling occurs for more than 1 second.

Reserved.

0x00

DIS_RI_SYNC Disable Ri Synchronization check: Ri is normally checked both before and after the start

of frame 128. The check at frame 127 ensures synchronization between the two. Setting

this bit to a 1 will disable the check at frame 127.

RGB_CHKSU Enable RBG video line checksum: Enables sending of ones-complement checksum for

M_EN

each 8-bit RBG data channel following end of each video data line.

FC_TESTMOD Frame Counter Testmode: Speeds up frame counter used for Pj and Ri verification.

When set to a 1, Pj is computed every 2 frames and Ri is computed every 16 frames.

When set to a 0, Pj is computed every 16 frames and Ri is computed every 128 frames.

TMR_SPEEDU Timer Speedup: Speed up HDCP authentication timers.

HDCP_I2C_FA HDCP I2C Fast Mode Enable Setting this bit to a 1 will enable the HDCP I2C Master in

the HDCP Receiver to operation with Fast mode timing. If set to a 0, the I2C Master will

operation with Standard mode timing. This bit is mirrored in the IND_STS register.

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Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

194

0xC2

HDCP_CFG

0xA8

ENH_LV

Enable Enhanced Link Verification: Enables enhanced link verification. Allows checking

of the encryption Pj value on every 16th frame.

0 = Enhanced Link Verification disabled.

1 = Enhanced Link Verification enabled.

HDCP_EESS

TX_RPTR

Enable Enhanced Encryption Status Signaling: Enables Enhanced Encryption Status

Signaling (EESS) instead of the Original Encryption Status Signaling (OESS).

0 = OESS mode enabled.

1 = EESS mode enabled.

Transmit Repeater Enable: Enables the transmitter to act as a repeater. In this mode, the

HDCP Transmitter incorporates the additional authentication steps required of an HDCP

Repeater.

0 = Transmit Repeater mode disabled.

1 = Transmit Repeater mode enabled.

4:3

ENC_MODE

Encryption Control Mode: Determines mode for controlling whether encryption is required

for video frames.

00 = Enc_Authenticated.

01 = Enc_Reg_Control.

10 = Enc_Always.

11 = Enc_InBand_Control (per frame).

WAIT_100MS Enable 100MS Wait: The HDCP 1.3 specification allows for a 100Ms wait to allow the

HDCP Receiver to compute the initial encryption values. The FPD-LinkIII implementation

guarantees that the Receiver will complete the computations before the HDCP

Transmitter. Thus the timer is unnecessary. To enable the 100ms timer, set this bit to a 1.

RX_DET_SEL RX Detect Select: Controls assertion of the Receiver Detect Interrupt. If set to 0, the

Receiver Detect Interrupt will be asserted on detection of an FPD-Link III Receiver. If set

to 1, the Receiver Detect Interrupt will also require a receive lock indication from the

receiver.

HDCP_AVMU Enable AVMUTE: Setting this bit to a 1 will initiate AVMUTE operation. The transmitter

will ignore encryption status controls while in this state. If this bit is set to a 0, normal

opera¬tion will resume. This bit may only be set if the HDCP_EESS bit is also set.

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Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

195

0xC3

HDCP_CTL

0x00

HDCP_RST

HDCP Reset : Setting this bit will reset the HDCP transmitter and dis-able HDCP

authentication. This bit is self-clearing.

Reserved.

KSV_LIST_VA KSV List Valid : The controller sets this bit after validating the Repeater’s KSV List

LID

against the Key revocation list. This allows completion of the Authentication process. This

bit is self-clearing.

KSV_VALID

KSV Valid : The controller sets this bit after validating the Receiver’s KSV against the

Key revocation list. This allows continuation of the Authentication process. This bit will be

cleared upon assertion of the KSV_RDY flag in the HDCP_STS register. Setting this bit

to a 0 will have no effect.

HDCP_ENC_D HDCP Encrypt Disable : Disables HDCP encryption. Setting this bit to a 1 will cause

video data to be sent without encryption. Authen-tication status will be maintained. This

bit is self-clear-ing.

HDCP_ENC_E HDCP Encrypt Enable : Enables HDCP encryption. When set, if the device is

authenticated, encrypted data will be sent. If device is not authenticated, a blue screen

will be sent. Encryption should always be enabled when video data requiring content

protection is being supplied to the transmitter. When this bit is not set, video data will be

sent without encryption. Note that when CFG_ENC_MODE is set to Enc_Always, this bit

will be read only with a value of 1.

HDCP_DIS

HDCP_EN

HDCP Disable: Disables HDCP authentication. Setting this bit to a 1 will disable the

HDCP authentication. This bit is self-clearing.

HDCP Enable/Restart: Enables HDCP authentication. If HDCP is already en-abled,

setting this bit to a 1 will restart authentication. Setting this bit to a 0 will have no effect. A

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Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

196

0xC4

HDCP_STS

0x00

I2C_ERR_DET HDCP I2C Error Detected: This bit indicates an error was detected on the embedded

communications channel with the HDCP Receiver. Setting of this bit might indicate that a

problem exists on the link between the HDCP Transmitter and HDCP Receiver. This bit

will be cleared on read.

RX_INT

RX Interrupt : Status of the RX Interrupt signal. The signal is received from the attached

HDCP Receiver and is the status on the INTB_IN pin of the HDCP Receiver. The signal

is active low, so a 0 indicates an interrupt condition.

RX_LOCK_DE Receiver Lock Detect : This bit indicates that the downstream Receiver has indicated

Receive Lock to incoming serial data.

DOWN_HPD

Downstream Hot Plug Detect: This bit indicates a downstream repeater has reported a

Hot Plug event, indicating addition of a new receiver. This bit will be cleared on read.

RX_DETECT

Receiver Detect : This bit indicates that a downstream Receiver has been detected.

KSV_LIST_RD HDCP Repeater KSV List Ready : This bit indicates that the Receiver KSV list has been

read and is available in the KSV_FIFO registers. The device will wait for the controller to

set the KSV_LIST_VALID bit in the HDCP_CTL register before continuing. This bit will be

cleared once the controller sets the KSV_LIST_VALID bit.

KSV_RDY

HDCP Receiver KSV Ready : This bit indicates that the Receiver KSV has been read and

is available in the HDCP_BKSV registers. If the de-vice is not a Repeater, it will wait for

the controller to set the KSV_VALID bit in the HDCP_CTL register before continuing. This

bit will be cleared once the controller sets the KSV_VALID bit.

AUTHED

HDCP Authenticated: Indicates the HDCP authentication has completed successfully.

The controller may now send video data re-quiring content protection. This bit will be

cleared if authentication is lost or if the controller restarts authentication.

198

0xC6

ICR

0x00

IE_IND_ACC

Interrupt on Indirect Access Complete: Enables interrupt on completion of Indirect

IE_RXDET_IN Interrupt on Receiver Detect: Enables interrupt on detection of a downstream Receiver. If

HDCP_CFG:RX_DET_SEL is set to a 1, the interrupt will wait for Receiver Lock Detect.

IE_RX_INT

Interrupt on Receiver interrupt: Enables interrupt on indication from the HDCP Receiver.

Allows propagation of interrupts from downstream devices.

IE_LIST_RDY Interrupt on KSV List Ready: Enables interrupt on KSV List Ready.

IE_KSV_RDY Interrupt on KSV Ready: Enables interrupt on KSV Ready.

IE_AUTH_FAI Interrupt on Authentication Failure: Enables interrupt on authentication failure or loss of

authentication.

IE_AUTH_PAS Interrupt on Authentication Pass: Enables interrupt on successful completion of

authentication.

INT_EN

Global Interrupt Enable: Enables interrupt on the interrupt signal to the controller.

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Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

199

0xC7

ISR

0x00

IS_IND_ACC

Interrupt on Indirect Access Complete: Indirect Register Access has completed.

IS_RXDET_IN Interrupt on Receiver Detect interrupt: A downstream receiver has been detected. If

HDCP_CFG:RX_DET_SEL is set to a 1, the interrupt will wait for Receiver Lock Detect.

IS_RX_INT

Interrupt on Receiver interrupt: Receiver has indicated an interrupt request from down-

stream device.

IS_LIST_RDY Interrupt on KSV List Ready: The KSV list is ready for reading by the controller.

IS_KSV_RDY Interrupt on KSV Ready: The Receiver KSV is ready for reading by the controller.

IS_AUTH_FAI Interrupt on Authentication Failure: Authentication failure or loss of authentication has

occurred.

IS_AUTH_PAS Interrupt on Authentication Pass: Authentication has completed successfully.

INT

Global Interrupt: Set if any enabled interrupt is indicated.

200

0xC8

NVM_CTL

0x00

NVM_PASS

NVM Verify pass: This bit indicates the completion status of the NVM verification process.

This bit is valid only when NVM_DONE is asserted.

0: NVM Verify failed.

1: NVM Verify passed.

NVM_DONE

NVM Verify done: This bit indicates that the NVM Verifcation has completed.

NVM_PARALL NVM Parallel Load Enable: Setting this bit enables external parallel data to be written to

NVM SRAM. Byte data and a memory clock are brought in on the R[7:0] and G[0] pins

respectively. In this mode of operation NVM_DATA[0] acts as a memory enable to enable

writes to the NVM SRAM.

4:3

Reserved.

0x00

0xFF

NVM_VFY

NVM Verify: Setting this bit will enable a verification of the NVM contents. This is done by

reading all NVM keys, computing a SHA-1 hash value, and verifying against the SHA-1

hash stored in NVM. This bit will be cleared upon completion of the NVM Verification.

NVM_PROG

NVM Program: Setting this bit to a 1 allows programming of the NVM memory from the

NVM SRAM.

NVM_PROG_ NVM Program Enable: Set to a 1 to allow erase or programming of NVM.

206

224

226

227

0xCE

0xE0

0xE2

0xE3

BLUE_SCREEN

7:0

BLUE_SCREE Blue Screen Data Value: Provides the 8-bit data value sent on the Blue channel when the

N_VAL

HDCP Transmitter is sending a blue screen.

HDCP_DBG_ALI

HDCP_DBG

Read-only alias of HDCP_DBG register.

HDCP_CFG_ALI

HDCP_CFG

HDCP_CTL

Read-only alias of HDCP_CFG register.

Read-only alias of HDCP_CTL register.

HDCP_CTL_ALI

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Table 10. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

NAME

TYPE

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

Read-only alias of HDCP_STS register.

228

230

231

0xE4

0xE6

0xE7

HDCP_STS_ALI

7:0

HDCP_STS

HDCP_ICR_ALI

7:0

HDCP_ICR

HDCP_ISR

Read-only alias of HDCP_ICR register.

Read-only alias of HDCP_ISR register.

HDCP_ISR_ALI

240

241

242

243

244

245

0xF0

0xF1

0xF2

0xF3

0xF4

0xF5

TX ID

7:0

0x5F

0x55

0x48

0x39

0x34

0x39

ID0

ID1

ID2

ID3

ID4

ID5

First byte ID code: "_".

Second byte of ID code: "U".

Third byte of ID code: "H".

Fourth byte of ID code: "9".

Fifth byte of ID code: "4".

Sixth byte of ID code: “9”.

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Applications Information

The DS90UH949A-Q1, in conjunction with the DS90UH940A-Q1/DS90UH948A-Q1 deserializer, is intended to

interface between a host (graphics processor) and a display, supporting 24-bit color depth (RGB888) and high-

definition (2K) digital video format. The DS90UH949A-Q1 can receive an 8-bit RGB stream with a pixel clock rate

up to 210 MHz together with four I2S audio streams when paired with the DS90UH940A-Q1/DS90UH948A-Q1

deserializer.

8.2 Typical Applications

Bypass capacitors should be placed near the power supply pins. A capacitor and resistor are placed on the PDB

pin to delay the enabling of the device until power is stable. See 图 25 and 图 26 typical STP and coax

connection diagrams.

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Typical Applications (接下页)

VDD18

(Filtered1.8V)

1.8V

VDD18

VDDIO

VDDL11

VDDHA11

VDDHS11

VDDS11

1.1V

0.01µF

- 0.1µF

FB1

0.01µF

- 0.1µF

FB3

0.1µF

1µF

10µF

1µF 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

1µF

0.1µF

FB4

0.01µF

- 0.1µF

1µF

0.1µF

1µF

10µF

1.1V

0.01µF

- 0.1µF

0.01µF

- 0.1µF

FB2

10µF

1µF

0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

3.3V (DC coupled)/1.8V (AC coupled)

VDDA11

0.01µF

- 0.1µF

VTERM

FB5

VDDP11

0.01µF

- 0.1µF

IN_CLK+

IN_CLK-

DOUT0+

DOUT0-

IN_D0+

IN_D0-

FPD-Link III

TMDS

DOUT1+

DOUT1-

LFT

(DC coupled)

IN_D1+

IN_D1-

IN_D2+

IN_D2-

10nF

VDD18

(Filtered

1.8V)

IDx

MODE_SEL0

MODE_SEL1

0.1µF

RX_5V

HPD

Hot Plug Detect

3.3V

0.1µF

MOSI

MISO

SPLK

27k

47k

SPI

DDC_SDA

DDC_SCL

CEC

HDMI Control

V_DDI2C

1.8V

4.7k 4.7k 4.7k

4.7k

10k

SDA

SCL

I2C

Controller (Optional)

>10µF

PDB

INTB

Interrupts

REF CLKIN

REM_INTB

I2S_WC

I2S_CLK

I2S_DA

I2S_DB

I2S_DC

I2S_DD

SCLK

SWC

Aux Audio

SDIN

MCLK

I2S Audio

NOTE:

RES0

RES1

RES2

FB1,FB5: DCR<=0.3Ohm; Z=1Kohm@100MHz

FB2-FB4: DCR<=25mOhm; Z=120ohm@100MHz

C1-C4 = 0.1µF (50 WV; 0402) with DS90UH926/928

C1-C4 = 0.033µF (50 WV; 0402) with DS90UH940A/948A

R1 œ R2 (see IDx Resistor Values Table)

float

NC0

NC1

NC2

float

DAP

R3 œ R6 (see MODE_SEL Resistor Values Table)

V_DDI2C= Pull up voltage of I2C bus. Refer to I2CSEL pin

description for 1.8V or 3.3V operation.

DS90UH949A-Q1

图 25. Typical Application Connection -- STP

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Typical Applications (接下页)

VDD18

(Filtered 1.8V)

1.8V

VDD18

VDDIO

VDDL11

VDDHA11

VDDHS11

VDDS11

1.1V

0.01µF

- 0.1µF

FB1

0.01µF

- 0.1µF

FB3

0.1µF

1µF

10µF

1µF

0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

1µF

0.1µF

FB4

0.01µF

- 0.1µF

1µF

0.1µF

1µF

10µF

1.1V

0.01µF

- 0.1µF

0.01µF

- 0.1µF

FB2

10µF

1µF

0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

3.3V (DC coupled)/1.8V (AC coupled)

VDDA11

0.01µF

- 0.1µF

VTERM

FB5

VDDP11

0.01µF

- 0.1µF

IN_CLK+

IN_CLK-

DOUT0+

DOUT0-

IN_D0+

IN_D0-

FPD-Link III

TMDS

(DC coupled)

DOUT1+

DOUT1-

LFT

IN_D1+

IN_D1-

IN_D2+

IN_D2-

10nF

VDD18

(Filtered

1.8V)

IDx

MODE_SEL0

MODE_SEL1

0.1µF

RX_5V

HPD

Hot Plug Detect

3.3V

0.1µF

MOSI

MISO

SPLK

27k

47k

SPI

DDC_SDA

DDC_SCL

CEC

HDMI Control

V_DDI2C

1.8V

I2C

1.8V

4.7k 4.7k 4.7k

4.7k

10k

SDA

SCL

Controller (Optional)

>10µF

PDB

INTB

Interrupts

REM_INTB

REF CLKIN

I2S_WC

I2S_CLK

I2S_DA

I2S_DB

I2S_DC

I2S_DD

SCLK

SWC

Aux Audio

SDIN

MCLK

I2S Audio

RES0

RES1

RES2

NOTE:

float

NC0

NC1

NC2

FB1,FB5: DCR<=0.3Ohm; Z=1Kohm@100MHz

FB2-FB4: DCR<=25mOhm; Z=120ohm@100MHz

C1,C3 = 0.033µF (50 WV; 0402)

float

DAP

C2,C4 = 0.015µF (50 WV; 0402)

R1 œ R2 (see IDx Resistor Values Table)

R3 œ R6 (see MODE_SEL Resistor Values Table)

V_DDI2C= Pull up voltage of I2C bus. Refer to I2CSEL pin

description for 1.8V or 3.3V operation.

DS90UH949A-Q1

图 26. Typical Application Connection -- Coax

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Typical Applications (接下页)

SDA

t_BUF

t_f

t_HD;STA

t_SP

t_LOW

t_r

t_f

t_r

SCL

t_SU;STA

t_HD;STA

t_HD;DAT

t_SU;STO

t_HIGH

t_SU;DAT

STOP START

START

REPEATED

START

图 27. Typical System Diagram

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Typical Applications (接下页)

8.2.1 Design Requirements

The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme.

External AC-coupling capacitors must be placed in series in the FPD-Link III signal path as shown in 图 28.

表 11. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

VDDIO

1.8 V

AC Coupling Capacitor for

DOUT0± and DOUT1± with 92x

deserializers

100 nF

AC Coupling Capacitor for

DOUT0± and DOUT1± with 94x

deserializers

33 nF or 100nF

For applications using a single-ended, 50-Ω coaxial cable, the unused data pins (DOUT0–, DOUT1–) should use

a 15-nF capacitor and should be terminated with a 50-Ω resistor.

OUT

SER

DES

OUT

图 28. AC-Coupled Connection (STP)

OUT

SER

DES

OUT

50Q

图 29. AC-Coupled Connection (Coaxial)

For high-speed FPD–Link III transmissions, the smallest available package should be used for the AC-coupling

capacitor. This will help minimize degradation of signal quality due to package parasitics.

8.2.2 Detailed Design Procedure

8.2.2.1 High-Speed Interconnect Guidelines

See Channel-Link PCB and Interconnect Design-In Guidelines, (SNLA008) and Transmission Line

RAPIDESIGNER Operation and Application Guide (SNLA035) for full details.

•

Use 100-Ω coupled differential pairs

Use the S/2S/3S rule in spacings

–

S = space between the pair

2S = space between pairs

3S = space to LVCMOS signal

•

Minimize the number of Vias

Use differential connectors when operating above 500-Mbps line speed

Maintain balance of the traces

Minimize skew within the pair

Terminate as close to the TX outputs and RX inputs as possible

Additional general guidance can be found in the LVDS Owner's Manual (SNLA187) available on ti.com.

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8.2.3 Application Curves

图 30 corresponds to 1080p60 video application with 2-lane FPD-Link III output. 图 31 corresponds to 3.36Gbps

single-lane output from 96MHz input

图 30. Serializer Output at 2.975Gbps (85MHz Clock)

图 31. Serializer Output at 3.36Gbps (96MHz Clock)

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9 Power Supply Recommendations

This device provides separate power and ground pins for different portions of the circuit. This is done to isolate

switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not

required. The Pin Functions table in the Pin Configuration and Functions section provides guidance on which

circuit blocks are connected to which power pins. In some cases, an external filter many be used to provide clean

power to sensitive circuits such as PLLs.

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10 Layout

10.1 Layout Guidelines

Circuit board layout and stack-up for the LVDS serializer and deserializer devices should be designed to provide

low-noise power to the device. Good layout practice will also separate high frequency or high-level inputs and

outputs to minimize unwanted stray noise, feedback, and interference. Power system performance may be

greatly improved by using thin dielectrics (2 to 4 mil) for power / ground sandwiches. This arrangement uses the

plane capacitance for the PCB power system and has low-inductance, which has proven effectiveness especially

at high frequencies, and makes the value and placement of external bypass capacitors less critical. External

bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values

in the range of 0.01 μF to 10 μF. Tantalum capacitors may be in the 2.2-μF to 10-μF range. The voltage rating of

the tantalum capacitors should be at least 5X the power supply voltage being used.

MLCC surface mount capacitors are recommended due to their smaller parasitic properties. When using multiple

capacitors per supply pin, place the smaller value closest to the pin. A large bulk capacitor is recommended at

the point of power entry. This is typically in the 50-μF to 100-μF range and will smooth low frequency switching

noise. TI recommends connecting the power and ground pins directly to the power and ground planes with

bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground

pins to an external bypass capacitor will increase the inductance of the path. A small body size X7R chip

capacitor, such as 0603 or 0805, is recommended for external bypass. A small body sized capacitor has less

inductance. The user must pay attention to the resonance frequency of these external bypass capacitors, usually

in the range of 20 MHz to 30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve

low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common

practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency.

Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate

switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not

required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power

pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as

PLLs. For DS90UH949A-Q1, only one common ground plane is required to connect all device related ground

pins.

Use at least a four-layer board with a power and ground plane. Place LVCMOS signals away from the LVDS

lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely coupled differential lines of 100 Ω

are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise

will appear as common mode and thus is rejected by the receivers. The tightly coupled lines will also radiate

less.

At least 9 thermal vias are necessary from the device center DAP to the ground plane. They connect the device

ground to the PCB ground plane, as well as conduct heat from the exposed pad of the package to the PCB

ground plane. More information on the LLP style package, including PCB design and manufacturing

requirements, is provided in TI Leadless Leadframe Package (LLP) Application Report, (SNOA401).

10.2 Layout Example

图 32 is derived from a layout design of the DS90UH949A-Q1. This graphic is used to demonstrate proper high-

speed routing when designing in the Serializer.

图 32. DS90UH949A-Q1 Serializer Layout Example

DS90UH949A-Q1

ZHCSIO8 –AUGUST 2018

www.ti.com.cn

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

请参阅如下相关文档：

•

《焊接规格应用报告》，(SNOA549)

《IC 封装热指标应用报告》，(SPRA953)

《通道链路 PCB 和互连设计选型指南》，(SNLA008)

《传输线路 RAPIDESIGNER 操作和应用指南》，(SNLA035)

《无引线框架封装 (LLP) 应用报告》，(SNOA401)

《LVDS 用户手册》，(SNLA187)

《通过具有双向控制通道的 FPD-Link III 进行 I2C 通信》，(SNLA131)

《使用 DS90Ux92x FPD-Link III 器件的 I2S 音频接口》，(SNLA221)

《探索 720p FPD-Link III 器件的内部测试图案生成特性》，(SNLA132)

11.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.4 商标

TRI-STATE, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.6 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

DS90UH949ATRGCRQ1

DS90UH949ATRGCTQ1

ACTIVE

VQFN

RGC

2000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 105

UH949AQ

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

GENERIC PACKAGE VIEW

RGC 64

9 x 9, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224597/A

www.ti.com

PACKAGE OUTLINE

VQFN - 1 mm max height

RGC0064K

PLASTIC QUAD FLAT PACK- NO LEAD

9.1

8.9

9.1

8.9

PIN 1 INDEX AREA

1.00

0.80

SEATING PLANE

0.08 C

0.05

0.00

7.5

5.75±0.1

(0.2) TYP

60X 0.5

SYMM

7.5

0.30

64X

PIN 1 ID

(OPTIONAL)

0.18

SYMM

0.5

0.3

0.1

C A B

64X

0.05

4224668/B 08/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RGC0064K

PLASTIC QUAD FLAT PACK- NO LEAD

2X (8.8)

2X (7.5)

(

5.75)

64X (0.6)

64X (0.24)

60X (0.5)

(1.36)

SYMM

(7.5) (8.8)

(Ø0.2) VIA

TYP

(1.265)

(R0.05)

TYP

2X (1.36)

2X (1.265)

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 8X

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

0.07 MIN

ALL AROUND

EXPOSED METAL

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4224668/B 08/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271)

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RGC0064K

PLASTIC QUAD FLAT PACK- NO LEAD

2X (8.8)

2X (7.5)

16X ( 1.16)

64X (0.6)

64X (0.24)

60X (0.5)

(0.68)

SYMM

(7.5) (8.8)

METAL

TYP

(1.36)

(R0.05)

TYP

2X (0.68)

2X (1.36)

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

65% PRINTED COVERAGE BY AREA

SCALE: 8X

4224668/B 08/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122

DS90UH949ATRGCRQ1 [TI]

相关型号：

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SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E