DS90UH928Q-Q1 [TI]
具有 HDCP 的 5MHz 至 85MHz 24 位彩色 FPD-Link III 转 FPD-Link 解串器;
| 型号： | DS90UH928Q-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 HDCP 的 5MHz 至 85MHz 24 位彩色 FPD-Link III 转 FPD-Link 解串器 光电二极管 |
| 文件： | 总68页 (文件大小：1182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DS90UH928Q-Q1
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
DS90UH928Q-Q1 5MHz 至 85MHz 24 位彩色 FPD-Link III 至 FPD-Link
解串器，具有 HDCP 功能
1 特性
3 说明
1
•
•
•
支持片载密钥存储的集成型 HDCP 密码引擎
DS90UH928Q-Q1 解串器与 DS90UH925Q-Q1 或
DS90UH927Q-Q1 串行器配套使用，可针对汽车信息
娱乐系统内的内容受保护数字视频的安全分发提供一套
解决方案。。 该解串器借助嵌入式时钟（由单信号对
(FPD-Link III) 提供）将高速串行化接口数据转换为四
个低压差分信令 (LVDS) 数据/控制流、一个 LVDS 时
钟对 (FPD-Link) 以及 I2S 音频数据。 数字视频和音频
数据采用业界标准的 HDCP 复制保护方案加以保
护。FPD-Link III 串行总线方案支持通过单个差分链路
实现高速正向通道数据传输和低速全双工反向通道通
信。 通过单个差分对整合音频、视频和和控制数据可
减小互连线尺寸和重量，同时还消除了偏差问题并简化
了系统设计。
支持 HDCP 中继器应用
双向控制通道接口，可连接到 I2C 兼容串行控制总
线
•
•
•
•
•
•
低电磁干扰 (EMI) FPD-Link 视频输出
支持高清 (720p) 数字视频
支持 RGB888 + VS，HS，DE 和 I2S 音频
支持 5MHz、85MHz 像素时钟
多达 4 个针对环绕立体声应用的 I2S 数字音频输出
4 条具有 2 个专用引脚的双向通用输入输出 (GPIO)
通道
•
通过 1.8V 或 3.3V 兼容 LVCMOS I/O 接口实现
3.3V 单电源运行
•
•
•
•
•
•
长达 10 米的交流耦合屏蔽双绞线 (STP) 互连
具有嵌入式时钟的直流均衡和扰频数据
自适应电缆均衡
通过对串行输入数据流使用自适应输入均衡功能，可对
传输介质损耗和确定性抖动进行补偿。 通过使用低压
差分信令可最大限度减少电磁干扰 (EMI)。
图像增强（白平衡和抖动）和内部图案生成
汽车应用级产品：符合 AEC-Q100 2 级要求
串化器和解串器上都执行 HDCP 密钥引擎。 HDCP 密
钥被存储在片载存储器中。
>8kV 的人体模型 (HBM) 和 ISO 10605 静电放电
(ESD) 额定值
器件信息(1)
•
向后兼容模式
器件型号
封装
WQFN (48)
封装尺寸（标称值）
DS90UH928Q-Q1
7.00mm x 7.00mm
2 应用范围
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
•
•
汽车导航显示屏
后座娱乐系统
4 应用图
FPD-Link
FPD-Link
VDDIO
VDD33
VDD33
VDDIO
(1.8V or 3.3V) (3.3V)
(3.3V) (1.8V or 3.3V)
RxIN3+/-
RxIN2+/-
TxOUT3+/-
TxOUT2+/-
FPD-Link III
1 Pair/AC Coupled
DOUT+
DOUT-
RIN+
RIN-
HOST
Graphics
Processor
RGB Display
720p
24-bit Color Depth
RxIN1+/-
RxIN0+/-
TxOUT1+/-
TxOUT0+/-
100Q STP Cable
RxCLKIN+/-
TxCLKOUT+/-
INTB_IN
DS90UH927Q-Q1
Serializer
DS90UH928Q-Q1
Deserializer
OEN
LOCK
PDB
INTB
I2S
OSS_SEL
PDB
PASS
I2S
6
6
MAPSEL
LFMODE
REPEAT
BKWD
MAPSEL
LFMODE
BISTEN
MCLK
SCL
SDA
IDx
SCL
SDA
IDx
MODE_SEL
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SNLS440
DS90UH928Q-Q1
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
www.ti.com.cn
目录
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 28
8.5 Programming........................................................... 34
8.6 Register Maps......................................................... 36
Application and Implementation ........................ 53
9.1 Application Information............................................ 53
9.2 Typical Application .................................................. 53
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
应用图 ...................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ..................................... 5
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 DC Electrical Characteristics .................................... 7
7.6 AC Electrical Characteristics..................................... 9
7.7 Timing Requirements for the Serial Control Bus .... 10
7.8 Timing Requirements.............................................. 10
7.9 DC and AC Serial Control Bus Characteristics....... 11
7.10 Typical Characteristics.......................................... 15
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
9
10 Power Supply Recommendations ..................... 56
11 Layout................................................................... 56
11.1 Layout Guidelines ................................................. 56
11.2 Layout Example .................................................... 58
12 器件和文档支持 ..................................................... 60
12.1 文档支持................................................................ 60
12.2 商标....................................................................... 60
12.3 静电放电警告......................................................... 60
12.4 术语表 ................................................................... 60
13 机械封装和可订购信息 .......................................... 60
8
5 修订历史记录
Changes from Revision A (April 2013) to Revision B
Page
•
已添加 ESD 额定值表，特性描述部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文档
支持部分以及机械、封装和可订购信息部分 ........................................................................................................................... 1
2
Copyright © 2013–2015, Texas Instruments Incorporated
DS90UH928Q-Q1
www.ti.com.cn
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
6 Pin Configuration and Functions
RHS Package
48-Pin WQFN
Top View
I2S_DC/GPIO2
37
24
TxOUT0-
VDD33_A
RES1
38
39
23
22
21
20
19
18
17
16
15
TxOUT0+
TxOUT1-
TxOUT1+
TxOUT2-
TxOUT2+
RIN+ 40
RIN- 41
CMF 42
DS90UH928Q-Q1
TOP VIEW
43
44
45
46
47
48
BISTC/INTB_IN
CMLOUTP
TxCLKOUT-
TxCLKOUT+
TxOUT3-
DAP = GND
CMLOUTN
CAPR12
TxOUT3+
CAPP12
14 GPIO0
GPIO1
MODE_SEL
13
Pin Functions
PIN
I/O, TYPE
DESCRIPTION
NAME
NO.
FPD-LINK OUTPUT INTERFACE
TxCLKOUT-
TxCLKOUT+
TxOUT[3:0]-
TxOUT[3:0]+
18
17
O, LVDS
O, LVDS
O, LVDS
O, LVDS
Inverting LVDS Clock Output
The pair requires external 100Ω differential termination for standard LVDS levels
True LVDS Clock Output
The pair requires external 100Ω differential termination for standard LVDS levels
16, 20, 22,
24
Inverting LVDS Data Outputs
Each pair requires external 100Ω differential termination for standard LVDS levels
15, 19, 21,
23
True LVDS Data Outputs
Each pair requires external 100Ω differential termination for standard LVDS levels
LVCMOS INTERFACE
GPIO[1:0]
13, 14
I/O, LVCMOS General Purpose IO
with pulldown
GPIO[3:2]
36, 37
I/O, LVCMOS General Purpose I/O
with pulldown Shared with I2S_DD, I2S_DC
Copyright © 2013–2015, Texas Instruments Incorporated
3
DS90UH928Q-Q1
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
www.ti.com.cn
Pin Functions (continued)
PIN
I/O, TYPE
DESCRIPTION
NAME
NO.
GPIO_REG[8
:5]
8, 10, 7, 3
I/O, LVCMOS General Purpose I/O, register access only
with pulldown Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB
I2S_DA
I2S_DB
I2S_DC
I2S_DD
7
3
37
36
O, LVCMOS Digital Audio Interface I2S Data Outputs
Shared with GPIO_REG6, GPIO_REG5, GPIO2, GPIO3
INTB_IN
43
I, LVCMOS HDCP Interrupt Input
with pulldown Shared with BISTC
MCLK
I2S_WC
I2S_CLK
11
10
8
O, LVCMOS Digital Audio Interface I2S Master Clock, Word Clock and I2S Bit Clock Outputs
I2S_WC and I2S_CLK are shared with GPIO_REG7 and GPIO_REG8
CONTROL AND CONFIGURATION
BISTC
43
I, LVCMOS BIST Clock Select
with pulldown Shared with INTB_IN
Requires a 10-kΩ pullup if set HIGH
BISTEN
IDx
9
I, LVCMOS BIST Enable
with pulldown Requires a 10-kΩ pullup if set HIGH
12
I, Analog
I2C Address Select
External pullup to VDD33 is required under all conditions. DO NOT FLOAT.
Connect to external pullup to VDD33 and pulldown to GND to create a voltage divider.
See Table 6
LFMODE
MAPSEL
32
26
48
I, LVCMOS Low Frequency Mode Select
with pulldown LFMODE = 0, 15 MHz ≤ TxCLKOUT ≤ 85 MHz (Default)
LFMODE = 1, 5 MHz ≤ TxCLKOUT < 15 MHz
Requires a 10-kΩ pullup if set HIGH
I, LVCMOS FPD-Link Output Map Select
with pulldown MAPSEL = 0, LSBs on TxOUT3± (Default)
MAPSEL = 1, MSBs on TxOUT3±
Requires a 10-kΩ pullup if set HIGH
MODE_SEL
I, Analog
Device Configuration Select
Configures Backwards Compatibility (BKWD), Repeater (REPEAT), I2S 4-channel (I2S_B),
and Long Cable (LCBL) modes
Connect to external pullup to VDD33 and pulldown to GND resistors to create a voltage
divider. DO NOT FLOAT
See Table 5
OEN
30
35
1
I, LVCMOS Output Enable
with pulldown Requires a 10-kΩ pullup if set HIGH
See Table 4
OSS_SEL
PDB
I, LVCMOS Output Sleep State Select
with pulldown Requires a 10-kΩ pullup if set HIGH
See Table 4
I, LVCMOS Power-down Mode Input Pin
Must be driven or pulled up to VDD33. Refer to “Power Up Requirements and PDB Pin" in the
Applications Information Section.
PDB = H, device is enabled (normal operation)
PDB = L, device is powered down
When the device is in the powered down state, the LVDS and LVCMOS outputs are tri-state,
the PLL is shutdown, and IDD is minimized. Control Registers are RESET.
SCL
SDA
5
4
I/O, Open
Drain
I2C Clock Input/Output Interface
Must have an external pullup to VDD33. DO NOT FLOAT
Recommended pullup: 4.7 kΩ
I/O, Open
Drain
I2C Data Input/Output Interface
Must have an external pullup to VDD33. DO NOT FLOAT
Recommended pullup: 4.7 kΩ
STATUS
LOCK
27
O, LVCMOS LOCK Status Output
0: PLL is unlocked, I2S, GPIO, TxOUT[3:0]±, and TxCLKOUT± are idle with output states
controlled by OEN and OSS_SEL. May be used to indicate Link Status or Display Enable.
1: PLL is locked, outputs are active with output states controlled by OEN and OSS_SEL
Route to test point or pad (Recommended). Float if unused.
4
Copyright © 2013–2015, Texas Instruments Incorporated
DS90UH928Q-Q1
www.ti.com.cn
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
Pin Functions (continued)
PIN
I/O, TYPE
DESCRIPTION
NAME
NO.
PASS
28
O, LVCMOS PASS Status Output
0: One or more errors were detected in the received BIST payload (BIST Mode)
1: Error-free transmission (BIST Mode)
Route to test point or pad (Recommended). Float if unused.
FPD-LINK III SERIAL INTERFACE
CMF
42
45
44
41
40
Analog
O, LVDS
O, LVDS
I/O, LVDS
I/O, LVDS
Common Mode Filter
Requires a 0.1-µF capacitor to GND
CMLOUTN
CMLOUTP
RIN-
Inverting Loop-through Driver Output
Monitor point for equalized forward channel differential signal
True Loop-through Driver Output
Monitor point for equalized forward channel differential signal
FPD-Link III Inverting Input
The output must be AC-coupled with a 0.1-µF capacitor
RIN+
FPD-Link III True Input
The output must be AC-coupled with a 0.1-µF capacitor
POWER AND GROUND(1)
GND
DAP
Ground
Power
Power
Large metal contact at the bottom center of the device package
Connect to the ground plane (GND) with at least 9 vias
VDD33_A
VDD33_B
38
31
3.3-V Power to on-chip regulator
Each pin requires a 4.7-µF capacitor to GND
VDDIO
6
1.8 V/3.3 V LVCMOS I/O Power
Requires a 4.7-µF capacitor to GND
REGULATOR CAPACITOR
CAPI2S
2
CAP
Decoupling capacitor connection for on-chip regulator
Each requires a 4.7-µF decoupling capacitor to GND
CAPLV25
CAPLV12
CAPR12
CAPP12
25
29
46
47
CAPL12
33
CAP
GND
Decoupling capacitor connection for on-chip regulator
Requires two 4.7-µF decoupling capacitors to GND
OTHER
RES[1:0]
39, 34
Reserved
Connect to GND
(1) The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.
7 Specifications
7.1 Absolute Maximum Ratings(1) (2)
MIN
−0.3
−0.3
MAX
4.0
UNIT
V
(3)
Supply Voltage – VDD33
(3)
Supply Voltage – VDDIO
4.0
V
LVCMOS I/O Voltage
(VDDIO
0.3)
+
−0.3
−0.3
V
Deserializer Input Voltage
2.75
150
V
Junction Temperature
°C
48 LLP Package Maximum Power Dissipation Capacity at 25°C
Storage temperature, Tstg
−65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) For soldering specifications, see product folder at www.ti.com and SNOA549.
(3) The DS90UH928Q-Q1VDD33 and VDDIO voltages require a specific ramp rate during power up. The power supply ramp time must be
less than 1.5 ms with a monotonic rise.
Copyright © 2013–2015, Texas Instruments Incorporated
5
DS90UH928Q-Q1
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
www.ti.com.cn
UNIT
7.2 ESD Ratings
VALUE
±8000
±1250
±250
Human body model (HBM), per AEC Q100-002, all pins(1)
Charged device model (CDM), per AEC Q100-011, all pins
Machine model (MM)
Air Discharge (Pins 40, 41, 44, and 45)
±15000
±8000
±15000
±8000
±15000
(IEC, powered-up only)
RD = 330 Ω, CS = 150 pF
Electrostatic
discharge
Contact Discharge (Pins 40, 41, 44, and 45)
Air Discharge (Pins 40, 41, 44, and 45)
Contact Discharge (Pins 40, 41, 44, and 45)
Air Discharge (Pins 40, 41, 44, and 45)
V(ESD)
V
(ISO10605)
RD = 330 Ω, CS = 150 pF
(ISO10605)
RD = 2 kΩ, CS = 150 pF or
330 pF
Contact Discharge (Pins 40, 41, 44, and 45)
±8000
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
MIN NOM
MAX UNIT
(1)
Supply Voltage (VDD33
)
3.0
3.0
3.3
3.3
1.8
3.6
3.6
V
V
V
(1) (2)
LVCMOS Supply Voltage (VDDIO
)
Connect VDDIO to 3.3 V and use 3.3-V IOs
Connect VDDIO to 1.8 V and use 1.8-V IOs
1.71
1.89
Operating Free Air
Temperature (TA)
−40
+25
+105
°C
PCLK Frequency (out of TxCLKOUT±)
Supply Noise(3)
5
85 MHz
100 mVP-P
(1) The DS90UH928Q-Q1VDD33 and VDDIO voltages require a specific ramp rate during power up. The power supply ramp time must be
less than 1.5 ms with a monotonic rise.
(2) VDDIO should not exceed VDD33 by more than 300 mV (VDDIO < VDD33 + 0.3 V).
(3) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the VDD33 and VDDIO supplies
with amplitude >100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the
Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no
error when the noise frequency is less than 50 MHz.
7.4 Thermal Information
DS90UH928Q-Q1
THERMAL METRIC(1)
RHS (WQFN)
UNIT
48 PINS
26.4
4.4
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
4.3
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
ψJB
4.3
RθJC(bot)
0.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6
Copyright © 2013–2015, Texas Instruments Incorporated
DS90UH928Q-Q1
www.ti.com.cn
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
7.5 DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
(1) (2) (3)
PARAMETER
3.3 V LVCMOS I/O
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX UNIT
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
GPIO[3:0],
REG_GPIO[8:
5], LFMODE,
MAPSEL,
BISTEN,
2.0
VDDIO
0.8
V
V
VDDIO = 3.0 V to 3.6 V
GND
BISTC,
INTB_IN,
OEN,
IIN
Input Current
VIN = 0 V or VIN = 3.0 V to 3.6 V
−10
±1
+10
μA
OSS_SEL
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
2.0
VDDIO
0.7
V
V
GND
(4)PDB
VIN = 0 V or VIN = 3.0 V to 3.6 V
IIN
Input Current
−10
±1
+10
μA
(4)
VOH
VOL
IOS
HIGH Level Output Voltage
LOW Level Output Voltage
Output Short Circuit Current
IOH = -4 mA
IOL = +4 mA
VOUT = 0 V(5)
GPIO[3:0],
REG_GPIO[8:
5], MCLK,
2.4
0
VDDIO
0.4
V
V
−55
mA
I2S_WC,
I2S_CLK,
I2S_D[A:D],
LOCK, PASS
IOZ
Tri-state Output Current
VOUT = 0 V or VDDIO, PDB = L
−20
+20
μA
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, Ta = +25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
(4) PDB is specified to 3.3 V LVCMOS only and must be driven or pulled up to VDD33 or to VDDIO ≥ 3.0 V.
(5) IOS is not specified for an indefinite period of time. Do not hold in short circuit for more than 500 ms or part damage may result.
Copyright © 2013–2015, Texas Instruments Incorporated
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DS90UH928Q-Q1
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
www.ti.com.cn
MAX UNIT
DC Electrical Characteristics (continued)
(1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
1.8 V LVCMOS I/O
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
GPIO[3:0],
REG_GPIO[8:
5], LFMODE,
MAPSEL,
BISTEN,
0.65 *
VDDIO
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
VDDIO
V
V
VDDIO = 1.71 V to 1.89 V
0.35 *
VDDIO
0
BISTC,
INTB_IN,
OEN,
VIN = 0 V or VIN = 1.71 V to
1.89 V
IIN
Input Current
-10
10
μA
OSS_SEL
GPIO[3:0],
REG_GPIO[8:
5], MCLK,
I2S_WC,
I2S_CLK,
VDDIO -
0.45
VOH
HIGH Level Output Voltage
IOH = -4 mA
VDDIO
0.45
V
VOL
IOS
LOW Level Output Voltage
Output Short Circuit Current
IOL = +4 mA
VOUT = 0 V(5)
0
V
-35
mA
I2S_D[A:D],
LOCK, PASS
IOZ
TRI-STATE® Output Current
VOUT = 0 V or VDDIO, PDB = L,
-20
20
μA
FPD-LINK LVDS OUTPUT
Output Voltage Swing (single-
ended)
VOD
350
450
600
mV
VODp-p
ΔVOD
VOS
Differential Output Voltage
Output Voltage Unbalance
Common Mode Voltage
Offset Voltage Unbalance
Output Short Circuit Current
900
1
mV
mV
V
RL = 100 Ω
50
1.5
50
TxCLK±,
TxOUT[3:0]±
1.0
-500
-50
1.2
1
ΔVOS
IOS
mV
mA
VOUT = GND
-5
OEN = GND, VOUT = VDDIO or
GND, 0.8 V≤VIN≤1.6 V
IOZ
Output TRI-STATE® Current
500
μA
FPD-LINK III RECEIVER
VTH
VTL
VID
Input Threshold High
50
mV
mV
mV
V
Input Threshold Low
VCM = 2.1 V (Internal VBIAS)
Input Differential Threshold
Common-mode Voltage
100
RIN±
VCM
2.1
Internal Termination Resistance
(Differential)
RT
80
100
120
Ω
LOOP-THROUGH MONITOR OUTPUT
VODp-p Differential Output Voltage
CMLOUTP,
CMLOUTN
RL = 100 Ω
360
mV
SUPPLY CURRENT
IDD1
VDD33= 3.6 V
VDDIO = 3.6 V
VDDIO = 1.89 V
VDD33= 3.6 V
VDDIO = 3.6 V
VDDIO = 1.89 V
VDD33 = 3.6 V
VDDIO = 3.6 V
VDDIO = 1.89 V
190
0.1
0.1
185
0.1
0.1
3
250
1
mA
mA
mA
mA
mA
mA
mA
μA
Checkerboard Pattern
Random Pattern
IDDIO1
Supply Current
RL = 100Ω,
PCLK = 85MHz
1
IDD2
IDDIO2
IDDZ
8
500
250
PDB = 0 V, All other LVCMOS
inputs = 0 V
Supply Current — Power Down
100
50
IDDIOZ
μA
8
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7.6 AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
(1) (2) (3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX UNIT
GPIO
GPIO[3:0],
PCLK =
5MHz to
85MHz
GPIO Pulse Width, Forward
Channel
(4)
tGPIO,FC
See
>2/PCLK
s
(4)
(4)
tGPIO,BC
RESET
tLRST
GPIO Pulse Width, Back Channel See
GPIO[3:0]
20
2
µs
ms
PDB Reset Low Pulse
See
PDB
LOOP-THROUGH MONITOR OUTPUT
EW
Differential Output Eye Opening
Width
RL = 100 Ω, Jitter freq > f/40
RIN±
>0.4
UI
EH
Differential Output Eye Height
>300
mV
FPD-LINK LVDS OUTPUT
tTLHT
tTHLT
tDCCJ
Low to High Transition Time
RL = 100 Ω
TxCLK±,
TxOUT[3:0]±
0.25
0.25
0.5
0.5
275
55
ns
ns
ps
High to Low Transition Time
Cycle-to-Cycle Output Jitter
PCLK = 5 MHz
PCLK = 85 MHz
TxCLK±
170
35
tTTPn
Transmitter Pulse Position
5 MHz≤PCLK≤85 MHz
n=[6:0] for bits [6:0]
See Figure 13
TxOUT[3:0]±
0.5 + n
UI
UI
ΔtTTP
Offset Transmitter Pulse Position
(bit 6 - bit 0)
PCLK = 85 MHz
<0.1
tDD
Delay Latency
147*T
900
6
T
tTPDD
tTXZR
Power Down Delay Active to OFF
Enable Delay OFF to Active
µs
ns
FPD-LINK III INPUT
tDDLT
Lock Time(4)
5 MHz≤PCLK≤85 MHz
RIN±, LOCK
LOCK, PASS
6
40
ms
LVCMOS OUTPUTS
tCLH
Low to High Transition Time
CL = 8 pF
3
2
7
5
ns
ns
tCHL
High to Low Transition Time
BIST MODE
tPASS
BIST PASS Valid Time
PASS
MCLK
800
ns
I2S TRANSMITTER
tJ
Clock Output Jitter
2
ns
ns
TI2S
I2S Clock Period
PCLK=5 MHz to 85 MHz
I2S_CLK,
PCLK =
5MHz to
85MHz
>2/PCL
K or
(4) (5)
Figure 10,
>77
THC
TLC
I2S Clock High Time
Figure 10,
I2S_CLK
0.35
0.35
TI2S
TI2S
(5)
I2S Clock Low Time
I2S_CLK
(5)
Figure 10,
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, Ta = +25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
(4) Specification is ensured by design and is not tested in production.
(5) I2S specifications for tLC and tHC pulses must each be greater than 1 PCLK period to ensure sampling and supersedes the 0.35*TI2S_CLK
requirement. tLC and tHC must be longer than the greater of either 0.35*TI2S_CLK or 2*PCLK.
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AC Electrical Characteristics (continued)
(1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX UNIT
tsr
thr
I2S Set-up Time
I2S_WC
I2S_D[A:D]
0.2
TI2S
I2S Hold Time
I2S_WC
0.2
TI2S
I2S_D[A:D]
7.7 Timing Requirements for the Serial Control Bus
Over 3.3-V supply and temperature ranges unless otherwise specified.
(1) (2)
MIN
TYP
MAX UNIT
fSCL
Standard Mode
Fast Mode
0
0
100 kHz
SCL Clock Frequency
SCL Low Period
400 kHz
tLOW
Standard Mode
Fast Mode
4.7
1.3
4.0
0.6
4.0
µs
µs
µs
µs
µs
tHIGH
Standard Mode
Fast Mode
SCL High Period
tHD;STA
Hold time for a start or a
Standard Mode
repeated start condition
(3)
Fast Mode
0.6
4.7
0.6
µs
µs
µs
tSU:STA
Set Up time for a start or a
Standard Mode
Fast Mode
repeated start condition
(3)
tHD;DAT
tSU;DAT
tSU;STO
Standard Mode
Fast Mode
0
0
3.45
0.9
µs
µs
ns
ns
µs
Data Hold Time
(3)
Standard Mode
Fast Mode
250
100
4.0
Data Set Up Time
(3)
Set Up Time for STOP
Standard Mode
Condition
(3)
Fast Mode
0.6
4.7
1.3
µs
µs
µs
Bus Free Time
Standard Mode
Fast Mode
tBUF
Between STOP and START
(3)
Standard Mode
Fast Mode
1000
300
300
300
ns
ns
ns
ns
SCL & SDA Rise Time,
tr
tf
(3)
Standard Mode
Fast mode
SCL & SDA Fall Time,
(3)
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = +25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
(3) Specification is ensured by design and is not tested in production.
7.8 Timing Requirements
MIN
NOM
430
20
MAX
UNIT
ns
tR
SDA RiseTime – READ
SDA Fall Time – READ
Set Up Time — READ
Hold Up Time — READ
SDA, RPU = 10 kΩ, Cb ≤
400 pF, Figure 9
tF
ns
tSU;DAT
tHD;DAT
Figure 9
Figure 9
560
615
ns
ns
10
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7.9 DC and AC Serial Control Bus Characteristics
Over 3.3-V supply and temperature ranges unless otherwise specified.
(1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIH
VIL
0.7*
VDDIO
Input High Level
SDA and SCL
SDA and SCL
VDD33
V
V
0.3*
VDD33
Input Low Level Voltage
Input Hysteresis
GND
VHY
VOL
Iin
>50
mV
V
SDA or SCL, IOL = 1.25 mA
0
0.36
+10
SDA or SCL, Vin = VDDIO or GND
-10
µA
ns
pF
tSP
Cin
Input Filter
50
<5
Input Capacitance
SDA or SCL
(1) The Electrical Characteristics tables list specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not
ensured.
(2) Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = +25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
+VOD
TxCLKOUT
-VOD
+VOD
TxOUT3
-VOD
+VOD
TxOUT2
-VOD
+VOD
TxOUT1
-VOD
+VOD
TxOUT0
-VOD
Cycle N
Cycle N+1
Figure 1. Checkerboard Data Pattern
EW
VOD (+)
RIN
(Diff.)
EH
0V
EH
VOD (-)
t
(1 UI)
BIT
Figure 2. CML Output Driver
V
DDIO
80%
20%
GND
t
t
CHL
CLH
Figure 3. LVCMOS Transition Times
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START
BIT
STOP
BIT
START
BIT
STOP
BIT
START
BIT
STOP
BIT
START STOP
BIT BIT
SYMBOLN+3
SYMBOLN
SYMBOLN+1
SYMBOLN+2
RIN
DCA, DCB
t
DD
TxCLKOUT
TxOUT[3:0]
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
Figure 4. Latency Delay
PDB
VILmax
RIN
X
t
TPDD
LOCK
PASS
Z
Z
TxCLKOUT
TxOUT[3:0]
Z
Z
Figure 5. FPD-Link & LVCMOS Power Down Delay
PDB
LOCK
OEN
t
TXZR
VIHmin
Z
Z
TxCLKOUT
TxOUT[3:0]
Figure 6. FPD-Link Outputs Enable Delay
PDB
VIH(min)
RIN±
tDDLT
LOCK
VOH(min)
TRI-STATE
Figure 7. CML PLL Lock Time
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RIN+
RIN-
VTL
VCM
VTH
GND
Figure 8. FPD-Link III Receiver DC VTH/VTL Definition
V
DDIO
I2S_CLK,
MCLK
1/2 V
DDIO
GND
V
DDIO
GPIO,
I2S_WC,
I2S_D[D:A]
V
OHmin
V
OLmax
GND
t
t
ROH
ROS
Figure 9. Output Data Valid (Setup and Hold) Times
PDB = H
VIH
OSS_SEL
OEN
VIL
VIH
VIL
RIN
(Diff.)
'RQ¶Wꢀ&DUH
t
SEH
t
SES
t
t
ONH
ONS
TRI-STATE
LOCK
(HIGH)
ACTIVE
PASS
HIGH
HIGH
GPIO,
I2S_WC,
I2S_D[A..D]
TRI-STATE
TRI-STATE
LOW
LOW
TRI-STATE
TRI-STATE
ACTIVE
ACTIVE
LOW
LOW
I2S_CLK
Figure 10. Output State (Setup and Hold) Times
+VOD
0V
80%
TxOUT[3:0]
TxCLKOUT
(Differential)
20%
-VOD
t
t
HLT
LHT
Figure 11. Input Transition Times
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TxOUT[3:0]+
TxCLKOUT+
VOD-
VOD+
TxOUT[3:0]-
TxCLKOUT-
VOS
GND
(TxOUT[3:0]+) -
(TxOUT[3:0]-) or
(TxCLKOUT+) -
(TxCLKOUT-)
VOD+
0V
VODp-p
VOD-
Figure 12. FPD-Link Single-Ended and Differential Waveforms
T
TxCLKOUT±
TxOUT[3:0]±
bit 1 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
t
t
t
t
t
t
t
TTP1
TTP2
TTP3
TTP4
TTP5
TTP6
TTP7
0.5UI
1.5UI
2.5UI
2¨t
TTP
3.5UI
4.5UI
5.5UI
6.5UI
Figure 13. FPD-Link Transmitter Pulse Positions
Ideal Data
Bit End
Sampling
Window
Ideal Data Bit
Beginning
V
TH
0V
RxIN_TOL
Left
RxIN_TOL
Right
V
TL
Ideal Center Position (t /2)
BIT
t
(1 UI)
BIT
t
IJIT = RxIN_TOL (Left + Right)
Sampling Window = 1 UI - t
IJIT
Figure 14. Receiver Input Jitter Tolerance
BISTEN
1/2 V
DDIO
t
PASS
1/2 V
PASS
(w/errors)
DDIO
Result Held
Prior BIST Result
Current BIST Test - Toggle on Error
Figure 15. BIST PASS Waveform
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SDA
SCL
t
BUF
t
f
t
t
HD;STA
t
r
LOW
t
t
f
r
t
t
HD;STA
SU;STA
t
SU;STO
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
START
REPEATED
START
Figure 16. Serial Control Bus Timing Diagram
7.10 Typical Characteristics
Input to Serializer
Output at Deserializer
Figure 17. Serializer Output Stream with 48MHz Input Clock
Figure 18. 48MHz Clock at Serializer and Deserializer
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8 Detailed Description
8.1 Overview
The DS90UH928Q-Q1 receives a 35-bit symbol over a single serial FPD-Link III pair operating at up to 2.975
Gbps line rate and converts this stream into an FPD-Link Interface (4 LVDS data channels + 1 LVDS Clock). The
FPD-Link III serial stream contains an embedded clock, video control signals, and the DC-balanced video data
and audio data which enhance signal quality to support AC coupling.
The DS90UH928Q-Q1 deserializer attains lock to a data stream without the use of a separate reference clock
source, which greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the
serializer regardless of the data pattern, delivering true automatic “plug and lock” performance. It can lock to the
incoming serial stream without the need of special training patterns or sync characters. The deserializer recovers
the clock and data by extracting the embedded clock information, validating then deserializing the incoming data
stream. It also applies decryption through a High-Bandwidth Digital Content Protection (HDCP) Cipher to this
video and audio data stream following reception of the data from the FPD-Link III decoder. On-chip non-volatile
memory stores the HDCP keys. All key exchange is done through the FPD-Link III bidirectional control interface.
The decrypted FPD-Link LVDS video bus is provided to the display.
The DS90UH928Q-Q1 deserializer incorporates an I2C compatible interface. The I2C compatible interface allows
programming of serializer or deserializer devices from a local host controller. In addition, the devices incorporate
a bidirectional control channel (BCC) that allows communication between serializer/deserializer as well as remote
I2C slave devices.
The bidirectional control channel (BCC) is implemented via embedded signaling in the high-speed forward
channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to
serializer). Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial link
from one I2C bus to another. The implementation allows for arbitration with other I2C compatible masters at either
side of the serial link.
The DS90UH928Q-Q1 deserializer is intended for use with DS90UH925Q-Q1 or DS90UH927Q-Q1 serializers,
but is also backward compatible with DS90UR905Q and DS90UR907Q FPD-Link II serializers.
8.2 Functional Block Diagram
OEN
REGULATOR
OSS_SEL
CMF
TxOUT3±
TxOUT2±
RIN+
TxOUT1±
RIN-
TxOUT0±
TxCLKOUT±
8
I2S / GPIO
Error
Detector
BISTEN
BISTC
PASS
LFMODE
MAPSEL
Clock and
Data
Recovery
PDB
SCL
SCA
LOCK
Timing and
Control
IDx
MODE_SEL
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8.3 Feature Description
8.3.1 High Speed Forward Channel Data Transfer
The High Speed Forward Channel is composed of a 35-bit frame containing video data, sync signals, HDCP, I2C,
and I2S audio transmitted from serializer to deserializer. Figure 19 illustrates the serial stream PCLK cycle. This
data payload is optimized for signal transmission over an AC coupled link. Data is randomized, DC-balanced and
scrambled.
C0
C1
Figure 19. FPD-Link III Serial Stream
The device supports pixel clock ranges of 5 MHz to 15 MHz (LFMODE=1) and 15 MHz to 85 MHz (LFMODE=0).
This corresponds to an application payload rate range of 155 Mbps to 2.635 Gbps, with an actual line rate range
of 525 Mbps to 2.975 Gbps.
8.3.2 Low Speed Back Channel Data Transfer
The Low-Speed Back Channel of the DS90UH928Q-Q1 provides bidirectional communication between the
display and host processor. The back channel control data is transferred over the single serial link along with the
high-speed forward data, DC balance coding and embedded clock information. Together, the forward channel
and back channel for the bidirectional control channel (BCC). This architecture provides a backward path across
the serial link together with a high speed forward channel. The back channel contains the I2C, HDCP, CRC and 4
bits of standard GPIO information with 10 Mbps line rate.
8.3.3 Backward Compatible Mode
The DS90UH928Q-Q1 is also backward compatible to the DS90UR905Q and DS90UR907Q for PCLK
frequencies ranging from 15 MHz to 65 MHz. The deserializer receives 28-bits of data over a single serial FPD-
Link II pair operating at a payload rate of 120 Mbps to 1.8 Gbps, corresponding to a line rate of 140 Mbps to 2.1
Gbps. The Backward Compatibility configuration can be selected through the MODE_SEL pin or programmed
through the device control registers (Table 7). The bidirectional control channel, HDCP, bidirectional GPIOs, I2S,
and interrupt (INTB) are not active in this mode. However, local I2C access to the serializer is still available. Note:
PCLK frequency range in this mode is 15 MHz to 65 MHz for LFMODE=0 and 5 MHZ to <15 MHz for
LFMODE=1.
8.3.4 Input Equalization
An FPD-Link III input adaptive equalizer provides compensation for transmission medium losses and reduces
medium-induced deterministic jitter. It equalizes up to 10m STP cables with 3 connection breaks at maximum
serializer stream payload rate of 2.975 Gbps.
The adaptive equalizer may be set to a Long Cable Mode (LCBL), using the MODE_SEL pin (Table 5). This
mode is typically used with longer cables where it may be desirable to start adaptive equalization from a higher
default gain. In this mode, the device attempts to lock from a minimum floor AEQ value, defined by a value
stored in the control registers (Table 7).
8.3.5 Common Mode Filter Pin (CMF)
The deserializer provides access to the center tap of the internal CML termination. A 0.1-μF capacitor must be
connected from this pin to GND for additional common-mode filtering of the differential pair (Figure 39). This
increases noise rejection capability in high-noise environments.
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Feature Description (continued)
8.3.6 Power Down (PDB)
The deserializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin may be controlled by
an external device, or through VDDIO, where VDDIO = 3.0 V to 3.6 V or VDD33. To save power, disable the link
when the display is not needed (PDB = LOW). Ensure that this pin is not driven HIGH before VDD33 and VDDIO
have reached final levels. When PDB is driven low, ensure that the pin is driven to 0 V for at least 1.5 ms before
releasing or driving high (See Recommended Operating Conditions). In the case where PDB is pulled up to VDDIO
= 3.0 V to 3.6 V or VDD33 directly, a 10-kΩ pullup resistor and a >10-µF capacitor to ground are required (See
Figure 39 ).
Toggling PDB low will POWER DOWN the device and RESET all control registers to default. During this time,
PDB must be held low for a minimum of 2 ms (See AC Electrical Characteristics).
8.3.7 Video Control Signals
The video control signal bits embedded in the high-speed FPD-Link LVDS are subject to certain limitations
relative to the video pixel clock period (PCLK). By default, the device applies a minimum pulse width filter on
these signals to help eliminate spurious transitions.
Normal Mode Control Signals (VS, HS, DE) have the following restrictions:
•
Horizontal Sync (HS): The video control signal pulse width must be 3 PCLKs or longer when the Control
Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this
restriction (minimum is 1 PCLK). See Table 7. HS can have at most two transitions per 130 PCLKs.
•
•
Vertical Sync (VS): The video control signal pulse is limited to 1 transition per 130 PCLKs. Thus, the minimum
pulse width is 130 PCLKs.
Data Enable Input (DE): The video control signal pulse width must be 3 PCLKs or longer when the Control
Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this
restriction (minimum is 1 PCLK). See Table 7. DE can have at most two transitions per 130 PCLKs.
8.3.8 EMI Reduction Features
8.3.8.1 LVCMOS VDDIO Option
The 1.8 V/3.3 V LVCMOS inputs and outputs are powered from a separate VDDIO supply pin to offer
compatibility with external system interface signals. Note: When configuring the VDDIO power supplies, all the
single-ended control input pins (except PDB) for device need to scale together with the same operating VDDIO
levels. If VDDIO is selected to operate in the 3.0 V to 3.6 V range, VDDIO must be operated within 300 mV of VDD33
(See Recommended Operating Conditions).
8.3.9 Built In Self Test (BIST)
An optional At-Speed Built-In Self Test (BIST) feature supports testing of the high speed serial link and the low-
speed back channel without external data connections. This is useful in the prototype stage, equipment
production, in-system test, and system diagnostics.
8.3.9.1 BIST Configuration and Status
The BIST mode is enabled at the deserializer by pin (BISTEN) or BIST configuration register. The test may
select either an external PCLK or the 33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK,
the user can select the internal OSC frequency at the deserializer through the BISTC pin or BIST configuration
register.
When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer through the Back
Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test
pattern and monitors it for errors. The deserializer PASS output pin toggles to flag each frame received
containing one or more errors. The serializer also tracks errors indicated by the CRC fields in each back channel
frame.
18
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Feature Description (continued)
The BIST status can be monitored real time on the deserializer PASS pin, with each detected error resulting in a
half pixel clock period toggled LOW. After BIST is deactivated, the result of the last test is held on the PASS
output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low
on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width
applied to the deserializer BISTEN pin. LOCK status is valid throughout the entire duration of BIST.
See Figure 20 for the BIST mode flow diagram.
8.3.9.1.1 Sample BIST Sequence
1. BIST Mode is enabled via the BISTEN pin of Deserializer. The desired clock source is selected through the
deserializer BISTC pin.
2. The serializer is awakened through the back channel if it is not already on. An all-zeros pattern is balanced,
scrambled, randomized, and sent through the FPD-Link III interface to the deserializer. Once the serializer
and the deserializer are in BIST mode and the deserializer acquires LOCK, the PASS pin of the deserializer
goes high and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the
PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be
monitored and counted to determine the payload error rate.
3. To Stop BIST mode, set the BISTEN pin LOW. The deserializer stops checking the data, and the final test
result is held on the PASS pin. If the test ran error free, the PASS output will remain HIGH. If there one or
more errors were detected, the PASS output will output constant LOW. The PASS output state is held until a
new BIST is run, the device is RESET, or the device is powered down. BIST duration is user-controlled and
may be of any length.
The link returns to normal operation after the deserializer BISTEN pin is low. Figure 21 shows the waveform
diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In
most cases it is difficult to generate errors due to the robustness of the link (differential data transmission etc.),
thus they may be introduced by greatly extending the cable length, faulting the interconnect medium, or reducing
signal condition enhancements (Rx Equalization).
Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: DES/SER in Normal
Figure 20. BIST Mode Flow Diagram
8.3.9.2 Forward Channel and Back Channel Error Checking
The deserializer, on locking to the serial stream, compares the recovered serial stream with all-zeroes and
records any errors in status registers. Errors are also dynamically reported on the PASS pin of the deserializer.
Forward channel errors may also be read from register 0x25 (Table 7).
The back-channel data is checked for CRC errors once the serializer locks onto the back-channel serial stream,
as indicated by link detect status (register bit 0x0C[0] - Table 7). CRC errors are recorded in an 8-bit register in
the deserializer. The register is cleared when the serializer enters the BIST mode. As soon as the serializer
enters BIST mode, the functional mode CRC register starts recording any back channel CRC errors. The BIST
mode CRC error register is active in BIST mode only and keeps the record of the last BIST run until cleared or
the serializer enters BIST mode again.
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Feature Description (continued)
BISTEN
(DES)
TxCLKOUT
TxOUT[3:0]
7 bits/frame
DATA
(internal)
PASS
Prior Result
Prior Result
PASS
FAIL
X = bit error(s)
DATA
(internal)
X
X
X
PASS
BIST
Result
Held
Normal
SSO
Normal
BIST Test
BIST Duration
Figure 21. BIST Waveforms
8.3.10 Internal Pattern Generation
The DS90UH928Q-Q1 deserializer features an internal pattern generator. It allows basic testing and debugging
of an integrated panel. The test patterns are simple and repetitive and allow for a quick visual verification of
panel operation. As long as the device is not in power down mode, the test pattern will be displayed even if no
input is applied. If no clock is received, the test pattern can be configured to use a programmed oscillator
frequency. For detailed information, refer to TI Application Note: ( ).
8.3.10.1 Pattern Options
The DS90UH928Q-Q1 deserializer pattern generator is capable of generating 17 default patterns for use in basic
testing and debugging of panels. Each pattern can be inverted using register bits (see Table 7). The 17 default
patterns are listed as follows:
1. White/Black (default/inverted)
2. Black/White
3. Red/Cyan
4. Green/Magenta
5. Blue/Yellow
6. Horizontally Scaled Black to White/White to Black
7. Horizontally Scaled Black to Red/Cyan to White
8. Horizontally Scaled Black to Green/Magenta to White
9. Horizontally Scaled Black to Blue/Yellow to White
10. Vertically Scaled Black to White/White to Black
11. Vertically Scaled Black to Red/Cyan to White
12. Vertically Scaled Black to Green/Magenta to White
13. Vertically Scaled Black to Blue/Yellow to White
14. Custom Color / Inverted configured in PGRS
15. Black-White/White-Black Checkerboard (or custom checkerboard color, configured in PGCTL)
16. YCBR/RBCY VCOM pattern, orientation is configurable from PGCTL
17. Color Bars (White, Yellow, Cyan, Green, Magenta, Red, Blue, Black) – Note: not included in the auto-
scrolling feature
20
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Feature Description (continued)
8.3.10.2 Color Modes
By default, the Pattern Generator operates in 24-bit color mode, where all bits of the Red, Green, and Blue
outputs are enabled. 18-bit color mode can be activated from the configuration registers (Table 7). In 18-bit
mode, the 6 most significant bits (bits 7-2) of the Red, Green, and Blue outputs are enabled; the 2 least
significant bits will be 0.
8.3.10.3 Video Timing Modes
The Pattern Generator has two video timing modes – external and internal. In external timing mode, the Pattern
Generator detects the video frame timing present on the DE and VS inputs. If Vertical Sync signaling is not
present on VS, the Pattern Generator determines Vertical Blank by detecting when the number of inactive pixel
clocks (DE = 0) exceeds twice the detected active line length. In internal timing mode, the Pattern Generator
uses custom video timing as configured in the control registers. The internal timing generation may also be
driven by an external clock. By default, external timing mode is enabled. Internal timing or Internal timing with
External Clock are enabled by the control registers (Table 7). If internal clock generation is used, register 0x39
bit 1 must be set.
8.3.10.4 External Timing
In external timing mode, the Pattern Generator passes the incoming DE, HS, and VS signals unmodified to the
video control outputs after a two pixel clock delay. It extracts the active frame dimensions from the incoming
signals in order to properly scale the brightness patterns. If the incoming video stream does not use the VS
signal, the Pattern Generator determines the Vertical Blank time by detecting a long period of pixel clocks without
DE asserted.
8.3.10.5 Pattern Inversion
The Pattern Generator also incorporates a global inversion control, located in the PGCFG register, which causes
the output pattern to be bitwise-inverted. For example, the full screen Red pattern becomes full-screen cyan, and
the Vertically Scaled Black to Green pattern becomes Vertically Scaled White to Magenta.
8.3.10.6 Auto Scrolling
The Pattern Generator supports an Auto-Scrolling mode, in which the output pattern cycles through a list of
enabled pattern types. A sequence of up to 16 patterns may be defined in the registers. The patterns may
appear in any order in the sequence and may also appear more than once.
8.3.10.7 Additional Features
Additional pattern generator features can be accessed through the Pattern Generator Indirect Register Map. It
consists of the Pattern Generator Indirect Address (PGIA — Table 7) and the Pattern Generator Indirect Data
(PGID — Table 7).
8.3.11 Image Enhancement Features
Several image enhancement features are provided. The White Balance LUTs allow the user to define and map
the color profile of the display. Adaptive Hi-FRC Dithering enables the presentation of 'true color' images on an
18-bit display.
8.3.11.1 White Balance
The White Balance feature enables similar display appearance when using LCD’s from different vendors. It
compensates for native color temperature of the display, and adjusts relative intensities of R, G, and B to
maintain specified color temperature. Programmable control registers are used to define the contents of three
LUTs (8-bit color value for Red, Green and Blue) for the White Balance Feature. The LUTs map input RGB
values to new output RGB values. There are three LUTs, one LUT for each color. Each LUT contains 256
entries, 8-bits per entry with a total size of 6144 bits (3 x 256 x 8). All entries are readable and writable.
Calibrated values are loaded into registers through the I2C interface (deserializer is a slave device). This feature
may also be applied to lower color depth applications such as 18–bit (666) and 16–bit (565). White balance is
enabled and configured via serial control bus register.
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Feature Description (continued)
8.3.11.1.1 LUT Contents
The user must define and load the contents of the LUT for each color (R,G,B). Regardless of the color depth
being driven (888, 666, 656), the user must always provide contents for 3 complete LUTs - 256 colors x 8 bits x 3
tables. Unused bits - LSBs -shall be set to “0” by the user.
When 24-bit (888) input data is being driven to a 24-bit display, each LUT (R, G and B) must contain 256 unique
8-bit entries. The 8-bit white balanced data is then available at the output of the deserializer, and driven to the
display.
The user must define and load the contents of the LUT for each color (R,G,B). Regardless of the color depth
being driven (888, 666, 656), the user must always provide contents for 3 complete LUTs - 256 colors x 8 bits x 3
tables. Unused bits - LSBs -shall be set to “0” by the user. When 24-bit (888) input data is being driven to a 24-
bit display, each LUT (R, G and B) must contain 256 unique 8-bit entries. The 8-bit white balanced data is then
available at the output of the deserializer, and driven to the display.
Alternatively, with 6-bit input data the user may choose to load complete 8-bit values into each LUT. This mode
of operation provides the user with finer resolution at the LUT output to more closely achieve the desired white
point of the calibrated display. Although 8-bit data is loaded, only 64 unique 8-bit white balance output values are
available for each color (R, G and B). The result is 8-bit white balanced data. Before driving to the output of the
deserializer, the 8-bit data must be reduced to 6-bit with an FRC dithering function. To operate in this mode, the
user must configure the deserializer to enable the FRC2 function.
Examples of the three types of LUT configurations described are shown in Figure 22.
8.3.11.1.2 Enabling White Balance
The user must load all 3 LUTs prior to enabling the white balance feature. The following sequence must be
followed by the user.
To initialize white balance after power-on:
1. Load contents of all 3 LUTs . This requires a sequential loading of LUTs - first RED, second GREEN, third
BLUE. 256, 8-bit entries must be loaded to each LUT. Page registers must be set to select each LUT.
2. Enable white balance. By default, the LUT data may not be reloaded after initialization at power-on.
An option does exist to allow LUT reloading after power-on and initial LUT loading (as described above). This
option may only be used after enabling the white balance reload feature via the associated serial control bus
register. In this mode the LUTs may be reloaded by the master controller via I2C. This provides the user with the
flexibility to refresh LUTs periodically , or upon system requirements to change to a new set of LUT values. The
host controller loads the updated LUT values via the serial bus interface. There is no need to disable the white
balance feature while reloading the LUT data. Refreshing the white balance to the new set of LUT data will be
seamless - no interruption of displayed data.
It is important to note that initial loading of LUT values requires that all 3 LUTs be loaded sequentially. When
reloading, partial LUT updates may be made.
22
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Feature Description (continued)
8-bit in / 8 bit out
6-bit in / 6 bit out
6-bit in / 8 bit out
Gray level Data Out
Gray level Data Out
Gray level Data Out
Entry
(8-bits)
Entry
(8-bits)
Entry
(8-bits)
0
1
2
3
4
5
6
7
8
9
00000000b
00000001b
00000011b
00000011b
00000110b
00000110b
00000111b
00000111b
00001000b
00001010b
0
00000000b
0
00000001b
1 N/A
2 N/A
3 N/A
1 N/A
2 N/A
3 N/A
4
00000100b
4
00000110b
5 N/A
6 N/A
7 N/A
5 N/A
6 N/A
7 N/A
8
00001000b
8
00001011b
9 N/A
10 N/A
11 N/A
9 N/A
10 N/A
11 N/A
10 00001001b
11 00001011b
248 11111010b
249 11111010b
250 11111011b
251 11111011b
252 11111110b
253 11111101b
254 11111101b
255 11111111b
248 11111000b
249 N/A
248 11111010b
249 N/A
250 N/A
250 N/A
251 N/A
251 N/A
252 11111100b
253 N/A
252 11111111b
253 N/A
254 N/A
255 N/A
254 N/A
255 N/A
Figure 22. White Balance LUT Configuration
8.3.11.2 Adaptive Hi-FRC Dithering
The Adaptive FRC Dithering Feature delivers product-differentiating image quality. It reduces 24-bit RGB (8 bits
per sub-pixel) to 18-bit RGB (6 bits per sub-pixel), smoothing color gradients, and allowing the flexibility to use
lower cost 18-bit displays. FRC (Frame Rate Control) dithering is a method to emulate “missing” colors on a
lower color depth LCD display by changing the pixel color slightly with every frame. FRC is achieved by
controlling on and off pixels over multiple frames (Temporal). Static dithering regulates the number of on and off
pixels in a small defined pixel group (Spatial). The FRC module includes both Temporal and Spatial methods and
also Hi-FRC. Conventional FRC can display only 16,194,277 colors with 6-bit RGB source. “Hi-FRC” enables full
(16,777,216) color on an 18-bit LCD panel. The “adaptive” FRC module also includes input pixel detection to
apply specific Spatial dithering methods for smoother gray level transitions. When enabled, the lower LSBs of
each RGB output are not active; only 18 bit data (6 bits per R,G and B) are driven to the display. This feature is
enabled via serial control bus register. Two FRC functional blocks are available, and may be independently
enabled. FRC1 precedes the white balance LUT, and is intended to be used when 24-bit data is being driven to
an 18-bit display with a white balance LUT that is calibrated for an 18-bit data source. The second FRC block,
RC2, follows the white balance block and is intended to be used when fine adjustment of color temperature is
required on an 18-bit color display, or when a 24-bit source drives an 18-bit display with a white balance LUT
calibrated for 24-bit source data.
For proper operation of the FRC dithering feature, the user must provide a description of the display timing
control signals. The timing mode, “sync mode” (HS, VS) or “DE only” must be specified, along with the active
polarity of the timing control signals. All this information is entered to device control registers via the serial bus
interface.
Adaptive Hi-FRC dithering consists of several components. Initially, the incoming 8-bit data is expanded to 9-bit
data. This allows the effective dithered result to support a total of 16.7 million colors. The incoming 9-bit data is
evaluated, and one of four possible algorithms is selected. The majority of incoming data sequences are
supported by the default dithering algorithm. Certain incoming data patterns (black/white pixel, full on/off sub-
pixel) require special algorithms designed to eliminate visual artifacts associated with these specific gray level
transitions. Three algorithms are defined to support these critical transitions.
An example of the default dithering algorithm is illustrated in Figure 23. The 1 or 0 value shown in the table
describes whether the 6-bit value is increased by 1 (“1”) or left unchanged (“0”). In this case, the 3 truncated
LSBs are “001”.
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www.ti.com.cn
Feature Description (continued)
F0L0
PD1
Frame = 0, Line = 0
Pixel Data one
Cell Value 010
R[7:2]+0, G[7:2]+1, B[7:2]+0
LSB=001
three lsb of 9 bit data (8 to 9 for Hi-Frc)
Pixel Index
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
LSB = 001
F0L0
F0L1
F0L2
F0L3
010
101
000
000
000
000
000
000
000
000
010
101
000
000
000
000
000
101
010
000
000
000
000
000
010
000
000
101
000
000
000
000
R = 4/32
G = 4/32
B = 4/32
F1L0
F1L1
F1L2
F1L3
000
000
000
000
000
111
000
000
000
000
000
000
000
000
000
111
000
000
000
000
000
111
000
000
000
000
000
000
000
000
000
111
R = 4/32
G = 4/32
B = 4/32
F2L0
F2L1
F2L2
F2L3
000
000
010
101
000
000
000
000
010
101
000
000
000
000
000
000
010
000
000
101
000
000
000
000
000
101
010
000
000
000
000
000
R = 4/32
G = 4/32
B = 4/32
F3L0
F3L1
F3L2
F3L3
000
000
000
000
000
000
000
111
000
000
000
000
000
111
000
000
000
000
000
000
000
000
000
111
000
000
000
000
000
111
000
000
R = 4/32
G = 4/32
B = 4/32
Figure 23. Default FRC Algorithm
8.3.12 Serial Link Fault Detect
The DS90UH928Q-Q1 can detect fault conditions in the FPD-Link III interconnect. If a fault condition occurs, the
Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x0C (Table 7). The device will detect any of
the following conditions:
1. Cable open
2. RIN+ to - short
3. RIN+ to GND short
4. RIN- to GND short
5. RIN+ to battery short
6. RIN- to battery short
7. Cable is linked incorrectly (RIN+/RIN- connections reversed)
NOTE
The device will detect any of the above conditions, but does not report specifically which
one has occurred.
8.3.13 Oscillator Output
The deserializer provides an optional TxCLKOUT± output when the input clock (serial stream) has been lost.
This is based on an internal oscillator and may be controlled from register 0x02, bit 5 (OSC Clock Output Enable)
Table 7.
8.3.14 Interrupt Pin (INTB)
1. On the serializer, set register (HDCP_ICR) 0xC6[5] = 1 and 0xC6[0] = 1 (Table 7) to configure the interrupt.
2. On the serializer, read from HDCP_ISR register 0xC7 to arm the interrupt for the first time.
24
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Feature Description (continued)
3. When INTB_IN is set LOW, the INTB pin on the serializer also pulls low, indicating an interrupt condition.
4. The external controller detects INTB = LOW and reads the HDCP_ISR register (Table 7) to determine the
interrupt source. Reading this register also clears and resets the interrupt.
8.3.15 General-Purpose I/O
8.3.15.1 GPIO[3:0]
In normal operation, GPIO[3:0] may be used as general purpose IOs in either forward channel (outputs) or back
channel (inputs) mode. GPIO modes may be configured from the registers (Table 7). GPIO[1:0] are dedicated
pins and GPIO[3:2] are shared with I2S_DC and I2S_DD respectively. Note: if the DS90UH928Q-Q1 is paired
with a DS90UH925Q-Q1 serializer, the devices must be configured into 18-bit mode to allow usage of GPIO pins
on the serializer. To enable 18-bit mode, set serializer register 0x12[2] = 1. 18-bit mode will be auto-loaded into
the deserializer from the serializer. See Table 1 for GPIO enable and configuration.
Table 1. GPIO Enable and Configuration
DESCRIPTION
DEVICE
FORWARD CHANNEL
BACK CHANNEL
GPIO3
DS90UH925Q-
0x0F = 0x03
0x0F = 0x05
Q1/DS90UH927Q-Q1
DS90UH928Q-Q1
0x1F = 0x05
0x0E = 0x30
0x1F = 0x03
0x0E = 0x50
GPIO2
GPIO1
GPIO0
DS90UH925Q-
Q1/DS90UH927Q-Q1
DS90UH928Q-Q1
0x1E = 0x50
0x0E = 0x03
0x1E = 0x30
0x0E = 0x05
DS90UH925Q-
Q1/DS90UH927Q-Q1
DS90UH928Q-Q1
0x1E = 0x05
0x0D = 0x03
0x1E = 0x03
0x0D = 0x05
DS90UH925Q-
Q1/DS90UH927Q-Q1
DS90UH928Q-Q1
0x1D = 0x05
0x1D = 0x03
The input value present on GPIO[3:0] may also be read from register, or configured to local output mode
(Table 7).
8.3.15.2 GPIO[8:5]
GPIO_REG[8:5] are register-only GPIOs and may be programmed as outputs or read as inputs through local
register bits only. Where applicable, these bits are shared with I2S pins and will override I2S input if enabled into
GPIO_REG mode. See Table 2 for GPIO enable and configuration.
Note: Local GPIO value may be configured and read either through local register access, or remote register
access through the Low-Speed Bidirectional Control Channel. Configuration and state of these pins are not
transported from serializer to deserializer as is the case for GPIO[3:0].
Table 2. GPIO_REG and GPIO Local Enable and Configuration
DESCRIPTION
REGISTER CONFIGURATION
0x21 = 0x01
FUNCTION
Output, L
GPIO_REG8
0x21 = 0x09
Output, H
0x21 = 0x03
Input, Read: 0x6F[0]
Output, L
GPIO_REG7
GPIO_REG6
0x21 = 0x01
0x21 = 0x09
Output, H
0x21 = 0x03
Input, Read: 0x6E[7]
Output, L
0x20 = 0x01
0x20 = 0x09
Output, H
0x20 = 0x03
Input, Read: 0x6E[6]
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Table 2. GPIO_REG and GPIO Local Enable and Configuration (continued)
DESCRIPTION
REGISTER CONFIGURATION
0x20 = 0x01
FUNCTION
Output, L
GPIO_REG5
0x20 = 0x09
Output, H
0x20 = 0x03
Input, Read: 0x6E[5]
Output, L
GPIO3
GPIO2
GPIO1
GPIO0
0x1F = 0x01
0x1F = 0x09
0x1F = 0x03
0x1E = 0x01
0x1E = 0x09
0x1E = 0x03
0x1E = 0x01
0x1E = 0x09
0x1E = 0x03
0x1D = 0x01
0x1D = 0x09
0x1D = 0x03
Output, H
Input, Read: 0x6E[3]
Output, L
Output, H
Input, Read: 0x6E[2]
Output, L
Output, H
Input, Read: 0x6E[1]
Output, L
Output, H
Input, Read: 0x6E[0]
8.3.16 I2S Audio Interface
The DS90UH928Q-Q1 deserializer features six I2S output pins that, when paired with a DS90UH927Q-
Q1serializer, supports surround sound audio applications. The bit clock (I2S_CLK) supports frequencies between
1 MHz and the smaller of <PCLK/2 or <13 MHz. Four I2S data outputs carry two channels of I2S-formatted
digital audio each, with each channel delineated by the word select (I2C_WC) input. The I2S audio interface is
not available in Backwards Compatibility Mode (BKWD = 1).
Deserializer
System Clock
MCLK
Bit Clock
I2S_CLK
I2S Receiver
4
Word Select
Data
I2S_WC
I2S_Dx
Figure 24. I2S Connection Diagram
I2S_WC
I2S_CLK
MSB
LSB
MSB
LSB
I2S_Dx
Figure 25. I2S Frame Timing Diagram
When paired with a DS90UH925Q-Q1, the DS90UH928Q-Q1 I2S interface supports a single I2S data output
through I2S_DA (24-bit video mode), or two I2S data outputs through I2S_DA and I2S_DB (18-bit video mode).
26
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8.3.16.1 I2S Transport Modes
By default, packetized audio is received during video blanking periods in dedicated Data Island Transport frames.
The transport mode is set in the serializer and auto-loaded into the deserializer by default. The audio
configuration may be disabled from control registers if Forward Channel Frame Transport of I2S data is desired.
In frame transport, only I2S_DA is received to the DS90UH928Q-Q1 deserializer. Surround Sound Mode, which
transmits all four I2S data inputs (I2S_D[D:A]), may only be operated in Data Island Transport mode. This mode
is only available when connected to a DS90UH927Q-Q1 serializer. If connected to a DS90UH925Q-Q1serializer,
only I2S_DA and I2S_DB may be received.
8.3.16.2 I2S Repeater
I2S audio may be fanned-out and propagated in the repeater application. By default, data is propagated via Data
Island Transport on the FPD-Link interface during the video blanking periods. If frame transport is desired, then
the I2S pins should be connected from the deserializer to all serializers. Activating surround sound at the top-
level serializer automatically configures downstream serializers and deserializers for surround sound transport
utilizing Data Island Transport. If 4-channel operation utilizing I2S_DA and I2S_DB only is desired, this mode
must be explicitly set in each serializer and deserializer control register throughout the repeater tree (Table 7).
A DS90UH928Q-Q1 deserializer configured in repeater mode may also regenerate I2S audio from its I2S input
pins in lieu of Data Island frames. See the HDCP Repeater Connection Diagram (Figure 31) and the I2C Control
Registers (Table 7) for additional details.
8.3.16.3 I2S Jitter Cleaning
The DS90UH928Q-Q1 features a standalone PLL to clean the I2S data jitter, supporting high-end car audio
systems. If I2S_CLK frequency is less than 1MHz, this feature must be disabled through register 0x2B[7]. See
Table 7.
8.3.16.4 MCLK
The deserializer has an I2S Master Clock Output (MCLK). It supports x1, x2, or x4 of I2S CLK Frequency. When
the I2S PLL is disabled, the MCLK output is off. Table 3 covers the range of I2S sample rates and MCLK
frequencies. By default, all the MCLK output frequencies are x2 of the I2S CLK frequencies. The MCLK
frequencies can also be enabled through the register bits 0x3A[6:4] (I2S DIVSEL), shown in Table 7. To select
desired MCLK frequency, write 0x3A[7], then write to bit [6:4] accordingly.
Table 3. Audio Interface Frequencies
SAMPLE RATE
I2S DATA WORD SIZE (BITS) I2S_CLK (MHz)
MCLK OUTPUT (MHz)
REGISTER 0x3A[6:4]'b
(kHz)
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
000
001
010
000
001
010
000
001
010
001
010
011
010
011
100
32
1.024
44.1
48
1.4112
16
1.536
3.072
6.144
96
192
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Table 3. Audio Interface Frequencies (continued)
SAMPLE RATE
(kHz)
I2S DATA WORD SIZE (BITS) I2S_CLK (MHz)
MCLK OUTPUT (MHz)
REGISTER 0x3A[6:4]'b
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
000
001
010
001
010
011
001
010
011
010
011
100
011
100
101
001
010
011
001
010
011
001
010
011
010
011
100
011
100
110
32
44.1
48
1.536
2.117
24
2.304
4.608
9.216
2.048
2.8224
3.072
6.144
12.288
96
192
32
44.1
48
32
96
192
8.4 Device Functional Modes
8.4.1 Clock and Output Status
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK is TRI-STATE or LOW
(depending on the value of the OEN setting). After the deserializer completes its lock sequence to the input serial
data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is available
on the LVCMOS and LVDS outputs. The State of the outputs is based on the OEN and OSS_SEL setting
(Table 4) or register bit (Table 7).
Table 4. Output State Table
INPUTS
OEN
OUTPUTS
DATA/GPIO/I2S
SERIAL
INPUT
TxCLKOUT/Tx
OUT[3:0]
PDB
OSS_SEL
LOCK
PASS
X
X
X
L
H
H
X
L
L
X
L
Z
Z
L
Z
Z
L
Z
Z
L
Z
L or H
L or H
H
28
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Device Functional Modes (continued)
Table 4. Output State Table (continued)
INPUTS
OUTPUTS
L/OSC (Register
EN)
Static
H
H
L
L
L
L
Static
Active
Active
H
H
H
H
H
H
H
L
L
L
Previous Status
L
L
L
L
L
H
H
Valid
Valid
Valid
8.4.2 FPD-Link Input Frame and Color Bit Mapping Select
The DS90UH928Q-Q1 can be configured to output 24-bit color (RGB888) or 18-bit color (RGB666) with 2
different mapping schemes, shown in Figure 26, or MSBs on TxOUT[3], shown in Figure 27. Each frame
corresponds to a single pixel clock (PCLK) cycle. The LVDS clock output from TxCLKOUT± follows a 4:3 duty
cycle scheme, with each 28-bit pixel frame starting with two LVDS bit clock periods high, three low, and ending
with two high. The mapping scheme is controlled by MAPSEL pin or by Register (Table 7).
TxCLKOUT
Previous cycle
Current cycle
B[1]
(bit 26)
B[0]
(bit 25)
G[1]
(bit 24)
G[0]
(bit 23)
R[1]
(bit 22)
R[0]
(bit 21)
TxOUT3
TxOUT2
DE
(bit 20)
VS
(bit 19)
HS
(bit 18)
B[7]
(bit 17)
B[6]
(bit 16)
B[5]
(bit 15)
B[4]
(bit 14)
B[3]
(bit 13)
B[2]
(bit 12)
G[7]
(bit 11)
G[6]
(bit 10)
G[5]
(bit 9)
G[4]
(bit 8)
G[3]
(bit 7)
TxOUT1
TxOUT0
G[2]
(bit 6)
R[7]
(bit 5)
R[6]
(bit 4)
R[5]
(bit 3)
R[4]
(bit 2)
R[3]
(bit 1)
R[2]
(bit 0)
Figure 26. 24-bit Color FPD-Link Mapping: LSBs on TxOUT3 (MAPSEL=L)
TxCLKOUT
Previous cycle
Current cycle
B[7]
(bit 26)
B[6]
(bit 25)
G[7]
(bit 24)
G[6]
(bit 23)
R[7]
(bit 22)
R[6]
(bit 21)
TxOUT3
TxOUT2
DE
(bit 20)
VS
(bit 19)
HS
(bit 18)
B[5]
(bit 17)
B[4]
(bit 16)
B[3]
(bit 15)
B[2]
(bit 14)
B[1]
(bit 13)
B[0]
(bit 12)
G[5]
(bit 11)
G[4]
(bit 10)
G[3]
(bit 9)
G[2]
(bit 8)
G[1]
(bit 7)
TxOUT1
TxOUT0
G[0]
(bit 6)
R[5]
(bit 5)
R[4]
(bit 4)
R[3]
(bit 3)
R[2]
(bit 2)
R[1]
(bit 1)
R[0]
(bit 0)
Figure 27. 24-bit ColorFPD-Link Mapping: MSBs on TxOUT3 (MAPSEL=H)
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TxCLKOUT
Previous cycle
Current cycle
TxOUT3
TxOUT2
DE
(bit 20)
VS
(bit 19)
HS
(bit 18)
B[5]
(bit 17)
B[4]
(bit 16)
B[3]
(bit 15)
B[2]
(bit 14)
B[1]
(bit 13)
B[0]
(bit 12)
G[5]
(bit 11)
G[4]
(bit 10)
G[3]
(bit 9)
G[2]
(bit 8)
G[1]
(bit 7)
TxOUT1
TxOUT0
G[0]
(bit 6)
R[5]
(bit 5)
R[4]
(bit 4)
R[3]
(bit 3)
R[2]
(bit 2)
R[1]
(bit 1)
R[0]
(bit 0)
Figure 28. 18-bit Color FPD-Link Mapping (MAPSEL = L)
TxCLKOUT
Previous cycle
Current cycle
B[5]
(bit 26)
B[4]
(bit 25)
G[5]
(bit 24)
G[4]
(bit 23)
R[5]
(bit 22)
R[4]
(bit 21)
TxOUT3
TxOUT2
DE
(bit 20)
VS
(bit 19)
HS
(bit 18)
B[3]
(bit 17)
B[2]
(bit 16)
B[1]
(bit 15)
B[0]
(bit 14)
G[3]
(bit 11)
G[2]
(bit 10)
G[1]
(bit 9)
G[0]
(bit 8)
TxOUT1
TxOUT0
R[3]
(bit 5)
R[2]
(bit 4)
R[1]
(bit 3)
R[0]
(bit 2)
Figure 29. 18-bit Color FPD-Link Mapping (MAPSEL = H)
8.4.3 Low Frequency Optimization (LFMODE)
The LFMODE is set via register (Table 7) or by the LFMODE Pin. This mode optimizes device operation for
lower input data clock ranges supported by the serializer. If LFMODE is Low (LFMODE=0, default), the
TxCLKOUT± PCLK frequency is between 15 MHz and 85 MHz. If LFMODE is High (LFMODE=1), the
TxCLKOUT± frequency is between 5 MHz and <15 MHz. Note: when the device LFMODE is changed, a PDB
reset is required. When LFMODE is high (LFMODE=1), the line rate relative to the input data rate is multiplied by
four. Thus, for the operating range of 5 MHz to <15 MHz, the line rate is 700 Mbps to <2.1 Gbps with an effective
data payload of 175 Mbps to 525 Mbps. Note: for Backwards Compatibility Mode (BKWD=1), the line rate relative
to the input data rate remains the same.
8.4.4 Mode Select (MODE_SEL)
Device configuration may be done via the MODE_SEL pin or via register (Table 7). A pullup resistor and a
pulldown resistor of suggested values may be used to set the voltage ratio of the MODE_SEL input (VR4) and
VDD33 to select one of the 9 possible selected modes. See Figure 30 and Table 5.
30
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V
DD33
R
3
VR4
MODE_SEL
Deserializer
R
4
Figure 30. MODE_SEL Connection Diagram
Table 5. Configuration Select (MODE_SEL)
Suggested
Resistor R3
(kΩ, 1% tol)
Suggested
Resistor R4
(kΩ, 1% tol)
Ideal Ratio
Ideal
VR4 (V)
NO.
REPEAT
BKWD
I2S_B
LCBL
(VR4/VDD33
)
1
2
3
4
5
6
7
8
9
0
0
OPEN
294
255
267
255
226
205
162
124
40.2
40.2
49.9
76.8
102
130
165
191
210
L
L
L
L
L
L
L
L
L
H
L
L
0.120
0.164
0.223
0.286
0.365
0.446
0.541
0.629
0.397
0.540
0.737
0.943
1.205
1.472
1.786
2.075
L
H
L
L
H
H
L
L
H
L
L
H
H
H
H
L
L
H
L
H
H
L
H
L
8.4.5 Repeater Connections
The HDCP Repeater requires the following connections between the HDCP Receiver and each HDCP
Transmitter Figure 31.
1. Video Data – Connect all FPD-Link data and clock pairs
2. I2C – Connect SCL and SDA signals. Both signals should be pulled up to VDD33 or VDDIO = 3.0 V to 3.6 V
with 4.7-kΩ resistors.
3. Audio (optional) – Connect I2S_CLK, I2S_WC, and I2S_Dx signals.
4. IDx pin – Each Transmitter and Receiver must have an unique I2C address.
5. REPEAT & MODE_SEL pins — All Transmitters and Receivers must be set into Repeater Mode.
6. Interrupt pin – Connect DS90UH928Q-Q1 INTB_IN pin to the DS90UH927Q-Q1 INTB pin. The signal must
be pulled up to VDDIO with a 10-kΩ resistor.
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Deserializer
Serializer
RxIN0+
TxOUT0+
RxIN0-
TxOUT0-
TxOUT1+
TxOUT1-
RxIN1+
RxIN1-
RxIN2+
RxIN2-
TxOUT2+
TxOUT2-
RxIN3+
RxIN3-
TxOUT3+
TxOUT3-
RxCLKIN+
RxCLKIN-
TxCLKOUT+
TxCLKOUT-
VDD33
VDD33
MODE_SEL
REPEAT
I2S_CLK
I2S_WC
I2S_Dx
I2S_CLK
I2S_WC
I2S_Dx
Optional
VDDIO
VDD33
VDD33
IDx
IDx
INTB
INTB_IN
VDD33
SDA
SCL
SDA
SCL
Figure 31. HDCP Repeater Connection Diagram
8.4.5.1 Repeater Fan-Out Electrical Requirements
Repeater applications requiring fan-out from one DS90UH928Q-Q1 deserializer to up to three DS90UH927Q-Q1
serializers requires special considerations for routing and termination of the FPD-Link differential traces.
Figure 32 details the requirements that must be met for each signal pair:
L3 < 60 mm
TX
R1=100ꢀ
R2=100ꢀ
RX
TX
TX
L1 < 75 mm
L2 < 60 mm
L3 < 60 mm
Figure 32. FPD-Link Fan-Out Electrical Requirements
32
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8.4.6 HDCP I2S Audio Encryption
Depending on the quality and specifications of the audiovisual source, HDCP encryption of digital audio may be
required. When HDCP is active, packetized Data Island Transport audio is also encrypted along with the video
data per HDCP v.1.3. I2S audio transmitted in Forward Channel Frame Transport mode is not encrypted. System
designers should consult the specific HDCP specifications to determine if encryption of digital audio is required
by the specific application audiovisual source.
8.4.7 Repeater Configuration
The HDCP Cipher function is implemented in the deserializer per HDCP v1.3 specification. The DS90UH928Q-
Q1 provides HDCP decryption of audiovisual content when connected to an HDCP capable FPD-Link III
serializer. HDCP authentication and shared key generation is performed using the HDCP Control Channel, which
is embedded in the forward and backward channels of the serial link. On-chip Non-Volatile Memory (NVM) is
used to store the HDCP keys. The confidential HDCP keys are loaded by TI during the manufacturing process
and are not accessible external to the device.
The supported HDCP Repeater application provides a mechanism to extend HDCP transmission over multiple
links to multiple display devices. It authenticates all HDCP devices in the system and distributes protected
content to the HDCP Receivers using the encryption mechanisms provided in the HDCP specification.
1:3 Repeater
1:3 Repeater
Display
Display
RX
RX
TX
TX
TX
RX
TX
TX
TX
Source
TX
RX
Display
RX
1:3 Repeater
Display
Display
RX
RX
TX
TX
TX
RX
Display
RX
1:3 Repeater
Display
Display
RX
RX
TX
TX
TX
RX
Display
RX
Figure 33. HDCP Maximum Repeater Application
In the HDCP repeater application, this document refers to the DS90UH927Q-Q1 or DS90UH925Q-Q1 as the
HDCP Transmitter (TX), and refers to the DS90UH928Q-Q1 or DS90UH926Q-Q1 as the HDCP Receiver (RX).
Figure 33 shows the maximum configuration supported for HDCP Repeater implementations. Two levels of
HDCP Repeaters are supported with a maximum of three HDCP Transmitters per HDCP Receiver.
In a repeater application, the I2C interface at each TX and RX is configured to transparently pass I2C
communications upstream or downstream to any I2C device within the system. This includes a mechanism for
assigning alternate IDs (Slave Aliases) to downstream devices in the case of duplicate addresses.
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To support HDCP Repeater operation, the RX includes the ability to control the downstream authentication
process, assemble the KSV list for downstream HDCP Receivers, and pass the KSV list to the upstream HDCP
Transmitter. An I2C master within the RX communicates with the I2C slave within the TX. The TX handles
authenticating with a downstream HDCP Receiver and makes status available through the I2C interface. The RX
monitors the transmit port status for each TX and reads downstream KSV and KSV list values from the TX.
In addition to the I2C interface used to control the authentication process, the HDCP Repeater implementation
includes two other interfaces. The FPD-Link LVDS interface outputs the unencrypted video data. In addition to
providing the video data, the LVDS interface communicates control information and packetized audio data. All
audio and video data is decrypted at the output of the HDCP Receiver and is re-encrypted by the HDCP
Transmitter. Figure 34 provides more detailed block diagram of a 1:2 HDCP repeater configuration.
If the repeater node includes a local output to a display, White Balancing and Hi-FRC dithering functions should
not be used as they will block encrypted I2S audio and HDCP authentication.
HDCP Transmitter
TX
downstream
Receiver
or
Repeater
I2C
Slave
I2C
I2C
Master
upstream
Transmitter
FPD-Link
I2S Audio
HDCP Transmitter
TX
HDCP Receiver
(RX)
downstream
Receiver
or
I2C
Slave
Repeater
FPD-Link III interfaces
Figure 34. HDCP 1:2 Repeater Configuration
8.5 Programming
8.5.1 Serial Control Bus
The DS90UH928Q-Q1 may also be configured by the use of an I2C compatible serial control bus. Multiple
devices may share the serial control bus (up to 10 device addresses supported). The device address is set via a
resistor divider (R1 and R2 — see Figure 35) connected to the IDx pin.
VDD33
VDD33
R1
R2
VR2
IDx
4.7kQ
4.7kQ
HOST
DES
SCL
SDA
SCL
SDA
To other
Devices
Figure 35. Serial Control Bus Connection
The serial control bus consists of two signals and an address configuration pin. SCL is a Serial Bus Clock
Input/Output. SDA is the Serial Bus Data Input/Output signal. Both SCL and SDA signals require an external
pullup resistor to VDD33 or VDDIO = 3.0 V to 3.6 V. For most applications, a 4.7-kΩ pullup resistor to VDD33 is
recommended. The signals are either pulled HIGH, or driven LOW.
34
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Programming (continued)
The IDx pin configures the control interface to one of 10 possible device addresses. A pullup resistor and a
pulldown resistor should be used to set the appropriate voltage ratio between the IDx input pin (VR2) and VDD33
,
each ratio corresponding to a specific device address. See Table 7 below.
Table 6. Serial Control Bus Addresses for IDx
SUGGESTED
RESISTOR R1 kΩ
(1% tol)
SUGGESTED
RESISTOR R2 kΩ
(1% tol)
IDEAL RATIO
VR2 / VDD33
IDEAL VR2
(V)
NO.
ADDRESS 7'b
ADDRESS 8'b
1
2
0
0
OPEN
226
215
200
187
174
154
150
137
90.9
40.2 or >10
97.6
113
0x2C
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x58
0x66
0x68
0x6A
0x6C
0x6E
0x70
0x72
0x74
0x76
0.995
1.137
1.282
1.413
1.570
1.707
1.848
1.997
2.535
0.302
0.345
0.388
0.428
0.476
0.517
0.560
0.605
0.768
3
4
127
5
140
6
158
7
165
8
191
9
210
10
301
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See
Figure 36.
SDA
SCL
S
P
START condition, or
STOP condition
START repeat condition
Figure 36. START and STOP Conditions
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus LOW. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled HIGH. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 37 and a WRITE is shown in Figure 38.
Register Address
Slave Address
Slave Address
Data
a
c
k
a
c
k
a
c
k
a
c
k
A
2
A
1
A
0
A
2
A
1
A
0
0
S
S
1
P
Figure 37. Serial Control Bus — READ
Register Address
Slave Address
Data
a
c
k
a
c
k
a
c
k
A
2
A
1
A
0
0
S
P
Figure 38. Serial Control Bus — WRITE
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To support I2C transactions over the BCC. the I2C Master located at the DS90UH928Q-Q1 deserializer must
support I2C clock stretching. For more information on I2C interface requirements and throughput considerations,
please refer to TI Application Note SNLA131.
8.6 Register Maps
Table 7. Serial Control Bus Registers(1) (2)
ADD
(dec)
ADD
(hex)
Register
Type
Default
(hex)
Register Name
Bit
Function
Description
0
0x00 I2C Device ID
7:1
RW
IDx
Device ID
7–bit address of Deserializer
Note: Read-only unless bit 0 is set
0
RW
ID Setting
I2C ID Setting
0: Device ID is from IDx pin
1: Register I2C Device ID overrides IDx pin
1
0x01 Reset
7:3
2
0x04
Reserved
RW
RW
BC Enable Back Channel Enable
0: Disable
1: Enable
1
0
7
Digital
RESET1
Reset the entire digital block including registers
This bit is self-clearing.
0: Normal operation (default)
1: Reset
RW
RW
Digital
RESET0
Reset the entire digital block except registers
This bit is self-clearing
0: Normal operation (default)
1: Reset
2
0x02 General
Configuration 0
0x00
OEN
LVCMOS Output Enable. Self-clearing on loss of
LOCK
0: Disable, Tristate Outputs (default)
1: Enable
6
5
RW
RW
OEN/OSS_ Output Enable and Output Sleep State Select override
SEL
Override
0: Disable over-write (default)
1: Enable over-write
Auto Clock OSC Clock Output. Enable On loss of lock, OSC
Enable
clock is output onto TxCLK±
0: Disable (default)
1: Enable
4
RW
OSS_SEL
Output Sleep State Select. Enable Select to control
output state during lock low period
0: Disable, Tri-State Outputs (default)
1: Enable
3
2
1
0
RW
RW
RW
RW
BKWD
Override
Backwards Compatibility Mode Override
0: Use MODE_SEL pin (default)
1: Use register bit to set BKWD mode
BKWD
Mode
Backwards Compatibility Mode Select
0: Backwards Compatibility Mode disabled (default)
1: Backwards Compatibility Mode enabled
LFMODE
Override
Low Frequency Mode Override
0: Use LFMODE pin (default)
1: User register bit to set LFMODE
LFMODE
Low Frequency Mode
0: 15MHz ≤ PCLK ≤ 85MHz (default)
1: 5MHz ≤ PCLK < 15MHz
(1) Addresses not listed are reserved.
(2) Do not alter Reserved fields from their default values.
36
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Register Maps (continued)
Table 7. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register
Type
Default
(hex)
Register Name
Bit
Function
Description
3
0x03 General
Configuration 1
7
6
0xF0
Reserved
RW
Back
channel
CRC
Back Channel CRC Generator Enable
0: Disable
1: Enable (default)
Generator
Enable
5
4
RW
RW
Failsafe
Outputs Failsafe Mode. Determines the pull direction
for undriven LVCMOS inputs
0: Pullup
1: Pulldown (default)
Filter
Enable
HS, VS, DE two clock filter. When enabled, pulses
less than two full PCLK cycles on the DE, HS, and VS
inputs will be rejected
0: Filtering disable
1: Filtering enable (default)
3
2
RW
I2C Pass-
Through
I2C Pass-Through Mode
Read/Write transactions matching any entry in the
DeviceAlias registers will be passed through to the
remote serializer I2C interface.
0: Pass-Through Disabled (default)
1: Pass-Through Enabled
RW
RW
Auto ACK
Automatically Acknowledge I2C transactions
independent of the forward channel Lock state.
0: Disable (default)
1: Enable
1:0
7:1
Reserved
4
0x04 BCC Watchdog
Control
0xFE
BCC
Watchdog
Timer
BCC Watchdog Timer The watchdog timer allows
termination of a control channel transaction if it fails to
complete within a programmed amount of time. This
field sets the Bidirectional Control Channel Watchdog
Timeout value in units of 2 milliseconds. This field
should not be set to 0.
0
RW
RW
RW
RW
BCC
Watchdog
Disable
Disable Bidirectional Control Channel Watchdog
Timer
0: Enable (default)
1: Disable
5
0x05 I2C Control 1
7
0x1E
I2C Pass-
All
I2C Pass-Through All Transactions. Pass all local I2C
transactions to the remote serializer.
0: Disable (default)
1: Enable
6:4
3:0
I2C SDA
Hold
Internal I2C SDA Hold Time
This field configures the amount of internal hold time
is provided for the SDA input relative to the SCL input.
Units are 50ns.
I2C Filter
Depth
I2C Glitch Filter Depth
This field configures the maximum width of glitch
pulses on the SCL and SDA inputs that will be
rejected. Units are 5 nanoseconds.
Copyright © 2013–2015, Texas Instruments Incorporated
37
DS90UH928Q-Q1
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
www.ti.com.cn
Register Maps (continued)
Table 7. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register
Type
Default
(hex)
Register Name
Bit
Function
Description
6
0x06 I2C Control 2
7
RW
0x00
Forward
Channel
Sequence
Error
Control Channel Sequence Error Detected
Indicates a sequence error has been detected in
forward control channel. It this bit is set, an error may
have occurred in the control channel operation.
6
RW
Clear
Sequence
Error
Clears the Sequence Error Detect bit This bit is not
self-clearing.
5
Reserved
4:3
RW
SDA Output SDA Output Delay
Delay This field configures output delay on the SDA output.
Setting this value will increase output delay in units of
50ns. Nominal output delay values for SCL to SDA
are:
00: 250ns (default)
01: 300ns
10: 350ns
11: 400ns
2
RW
Local Write Disable Remote Writes to Local Registers through
Disable
Serializer (Does not affect remote access to I2C
slaves)
0: Remote write to local device registers (default)
1: Stop remote write to local device registers
1
0
RW
RW
I2C Bus
Timer
Speedup
Speed up I2C Bus Watchdog Timer
0: Timer expires after approximately 1s (default)
1: Timer expires after approximately 50µs
I2C Bus
Timer
Disable
Disable I2C Bus Watchdog Timer.
When the I2C Watchdog Timer may be used to detect
when the I2C bus is free or hung up following an
invalid termination of a transaction. If SDA is high and
no signaling occurs for approximately 1 second, the
I2C bus is assumed to be free. If SDA is low and no
signaling occurs, the device will attempt to clear the
bus by driving 9 clocks on SCL
7
8
0x07 Remote ID
7:1
0
R
0x00
0x00
Remote ID Remote Serializer ID
RW if bit 0 is set
RW
Freeze
Freeze Serializer Device ID
Device ID
0: Auto-load Serializer Device ID (default)
1: Prevent auto-loading of Serializer Device ID from
the remote device. The ID will be frozen at the value
written.
0x08 Slave ID[0]
7:1
RW
RW
Slave
7-bit Remote Slave Device ID 0
Device ID0 Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[0], the transaction will be re-mapped to this
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
0
Reserved
9
0x09 Slave ID[1]
7:1
0x00
Slave
7-bit Remote Slave Device ID1
Device ID1 Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[1], the transaction will be re-mapped to this
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
0
Reserved
38
Copyright © 2013–2015, Texas Instruments Incorporated
DS90UH928Q-Q1
www.ti.com.cn
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
Register Maps (continued)
Table 7. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register
Type
Default
(hex)
Register Name
Bit
Function
Description
10
11
12
13
14
15
16
0x0A Slave ID[2]
0x0B Slave ID[3]
0x0C Slave ID[4]
0x0D Slave ID[5]
0x0E Slave ID[6]
0x0F Slave ID[7]
0x10 Slave Alias[0]
7:1
RW
RW
RW
RW
RW
RW
RW
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Slave
7-bit Remote Slave Device ID2
Device ID2 Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[2], the transaction will be re-mapped to this
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
0
Reserved
7:1
Slave
7-bit Remote Slave Device ID3
Device ID3 Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[3], the transaction will be re-mapped to this
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
0
Reserved
7:1
Slave
7-bit Remote Slave Device ID4
Device ID4 Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[4], the transaction will be re-mapped to this
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
0
Reserved
7:1
Slave
7-bit Remote Slave Device ID5
Device ID5 Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[5], the transaction will be re-mapped to this
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
0
Reserved
7:1
Slave
7-bit Remote Slave Device ID6
Device ID6 Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[6], the transaction will be re-mapped to this
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
0
Reserved
7:1
Slave
7-bit Remote Slave Device ID 7
Device ID7 Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[7], the transaction will be re-mapped to this
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
0
Reserved
7:1
Slave
7-bit Remote Slave Alias 0
Device
Alias 0
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[0], the transaction will be re-mapped to the ID
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
0
Reserved
Copyright © 2013–2015, Texas Instruments Incorporated
39
DS90UH928Q-Q1
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
www.ti.com.cn
Register Maps (continued)
Table 7. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register
Type
Default
(hex)
Register Name
Bit
Function
Description
17
18
19
20
21
22
23
0x11 Slave Alias[1]
0x12 Slave Alias[2]
0x13 Slave Alias[3]
0x14 Slave Alias[4]
0x15 Slave Alias[5]
0x16 Slave Alias[6]
0x17 Slave Alias[7]
7:1
RW
RW
RW
RW
RW
RW
RW
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Slave
Device
Alias 1
7-bit Remote Slave Alias 1
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[1], the transaction will be re-mapped to the ID
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
0
Reserved
7:1
Slave
Device
Alias 2
7-bit Remote Slave Alias 2
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[2], the transaction will be re-mapped to the ID
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
0
Reserved
7:1
Slave
Device
Alias 3
7-bit Remote Slave Alias 3
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[3], the transaction will be re-mapped to the ID
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
0
Reserved
7:1
Slave
Device
Alias 4
7-bit Remote Slave Alias 4
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[4], the transaction will be re-mapped to the ID
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
0
Reserved
7:1
Slave
Device
Alias 5
7-bit Remote Slave Alias 5
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[5], the transaction will be re-mapped to the ID
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
0
Reserved
7:1
Slave
Device
Alias 6
7-bit Remote Slave Alias 6
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[6], the transaction will be re-mapped to the ID
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
0
Reserved
7:1
Slave
7-bit Remote Slave Alias 7
Device
Alias 7
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[7], the transaction will be re-mapped to the ID
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
0
Reserved
40
Copyright © 2013–2015, Texas Instruments Incorporated
DS90UH928Q-Q1
www.ti.com.cn
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
Register Maps (continued)
Table 7. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register
Type
Default
(hex)
Register Name
Bit
Function
Description
24
25
27
0x18 Mailbox[0]
7:0
RW
RW
RW
0x00
0x00
0x00
Mailbox
Register 0
Mailbox Register 0
This register may be used to temporarily store
temporary data, such as status or multi-master
arbitration
0x19 Mailbox[1]
7:0
7:0
Mailbox
Register 1
Mailbox Register 1
This register may be used to temporarily store
temporary data, such as status or multi-master
arbitration
0x1B Frequency
Counter
Frequency
Count
Frequency Counter control
A write to this register will enable a frequency counter
to count the number of pixel clock during a specified
time interval. The time interval is equal to the value
written multiplied by the oscillator clock period
(nominally 50ns). A read of the register returns the
number of pixel clock edges seen during the enabled
interval. The frequency counter will saturate at 0xff if it
reaches the maximum value. The frequency counter
will provide a rough estimate of the pixel clock period.
If the pixel clock frequency is known, the frequency
counter may be used to determine the actual oscillator
clock frequency.
28
0x1C General Status
7:4
3
0x00
Reserved
R
R
I2S Locked I2S Lock Status
0: I2S PLL controller not locked (default)
1: I2S PLL controller locked to input I2S clock
2
CRC Error
CRC Error Detected
0: No CRC errors detected
1: CRC errors detected
1
0
Reserved
R
LOCK
Deserializer CDR and PLL Locked to recovered clock
frequency
0: Deserializer not Locked (default)
1: Deserializer Locked to recovered clock
29
0x1D GPIO0
Configuration
7:4
3
R
0x20
Revision ID Device Revision ID:
0010: Production Device
RW
GPIO0
Output
Value
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, the
local GPIO direction is Output, and remote GPIO
control is disabled.
0: Output LOW (default)
1: Output HIGH
2
RW
GPIO0
Remote
Enable
Remote GPIO Control
0: Disable GPIO control from remote device (default)
1: Enable GPIO control from remote device. The
GPIO pin will be an output, and the value is received
from the remote device.
1
0
RW
RW
GPIO0
Direction
Local GPIO Direction
0: Output (default)
1: Input
GPIO0
Enable
GPIO Function Enable
0: Enable normal operation (default)
1: Enable GPIO operation
Copyright © 2013–2015, Texas Instruments Incorporated
41
DS90UH928Q-Q1
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
www.ti.com.cn
Register Maps (continued)
Table 7. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register
Type
Default
(hex)
Register Name
Bit
Function
Description
30
0x1E GPIO1 and
GPIO2
7
RW
0x00
GPIO2
Output
Value
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, the
local GPIO direction is Output, and remote GPIO
control is disabled.
Configuration
0: Output LOW (default)
1: Output HIGH
6
RW
GPIO2
Remote
Enable
Remote GPIO Control
0: Disable GPIO control from remote device (default)
1: Enable GPIO control from remote device. The
GPIO pin will be an output, and the value is received
from the remote device.
5
4
3
RW
RW
RW
GPIO2
Direction
Local GPIO Direction
0: Output (default)
1: Input
GPIO2
Enable
GPIO Function Enable
0: Enable normal operation (default)
1: Enable GPIO operation
GPIO1
Output
Value
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, the
local GPIO direction is Output, and remote GPIO
control is disabled.
0: Output LOW (default)
1: Output HIGH
2
RW
GPIO1
Remote
Enable
Remote GPIO Control
0: Disable GPIO control from remote device (default)
1: Enable GPIO control from remote device. The
GPIO pin will be an output, and the value is received
from the remote device.
1
0
RW
RW
GPIO1
Direction
Local GPIO Direction
1: Input
0: Output
GPIO1
Enable
GPIO function enable
1: Enable GPIO operation
0: Enable normal operation
31
0x1F GPIO3
Configuration
7:4
3
0x00
Reserved
RW
RW
GPIO3
Output
Value
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, the
local GPIO direction is Output, and remote GPIO
control is disabled.
0: Output LOW (default)
1: Output HIGH
2
GPIO3
Remote
Enable
Remote GPIO Control
0: Disable GPIO control from remote device (default)
1: Enable GPIO control from remote device. The
GPIO pin will be an output, and the value is received
from the remote device.
1
0
RW
RW
GPIO3
Direction
Local GPIO Direction
0: Output (default)
1: Input
GPIO3
Enable
GPIO Function Enable
0: Enable normal operation (default)
1: Enable GPIO operation
42
Copyright © 2013–2015, Texas Instruments Incorporated
DS90UH928Q-Q1
www.ti.com.cn
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
Register Maps (continued)
Table 7. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register
Type
Default
(hex)
Register Name
Bit
Function
Description
32
0x20 GPIO_REG5
and
7
RW
0x00
GPIO_REG Local GPIO Output Value This value is output on the
6 Output
Value
GPIO pin when the GPIO function is enabled, and the
local GPIO direction is Output.
0: Output LOW (default)
GPIO_REG6
Configuration
1: Output HIGH
6
5
Reserved
RW
RW
RW
GPIO_REG Local GPIO Direction
6 Direction 0: Output (default)
1: Input
4
3
GPIO_REG GPIO Function Enable
6 Enable
0: Enable normal operation (default)
1: Enable GPIO operation
GPIO_REG Local GPIO Output Value This value is output on the
5 Output
Value
GPIO pin when the GPIO function is enabled, and the
local GPIO direction is Output.
0: Output LOW (default)
1: Output HIGH
2
1
Reserved
RW
RW
RW
GPIO_REG GPIO Function Enable
5 Direction 0: Enable normal operation (default)
1: Enable GPIO operation
0
7
GPIO_REG GPIO Function Enable
5 Enable
0: Enable normal operation (default)
1: Enable GPIO operation
33
0x21 GPIO_REG7
and
0x00
GPIO_REG Local GPIO Output Value This value is output on the
8 Output
Value
GPIO pin when the GPIO function is enabled, and the
local GPIO direction is Output.
0: Output LOW (default)
GPIO_REG8
Configuration
1: Output HIGH
6
5
Reserved
RW
RW
RW
GPIO_REG Local GPIO Direction
8 Direction 0: Output (default)
1: Input
4
3
GPIO_REG GPIO Function Enable
8 Enable
0: Enable normal operation (default)
1: Enable GPIO operation
GPIO_REG Local GPIO Output Value This value is output on the
7 Output
Value
GPIO pin when the GPIO function is enabled, and the
local GPIO direction is Output.
0: Output LOW (default)
1: Output HIGH
2
1
Reserved
RW
RW
GPIO_REG Local GPIO Direction
7 Direction 0: Output (default)
1: Input
0
GPO_REG GPIO Function Enable
7 Enable
0: Enable normal operation (default)
1: Enable GPIO operation
Copyright © 2013–2015, Texas Instruments Incorporated
43
DS90UH928Q-Q1
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
www.ti.com.cn
Register Maps (continued)
Table 7. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register
Type
Default
(hex)
Register Name
Bit
Function
Description
34
0x22 Data Path
Control
7
RW
0x00
Override FC Override Configuration Loaded by Forward Channel
Configuratio 0: Allow forward channel loading of this register
n
(default)
1: Disable loading of this register from the forward
channel, keeping locally written values intact
Bits [6:0] are RW if this bit is set
6
R
Pass RGB
Pass RGB on DE
Setting this bit causes RGB data to be sent
independent of DE in DS90UH928, which can be
used to allow DS90UH928 to interoperate with
DS90UB925 and DS90UB926. However, setting this
bit prevents HDCP operation and blocks packetized
audio. This bit does not need to be set in Backward
Compatibility mode.
0: Normal operation (default)
1: Pass RGB independent of DE
5
4
3
R
R
R
DE Polarity This bit indicates the polarity of the DE (Data Enable)
signal.
0: DE is positive (active high, idle low) (default)
1: DE is inverted (active low, idle high)
I2S
Repeater
Regen
Regenerate I2S Data From Repeater I2S Pins
0: Output packetized audio on RGB video output pins.
(default)
1: Repeater regenerates I2S from I2S pins
I2S
I2S Channel B Override
Channel B
Enable
Override
0: Set I2S Channel B Disabled (default)
1: Set I2S Channel B Enable from register
2
1
R
R
18-bit Video Video Color Depth Mode
Select
0: Select 24-bit video mode (default)
1: Select 18-bit video mode
I2S
Select I2S Transport Mode
Transport
Select
0: Enable I2S Data Island Transport (default)
1: Enable I2S Data Forward Channel Frame
Transport
0
7
R
I2S
Channel B
Enable
I2S Channel B Enable
0: I2S Channel B disabled (default)
1: Enable I2S Channel B
35
0x23 Rx Mode Status
RW
0x10
RGB
Rx RGB Checksum Enable
Checksum
Enable
Setting this bit enables the Receiver to validate a one-
byte checksum following each video line. Checksum
failures are reported in the HDCP_STS register.
0: Disabled (default)
1: Enabled
6:4
3
Reserved
R
R
R
R
LFMODE
Status
Low Frequency Mode (LFMODE) pin status
0: 15 ≤ TxCLKOUT ≤ 85MHz (default)
1: 5 ≤ TxCLKOUT < 15MHz
2
1
0
REPEAT
Status
Repeater Mode (REPEAT) pin Status
0: Non-repeater (default)
1: Repeater
BKWD
Status
Backward Compatible Mode (BKWD) Status
0: Compatible to DS90UB925/7Q (default)
1: Backward compatible to DS90UR905/7Q
I2S
Channel B
Status
I2S Channel B Mode (I2S_DB) Status
0: I2S_DB inactive (default)
1: I2S_DB active
44
Copyright © 2013–2015, Texas Instruments Incorporated
DS90UH928Q-Q1
www.ti.com.cn
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
Register Maps (continued)
Table 7. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register
Type
Default
(hex)
Register Name
Bit
Function
Description
36
0x24 BIST Control
7:4
3
0x08
Reserved
RW
RW
BIST Pin
Config
BIST Pin Configuration
0: BIST enabled from register
1: BIST enabled from pin (default)
2:1
OSC Clock Internal OSC clock select for Functional Mode or
Source
BIST. Functional Mode when PCLK is not present and
0x03[1]=1.
00: 33 MHz Oscillator (default)
01: 33 MHz Oscillator
Note: In LFMODE=1, the internal oscillator is
12.5MHz
0
RW
R
BIST
Enable
BIST Control
0: Disabled (default)
1: Enabled
37
0x25 BIST Error
7:0
0x00
BIST Error Errors Detected During BIST
Count
Records the number (up to 255) of forward-channel
errors detected during BIST. The value stored in this
register is only valid after BIST terminates (BISTEN =
0). Resets on PDB = 0 or start of another BIST
(BISTEN = 1).
38
39
0x26 SCL High Time
0x27 SCL Low Time
7:0
7:0
RW
RW
0x83
0x84
SCL High
Time
I2C Master SCL High Time
This field configures the high pulse width of the SCL
output when the deserializer is the Master on the local
I2C bus. Units are 50 ns for the nominal oscillator
clock frequency.
SCL Low
Time
I2C SCL Low Time
This field configures the low pulse width of the SCL
output when the deserializer is the Master on the local
I2C bus. This value is also used as the SDA setup
time by the I2C Slave for providing data prior to
releasing SCL during accesses over the Bidirectional
Control Channel. Units are 50 ns for the nominal
oscillator clock frequency.
40
0x28 Data Path
Control 2
7
RW
0x00
Block I2S
Override Forward Channel Configuration
Auto Config 0: Enable forward-channel loading of this register
1: Disable loading of this register from the forward
channel, keeping local values intact
6:4
3
Reserved
RW
RW
Aux I2S
Enable
Auxiliary I2S Channel Enable
0: Normal GPIO[1:0] operation
1: Enable Aux I2S channel on GPIO1 (AUX word
select) and GPIO0 (AUX data)
2
I2S Disable Disable All I2S Outputs
0: I2S Outputs Enabled (default)
1: I2S Outputs Disabled
1
0
Reserved
RW
I2S
Surround
Enable 5.1- or 7.1-channel I2S audio transport
0: 2-channel or 4-channel I2S audio is enabled as
configured in register or MODE_SEL (default)
1: 5.1- or 7.1-channel audio is enabled
Note that I2S Data Island Transport is the only option
for surround audio. Also note that in a repeater, this
bit may be overridden by the in-band I2S mode
detection.
Copyright © 2013–2015, Texas Instruments Incorporated
45
DS90UH928Q-Q1
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
www.ti.com.cn
Register Maps (continued)
Table 7. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register
Type
Default
(hex)
Register Name
Bit
Function
Description
41
0x29 FRC Control
7
RW
RW
RW
RW
RW
RW
RW
RW
RW
0x00
Timing
Mode
Select
Select Display Timing Mode
0: DE only Mode (default)
1: Sync Mode (VS,HS)
6
5
HS Polarity Horizontal Sync Polarity Select
0: Active High (default)
1: Active Low
VS Polarity Vertical Sync Polarity Select
0: Active High (default)
1: Active Low
4
DE Polarity Data Enable Sync Polarity Select
0: Active High (default)
1: Active Low
3
FRC2
Enable
FRC2 Enable
0: FRC2 disable (default)
1: FRC2 enable
2
FRC1
Enable
FRC1 Enable
0: FRC1 disable (default)
1: FRC1 enable
1
Hi-FRC2
Enable
Hi-FRC2 Enable
0: Hi-FRC2 enable (default)
1: Hi-FRC2 disable
0
Hi-FRC1
Enable
Hi-FRC1 Enable
0: Hi-FRC1 enable (default)
1: Hi-FRC1 disable
42
0x2A White Balance
Control
7:6
0x00
Page
Setting
Control/LUT Setting Page Select
00: Configuration Registers (default)
01: Red LUT
10: Green LUT
11: Blue LUT
5
4
RW
RW
White
Balance
Enable
White Balance Enable
0: White Balance Disabled (default)
1: White Balance Enabled
LUT Reload Enable LUT Reload
Enable
0: Reload Disable (default)
1: Reload Enable
3:0
7
Reserved
43
0x2B I2S Control
RW
RW
0x00
I2S PLL
Override
Override I2S PLL
0: PLL override disabled (default)
1: PLL override enabled
6
I2S PLL
Enable
Enable I2S PLL
0: I2S PLL is on for I2S data jitter cleaning (default)
1: I2S PLL is off. No jitter cleaning
5:1
0
Reserved
RW
I2S Clock
Edge
I2S Clock Edge Select
0: I2S Data is strobed on the Falling Clock Edge
(default)
1: I2S Data is strobed on the Rising Clock Edge
46
Copyright © 2013–2015, Texas Instruments Incorporated
DS90UH928Q-Q1
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ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
Register Maps (continued)
Table 7. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register
Type
Default
(hex)
Register Name
Bit
Function
Description
53
0x35 AEQ Control
7
6
0x00
Reserved
RW
AEQ
Restart
Restart AEQ adaptation from initial (Floor) values
0: Normal operation (default)
1: Restart AEQ adaptation
Note: This bit is not self-clearing. It must be set, then
reset.
5
4
RW
RW
LCBL
Override
Override LCBL Mode Set by MODE_SEL
0: LCBL controlled by MODE_SEL pin
1: LCBL controlled by register
LCBL
Set LCBL Mode
0: LCBL Mode disabled
1: LCBL Mode enabled. AEQ Floor value is controlled
from Adaptive EQ MIN/MAX register
3:0
7:2
1
Reserved
Reserved
57
0x39 PG Internal
Clock Enable
0x00
RW
PG INT
CLK
Enable Pattern Generator Internal Clock
This bit must be set to use the Pattern Generator
Internal Clock Generation
0: Pattern Generator with external PCLK
1: Pattern Generator with internal PCLK
See TI Application Note ( ) for details
0
7
Reserved
58
0x3A I2S DIVSEL
RW
RW
0x00
MCLK Div
Override
Override MCLK Divider Setting
0: No override for MCLK divider (default)
1: Override divider select for MCLK
6:4
3:0
7:6
5:0
MCLK Div
See Table 3
Reserved
Reserved
59
68
0x3B Adaptive EQ
Status
EQ Status
Equalizer Status
Current equalizer level set by AEQ or Override
Register
0x44 Adaptive
Equalizer
7:5
RW
0x60
EQ Stage 1 EQ Stage 1 select value. Used if adaptive EQ is
Select
Value
bypassed. Used if adaptive EQ is bypassed.
Bypass
4
Reserved
3:1
RW
RW
EQ Stage 2 EQ Stage 2 select value. Used if adaptive EQ is
Select
Value
bypassed Used if adaptive EQ is bypassed.
0
Adaptive
Bypass Adaptive EQ
EQ Bypass Overrides Adaptive EQ search and sets the EQ to the
static value configured in this register
0: Enable adaptive EQ (default)
1: Disable adaptive EQ (to write EQ select values)
69
73
0x45 Adaptive EQ
MIN/MAX
7:4
3:0
RW
RW
0x88
0x00
Reserved
Adaptive
EQ Floor
Adaptive Equalizer Floor Value
Sets the AEQ floor value when Long Cable Mode
(LCBL) is enabled by register or MODE_SEL
0x49 Map Select
7
6
R
MAPSEL
Pin Status
Returns Status of MAPSEL pin
RW
MAPSEL
Override
Map Select (MAPSEL) Setting Override
0: MAPSEL set from pin
1: MAPSEL set from register
5
RW
MAPSEL
Map Select (MAPSEL) Setting
0: LSBs on TxOUT3±
1: MSBs on TxOUT3±
4:0
Reserved
Copyright © 2013–2015, Texas Instruments Incorporated
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DS90UH928Q-Q1
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
www.ti.com.cn
Register Maps (continued)
Table 7. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register
Type
Default
(hex)
Register Name
Bit
Function
Description
86
0x56 Loop-Through
Driver
7:4
3
0x08
Reserved
RW
RW
Loop-
Through
Driver
Enable CML Loop-Through Driver
(CMLOUTP/CMLOUTN)
0: Enable
Enable
1: Disable (default)
2:0
7:4
Reserved
100
0x64 Pattern
Generator
Control
0x10
Pattern
Generator
Select
Fixed Pattern Select
Selects the pattern to output when in Fixed Pattern
Mode. Scaled patterns are evenly distributed across
the horizontal or vertical active regions. This field is
ignored when Auto-Scrolling Mode is enabled.
xxxx: normal/inverted
0000: Checkerboard
0001: White/Black (default)
0010: Black/White
0011: Red/Cyan
0100: Green/Magenta
0101: Blue/Yellow
0110: Horizontal Black-White/White-Black
0111: Horizontal Black-Red/White-Cyan
1000: Horizontal Black-Green/White-Magenta
1001: Horizontal Black-Blue/White-Yellow
1010: Vertical Black-White/White— Black
1011: Vertically Scaled Black to Red/White to Cyan
1100: Vertical Black-Green/White-Magenta
1101: Vertical Black-Blue/White-Yellow
1110: Custom color (or its inversion) configured in
PGRS, PGGS, PGBS registers
1111: VCOM
See TI App Note AN-2198 ().
3
2
Reserved
RW
Color Bars Enable Color Bars Pattern
Pattern
0: Color Bars disabled (default)
1: Color Bars enabled
Overrides the selection from bits [7:4]
1
0
RW
RW
VCOM
Pattern
Reverse
Reverse order of color bands in VCOM pattern
0: Color sequence from top left is (YCBR) (default)
1: Color sequence from top left is (RBCY)
Pattern
Pattern Generator Enable
Generator
Enable
0: Disable Pattern Generator (default)
1: Enable Pattern Generator
See TI App Note AN-2198 ().
48
Copyright © 2013–2015, Texas Instruments Incorporated
DS90UH928Q-Q1
www.ti.com.cn
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
Register Maps (continued)
Table 7. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register
Type
Default
(hex)
Register Name
Bit
Function
Description
101
0x65 Pattern
Generator
Configuration
7
6
0x00
Reserved
Checkerboa Scale Checkerboard Patterns:
RW
rd Scale
0: Normal operation (each square is 1x1 pixel)
(default)
1: Scale checkered patterns (VCOM and
checkerboard) by 8 (each square is 8x8 pixels)
Setting this bit gives better visibility of the checkered
patterns.
5
4
RW
RW
Custom
Use Custom Checkerboard Color
Checkerboa 0: Use white and black in the Checkerboard pattern
rd
(default)
1: Use the Custom Color and black in the
Checkerboard pattern
PG 18–bit
Mode
18-bit Mode Select:
0: Enable 24-bit pattern generation. Scaled patterns
use 256 levels of brightness. (default)
1: Enable 18-bit color pattern generation. Scaled
patterns will have 64 levels of brightness and the R,
G, and B outputs use the six most significant color
bits.
3
2
RW
RW
External
Clock
Select External Clock Source:
0: Selects the internal divided clock when using
internal timing (default)
1: Selects the external pixel clock when using internal
timing. This bit has no effect in external timing mode
(PATGEN_TSEL = 0).
Timing
Select
Timing Select Control:
0: the Pattern Generator uses external video timing
from the pixel clock, Data Enable, Horizontal Sync,
and Vertical Sync signals. (default)
1: The Pattern Generator creates its own video timing
as configured in the Pattern Generator Total Frame
Size, Active Frame Size. Horizontal Sync Width,
Vertical Sync Width, Horizontal Back Porch, Vertical
Back Porch, and Sync Configuration registers.
1
0
RW
RW
Color Invert Enable Inverted Color Patterns:
0: Do not invert the color output. (default)
1: Invert the color output.
Auto Scroll Auto Scroll Enable:
0: The Pattern Generator retains the current pattern.
(default)
1: The Pattern Generator will automatically move to
the next enabled pattern after the number of frames
specified in the Pattern Generator Frame Time
(PGFT) register.
See TI App Note AN-2198 ().
102
103
0x66 PGIA
7:0
7:0
RW
RW
0x00
0x00
PG Indirect This 8-bit field sets the indirect address for accesses
Address
to indirectly-mapped registers. It should be written
prior to reading or writing the Pattern Generator
Indirect Data register.
See TI App Note AN-2198 ().
0x67 PGID
PG Indirect When writing to indirect registers, this register
Data
contains the data to be written. When reading from
indirect registers, this register contains the read back
value.
See TI App Note AN-2198 ().
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www.ti.com.cn
Register Maps (continued)
Table 7. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register
Type
Default
(hex)
Register Name
Bit
Function
Description
110
0x6E GPI Pin Status
1
7
R
R
R
0x00
GPI7 Pin
Status
GPI7 Pin Status. Readable when REG_GPIO7 is set
as an input.
6
5
GPI6 Pin
Status
GPI6 Pin Status. Readable when REG_GPIO6 is set
as an input.
GPI5 Pin
Status
GPI5 Pin Status. Readable when REG_GPIO5 is set
as an input.
4
3
Reserved
R
R
R
R
GPI3 Pin
Status
GPI3 Pin Status. Readable when GPIO3 is set as an
input.
2
1
0
GPI2 Pin
Status
GPI2 Pin Status. Readable when GPIO2 is set as an
input.
GPI1 Pin
Status
GPI1 Pin Status. Readable when GPIO1 is set as an
input.
GPI0 Pin
Status
GPI0 Pin Status. Readable when GPIO0 is set as an
input.
111
0x6D GPI Pin Status
2
7:1
0
0x00
Reserved
R
GPI8 Pin
Status
GPI8 Pin Status. Readable when REG_GPIO8 is set
as an input.
128
129
130
131
132
144
145
146
147
148
152
153
154
155
156
157
158
159
0x80 RX_BKSV0
0x81 RX_BKSV1
0x82 RX_BKSV2
0x83 RX_BKSV3
0x84 RX_BKSV4
0x90 TX_KSV0
0x91 TX_KSV1
0x92 TX_KSV2
0x93 TX_KSV3
0x94 TX_KSV4
0x98 TX_AN0
0x99 TX_AN1
0x9A TX_AN2
0x9B TX_AN3
0x9C TX_AN4
0x9D TX_AN5
0x9E TX_AN6
0x9F TX_AN7
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
RX BKSV0 BKSV0: Value of byte 0 of the Receiver KSV
RX BKSV1 BKSV1: Value of byte 1 of the Receiver KSV
RX BKSV2 BKSV2: Value of byte 2 of the Receiver KSV
RX BKSV3 BKSV3: Value of byte 3of the Receiver KSV.
RX BKSV4 BKSV4: Value of byte 4of the Receiver KSV.
TX KSV0
TX KSV1
TX KSV2
TX KSV3
TX KSV4
TX AN0
TX AN1
TX AN2
TX AN3
TX AN4
TX AN5
TX AN6
TX AN7
KSV0: Value of byte 0 of the Transmitter KSV.
KSV1: Value of byte 1 of the Transmitter KSV.
KSV2: Value of byte 2 of the Transmitter KSV.
KSV3: Value of byte 3 of the Transmitter KSV.
KSV4: Value of byte 4 of the Transmitter KSV.
TX_AN0: Value of byte 0 of the Transmitter AN Value
TX_AN1: Value of byte 1 of the Transmitter AN Value
TX_AN2: Value of byte 2 of the Transmitter AN Value
TX_AN3: Value of byte 3 of the Transmitter AN Value
TX_AN4: Value of byte 4 of the Transmitter AN Value
TX_AN5: Value of byte 5 of the Transmitter AN Value
TX_AN6: Value of byte 6 of the Transmitter AN Value
TX_AN7: Value of byte 7 of the Transmitter AN Value
50
Copyright © 2013–2015, Texas Instruments Incorporated
DS90UH928Q-Q1
www.ti.com.cn
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
Register Maps (continued)
Table 7. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register
Type
Default
(hex)
Register Name
Bit
Function
Description
192
0xC0 HDCP Debug 1
7
6
0x00
Reserved
R
HDCP
HDCP I2C Timeout Disable
Timeout
Disable
Setting this bit to a 1 will disable the bus timeout
function in the HDCP I2C master. When enabled, the
bus timeout function allows the I2C master to assume
the bus is free if no signaling occurs for more than 1
second.
Set via the HDCP_DBG register in the HDCP
Transmitter.
5:4
3
Reserved
R
R
RGB
Checksum
Enable
Enable RBG video line checksum
Enables sending of ones-complement checksum for
each 8-bit RBG data channel following end of each
video data line.
Set via the HDCP_DBG register in the HDCP
Transmitter.
2
Fast LV
Fast Link Verification
HDCP periodically verifies that the HDCP Receiver is
correctly synchronized. Setting this bit will increase
the rate at which synchronization is verified. When set
to a 1, Pj is computed every 2 frames and Ri is
computed every 16 frames. When set to a 0, Pj is
computed every 16 frames and Ri is computed every
128 frames.
Set via the HDCP_DBG register in the HDCP
Transmitter.
1
0
R
R
Timer
Speedup
Timer Speedup
Speed up HDCP authentication timers.
Set via the HDCP_DBG register in the HDCP
Transmitter.
HDCP I2C
Fast
HDCP I2C Fast mode Enable
Setting this bit to a 1 will enable the HDCP I2C Master
in the HDCP Receiver to operation with Fast mode
timing. If set to a 0, the I2C Master will operation with
Standard mode timing.
Set via the HDCP_DBG register in the HDCP
Transmitter.
193
0xC1 HDCP Debug 2
7:2
1
0x00
Reserved
RW
No Decrypt Disable HDCP Decryption
When disabled, the HDCP Receiver will output
encrypted RGB data. This provides a simple method
for verifying that the link is encrypted.
0: HDCP Decryption enabled
1: HDCP Decryption disabled
0
7:2
1
Reserved
Reserved
196
0xC4 HDCP Status
0x00
R
R
RGB
Checksum
ERR
RGB Checksum Error Detected
If RGB Checksum in enabled through the HDCP
Transmitter HDCP_DBG register, this bit will indicate
if a checksum error is detected. This register may be
cleared by writing any value to this register
0
AUTHED
HDCP Authenticated
Indicates the HDCP authentication has completed
successfully. The controller may now send video data
requiring content protection. This bit will be cleared if
authentication is lost or if the controller restarts
authentication.
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www.ti.com.cn
Register Maps (continued)
Table 7. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register
Type
Default
(hex)
Register Name
Bit
Function
Description
224
225
226
227
0xE0 RPTR TX0
0xE1 RPTR TX1
0xE2 RPTR TX2
0xE3 RPTR TX3
7:1
R
0x00
0x00
0x00
0x00
PORT0_AD Transmit Port 0 I2C Address
DR
Indicates the I2C address for the Repeater Transmit
Port.
0
R
PORT0_VA Transmit Port 0 Valid
LID Indicates that the HDCP Repeater has a transmit port
at the I2C Address identified by upper 7 bits of this
register
0: Address Invalid (default)
1: Address Valid
7:1
0
R
R
PORT1_AD Transmit Port 1 I2C Address
DR Indicates the I2C address for the Repeater Transmit
Port.
PORT1_VA Transmit Port 1 Valid
LID Indicates that the HDCP Repeater has a transmit port
at the I2C Address identified by upper 7 bits of this
register
0: Address Invalid (default)
1: Address Valid
7:1
0
R
R
PORT2_AD Transmit Port 2 I2C Address
DR Indicates the I2C address for the Repeater Transmit
Port.
PORT2_VA Transmit Port 2 Valid
LID Indicates that the HDCP Repeater has a transmit port
at the I2C Address identified by upper 7 bits of this
register
0: Address Invalid (default)
1: Address Valid
7:1
0
R
R
PORT3_AD Transmit Port 3 I2C Address
DR Indicates the I2C address for the Repeater Transmit
Port.
PORT3_VA Transmit Port 3 Valid
LID
Indicates that the HDCP Repeater has a transmit port
at the I2C Address identified by upper 7 bits of this
register
0: Address Invalid (default)
1: Address Valid
240
241
242
243
244
245
0xF0 HDCP RX ID
7:0
7:0
7:0
7:0
7:0
7:0
R
R
R
R
R
R
0x5F
0x55
0x48
0x39
0x32
0x38
ID0
ID1
ID2
ID3
ID4
ID5
First byte ID code, ‘_’
0xF1
0xF2
0xF3
0xF4
0xF5
Second byte of ID code, ‘U’
Third byte of ID code. ‘H'
Forth byte of ID code: ‘9’
Fifth byte of ID code: “2”
Sixth byte of ID code: “8”
52
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DS90UH928Q-Q1
www.ti.com.cn
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DS90UH928Q-Q1 deserializer, in conjunction with a DS90UH925Q-Q1 or DS90UH927Q-Q1 serializer,
provides a solution for secure distribution of content-protected digital video and audio within automotive
infotainment systems. It converts a high-speed serialized interface with an embedded clock, delivered over a
single signal pair (FPD-Link III), to four LVDS data/control streams, one LVDS clock pair (FPD-Link), and I2S
audio data. The digital video and audio data is protected using the industry standard HDCP copy protection
scheme.The serial bus scheme, FPD-Link III, supports high speed forward channel data transmission and low
speed full duplex back channel communication over a single differential link. Consolidation of audio, video data
and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew
issues and simplifying system design.
9.2 Typical Application
Figure 39 shows a typical application of the DS90UH928Q-Q1 deserializer for an 85 MHz 24-bit Color Display
Application. Inputs utilize 0.1-µF coupling capacitors to the line and the deserializer provides internal termination.
The voltage rating of the coupling capacitors should be ≥50 V and should use a small body capacitor size, such
as 0402 or 0602, to help ensure good signal integrity. The FPD-Link LVDS differential outputs require 100-Ω
termination resistors at the receiving device or display.
Bypass capacitors must be placed near the power supply pins. At a minimum, three 4.7-μF capacitors, one
placed at each power supply pin, are required for local device bypassing. If additional bypass capacitors are
used, place the smaller value components closer to the pin. Ferrite beads are required on the two supplies
(VDD33 and VDDIO) for effective noise suppression. Pins VDD33_A and VDD33_B should be connected directly to
ensure ESD performance. The interface to the display is FPD-Link LVDS. The VDDIO pin may be connected to
3.3 V or 1.8 V. A delay capacitor (>10 µF) and pullup resistor (10 kΩ) should be placed on the PDB signal to
delay the enabling of the device until power is stable.
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www.ti.com.cn
Typical Application (continued)
3.3V
DS90UH928Q-Q1
3.3V / 1.8V
VDDIO
VDD33_A
C6
FB1
FB2
C4
CAPLV25
VDD33_B
CAPL12
C7
C11
C12
C5
C8
CAPLV12
CAPP12
C9
CAPR12
C10
CAPI2S
C13
PASS
LOCK
C1
Serial
FPD-Link III
Interface
TxCLKOUT-
TxCLKOUT+
RIN+
RIN-
RTERM
C2
CMF
TxOUT3-
TxOUT3+
TxOUT2-
TxOUT2+
RTERM
C3
FPD-Link
Interface
RTERM
CMLOUTP
CMLOUTN
TxOUT1-
TxOUT1+
RTERM
OEN
OSS_SEL
LVCMOS
TxOUT0-
TxOUT0+
BISTEN
Control
RTERM
MAPSEL
LFMODE
Interface
VDD33
VDD33
R1
VDD33 or VDDIO=3.3V±0.3V
R5
IDx
SCL
SDA
INTB_IN
PDB
R2
NOTE:
FB1-FB2 (Optional): Impedance = 1kQ,
Low DC resistance (<1Q)
C14
VDD33
C1-C3 = 0.1 µF (50 WV; C1, C2: 0402; C3: 0603)
C4-C13 = 4.7 µF
C14 = > 10 µF
R1 and R2 (see IDx Resistor Value Table)
R3 and R4 (see MODE_SEL Resistor Value Table)
R5 = 10kQ
R3
R4
GPIO[1:0]
MCLK
I2S_CLK
I2S_WC
I2S_Dx
MODE_SEL
I2S / GPIO
Interface
4
RESx
DAP (GND)
RPU = 4.7kQ
RTERM = 100Q
Figure 39. Typical Connection Diagram
54
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ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
Typical Application (continued)
FPD-Link
FPD-Link
VDDIO
VDD33
VDD33
VDDIO
(1.8V or 3.3V) (3.3V)
(3.3V) (1.8V or 3.3V)
RxIN3+/-
RxIN2+/-
TxOUT3+/-
TxOUT2+/-
FPD-Link III
1 Pair/AC Coupled
DOUT+
DOUT-
RIN+
RIN-
HOST
Graphics
Processor
RGB Display
720p
24-bit Color Depth
RxIN1+/-
RxIN0+/-
TxOUT1+/-
TxOUT0+/-
100Q STP Cable
RxCLKIN+/-
TxCLKOUT+/-
INTB_IN
DS90UH927Q-Q1
Serializer
DS90UH928Q-Q1
Deserializer
OEN
LOCK
PDB
INTB
I2S
OSS_SEL
PDB
PASS
I2S
6
6
MAPSEL
LFMODE
REPEAT
BKWD
MAPSEL
LFMODE
BISTEN
MCLK
SCL
SDA
IDx
SCL
SDA
IDx
MODE_SEL
Figure 40. Typical Display System Diagram
9.2.1 Design Requirements
For the typical design application, use the following as input parameters:
Table 8. Design Parameters
DESIGN PARAMETER
VDDIO
EXAMPLE VALUE
1.8 V or 3.3 V
3.3 V
VDD33
AC Coupling Capacitor for RIN±
PCLK Frequency
100 nF
78 MHz
9.2.2 Detailed Design Procedure
9.2.2.1 Transmission Media
The DS90UH927Q-Q1 and DS90UH928Q-Q1 chipset is intended to be used in a point-to-point configuration
through a shielded twisted pair cable. The serializer and deserializer provide internal termination to minimize
impedance discontinuities. The interconnect (cable and connector) between the serializer and deserializer should
have a differential impedance of 100 Ω. The maximum length of cable that can be used is dependant on the
quality of the cable (gauge, impedance), connector, board (discontinuities, power plane), the electrical
environment (for example, power stability, ground noise, input clock jitter, PCLK frequency, etc.) and the
application environment.
The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the
differential eye opening of the serial data stream. The Receiver CML Monitor Driver Output Specifications define
the acceptable data eye opening width and eye opening height. A differential probe should be used to measure
across the termination resistor at the CMLOUT± pin Figure 2.
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9.2.2.2 Display Application
The DS90UH928Q-Q1, in conjunction with the DS90UH925Q-Q1 or DS90UH927Q-Q1, is intended for interfacing
with a HDCP compliant host (graphics processor) and a display supporting 24-bit color depth (RGB888) and high
definition (720p) digital video format. It can receive an 8-bit RGB stream with a pixel clock rate up to 85 MHz
together with three control bits (VS, HS and DE) and four I2S audio streams. The included HDCP 1.3 compliant
cipher block allows the authentication of the HDCP Deserializer, which decrypts both video and audio contents.
The HDCP keys are pre-loaded by TI into Non-Volatile Memory (NVM) for maximum security.
9.2.3 Application Curves
Input to Serializer
Output at Deserializer
Figure 42. CMLOUT of Deserializer from 48-MHz Input
Clock
Figure 41. 78-MHz Clock at Serializer and Deserializer
10 Power Supply Recommendations
This section describes power-up requirements and the PDB pin. The power supply ramp (VDD33 and VDDIO
)
should be faster than 1.5 ms with a monotonic rise. A large capacitor on the PDB pin is needed to ensure PDB
arrives after all the supply pins have settled to the recommended operating voltage. The PDB pin requires a 10-
kΩ pullup to VDD33 and a >10-μF capacitor to GND to delay the PDB input signal rise. If PDB is driven externally,
do not drive the pin HIGH until VDD33 and VDDIO have reached steady state. All inputs must not be driven until
both VDD33 and VDDIO have reached steady state. Pins VDD33_A and VDD33_B should both be externally
connected, bypassed, and driven to the same potential (they are not internally connected).
11 Layout
11.1 Layout Guidelines
Circuit board layout and stack-up for the LVDS serializer and deserializer devices should be designed to provide
low-noise power to the device. Good layout practice will also separate high frequency or high-level inputs and
outputs to minimize unwanted stray noise, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mil) for power / ground sandwiches. This arrangement utilizes the plane
capacitance for the PCB power system and has low-inductance, which has proven effectiveness especially at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 μF to 10 μF. Tantalum capacitors may be in the 2.2 μF to 10 μF range. The voltage rating of the
capacitors should be at least 5X the power supply voltage being used.
MLCC surface mount capacitors are recommended due to their smaller parasitic properties. When using multiple
capacitors per supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommended at
the point of power entry. This is typically in the 50 μF to 100 μF range and will smooth low frequency switching
noise. It is recommended to connect power and ground pins directly to the power and ground planes with bypass
capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an
external bypass capacitor will increase the inductance of the path. A small body size X7R chip capacitor, such as
56
Copyright © 2013–2015, Texas Instruments Incorporated
DS90UH928Q-Q1
www.ti.com.cn
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
Layout Guidelines (continued)
0603 or 0805, is recommended for external bypass. A small body sized capacitor has less inductance. The user
must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20
MHz to 30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance
between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use
two vias from power and ground pins to the planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs. This device requires only one common ground plane to connect all device related ground pins.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely coupled differential lines of 100 Ω
are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise
will appear as common mode and thus is rejected by the receivers. The tightly coupled lines will also radiate
less.
At least 9 thermal vias are necessary from the device center DAP to the ground plane. They connect the device
ground to the PCB ground plane, as well as conduct heat from the exposed pad of the package to the PCB
ground plane. More information on the LLP style package, including PCB design and manufacturing
requirements, is provided in TI Application Note SNOA401.
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste
deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve
board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow
unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown below:
Table 9. No Pullback WQFN Stencil Aperture Summary
DEVICE
PIN
COUNT
MKT Dwg
PCB I/O
Pad Size
(mm)
PCB
PITCH
(mm)
PCB DAP
SIZE (mm)
STENCIL I/O
APERTURE
(mm)
STENCIL DAP
Aperture (mm)
NUMBER of
DAP
APERTURE
OPENINGS
DS90UH928Q-
Q1
48
RHS0048A 0.25 x 0.4
0.5
5.1 x 5.1
0.25 x 0.6
5.1 x 5.1
1
Figure 43 shows the PCB layout example derived from the layout design of the DS90UH928QEVM Evaluation
Board. The graphic and layout description are used to determine both proper routing and proper solder
techniques when designing the Serializer board.
Copyright © 2013–2015, Texas Instruments Incorporated
57
DS90UH928Q-Q1
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
www.ti.com.cn
11.1.1 CML Interconnect Guidelines
See SNLA008 and SNLA035 for full details.
•
•
Use 100-Ω coupled differential pairs
Use the S/2S/3S rule in spacings
–
–
–
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
•
•
•
•
•
Minimize the number of Vias
Use differential connectors when operating above 500 Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual (SNLA187).
11.2 Layout Example
Length-Matched
OpenLDI Traces
High-Speed Traces
AC Capacitors
Figure 43. DS90UH928Q-Q1 Deserializer Example Layout
58
Copyright © 2013–2015, Texas Instruments Incorporated
DS90UH928Q-Q1
www.ti.com.cn
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
Layout Example (continued)
Figure 44. 48-Pin WQFN Stencil Example of Via and Opening Placement
版权 © 2013–2015, Texas Instruments Incorporated
59
DS90UH928Q-Q1
ZHCSDB4B –MARCH 2013–REVISED JANUARY 2015
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
相关文档如下：
•
•
•
•
•
AN-1108《通道链路 PCB 和互连设计指南》，SNLA008
AN-905《传输线路 RAPIDESIGNER 操作和应用指南》，SNLA035
AN-1187《无引线框架封装 (LLP)》，SNOA401
《LVDS 所有者手册》，SNLA187
AN-2173《通过具有双向控制通道的 FPD-Link III 进行 I2C 通信》，SNLA131
12.2 商标
All trademarks are the property of their respective owners.
12.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
60
版权 © 2013–2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90UH928QSQ/NOPB
DS90UH928QSQE/NOPB
DS90UH928QSQX/NOPB
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
RHS
RHS
RHS
48
48
48
1000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
-40 to 105
UH928QSQ
SN
SN
UH928QSQ
UH928QSQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90UH928QSQ/NOPB WQFN
DS90UH928QSQE/NOPB WQFN
DS90UH928QSQX/NOPB WQFN
RHS
RHS
RHS
48
48
48
1000
250
330.0
178.0
330.0
16.4
16.4
16.4
7.3
7.3
7.3
7.3
7.3
7.3
1.3
1.3
1.3
12.0
12.0
12.0
16.0
16.0
16.0
Q1
Q1
Q1
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90UH928QSQ/NOPB
DS90UH928QSQE/NOPB
DS90UH928QSQX/NOPB
WQFN
WQFN
WQFN
RHS
RHS
RHS
48
48
48
1000
250
356.0
208.0
356.0
356.0
191.0
356.0
35.0
35.0
35.0
2500
Pack Materials-Page 2
PACKAGE OUTLINE
RHS0048A
WQFN - 0.8 mm max height
S
C
A
L
E
1
.
8
0
0
PLASTIC QUAD FLATPACK - NO LEAD
7.15
6.85
B
A
PIN 1 INDEX AREA
0.5
0.3
7.15
6.85
0.30
0.18
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8
0.7
C
DIM A
SEATING PLANE
OPT 1
(0.1)
OPT 2
(0.2)
0.05
0.00
0.08 C
2X 5.5
(0.2)
5.1 0.1
(A) TYP
13
24
44X 0.5
12
25
EXPOSED
THERMAL PAD
2X
49
SYMM
5.5
SEE TERMINAL
DETAIL
1
36
0.30
0.18
48X
48
37
PIN 1 ID
(OPTIONAL)
SYMM
0.1
C A B
0.5
0.3
48X
0.05
4214990/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHS0048A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
5.1)
SYMM
48
37
48X (0.6)
1
36
48X (0.25)
44X (0.5)
(1.05) TYP
(1.25) TYP
(6.8)
49
SYMM
(R0.05)
TYP
(
0.2) TYP
VIA
25
12
13
24
(1.25)
TYP
(1.05)
TYP
(6.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL EDGE
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214990/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHS0048A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.625) TYP
(1.25)
TYP
37
48
48X (0.6)
1
36
49
48X (0.25)
44X (0.5)
(1.25)
TYP
(0.625) TYP
(6.8)
SYMM
(R0.05) TYP
METAL
TYP
12
25
24
13
16X
1.05)
SYMM
(
(6.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 49
68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:15X
4214990/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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相关型号：
DS90UH928QSQ/NOPB
具有 HDCP 的 5MHz 至 85MHz 24 位彩色 FPD-Link III 转 FPD-Link 解串器 | RHS | 48 | -40 to 105
TI
DS90UH928QSQE/NOPB
具有 HDCP 的 5MHz 至 85MHz 24 位彩色 FPD-Link III 转 FPD-Link 解串器 | RHS | 48 | -40 to 105
TI
DS90UH928QSQX/NOPB
具有 HDCP 的 5MHz 至 85MHz 24 位彩色 FPD-Link III 转 FPD-Link 解串器 | RHS | 48 | -40 to 105
TI
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