DS90LV011AQMF [TI]
LINE DRIVER, PDSO5, 1.60 MM, MO-178, SOT-23, 5 PIN;
| 型号： | DS90LV011AQMF |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LINE DRIVER, PDSO5, 1.60 MM, MO-178, SOT-23, 5 PIN 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总8页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90LV011AQ
DS90LV011AQ Automotive LVDS Differential Driver
Literature Number: SNLS296C
October 14, 2008
DS90LV011AQ
Automotive LVDS Differential Driver
General Description
Features
The DS90LV011AQ is an LVDS driver optimized for high data
rate and low power applications. The DS90LV011AQ is a cur-
rent mode driver allowing power dissipation to remain low
even at high frequency. In addition, the short circuit fault cur-
rent is also minimized. The device is designed to support data
rates in excess of 400Mbps (200MHz) utilizing Low Voltage
Differential Signaling (LVDS) technology.
AECQ-100 Grade 1
■
■
■
Conforms to TIA/EIA-644-A Standard
>400Mbps (200MHz) switching rates
700 ps (100 ps typical) maximum differential skew
1.5 ns maximum propagation delay
Single 3.3V power supply
■
■
■
■
■
■
■
■
■
The device is offered in a 5-lead small outline transistor pack-
age. The LVDS outputs have been arranged for easy PCB
layout. The differential driver outputs provide low EMI with its
typical low output swing of 350 mV. The DS90LV011AQ can
be paired with its companion single line receiver, the
DS90LT012AQ, or with any of National's LVDS receivers, to
provide a high-speed LVDS interface.
±350 mV differential signaling
Power Off Protection (outputs in TRI-STATE)
Pinout simplifies PCB layout
Low power dissipation (23 mW @ 3.3V typical)
SOT-23 5-lead package
Pin compatible with SN65LVDS1
Connection Diagram
30063822
(Top View)
Order Number DS90LV011AQMF
See NS Package Number MF05A
Functional Diagram
30063802
© 2008 National Semiconductor Corporation
300638
www.national.com
(4 sec.)
+260°C
+135°C
Absolute Maximum Ratings (Note 4)
Maximum Junction Temperature
ESD Ratings
HBM (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
≥ 8kV
≥ 250V
≥ 1250V
MM (Note 2)
Supply Voltage (VDD
)
−0.3V to 4.0V
CDM (Note 3)
LVCMOS input voltage (TTL IN) −0.3V to to (VDD + 0.3V)
LVDS output voltage (OUT±)
LVDS output short circuit current
−0.3V to +3.9V
24mA
Note 1: Human Body Model, applicable std. JESD22-A114C
Note 2: Machine Model, applicable std. JESD22-A115-A
Note 3: Field Induced Charge Device Model, applicable std.
JESD22-C101-C
Maximum Package Power Dissipation @ +25°C
MF Package
794 mW
Derate MF Package
Package Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)
7.22 mW/°C above +25°C
Recommended Operating
Conditions
ꢀθJA
138.5°C/Watt
Min
Typ
Max
3.6
Units
V
ꢀθJC
107.0°C/Watt
−65°C to +150°C
Supply Voltage (VDD
Temperature (TA)
)
3.0
3.3
Storage Temperature
Lead Temperature Range Soldering
−40
+25 +125
°C
Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 5, 6, 11)
Symbol
Parameter
Output Differential Voltage
VOD Magnitude Change
Conditions
Pin
Min
Typ
350
3
Max
Units
|VOD
|
ΔVOD
VOS
OUT+,
OUT−
250
450
35
mV
mV
V
RL = 100Ω
(Figure 1 and Figure 2)
Offset Voltage
1.125
0
1.22
1
1.375
25
RL = 100Ω
(Figure 1)
Offset Magnitude Change
Power-off Leakage
mV
ΔVOS
IOFF
VOUT = 3.6V or GND, VDD = 0V
±1
−6
±10
−24
μA
mA
IOS
Output Short Circuit Current (Note VOUT+ and VOUT− = 0V
7)
IOSD
Differential Output Short Circuit
Current (Note 7)
VOD = 0V
−5
3
−12
mA
COUT
VIH
VIL
IIH
Output Capacitance
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Clamp Voltage
Input Capacitance
Power Supply Current
pF
V
TTL IN
2.0
VDD
0.8
GND
V
VIN = 3.3V or 2.4V
VIN = GND or 0.5V
ICL = −18 mA
±2
±1
−0.6
3
±10
±10
μA
μA
V
IIL
VCL
CIN
IDD
−1.5
pF
mA
mA
No Load
VIN = VDD or GND
VDD
5
8
7
10
RL = 100Ω
Switching Characteristics
Over Supply Voltage and Operating Temperature Ranges, unless otherwise specified. (Notes 6, 8, 9, 10)
Symbol
Parameter
Conditions
RL = 100Ω, CL = 15 pF
(Figure 3 and Figure 4)
Min
Typ
Max
Units
tPHLD
Differential Propagation Delay High to Low
0.3
1.0
1.5
ns
tPLHD
tSKD1
tSKD3
tSKD4
tTLH
Differential Propagation Delay Low to High
Differential Pulse Skew |tPHLD − tPLHD| (Note 12)
Differential Part to Part Skew (Note 13)
Differential Part to Part Skew (Note 14)
Transition Low to High Time
0.3
0
1.1
0.1
0.2
0.4
0.5
0.5
250
1.5
0.7
1.0
1.2
1.0
1.0
ns
ns
0
ns
0
ns
0.2
0.2
ns
tTHL
Transition High to Low Time
ns
fMAX
Maximum Operating Frequency (Note 15)
MHz
www.national.com
2
Note 4: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 5: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD
.
Note 6: All typicals are given for: VDD = +3.3V and TA = +25°C.
Note 7: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
Note 8: These parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage,
temperature) ranges.
Note 9: CL includes probe and fixture capacitance.
Note 10: Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr ≤ 1 ns, tf ≤ 1 ns (10%-90%).
Note 11: The DS90LV011AQ is a current mode device and only function with datasheet specification when a resistive load is applied to the drivers outputs.
Note 12: tSKD1, |tPHLD − tPLHD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
the same channel.
Note 13: tSKD3, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same VDD and within 5°C of each other within the operating temperature range.
Note 14: tSKD4, part to part skew, is the differential channel to channel skew of any event between devices. This specification applies to devices over recommended
operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay.
Note 15: fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0V to 3V. Output criteria: duty cycle = 45%/55%, VOD > 250mV.
Parameter Measurement Information
30063803
FIGURE 1. Differential Driver DC Test Circuit
30063824
FIGURE 2. Differential Driver Full Load DC Test Circuit
30063804
FIGURE 3. Differential Driver Propagation Delay and Transition Time Test Circuit
3
www.national.com
30063805
FIGURE 4. Differential Driver Propagation Delay and Transition Time Waveforms
Application Information
TABLE 1. Device Pin Descriptions
Pin Name
Package Pin Number
Description
LVTTL/LVCMOS driver input pins
SOT23
5
4
3
2
1
TTL IN
OUT+
OUT−
GND
Non-inverting driver output pin
Inverting driver output pin
Ground pin
VDD
Power supply pin, +3.3V ± 0.3V
www.national.com
4
Physical Dimensions inches (millimeters) unless otherwise noted
5-Lead SOT23, JEDEC MO-178, 1.6mm
Order Number DS90LV011AQMF
NS Package Number MF05A
5
www.national.com
Notes
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