DS90LT012AQ-Q1 [TI]
汽车类 LVDS 差动线路接收器;
| 型号： | DS90LT012AQ-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 LVDS 差动线路接收器 |
| 文件： | 总15页 (文件大小：967K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90LT012AQ
www.ti.com
SNLS297E –MAY 2008–REVISED APRIL 2013
DS90LT012AQ Automotive LVDS Differential Line Receiver
Check for Samples: DS90LT012AQ
1
FEATURES
DESCRIPTION
The DS90LT012AQ is a single CMOS differential line
receiver designed for applications requiring ultra low
power dissipation, low noise, and high data rates.
The devices are designed to support data rates in
excess of 400 Mbps (200 MHz) utilizing Low Voltage
Differential Swing (LVDS) technology
2
•
•
•
•
•
•
•
AECQ-100 Grade 1
-40 to +125°C Temperature Range Operation
Compatible with ANSI TIA/EIA-644-A Standard
>400 Mbps (200 MHz) Switching Rates
100 ps Differential Skew (Typical)
3.5 ns Maximum Propagation Delay
The DS90LT012AQ accepts low voltage (350 mV
typical) differential input signals and translates them
to 3V CMOS output levels. The DS90LT012AQ
includes an input line termination resistor for point-to-
point applications.
Integrated Line Termination Resistor (100Ω
Typical)
•
•
•
Single 3.3V power supply design
Power Down High Impedance on LVDS Inputs
The DS90LT012AQ and companion LVDS line driver
DS90LV011AQ provide a new alternative to high
power PECL/ECL devices for high speed interface
applications.
LVDS Inputs Accept LVDS/CML/LVPECL
Signals
•
•
Pinout Simplifies PCB Layout
Low Power Dissipation (10mW Typical@ 3.3V
Static)
•
SOT-23 5-Lead Package
Connection Diagram
Figure 1. Top View
See Package Number DBV
Functional Diagram
Figure 2. DS90LT012AQ
Truth Table
INPUTS
[IN+] − [IN−]
ID ≥ 0V
ID ≤ −0.1V
Full Fail-safe OPEN/SHORT or Terminated
OUTPUT
TTL OUT
V
H
L
V
H
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
DS90LT012AQ
SNLS297E –MAY 2008–REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage (VDD
)
−0.3V to +4V
−0.3V to +3.9V
Input Voltage (IN+, IN−)
Output Voltage (TTL OUT)
−0.3V to (VDD + 0.3V)
−100mA
Output Short Circuit Current
Maximum Package Power Dissipation @ +25°C
DBV Package
794mW
Derate DBV Package
7.22 mW/°C above +25°C
Package Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)
θJA
θJC
138.5°C/W
107.0°C/W
Lead Temperature
Soldering (4 sec.)
+260°C
–65°C to +150°C
+135°C
Storage Temperature Range
Maximum Junction Temperature
ESD Rating
(3)
HBM
>8 kV
>250V
(4)
MM
(5)
CDM
>1250V
(1) Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that
the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. JESD22-A114C
(4) Machine Model, applicable std. JESD22-A115-A
(5) Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions
Min
Typ
Max
Units
Supply Voltage (VDD
Operating Free Air
Temperature (TA)
)
+3.0
+3.3
+3.6
V
−40
25
+125
°C
Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.
(1)(2)
Symbol
VTH
Parameter
Differential Input High Threshold
Differential Input Low Threshold
Common-Mode Voltage
Input Current
Conditions
Pin
IN+, IN−
Min
Typ
Max
Units
mV
mV
V
VCM dependant on VDD
−30
−30
0
VTL
−100
0.10
−10
−10
−20
VCM
IIN
VDD = 3.0V to 3.6V, VID = 100mV
2.35
+10
+10
+20
VIN = +2.8V
VIN = 0V
VDD = 3.6V or 0V
±1
±1
μA
μA
VIN = +3.6V
VDD = 0V
μA
IIND
Differential Input Current
VIN+ = +0.4V, VIN− = +0V
VIN+ = +2.4V, VIN− = +2.0V
3
3.9
4.4
mA
RT
Integrated Termination Resistor
Input Capacitance
100
3
Ω
CIN
IN+ = IN− = GND
pF
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
unless otherwise specified (such as VID).
(2) All typicals are given for: VDD = +3.3V and TA = +25°C.
2
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SNLS297E –MAY 2008–REVISED APRIL 2013
Electrical Characteristics (continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1)(2)
Symbol
Parameter
Output High Voltage
Conditions
Pin
Min
2.4
2.4
2.4
Typ
3.1
Max
Units
V
VOH
IOH = −0.4 mA, VID = +200 mV
IOH = −0.4 mA, Inputs terminated
IOH = −0.4 mA, Inputs shorted
IOL = 2 mA, VID = −200 mV
TTL OUT
3.1
V
3.1
V
VOL
IOS
Output Low Voltage
0.3
0.5
V
(3)
Output Short Circuit Current
Input Clamp Voltage
VOUT = 0V
−15
−50
−0.7
5.4
−100
mA
V
VCL
IDD
ICL = −18 mA
−1.5
No Load Supply Current
Inputs Open
VDD
9
mA
(3) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted
at a time, do not exceed maximum junction temperature specification.
Switching Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.
(1)(2)(3)(4)
Symbol
tPHLD
tPLHD
tSKD1
tSKD3
tSKD4
tTLH
Parameter
Conditions
CL = 15 pF
Min
1.0
1.0
0
Typ
1.8
Max
3.5
Units
ns
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
VID = 200 mV
1.7
3.5
ns
(5)
Differential Pulse Skew |tPHLD − tPLHD
|
(Figure 3 and Figure 4)
100
0.3
400
1.0
ps
(6)
Differential Part to Part Skew
0
ns
(7)
Differential Part to Part Skew
0
0.4
2.5
ns
Rise Time
Fall Time
350
175
250
800
800
ps
tTHL
ps
(8)
fMAX
Maximum Operating Frequency
MHz
(1) All typicals are given for: VDD = +3.3V and TA = +25°C.
(2) These parameters are ensured by design. The limits are based on statistical analysis of the device performance over PVT (process,
voltage, temperature) ranges.
(3) CL includes probe and jig capacitance.
(4) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0% to 100%) ≤ 3 ns for IN±.
(5) tSKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of
the same channel.
(6) tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
at the same VDD and within 5°C of each other within the operating temperature range.
(7) tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over the recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min|
differential propagation delay.
(8) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria:
60%/40% duty cycle, VOL (max 0.4V), VOH (min 2.4V), load = 15 pF (stray plus probes).
Parameter Measurement Information
Figure 3. Receiver Propagation Delay and Transition Time Test Circuit
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Parameter Measurement Information (continued)
Figure 4. Receiver Propagation Delay and Transition Time Waveforms
Typical Applications
Figure 5. Balanced System — Point-to-Point Application
(DS90LT012AQ)
APPLICATION INFORMATION
General application guidelines and hints for LVDS drivers and receivers may be found in the following application
notes: LVDS Owner's Manual (lit #550062-003), AN-808 (SNLA028), AN-977 (SNLA166), AN-971 (SNLA165),
AN-916 (SNLA219), AN-805 (SNOA233), AN-903 (SNLA034).
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 5. This configuration provides a clean signaling environment for the fast edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the
range of 100Ω. The internal termination resistor converts the driver output (current mode) into a voltage that is
detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects
of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise
margin limits, and total termination loading must be taken into account.
The DS90LT012AQ differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V
common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V.
The driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting
may be the result of a ground potential difference between the driver's ground reference and the receiver's
ground reference, the common-mode effects of coupled noise, or a combination of the two. The AC parameters
of both receiver input pins are optimized for a recommended operating input voltage range of 0V to +2.4V
(measured from each pin to ground). The device will operate for receiver input voltages up to VDD, but exceeding
VDD will turn on the ESD protection circuitry which will clamp the bus voltages.
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SNLS297E –MAY 2008–REVISED APRIL 2013
POWER DECOUPLING RECOMMENDATIONS
Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended)
0.1μF and 0.001μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the
device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple
vias should be used to connect the decoupling capacitors to the power planes. A 10μF (35V) or greater solid
tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply
and ground.
PC BOARD CONSIDERATIONS
Use at least 4 PCB board layers (top to bottom): LVDS signals, ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL signals may couple onto the LVDS lines. It is best to
put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side) connectors as possible.
DIFFERENTIAL TRACES
Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable)
and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave
the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as
common-mode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than
traces 3mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise
induced on the differential lines is much more likely to appear as common-mode which is rejected by the
receiver.
Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase
difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI
will result! (Note that the velocity of propagation, v = c/E where c (the speed of light) = 0.2997mm/ps or 0.0118
r
in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match
differential impedance and provide isolation for the differential lines. Minimize the number of vias and other
discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.
Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode
rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid
discontinuities in differential impedance. Minor violations at connection points are allowable.
TERMINATION
The DS90LT012AQ integrates the terminating resistor for point-to-point applications. The resistor value will be
between 90Ω and 133Ω.
THRESHOLD
The LVDS Standard (ANSI/TIA/EIA-644-A) specifies a maximum threshold of ±100mV for the LVDS receiver.
The DS90LT012AQ supports an enhanced threshold region of −100mV to 0V. This is useful for fail-safe biasing.
The threshold region is shown in the Voltage Transfer Curve (VTC) in Figure 6. The typical DS90LT012AQ LVDS
receiver switches at about −30mV. Note that with VID = 0V, the output will be in a HIGH state. With an external
fail-safe bias of +25mV applied, the typical differential noise margin is now the difference from the switch point to
the bias point. In the example below, this would be 55mV of Differential Noise Margin (+25mV − (−30mV)). With
the enhanced threshold region of −100mV to 0V, this small external fail-safe biasing of +25mV (with respect to
0V) gives a DNM of a comfortable 55mV. With the standard threshold region of ±100mV, the external fail-safe
biasing would need to be +25mV with respect to +100mV or +125mV, giving a DNM of 155mV which is stronger
fail-safe biasing than is necessary for the DS90LT012AQ. If more DNM is required, then a stronger fail-safe bias
point can be set by changing resistor values.
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Figure 6. VTC of the DS90LT012AQ LVDS Receiver
FAIL SAFE BIASING
External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe
under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor
and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors
should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The common-
mode bias point ideally should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal
circuitry. Please refer to application note AN-1194 (SNLA051), “Failsafe Biasing of LVDS Interfaces” for more
information.
PROBING LVDS TRANSMISSION LINES
Always use high impedance (> 100kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing will give deceiving results.
CABLES AND CONNECTORS, GENERAL COMMENTS
When choosing cable and connectors for LVDS it is important to remember:
Use controlled impedance media. The cables and connectors you use should have a matched differential
impedance of about 100Ω. They should not introduce major impedance discontinuities.
Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax) for
noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and
also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by
the receiver.
For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3
(category 3) twisted pair cable works well, is readily available and relatively inexpensive.
PIN DESCRIPTIONS
Package Pin Number
Pin Name
Description
SOT-23
4
3
5
1
2
IN−
IN+
Inverting receiver input pin
Non-inverting receiver input pin
Receiver output pin
TTL OUT
VDD
Power supply pin, +3.3V ± 0.3V
Ground pin
GND
6
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DS90LT012AQ
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SNLS297E –MAY 2008–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................ 6
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90LT012AQMF/NOPB
DS90LT012AQMFE/NOPB
DS90LT012AQMFX/NOPB
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
5
5
5
1000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
N03Q
N03Q
N03Q
SN
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90LT012AQMF/NOPB SOT-23
DBV
DBV
5
5
1000
250
178.0
178.0
8.4
8.4
3.2
3.2
3.2
3.2
1.4
1.4
4.0
4.0
8.0
8.0
Q3
Q3
DS90LT012AQMFE/NOP SOT-23
B
DS90LT012AQMFX/NOP SOT-23
B
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2016
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90LT012AQMF/NOPB
DS90LT012AQMFE/NOPB
DS90LT012AQMFX/NOPB
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
5
5
5
1000
250
210.0
210.0
210.0
185.0
185.0
185.0
35.0
35.0
35.0
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
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EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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