DS90CR218A [TI]
+3.3V 上升沿数据选通 LVDS 21 位频道链接接收器 - 85MHz;
| 型号： | DS90CR218A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | +3.3V 上升沿数据选通 LVDS 21 位频道链接接收器 - 85MHz |
| 文件： | 总21页 (文件大小：684K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90CR218A
www.ti.com
SNLS054D –NOVEMBER 1999–REVISED APRIL 2013
DS90CR218A +3.3V Rising Edge Data Strobe LVDS
21-Bit Channel Link - 12 MHz to 85 MHz
Check for Samples: DS90CR218A
1
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
•
12 to 85 MHz Shift Clock Support
The DS90CR218A receiver deserializes three input
LVDS data streams into 21 bits of CMOS/TTL output
data. When operating at the maximum input clock
rate of 85 Mhz, the LVDS data is received at 595
Mbps per data channel for a total data throughput of
1.785 Gbit/sec (233 Mbytes/sec).
50% Duty Cycle on Receiver Output Clock
Low Power Consumption
±1V Common-mode Range (Around +1.2V)
Narrow Bus Reduces Cable Size and Cost
Up to 1.785 Gbps Throughput
The narrow bus and LVDS signalling of the
DS90CR218A is an ideal means to solve EMI and
cable size problems associated with wide, high-speed
TTL interfaces.
Up to 223 Mbytes/sec Bandwidth
345 mV (typ) Swing LVDS Devices for Low EMI
PLL Requires No External Components
Rising Edge Data Strobe
Compatible with TIA/EIA-644 LVDS Standard
Low Profile 48-Lead TSSOP Package
Block Diagram
Figure 1. DS90CR218A Top View
See Package Number DGG-48 (TSSOP)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DS90CR218A
SNLS054D –NOVEMBER 1999–REVISED APRIL 2013
www.ti.com
Connection Diagrams
Figure 2. DS90CR218A
Typical Application
Figure 3. Typical Application
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)(2)
Supply Voltage (VCC
)
−0.3V to +4V
−0.5V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
+150°C
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 4 sec.)
Maximum Package Power Dissipation @ +25°C TSSOP Package
Package Derating
−65°C to +150°C
+260°C
1.89 W
DS90CR218A
15 mW/°C above +25°C
> 7kV
ESD Rating
(HBM, 1.5kΩ, 100pF)
(EIAJ, 0Ω, 200pF)
> 700V
Latch Up Tolerance @ 25°C
> ±300mA
(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(2) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to
imply that the device should be operated at these limits. “Electrical Characteristics” specify conditions for device operation.
Recommended Operating Conditions
Min
3.0
−10
0
Nom
3.3
Max
3.6
Units
V
Supply Voltage (VCC
)
Operating Free Air Temperature (TA)
Receiver Input Range
+25
+70
2.4
°C
V
Supply Noise Voltage (VCC
)
100
mVPP
Electrical Characteristics(1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS/TTL DC SPECIFICATIONS
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Clamp Voltage
Input Current
2.0
GND
2.7
VCC
0.8
V
V
VOH
VOL
VCL
IIN
IOH = −0.4 mA
IOL = 2 mA
3.3
0.06
−0.79
+1.8
0
V
0.3
−1.5
+15
V
ICL = −18 mA
V
VIN = 0.4V, 2.5V or VCC
VIN = GND
μA
μA
mA
−10
IOS
Output Short Circuit Current
VOUT = 0V
−60
−120
LVDS RECEIVER DC SPECIFICATIONS
VTH
VTL
IIN
Differential Input High Threshold
Differential Input Low Threshold
Input Current
VCM = +1.2V
+100
mV
mV
μA
−100
VIN = +2.4V, VCC = 3.6V
VIN = 0V, VCC = 3.6V
±10
±10
μA
RECEIVER SUPPLY CURRENT
ICCRW
Receiver Supply Current(2) Worst Case
CL = 8 pF,
Worst Case Pattern
Figure 4 Figure 5
f = 33 MHz
f = 40 MHz
f = 66 MHz
f = 85 MHz
49
53
78
90
60
65
mA
mA
mA
mA
100
115
(1) Typical values are given for VCC = 3.3V and TA = +25°C.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except VOD and ΔVOD).
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Electrical Characteristics(1) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
ICCRZ
Parameter
Receiver Supply Current(2) Power Down
Conditions
Min
Typ
Max
Units
PWR DWN = Low
Receiver Outputs Stay Low during
Powerdown Mode
140
400
μA
Receiver Switching Characteristics(1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
CLHT
Parameter
CMOS/TTL Low-to-High Transition Time Figure 5
CMOS/TTL High-to-Low Transition Time Figure 5
Receiver Input Strobe Position for Bit 0 Figure 11
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin(2) Figure 12
Min
Typ
2.0
Max
3.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
μs
CHLT
1.8
3.5
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
f = 85 MHz
0.49
2.17
3.85
5.53
7.21
8.89
10.57
0.84
2.52
4.20
5.88
7.56
9.24
10.92
0.49
2.01
T
1.19
2.87
4.55
6.23
7.91
9.59
11.27
f = 85 MHz
f = 12MHz
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
RxCLK OUT Period Figure 6
11.76
4
83.33
6.5
6
RxCLK OUT High Time Figure 6
f = 85 MHz
5
RxCLK OUT Low Time Figure 6
3.5
3.5
3.5
5.5
5
RxOUT Setup to RxCLK OUT Figure 6
RxOUT Hold to RxCLK OUT Figure 6
RxCLK IN to RxCLK OUT Delay @ 25°C, VCC = 3.3V(3) Figure 7
Receiver Phase Lock Loop Set Figure 8
Receiver Powerdown Delay Figure 10
7
9.5
10
1
(1) Typical values are given for VCC = 3.3V and TA = +25°C.
(2) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the receiver
input setup and hold time (internal data sampling window). This margin do not take into account the Transmitter Pulse Position (TPPOS)
variance and is measured using the ideal TPPOS. This margin allows LVDS interconnect skew, inter-symbol interference (both
dependent on type/length of cable), Transmitter Pulse Position (TPPOS) variance, and source clock jitter less than 250 ps.
(3) Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver
(RCCD). The total latency for the 217/287 transmitter and 218A/288A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period.
AC Timing Diagrams
Figure 4. “Worst Case” Test Pattern
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SNLS054D –NOVEMBER 1999–REVISED APRIL 2013
Figure 5. DS90CR218A (Receiver) CMOS/TTL Output Load and Transition Times
Figure 6. DS90CR218A (Receiver) Setup/Hold and High/Low Times
Figure 7. DS90CR218A (Receiver) Clock In to Clock Out Delay
Figure 8. DS9OCR218A (Receiver) Phase Lock Loop Set Time
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Figure 9. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs
Figure 10. Receiver Powerdown Delay
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Figure 11. Receiver LVDS Input Strobe Position
Ideal Strobe Position
RxIN+ or RxIN-
RxIN+ or RxIN-
C
RSKM
RSKM
min
max
Tppos Ideal
Tppos Ideal
Rsposn
C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos Ideal — Calculated Transmitter output pulse position
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (Cycle-to-cycle)(1) + ISI (Inter-symbol interference) + TPPOS
variance (Tx dependent)(2)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
(1) Cycle-to-cycle jitter is less than 250 ps at 85MHz
(2) ISI is dependent on interconnect length; may be zero
Figure 12. Receiver LVDS Input Skew Margin
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APPLICATIONS INFORMATION
DS90CR218A PIN DESCRIPTIONS — Channel Link Receiver
Pin Name
RxIN+
I/O No.
Description
I
I
3
3
Positive LVDS differential data inputs.
Negative LVDS differential data inputs.
RxIN−
RxOUT
O
I
21 TTL level data outputs.
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DWN
VCC
1
1
1
1
4
5
1
2
1
3
Positive LVDS differential clock input.
Negative LVDS differential clock input.
I
O
I
TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
I
GND
I
Ground pins for TTL outputs.
PLL VCC
PLL GND
LVDS VCC
LVDS GND
I
Power supply for PLL.
1
I
Ground pin for PLL.
Power supply pin for LVDS inputs.
I
Ground pins for LVDS inputs.
The Channel Link devices are intended to be used in a wide variety of data transmission applications. Depending
upon the application the interconnecting media may vary. For example, for lower data rate (clock rate) and
shorter cable lengths (< 2m), the media electrical performance is less critical. For higher speed/long distance
applications the media's performance becomes more critical. Certain cable constructions provide tighter skew
(matched electrical length between the conductors and pairs). Twin-coax for example, has been demonstrated at
distances as great as 5 meters and with the maximum data transfer of 1.785 Gbit/s. Additional applications
information can be found in the following Interface Application Notes:
AN = ####
AN-1041 (SNLA218)
Topic
Introduction to Channel Link
AN-1108 (SNLA008)
AN-1109 (SNLA220)
AN-806 (SNLA026)
AN-905 (SNLA035)
AN-916 (SNLA219)
Channel Link PCB and Interconnect Design-In Guidelines
Multi-Drop Channel-Link Operation
Transmission Line Theory
Transmission Line Calculations and Differential Impedance
Cable Information
CABLES
A cable interface between the transmitter and receiver needs to support the differential LVDS pairs. The ideal
cable/connector interface would have a constant 100Ω differential impedance throughout the path. It is also
recommended that cable skew remain below 90ps (@ 85 MHz clock rate) to maintain a sufficient data sampling
window at the receiver.
In addition to the four or five cable pairs that carry data and clock, it is recommended to provide at least one
additional conductor (or pair) which connects ground between the transmitter and receiver. This low impedance
ground provides a common-mode return path for the two devices. Some of the more commonly used cable types
for point-to-point applications include flat ribbon, flex, twisted pair and Twin-Coax. All are available in a variety of
configurations and options. Flat ribbon cable, flex and twisted pair generally perform well in short point-to-point
applications while Twin-Coax is good for short and long applications. When using ribbon cable, it is
recommended to place a ground line between each differential pair to act as a barrier to noise coupling between
adjacent pairs. For Twin-Coax cable applications, it is recommended to utilize a shield on each cable pair. All
extended point-to-point applications should also employ an overall shield surrounding all cable pairs regardless
of the cable type. This overall shield results in improved transmission parameters such as faster attainable
speeds, longer distances between transmitter and receiver and reduced problems associated with EMS or EMI.
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The high-speed transport of LVDS signals has been demonstrated on several types of cables with excellent
results. However, the best overall performance has been seen when using Twin-Coax cable. Twin-Coax has very
low cable skew and EMI due to its construction and double shielding. All of the design considerations discussed
here and listed in the supplemental application notes provide the subsystem communications designer with many
useful guidelines. It is recommended that the designer assess the tradeoffs of each application thoroughly to
arrive at a reliable and economical cable solution.
RECEIVER FAILSAFE FEATURE
These receivers have input failsafe bias circuitry to guarantee a stable receiver output for floating or terminated
receiver inputs. Under these conditions receiver inputs will be in a HIGH state. If a clock signal is present, data
outputs will all be HIGH; if the clock input is also floating/terminated, data outputs will remain in the last valid
state. A floating/terminated clock input will result in a HIGH clock output.
BOARD LAYOUT
To obtain the maximum benefit from the noise and EMI reductions of LVDS, attention should be paid to the
layout of differential lines. Lines of a differential pair should always be adjacent to eliminate noise interference
from other signals and take full advantage of the noise canceling of the differential signals. The board designer
should also try to maintain equal length on signal traces for a given differential pair. As with any high-speed
design, the impedance discontinuities should be limited (reduce the numbers of vias and no 90 degree angles on
traces). Any discontinuities which do occur on one signal line should be mirrored in the other line of the
differential pair. Care should be taken to ensure that the differential trace impedance match the differential
impedance of the selected physical media (this impedance should also match the value of the termination
resistor that is connected across the differential pair at the receiver's input). Finally, the location of the CHANNEL
LINK TxOUT/RxIN pins should be as close as possible to the board edge so as to eliminate excessive pcb runs.
All of these considerations will limit reflections and crosstalk which adversely effect high frequency performance
and EMI.
UNUSED INPUTS
All unused outputs at the RxOUT outputs of the receiver must then be left floating.
TERMINATION
Use of current mode drivers requires a terminating resistor across the receiver inputs. The CHANNEL LINK
chipset will normally require a single 100Ω resistor between the true and complement lines on each differential
pair of the receiver input. The actual value of the termination resistor should be selected to match the differential
mode characteristic impedance (90Ω to 120Ω typical) of the cable. Figure 13 shows an example. No additional
pull-up or pull-down resistors are necessary as with some other differential technologies such as PECL. Surface
mount resistors are recommended to avoid the additional inductance that accompanies leaded resistors. These
resistors should be placed as close as possible to the receiver input pins to reduce stubs and effectively
terminate the differential lines.
Figure 13. LVDS Serialized Link Termination
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DECOUPLING CAPACITORS
Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance. For a
conservative approach three parallel-connected decoupling capacitors (Multi-Layered Ceramic type in surface
mount form factor) between each VCC and the ground plane(s) are recommended. The three capacitor values are
0.1 μF, 0.01 μF and 0.001 μF. An example is shown in Figure 14. The designer should employ wide traces for
power and ground and ensure each capacitor has its own via to the ground plane. If board space is limiting the
number of bypass capacitors, the PLL VCC should receive the most filtering/bypassing. Next would be the LVDS
VCC pins and finally the logic VCC pins.
Figure 14. CHANNEL LINK Decoupling Configuration
CLOCK JITTER
The CHANNEL LINK devices employ a PLL to generate and recover the clock transmitted across the LVDS
interface. The width of each bit in the serialized LVDS data stream is one-seventh the clock period. For example,
a 85 MHz clock has a period of 11.76 ns which results in a data bit width of 1.68 ns. Differential skew (Δt within
one differential pair), interconnect skew (Δt of one differential pair to another) and clock jitter will all reduce the
available window for sampling the LVDS serial data streams. Care must be taken to ensure that the clock input
to the transmitter be a clean low noise signal. Individual bypassing of each VCC to ground will minimize the noise
passed on to the PLL, thus creating a low jitter LVDS clock. These measures provide more margin for channel-
to-channel skew and interconnect skew as a part of the overall jitter/skew budget.
COMMON-MODE vs. DIFFERENTIAL MODE NOISE MARGIN
The typical signal swing for LVDS is 300 mV centered at +1.2V. The CHANNEL LINK receiver supports a 100
mV threshold therefore providing approximately 200 mV of differential noise margin. Common-mode protection is
of more importance to the system's operation due to the differential data transmission. LVDS supports an input
voltage range of Ground to +2.4V. This allows for a ±1.0V shifting of the center point due to ground potential
differences and common-mode noise.
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REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90CR218AMTD/NOPB
DS90CR218AMTDX/NOPB
ACTIVE
TSSOP
TSSOP
DGG
48
48
38
RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-10 to 70
-10 to 70
DS90CR218AMTD
>B
ACTIVE
DGG
1000 RoHS & Green
SN
DS90CR218AMTD
>B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90CR218AMTDX/
NOPB
TSSOP
DGG
48
1000
330.0
24.4
8.6
13.2
1.6
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DGG 48
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
DS90CR218AMTDX/NOPB
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
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9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
DGG TSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DS90CR218AMTD/NOPB
48
38
495
10
2540
5.79
Pack Materials-Page 3
PACKAGE OUTLINE
DGG0048A
TSSOP - 1.2 mm max height
SCALE 1.350
SMALL OUTLINE PACKAGE
C
8.3
7.9
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
46X 0.5
48
1
12.6
12.4
NOTE 3
2X
11.5
24
B
25
0.27
0.17
48X
6.2
6.0
1.2
1.0
0.08
C A B
(0.15) TYP
0.25
GAGE PLANE
0 - 8
SEE DETAIL A
0.15
0.75
0.05
0.50
DETAIL A
TYPICAL
4214859/B 11/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
DGG0048A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
48X (1.5)
SYMM
1
48
48X (0.3)
46X (0.5)
(R0.05)
TYP
SYMM
24
25
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214859/B 11/2020
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0048A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
48X (1.5)
SYMM
1
48
48X (0.3)
46X (0.5)
SYMM
(R0.05) TYP
24
25
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4214859/B 11/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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