DS90C363BMTX/NOPB [TI]
+3.3V 可编程 LVDS 发送器 18 位平板显示器 (FPD) 链路 - 65MHz | DGG | 48 | -10 to 70;
| 型号： | DS90C363BMTX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | +3.3V 可编程 LVDS 发送器 18 位平板显示器 (FPD) 链路 - 65MHz | DGG | 48 | -10 to 70 驱动 光电二极管 接口集成电路 驱动器 显示器 |
| 文件： | 总21页 (文件大小：702K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90C363B
www.ti.com
SNLS179F –APRIL 2004–REVISED APRIL 2013
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz
Check for Samples: DS90C363B
1
FEATURES
DESCRIPTION
The DS90C363B transmitter converts 21 bits of
CMOS/TTL data into three LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over a fourth LVDS link. Every cycle of the
transmit clock 21 bits of input data are sampled and
transmitted. At a transmit clock frequency of 65 MHz,
18 bits of RGB data and 3 bits of LCD timing and
control data (FPLINE, FPFRAME, DRDY) are
transmitted at a rate of 455 Mbps per LVDS data
channel. Using a 65 MHz clock, the data throughput
is 170 Mbytes/sec. The DS90C363B transmitter can
be programmed for Rising edge strobe or Falling
edge strobe through a dedicated pin. A Rising edge
or Falling edge strobe transmitter will interoperate
with a Falling edge strobe Receiver (DS90CF366)
without any translation logic.
23
•
No special start-up sequence required
between clock/data and /PD pins. Input signal
(clock and data) can be applied either before
or after the device is powered.
•
•
Support Spread Spectrum Clocking up to
100kHz frequency modulation and deviations
of ±2.5% center spread or −5% down spread.
"Input Clock Detection" feature will pull all
LVDS pairs to logic low when input clock is
missing and when /PD pin is logic high.
•
•
•
18 to 68 MHz shift clock support
Best–in–Class Set & Hold Times on TxINPUTs
Tx power consumption < 130 mW (typ) at
65MHz Grayscale
•
40% Less Power Dissipation than BiCMOS
Alternatives
This chipset is an ideal means to solve EMI and
cable size problems associated with wide, high speed
TTL interfaces.
•
•
Tx Power-down mode < 37μW (typ)
Supports VGA, SVGA, XGA and Dual Pixel
SXGA.
•
•
•
•
•
•
•
•
Narrow bus reduces cable size and cost
Up to 1.3 Gbps throughput
Up to 170 Megabytes/sec bandwidth
345 mV (typ) swing LVDS devices for low EMI
PLL requires no external components
Compatible with TIA/EIA-644 LVDS standard
Low profile 48-lead TSSOP package
Improved replacement for:
–
SN75LVDS84, DS90C363A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
TRI-STATE is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
DS90C363B
SNLS179F –APRIL 2004–REVISED APRIL 2013
www.ti.com
Block Diagram
Figure 1. DS90C363B
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
Absolute Maximum Ratings
Supply Voltage (VCC
)
−0.3V to +4 V
−0.3V to (VCC + 0.3) V
−0.3V to (VCC + 0.3) V
Continuous
CMOS/TTL Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit Duration
Junction Temperature
+150 °C
Storage Temperature
−65°C to +150 °C
+260 °C
Lead Temperature (Soldering, 4 sec)
Maximum Package Power Dissipation Capacity at 25°C
Package Power Dissipation Derating
TSSOP Package
1.98 W
16 mW/°C above +25°C
7 kV
HBM, 1.5 kΩ, 100 pF
EIAJ, 0Ω, 200 pF
ESD Rating
500 V
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be verified. They are not meant to imply
that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Recommended Operating Conditions
Min
3.0
Nom
3.3
Max
3.6
Unit
V
Supply Voltage (VCC
)
Operating Free Air Temperature (TA)
−10
+25
+70
200
68
°C
Supply Noise Voltage (VCC
)
mVPP
MHz
TxCLKIN frequency
18
2
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: DS90C363B
DS90C363B
www.ti.com
SNLS179F –APRIL 2004–REVISED APRIL 2013
Electrical Characteristics(1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ(2)
Max
Unit
CMOS/TTL DC SPECIFICATIONS
VIH
VIL
VCL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current
2.0
VCC
0.8
V
V
GND
ICL = −18 mA
−0.79
+1.8
0
−1.5
+10
V
V IN = 0.4V, 2.5V or VCC
V IN = GND
μA
μA
−10
LVDS DC SPECIFICATIONS
VOD
Differential Output Voltage
RL = 100Ω
250
345
450
35
mV
mV
ΔVOD
Change in VOD between complimentary
output states
(3)
VOS
Offset Voltage
1.13
1.25
1.38
35
V
ΔVOS
Change in VOS between complimentary
output states
mV
IOS
IOZ
Output Short Circuit Current
Output TRI-STATE® Current
VOUT = 0V, RL = 100Ω
−3.5
−5
mA
Power Down = 0V,
VOUT = 0V or VCC
±1
±10
μA
TRANSMITTER SUPPLY CURRENT
ICCTW
ICCTG
ICCTZ
Transmitter Supply Current, Worst Case
RL = 100Ω,
CL = 5 pF,
Worst Case Pattern
(Figure 2 Figure 5 ) "Typ"
values are given for VCC
3.6V and TA = +25°C,
f = 25MHz
f = 40 MHz
f = 65 MHz
29
34
42
40
45
55
mA
mA
mA
=
"Max" values are given for
VCC = 3.6V and TA = −10°C
Transmitter Supply Current, 16 Grayscale
RL = 100Ω,
CL = 5 pF,
16 Grayscale Pattern
(Figure 3 Figure 5 ) "Typ"
values are given for VCC
3.6V and TA = +25°C,
f = 25 MHz
f = 40 MHz
f = 65 MHz
28
32
39
40
45
50
mA
mA
mA
=
"Max" values are given for
VCC = 3.6V and TA = −10°C
Transmitter Supply Current, Power Down
Power Down = Low
11
150
μA
Driver Outputs in TRI-STATE® under
Power Down Mode
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except VOD and ΔVOD ).
(2) Typical values are given for VCC = 3.3V and TA = +25°C unless specified otherwise.
(3) VOS previously referred as VCM
.
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
TCIT
Parameter
Min
Typ
Max
5
Unit
ns
TxCLK IN Transition Time (Figure 6 )
TxCLK IN Period (Figure 7 )
TCIP
14.7
0.35T
0.35T
1.5
T
50
ns
TCIH
TCIL
TxCLK IN High Time (Figure 7 )
TxCLK IN Low Time (Figure 7 )
0.5T
0.5T
0.65T
0.65T
6.0
ns
ns
TXIT
TxIN, and Power Down pin transition Time
ns
TXPD
Minimum pulse width for Power Down pin signal
1
μs
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: DS90C363B
DS90C363B
SNLS179F –APRIL 2004–REVISED APRIL 2013
www.ti.com
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
Parameter
LVDS Low-to-High Transition Time (Figure 5 )
LVDS High-to-Low Transition Time (Figure 5 )
Min
Typ
0.75
0.75
0
Max
1.4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LHLT
1.4
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 12 )(1)
TPPos1 Transmitter Output Pulse Position for Bit 1
TPPos2 Transmitter Output Pulse Position for Bit 2
TPPos3 Transmitter Output Pulse Position for Bit 3
TPPos4 Transmitter Output Pulse Position for Bit 4
TPPos5 Transmitter Output Pulse Position for Bit 5
TPPos6 Transmitter Output Pulse Position for Bit 6
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 12 )(1)
TPPos1 Transmitter Output Pulse Position for Bit 1
TPPos2 Transmitter Output Pulse Position for Bit 2
TPPos3 Transmitter Output Pulse Position for Bit 3
TPPos4 Transmitter Output Pulse Position for Bit 4
TPPos5 Transmitter Output Pulse Position for Bit 5
TPPos6 Transmitter Output Pulse Position for Bit 6
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 12 )(1)
TPPos1 Transmitter Output Pulse Position for Bit 1
TPPos2 Transmitter Output Pulse Position for Bit 2
TPPos3 Transmitter Output Pulse Position for Bit 3
TPPos4 Transmitter Output Pulse Position for Bit 4
TPPos5 Transmitter Output Pulse Position for Bit 5
TPPos6 Transmitter Output Pulse Position for Bit 6
−0.20
2.00
+0.20
2.40
2.20
4.40
6.59
8.79
10.99
13.19
0
4.20
4.60
f = 65 MHz
f = 40 MHz
f = 25 MHz
6.39
6.79
8.59
8.99
10.79
12.99
−0.25
3.32
11.19
13.39
+0.25
3.82
3.57
7.14
10.71
14.29
17.86
21.43
0
6.89
7.39
10.46
14.04
17.61
21.18
−0.45
5.26
10.96
14.54
18.11
21.68
+0.45
6.16
5.71
11.43
17.14
22.86
28.57
34.29
10.98
16.69
22.41
28.12
33.84
2.5
11.88
17.59
23.31
29.02
34.74
TSTC
THTC
TCCD
TxIN Setup to TxCLK IN (Figure 7 )
TxIN Hold to TxCLK IN (Figure 7 )
0.5
TxCLK IN to TxCLK OUT Delay (Figure 8 ) 50% duty cycle input clock is
assumed, TA= −10°C, and 65MHz for "Min", TA = 70°C, and 25MHz for "Max",
VCC= 3.6V, R_FB = VCC
3.340
7.211
6.062
TxCLK IN to TxCLK OUT Delay (Figure 8 ) 50% duty cycle input clock is
assumed, TA= −10°C, and 65MHz for "Min", TA = 70°C, and 25MHz for "Max",
VCC= 3.6V, R_FB = GND
3.011
ns
SSCG
100kHz ±
2.5%/−5%
f = 25 MHz
Spread Spectrum Clock support; Modulation frequency with a
linear profile
100kHz ±
2.5%/−5%
f = 40 MHz
(2)
100kHz ±
2.5%/−5%
f = 65 MHz
TPLLS
TPDD
Transmitter Phase Lock Loop Set (Figure 9 )
Transmitter Power Down Delay (Figure 11 )
10
ms
ns
100
(1) The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature
ranges. This parameter is functionality tested only on Automatic Test Equipment (ATE).
(2) Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the
performance of tracking Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLK− pins.
4
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: DS90C363B
DS90C363B
www.ti.com
SNLS179F –APRIL 2004–REVISED APRIL 2013
AC Timing Diagrams
Figure 2. “Worst Case” Test Pattern
A. The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
B. The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
C. Figure 2 and Figure 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
D. Recommended pin to signal mapping. Customer may choose to define differently.
Figure 3. “16 Grayscale” Test Pattern
Figure 4. DS90C363B (Transmitter) LVDS Output Load
Figure 5. DS90C363B (Transmitter) LVDS Transition Times
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: DS90C363B
DS90C363B
SNLS179F –APRIL 2004–REVISED APRIL 2013
www.ti.com
AC Timing Diagrams (continued)
Figure 6. DS90C363B (Transmitter) Input Clock Transition Time
Figure 7. DS90C363B (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe)
Figure 8. DS90C363B (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe)
Figure 9. DS90C363B (Transmitter) Phase Lock Loop Set Time
Figure 10. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs
6
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: DS90C363B
DS90C363B
www.ti.com
SNLS179F –APRIL 2004–REVISED APRIL 2013
AC Timing Diagrams (continued)
Figure 11. Transmitter Power Down Delay
Figure 12. Transmitter LVDS Output Pulse Position Measurement
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: DS90C363B
DS90C363B
SNLS179F –APRIL 2004–REVISED APRIL 2013
www.ti.com
DS90C363B Pin Descriptions — FPD Link Transmitter
Pin Name
TxIN
I/O
No.
Description
I
21
TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME and
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
TxOUT+
O
O
I
3
3
1
1
1
1
1
Positive LVDS differentiaI data output.
TxOUT−
Negative LVDS differential data output.
FPSHIFT IN
R_FB
TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
Programmable strobe select (See Table 1).
Positive LVDS differential clock output.
I
TxCLK OUT+
TxCLK OUT−
PWR DOWN
O
O
I
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down.
See Applications Information .
VCC
I
I
I
I
I
I
3
4
1
2
1
3
1
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
GND
PLL VCC
PLL GND
LVDS VCC
LVDS GND
NC
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
No connect
8
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: DS90C363B
DS90C363B
www.ti.com
SNLS179F –APRIL 2004–REVISED APRIL 2013
APPLICATIONS INFORMATION
The DS90C363B are backward compatible with the DS90C363/DS90CF363, DS90C363A/DS90CF363A and are
a pin-for-pin replacement.
This device may also be used as a replacement for the DS90CF563 (5V, 65MHz) and DS90CF561 (5V, 40MHz)
FPD-Link Transmitters with certain considerations/modifications:
1. Change 5V power supply to 3.3V. Provide this supply to the VCC, LVDS VCC and PLL VCC of the transmitter.
2. To implement a falling edge device for the DS90C363B, the R_FB pin (pin 14) may be tied to ground OR left
unconnected (an internal pull-down resistor biases this pin low). Biasing this pin to Vcc implements a rising
edge device.
TRANSMITTER INPUT PINS
The DS90C363B transmitter input and control inputs accept 3.3V LVTTL/LVCMOS levels. They are not 5V
tolerant.
TRANSMITTER INPUT CLOCK/DATA SEQUENCING
The DS90C363B does not require any special requirement for sequencing of the input clock/data and PD
(PowerDown) signal. The DS90C363B offers a more robust input sequencing feature where the input clock/data
can be inserted after the release of the PD signal. In the case where the clock/data is stopped and reapplied,
such as changing video mode within Graphics Controller, it is not necessary to cycle the PD signal. However,
there are in certain cases where the PD may need to be asserted during these mode changes. In cases where
the source (Graphics Source) may be supplying an unstable clock or spurious noisy clock output to the LVDS
transmitter, the LVDS Transmitter may attempt to lock onto this unstable clock signal but is unable to do so due
the instability or quality of the clock source. The PD signal in these cases should then be asserted once a stable
clock is applied to the LVDS transmitter. Asserting the PWR DOWN pin will effectively place the device in reset
and disable the PLL, enabling the LVDS Transmitter into a power saving standby mode. However, it is still
generally a good practice to assert the PWR DOWN pin or reset the LVDS transmitter whenever the clock/data is
stopped and reapplied but it is not mandatory for the DS90C363B.
SPREAD SPECTRUM CLOCK SUPPORT
The DS90C363B can support Spread Spectrum Clocking signal type inputs. The DS90C383B outputs will
accurately track Spread Spectrum Clock/Data inputs with modulation frequencies of up to 100kHz (max.)with
either center spread of ±2.5% or down spread -5% deviations.
POWER SOURCES SEQUENCE
In typical applications, it is recommended to have VCC, LVDS VCC and PLL VCC from the same power source with
three separate de-coupling bypass capacitor groups. There is no requirement on which VCC entering the device
first.
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: DS90C363B
DS90C363B
SNLS179F –APRIL 2004–REVISED APRIL 2013
www.ti.com
Pin Diagram
DS90C363B
Order Number DS90C363BMT
DGG Package
Typical Application
Table 1. Programmable Transmitter (DS90C363B)
Pin
Condition
R_FB = VCC
Strobe Status
Rising edge strobe
Falling edge strobe
R_FB
R_FB
R_FB = GND or NC
10
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: DS90C363B
DS90C363B
www.ti.com
SNLS179F –APRIL 2004–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision E (April 2013) to Revision F
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 10
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: DS90C363B
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90C363BMT
NRND
TSSOP
DGG
48
38
Non-RoHS
& Green
Call TI
Level-2-235C-1 YEAR
-10 to 70
DS90C363BMT
DS90C363BMT/NOPB
DS90C363BMTX/NOPB
ACTIVE
ACTIVE
TSSOP
TSSOP
DGG
DGG
48
48
38
RoHS & Green
SN
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-10 to 70
-10 to 70
DS90C363BMT
DS90C363BMT
1000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90C363BMTX/NOPB TSSOP
DGG
48
1000
330.0
24.4
8.6
13.2
1.6
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DGG 48
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
DS90C363BMTX/NOPB
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DS90C363BMT
DS90C363BMT
DGG
DGG
DGG
TSSOP
TSSOP
TSSOP
48
48
48
38
38
38
495
495
495
10
10
10
2540
2540
2540
5.79
5.79
5.79
DS90C363BMT/NOPB
Pack Materials-Page 3
PACKAGE OUTLINE
DGG0048A
TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
3
5
0
SMALL OUTLINE PACKAGE
C
8.3
7.9
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
46X 0.5
48
1
12.6
12.4
NOTE 3
2X
11.5
24
B
25
0.27
0.17
48X
6.2
6.0
1.2
1.0
0.08
C A B
(0.15) TYP
0.25
GAGE PLANE
0 - 8
SEE DETAIL A
0.15
0.75
0.05
0.50
DETAIL A
TYPICAL
4214859/B 11/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0048A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
48X (1.5)
SYMM
1
48
48X (0.3)
46X (0.5)
(R0.05)
TYP
SYMM
24
25
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214859/B 11/2020
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0048A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
48X (1.5)
SYMM
1
48
48X (0.3)
46X (0.5)
SYMM
(R0.05) TYP
24
25
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4214859/B 11/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
相关型号：
DS90C363MTD
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) LinkΑ65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) LinkΑ65 MHz
NSC
DS90C363MTD
3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Linkâ65 MHz, 3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Linkâ65 MHz
TI
DS90C363MTD/NOPB
3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Linkâ65 MHz, 3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Linkâ65 MHz
TI
DS90C363MTDX/NOPB
IC QUAD LINE DRIVER, PDSO48, LOW PROFILE, PLASTIC, TSSOP-48, Line Driver or Receiver
NSC
DS90C363MTDX/NOPB
3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Linkâ65 MHz, 3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Linkâ65 MHz
TI
DS90C363_13
3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Linkâ65 MHz, 3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Linkâ65 MHz
TI
©2020 ICPDF网 联系我们和版权申明