DS160PR412RUAT [TI]
具有集成式 1:2 多路信号分离器的 PCIe® 4.0 16Gbps 4 通道线性转接驱动器
| RUA | 42 | -40 to 85;
| 型号： | DS160PR412RUAT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成式 1:2 多路信号分离器的 PCIe® 4.0 16Gbps 4 通道线性转接驱动器 | RUA | 42 | -40 to 85 PC 驱动 驱动器 |
| 文件： | 总36页 (文件大小：2794K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS160PR412
ZHCSMH5 –DECEMBER 2020
DS160PR412 具有集成式1:2 多路信号分离器的PCIe® 4.0 16Gbps 4 通道线性转
接驱动器
1 特性
3 说明
• 具有集成式1:2 多路信号分离器的四通道PCIe 4.0
线性转接驱动器或中继器
• 此线性转接驱动器与协议无关，可兼容UPI、
DisplayPort、SAS、SATA 和XFI
• 3.3V 单电源轨
• 120mW/通道的低有功功率
• 无需散热器
• 在8GHz 时提供高达17dB 的均衡，可处理高达
42dB 的PCIe 4.0 通道
• 具有-13dB 输入和-15dB 输出的超低差分回波损耗
• PRBS 数据具有70fs 的低附加随机抖动
• 80ps 低延迟
• 自动接收器检测和无缝支持PCIe 链路训练
• 通过引脚控制或SMBus/I2C 进行器件配置。
• 通过引脚选择多路复用器/多路信号分离器
• 工业温度范围为-40°C 至85°C
• 3.5mm x 9mm、42 引脚、0.5mm 间距WQFN 封
装
DS160PR412 是具有集成式多路信号分离器的四通道
线性转接驱动器。这款低功耗高性能线性转接驱动器专
为支持PCIe 4.0 和其他接口而设计。
DS160PR412 接收器部署了连续时间线性均衡器
(CTLE)，可提供高频增强。均衡器可以打开由于 PCB
布线或电缆等互连介质引起的码间串扰 (ISI) 而完全关
闭的输入眼图。线性转接驱动器和无源通道作为一个整
体接受链路训练，以便达到出色的传输和接收均衡设
置，从而实现更优的电气链路和尽可能低的延迟。该器
件具有低通道间串扰、低附加抖动和超低的回波损耗，
因此在链路中几乎可用作无源元件。这款器件具有内部
线性稳压器，对板上电源噪声具有高抗扰度，从而为高
速数据路径提供纯净电源。
DS160PR412 在量产期间实施了高速测试，从而确保
可靠的高产量制造。此器件还具有低交流和直流增益变
化，可在各种平台部署中提供一致的均衡功能。
器件信息(1)
封装尺寸（标称值）
器件型号
封装
WQFN (42)
2 应用
DS160PR412
3.5 mm x 9 mm
• 台式计算机/主板
• 机架式服务器
• 微服务器和塔式服务器
• 高性能计算
• 硬件加速器
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 网络连接存储
• 存储区域网络(SAN) 和主机总线适配器(HBA) 卡
• 网络接口卡(NIC)
PCIe Card
x16
Slot
x8
4-Ch
4-Ch
Connector-B
RXB 8-ch
x8
RX 8-ch
DS160PR421
4 Ch 2:1 Mux
4-Ch
4-Ch
CPU
TX 8-ch
TXB 8-ch
DS160PR412
4 Ch 1:2 De-mux
4-Ch
4-Ch
h
c
h
c
-
PCIe Card
-
8
8
XA
T
RXA
x8
Slot
Connector-A
x8
De-multiplexer
Multiplexer
PCIe Lane Muxing
应用用例
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNLS685
DS160PR412
ZHCSMH5 –DECEMBER 2020
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Table of Contents
7.4 Device Functional Modes..........................................17
7.5 Programming............................................................ 17
8 Application and Implementation..................................19
8.1 Application Information............................................. 19
8.2 Typical Applications.................................................. 19
9 Power Supply Recommendations................................24
10 Layout...........................................................................25
10.1 Layout Guidelines................................................... 25
11 Layout Example........................................................... 26
12 Device and Documentation Support..........................28
12.1 接收文档更新通知................................................... 28
12.2 支持资源..................................................................28
12.3 Trademarks.............................................................28
12.4 静电放电警告.......................................................... 28
12.5 术语表..................................................................... 28
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings ....................................... 6
6.2 ESD Ratings .............................................................. 6
6.3 Recommended Operating Conditions ........................6
6.4 Thermal Information ...................................................7
6.5 DC Electrical Characteristics ..................................... 7
6.6 High Speed Electrical Characteristics ........................8
6.7 SMBUS/I2C Timing Charateristics .............................9
6.8 Typical Characteristics.............................................. 11
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagram.........................................15
7.3 Feature Description...................................................15
Information.................................................................... 29
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
December 2020
*
Advance Info.
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5 Pin Configuration and Functions
1
38
38
GAIN/SDA
VREG1
RX0P
TXA0P
TXA0N
TXB0P
1
2
2
37
37
3
3
36
36
4
4
35 TXB0N
35
RX0N
5
34
TXA1P
34
VCC
GND
RX1P
RX1N
GND
5
6
6
33 TXA1N
33
7
7
32
32
TXB1P
8
8
31 TXB1N
31
EP=GND
9
9
30 GND
30
RX2P 10
10
29 TXA2P
29
11
11
28 TXA2N
28
RX2N
VREG2
VCC
12
12
27 TXB2P
27
13
13
26 TXB2N
26
RX3P 14
14
25
25
TXA3P
TXA3N
RX3N 15
15
24
24
16
16
23 TXB3P
23
GND
SEL
17
17
22
TXB3N
22
图5-1. RUA Package 42-Pin WQFN Top View
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Sets device control configuration modes. 4-level IO pin as defined in 表7-3. The
pin can be exercised at device power up or in normal operation mode.
L0: Pin Mode –device control configuration is done solely by strap pins.
L1 or L2: SMBus/I2C Slave Mode –device control configuration is done by an
external controller with SMBus/I2C master. This pin along with ADDR pin sets
devices slave address.
MODE
41
I, 4-level
L3 (Float): RESERVED –TI internal test mode.
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表5-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
EQ0 /ADDR
40
I, 4-level
In Pin Mode:
The EQ0 and EQ1 pins sets receiver linear equalization CTLE (AC gain) for all
channels according to 表7-1. These pins are sampled at device power-up only.
In SMBus/I2C Mode:
EQ1
20
I, 4-level
The ADDR pin in conjunction with MODE pin sets SMBus / I2C slave address
according to 表7-4. The pin is sampled at device power-up only.
In Pin Mode:
DC gain (broadbad gain including high frequency) from the input to the output of
the device for all channels. Note the device also provides AC (high frequency)
gain in the form of equalization controlled by EQ pins or SMBus/I2C registers.
In SMBus/I2C Mode:
GAIN /SDA
GND
1
I, 4-level / IO
3.3 V SMBus/I2C data. External pullup resistor such as 4.7 kΩ required for
operation.
EP, 6, 9, 16,
21, 30, 39
P
Ground reference for the device.
EP: the Exposed Pad at the bottom of the QFN package. It is used as the GND
return for the device. The EP should be connected to ground plane(s) through low
resistance path. A via array provides a low impedance path to GND. The EP also
improves thermal dissipation.
RSVD
PD
19
18
O
TI internal test pin. Keep no connect.
I, 3.3-V LVCMOS 2-level logic controlling the operating state of the redriver. Active in both Pin Mode
and SMBus/I2C Mode. The pin is used part of PCIe RX_DET state machine as
outlined in 表7-2.
High: Power down for all channels
Low: Power up, normal operation for all channels
RX_DET /SCL
42
I, 4-level / IO
In Pin Mode:
Sets receiver detect state machine options according to 表7-2. The pin is sampled
at device power-up only.
In SMBus/I2C Mode:
3.3 V SMBus/I2C clock. External pullup resistor such as 4.7 kΩ required for
operation.
RX0N
RX0P
RX1N
RX1P
RX2N
RX2P
RX3N
RX3P
SEL
4
3
I
I
I
I
I
I
I
I
Inverting differential RX inputs. Channel 0.
Noninverting differential RX inputs. Channel 0.
Inverting differential RX inputs. Channel 1.
Noninverting differential RX inputs. Channel 0.
Inverting differential RX inputs. Channel 2.
Noninverting differential RX inputs. Channel 2.
Inverting differential RX inputs. Channel 3.
Noninverting differential RX inputs. Channel 3.
8
7
11
10
15
14
17
I, 3.3 V LVCMOS Selects the mux path. Active in both Pin Mode and SMBus/I2C Mode. Note the
SEL pin must be exercised in system implementations for mux selection between
Port A vs Port B. The pin is used part of PCIe RX_DET state machine as outlined
in 表7-2.
L: Port A selected.
H: Port B selected.
TXA0N
TXA0P
TXA1N
TXA1P
TXA2N
TXA2P
TXA3N
TXA3P
37
38
33
34
28
29
24
25
O
O
O
O
O
O
O
O
Inverting differential TX output –Port A, Channel 0.
Non-inverting differential TX output –Port A, Channel 0.
Inverting differential TX output –Port A, Channel 1.
Non-inverting differential TX output –Port A, Channel 1.
Inverting differential TX output –Port A, Channel 2.
Non-inverting differential TX output –Port A, Channel 2.
Inverting differential TX output –Port A, Channel 3.
Non-inverting differential TX output –Port A, Channel 3.
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表5-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
TXB0N
TXB0P
TXB1N
TXB1P
TXB2N
TXB2P
TXB3N
TXB3P
VCC
NO.
35
O
O
O
O
O
O
O
O
P
Inverting differential TX output –Port B, Channel 0.
36
Non-inverting differential TX output –Port B, Channel 0.
Inverting differential TX output –Port B, Channel 1.
Non-inverting differential TX output –Port B, Channel 1.
Inverting differential TX output –Port B, Channel 2.
Non-inverting differential TX output –Port B, Channel 2.
Inverting differential TX output –Port B, Channel 3.
Non-inverting differential TX output –Port B, Channel 3.
31
32
26
27
22
23
5, 13
Power supply, VCC = 3.3 V ± 10%. The VCC pins on this device should be
connected through a low-resistance path to the board VCC plane.
VREG1
VREG2
2
P
P
Internal regulator output. Must add decoupling capacitor of 0.22 µF near the pin.
Do not route the pin beyond the decoupling capacitor. Do not connect to VREG2.
Do not use as a power supply for any other component on the board.
12
Internal regulator output. Must add decoupling caps of 0.22 µF near the pin. Do
not route the pin beyond the decoupling capacitor. Do not connect to VREG1. Do
not use as a power supply for any other component on the board.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
4.0
UNIT
V
VCCABSMAX
VIOCMOS,ABSMAX
VIO4LVL,ABSMAX
VIOHS-RX,ABSMAX
VIOHS-TX,ABSMAX
TJ,ABSMAX
Supply Voltage (VCC)
3.3 V LVCMOS and Open Drain I/O voltage
4-level Input I/O voltage
4.0
V
2.75
3.2
V
High-speed I/O voltage (RXnP, RXnN)
High-speed I/O voltage (TXnP, TXnN)
Junction temperature
V
2.75
150
150
V
°C
°C
Tstg
Storage temperature range
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2 kV
may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
DC plus AC power should not
exceed these limits
VCC
NVCC
Supply voltage, VCC to GND
Supply noise tolerance1
3.0
3.3
3.6
V
DC to <50 Hz, sinusoidal
50 Hz to 500 kHz, sinusoidal
500 kHz to 2.5 MHz, sinusoidal
>2.5 MHz, sinusoidal
250
100
33
mVpp
mVpp
mVpp
mVpp
ms
10
TRampVCC
VCC supply ramp time
From 0 V to 3.0 V
0.150
–40
–40
100
125
85
TJ
Operating junction temperature
Operating ambient temperature
Minimum pulse width required for
°C
TA
°C
PWLVCMOS the device to detect a valid signal PD, SEL
on LVCMOS inputs
200
uS
SMBus/I2C SDA and SCL Open Supply voltage for open drain
VCCSMBUS
3.6
400
V
Drain Termination Voltage
pull-up resistor
SMBus/I2C clock (SCL) frequency
in SMBus slave mode
FSMBus
10
kHz
Source differential launch
amplitude
VIDLAUNCH
800
1200
mVpp
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6.4 Thermal Information
DS160PR41
2,
DS160PR42
THERMAL METRIC(1)
UNIT
1
RUA, 42
Pins
RθJA-
Junction-to-ambient thermal resistance
26.1
℃/W
High K
RθJC(top) Junction-to-case (top) thermal resistance
14.1
8.7
1.6
8.6
2.6
℃/W
℃/W
℃/W
℃/W
℃/W
RθJB
ψJT
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
6.5 DC Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power
GAIN1/0 = L3
120
110
mW
mW
POWERCH
Active power per channel
GAIN1/0 = L0
Device current consumption when four
channels are active
IACTIVE
ISTBY
GAIN1/0 = L3, PD = L
145
190
45
mA
Device current consumption in standby
power mode
All channels disabled (PD = H)
30
mA
V
VREG
Control IO
VIH
Internal regulator output
2.5
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
SDA, SCL, PD, SEL pins
2.1
2.1
V
V
VIL
SDA, SCL, PD, SEL pins
1.08
VOH
V
Rpull-up = 4.7 kΩ (SDA, SCL pins)
IOL = –4 mA (SDA, SCL pins)
VOL
0.4
80
10
V
IIH,SEL
IIH
Input high leakage current for SEL pin VInput = VCC
µA
µA
µA
Input high leakage current
Input low leakage current
VInput = VCC, (SCL, SDA, PD pins)
VInput = 0 V, (SCL, SDA, PD, SEL pins)
IIL
-10
Input high leakage current for fail safe VInput = 3.6 V, VCC = 0 V, (SCL, SDA,
IIH,FS
150
10
µA
pF
input pins
PD, SEL pins)
CIN-CTRL
Input capacitance
SDA, SCL, PD, SEL pins
1.5
4 Level IOs (MODE, GAIN, EQ0, EQ1, RX_DET pins)
IIH_4L Input high leakage current, 4 level IOs VIN = 2.5 V
µA
µA
Input low leakage current for all 4 level
IOs except MODE.
IIL_4L
VIN = GND
VIN = GND
-10
Input low leakage current for MODE
pin
IIL_4L,MODE
-200
µA
Receiver
VRX-DC-CM
ZRX-DC
RX DC Common Mode (CM) Voltage Device is in active or standby state
Rx DC Single-Ended Impedance
2.5
50
V
Ω
ZRX-HIGH-IMP- DC input CM input impedance during
Inputs are at CM voltage
20
kΩ
Reset or power-down
DC-POS
Transmitter
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UNIT
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
100
MAX
Impedance of Tx during active
signaling, VID,diff = 1Vpp
ZTX-DIFF-DC
VTX-DC-CM
ITX-SHORT
DC Differential Tx Impedance
Tx DC common mode Voltage
Tx Short Circuit Current
Ω
V
0.75
Total current the Tx can supply when
shorted to GND
90
mA
6.6 High Speed Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Receiver
50 MHz to 1.25 GHz
-25
-22
-21
-14
dB
dB
dB
dB
1.25 GHz to 2.5 GHz
2.5 GHz to 4.0 GHz
4.0 GHz to 8.0 GHz
RLRX-DIFF
Input differential return loss
Pair-to-pair isolation (SDD21) between
two adjacent active receiver pairs from
10 MHz to 8 GHz.
XTRX
Receive-side pair-to-pair isolation
-47
dB
Transmitter
Measured with lowest EQ, GAIN = L3;
PRBS-7, 16 Gbps, over at least
106 bits using a bandpass-Pass Filter
from 30 Khz - 500 Mhz
Tx AC Peak-to-Peak Common Mode
Voltage
VTX-AC-CM-PP
50
mVpp
VTX-CM-DC = |VOUTn+ + VOUTn–|/2,
Absolute Delta of DC Common Mode Measured by taking the absolute
VTX-CM-DC-
0
100
10
mV
mV
ACTIVE-IDLE-
DELTA
Voltage during L0 and Electrical Idle
difference of VTX-CM-DC during PCIe
state L0 and Electrical Idle
Absolute Delta of DC Common Mode Measured by taking the absolute
Voltage between VOUTn+ and VOUTn– difference of VOUTn+ and VOUTn–
VTX-CM-DC-
LINE-DELTA
during L0
during PCIe state L0
Measured by taking the absolute
difference of VOUTn+ and VOUTn–
during Electrical Idle, Measured with a
band-pass filter consisting of two first-
order filters. The High-Pass and Low-
Pass -3-dB bandwidths are 10 kHz
and 1.25 GHz, respectively - zero at
input
VTX-IDLE-DIFF- AC Electrical Idle Differential Output
0
10
mV
Voltage
AC-p
Measured by taking the absolute
difference of VOUTn+ and VOUTn–
during Electrical Idle, Measured with a
first-order Low-Pass Filter with –3-dB
bandwidth of 10 kHz
VTX-IDLE-DIFF- DC Electrical Idle Differential Output
0
0
5
mV
mV
Voltage
DC
Measured while Tx is sensing whether
a low-impedance Receiver is present.
No load is connected to the driver
output
VTX-RCV-
Amount of Voltage change allowed
during Receiver Detection
600
DETECT
50 MHz to 1.25 GHz
1.25 GHz to 2.5 GHz
2.5 GHz to 4.0 GHz
4.0 GHz to 8.0 GHz
-20
-18
-18
-16
dB
dB
dB
dB
RLTX-DIFF
Output differential return loss
Minimum pair-to-pair isolation
(SDD21) between two adjacent active
transmitter pairs from 10 MHz to 8
GHz.
XTTX
Transmit-side pair-to-pair isolation
-48
dB
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over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Device Datapath
Input-to-output latency (propagation
delay) through a data channel
For either Low-to-High or High-to-Low
transition
TPLHD/PHLD
LTX-SKEW
80
110
20
ps
ps
Between any two lanes within a single
transmitter.
Lane-to-Lane Output Skew
-20
Difference between through redriver
and baseline setup. 16Gbps PRBS15.
Minimal input/output
channels. Minimum EQ. 800 mVpp-diff
input swing.
TRJ-DATA
Additive Random Jitter with data
70
90
4
fs
fs
Difference between through redriver
and baseline setup. 8 Ghz CK.
Minimal input/output
channels. Minimum EQ. 400 mVpp-diff
input swing.
Intrinsic additive Random Jitter with
clock
TRJ-INTRINSIC
Difference between through redriver
and baseline setup. 16 Gbps PRBS15.
Minimal input/output
channels. Minimum EQ. 800 mVpp-diff
input swing.
JITTERTOTAL-
Additive Total Jitter with data
ps
ps
DATA
Difference between through redriver
and baseline setup. 8 Ghz CK.
Intrinsic additive Total Jitter with clock Minimal input/output
channels. Minimum EQ. 800 mVpp-diff
JITTERTOTAL-
1
INTRINSIC
input swing.
Minimum EQ, GAIN = L0
Minimum EQ, GAIN = L1
Minimum EQ, GAIN = L2
Minimum EQ, GAIN = L3 (Float)
-4.2
-1.8
0.25
2.0
dB
dB
dB
dB
DCGAIN
DC flat gain input to output
EQ boost at max setting (EQ INDEX = AC gain at 8 GHz relative to gain at
EQ-MAX8G
17
dB
dB
15)
100 MHz.
GAIN = L2, minimum EQ setting. Max-
Min.
DCGAINVAR DC gain variation
EQGAINVAR EQ boost variation
-2.3
-3.3
1.7
3.7
At 8 Ghz. GAIN1/0 = L2, maximum EQ
setting. Max-Min.
dB
GAIN = L3 (defauult). 128T pattern at
2.5 Gbps.
LINDC
LINAC
Output DC Linearity
Output AC Linearity
1000
750
mVpp
mVpp
GAIN = L3 (default). 1T pattern at 16
Gbps.
6.7 SMBUS/I2C Timing Charateristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Slave Mode
Pulse width of spikes which must be
suppressed by the input filter
tSP
50
ns
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
tHD-STA
0.6
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
1.3
0.6
µs
µs
THIGH
Set-up time for a repeated START
condition
tSU-STA
tHD-DAT
0.6
0
µs
µs
Data hold time
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TSU-DAT
tr
Data setup time
0.1
µs
Rise time of both SDA and SCL
signals
120
2
ns
Pull-up resistor = 4.7 kΩ, Cb = 10pF
Pull-up resistor = 4.7 kΩ, Cb = 10pF
tf
Fall time of both SDA and SCL signals
Set-up time for STOP condition
ns
µs
tSU-STO
0.6
1.3
Bus free time between a STOP and
START condition
tBUF
µs
tVD-DAT
tVD-ACK
Cb
Data valid time
0.9
0.9
µs
µs
pF
Data valid acknowledge time
capacitive load for each bus line
400
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6.8 Typical Characteristics
Equalization Boost vs Frequency
20
EQ=0
EQ=1
EQ=7
EQ=13
EQ=2
EQ=8
EQ=14
EQ=3
EQ=9
EQ=15
EQ=4
EQ=5
18
EQ=6
EQ=10
EQ=11
16
14
12
10
8
EQ=12
6
4
2
0
-2
-4
0.1
1
10
Frequency (GHz)
图6-1. Typical EQ Boost vs Frequency
Equalization over Voltage and Temperature (EQ=15)
22
20
18
16
14
12
10
8
VCC=3.3V, Temp=25C
VCC=3.3V, Temp=-40C
VCC=3.3V, Temp=85C
VCC=3.0V, Temp=25C
VCC=3.0V, Temp=-40C
VCC=3.0V, Temp=85C
VCC=3.6V, Temp=25C
VCC=3.6V, Temp=-40C
VCC=3.6V, Temp=85C
6
4
2
0
0.1
1
10
Frequency (GHz)
图6-2. Typical EQ Boost over Voltage and Temperature with EQ=15
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6.8 Typical Characteristics
Input (RX) Differential Return Loss
0
-4
-8
-12
-16
-20
-24
-28
-32
SDD11
PCIe 4.0 Mask
-36
0
2
4
6
8
10
12
14
16
18
20
Frequency (GHz)
图6-3. Typical RX Differential Return Loss
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6.8 Typical Characteristics
Output (TX) Differential Return Loss
0
-4
-8
-12
-16
-20
-24
-28
-32
SDD22
PCIe 4.0 Mask
-36
0
2
4
6
8
10
12
14
16
18
20
Frequency (GHz)
图6-4. Typical TX Differential Return Loss
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6.8 Typical Characteristics
图6-5. Typical Jitter Characteristics - Top: 16Gbps PRBS15 Input to the Device, Bottom: Output of the Device.
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7 Detailed Description
7.1 Overview
The DS160PR412 is a four channel linear redriver with ingrated demultiplexer (demux). The low-power high-
performance linear repeater or redriver is designed to support PCIe 1.0/2.0/3.0/4.0. The device is a protocol
agnostic linear redriver that can operate for interfaces up to 16 Gbps.
The DS160PR412 can be configured two different ways:
Pin Mode – device control configuration is done solely by strap pins. Pin mode is expected to be good enough
for many system implementation needs.
SMBus/I2C Slave Mode - provides most flexibility. Requires a SMBus/I2C master device to configure
DS160PR412 though writing to its slave address.
7.2 Functional Block Diagram
One of Four 1:2 Demultiplexer Modules
RX Detect
Term
Term
RXnP
RXnN
TXAnP
TXAnN
Linear
Driver
CTLE
TXBnP
TXBnN
Linear
Driver
DS160PR412
Redriver Demux 1:2
Term
RX Detect
RX
Detect
Control
Select
mux
control
Driver
Control
CTLE
Control
VCC
Voltage Regulator
VREG1,2
Power-
On Reset
Always-On
10MHz
Shared Digital Core
GAIN/SDA
RX_DET/SCL
Shared Digital
GND
7.3 Feature Description
7.3.1 Linear Equalization
The DS160PR412 receivers feature a continuous-time linear equalizer (CTLE) that applies high-frequency boost
to help equalize the frequency-dependent insertion loss effects of the passive channel. 表 7-1 shows available
equalization boost through EQ control pins (EQ1 and EQ0), when in Pin Control mode (MODE = L0).
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表7-1. Equalization Control Settings
EQUALIZATION SETTING
TYPICAL EQ BOOST (dB)
EQ1_0 (Ch 0-3) / EQ1_1 (Ch EQ0_0 (Ch0-3) / EQ0_1 (Ch
EQ INDEX
@ 4 GHz @ 8 GHz
4-7)
L0
L0
L0
L0
L1
L1
L1
L1
L2
L2
L2
L2
L3
L3
L3
L3
4-7)
L0
L1
L2
L3
L0
L1
L2
L3
L0
L1
L2
L3
L0
L1
L2
L3
0
1
0.0
1.5
2.0
2.5
2.7
3.0
4.0
5.0
6.0
7.0
7.5
8.0
8.5
9.5
10.0
11.0
-0.1
4.5
2
5.5
3
6.5
4
7.0
5
8.0
6
9.0
7
10.0
11.0
12.0
12.5
13.0
14.0
15.0
16.0
17.0
8
9
10
11
12
13
14
15
The equalization of the device can also be set by writing to SMBus/I2C registers in slave mode. Refer to the
DS160PR412/421 Programming Guide for details.
7.3.2 Flat Gain
The GAIN pin can be used to set the overall datapath flat gain (broadbabd gain including high frequency) of the
DS160PR412 when the device is in Pin Mode. The default recommendation for most systems will be GAIN = L3
(float).
The flat gain and equalization of the DS160PR412 must be set such that the output signal swing at DC and high
frequency does not exceed the DC and AC linearity ranges of the devices, respectively.
Note the device also provides AC (high frequency) gain in the form of equalization controlled by EQ pins or
SMBus/I2C registers.
7.3.3 Receiver Detect State Machine
The DS160PR412 deploys an RX detect state machine that governs the RX detection cycle as defined in the
PCI express specifications. At device power up or through manually triggered event using PD or SEL pin or
writing to the relevant I2C/SMBus register, the redriver determines whether or not a valid PCI express
termination is present at the far end of the link. The RX_DET pin of DS160PR412 provides additional flexibility
for system designers to appropriately set the device in desired mode according to 表 7-2. For the PCIe
application the RX_DET pin can be left floating for default settings.
Note power up ramp or PD/SEL event triggers RX detect for all four channels. In applications where
DS160PR412 channels are used for multiple PCIe links, the RX detect function can be performed for individual
channels through writing in appropriate I2C/SMBus registers.
表7-2. Receiver Detect State Machine Settings
PD
RX_DET
RX Common-mode Impedance
COMMENTS
PCI Express RX detection state machine is disabled.
Recommended for non PCIe interface use case where the
DS160PR412 is used as buffer with equalization.
L
L0
Always 50 Ω
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表7-2. Receiver Detect State Machine Settings (continued)
PD
RX_DET
RX Common-mode Impedance
COMMENTS
TX polls every ≈150 µs until valid termination is detected. RX CM
impedance held at Hi-Z until detection Reset by asserting PD high
for 200 µs then low.
Pre Detect: Hi-Z
Post Detect: 50 Ω.
L
L3 (Float)
Reset Channels 0-3 signal path and set their RX impedance to Hi-
Z
H
L
X
X
Hi-Z
Pre Detect: Hi-Z
Post Detect: 50 Ω.
Reset Channels 4-7 signal path and set their RX impedance to Hi-
Z.
H
X
Hi-Z
7.4 Device Functional Modes
7.4.1 Active PCIe Mode
The device is in normal operation with PCIe state machine enabled by RX_DET = L3 (float). This mode is
recommended for PCIe use cases. In this mode PD pin is driven low in a system (for example by PCIe connector
"PRSNT" signal). In this mode, the device redrives and equalizes PCIe RX or TX signals to provide better signal
integrity.
7.4.2 Active Buffer Mode
The device is in normal operation with PCIe state machine disabled by RX_DET = L0. This mode is
recommended for non-PCIe use cases. In this mode the device is working as a buffer to provide linear
equalization to improve signal integrity.
7.4.3 Standby Mode
The device is in standby mode invoked by PD = H. In this mode, the device is in standby mode conserving
power.
7.5 Programming
7.5.1 Control and Configuration Interface
7.5.1.1 Pin Mode
The DS160PR412 can be fully configured through pin-strap pins. In this mode the device uses 2-level and 4-
level pins for device control and signal integrity optimum settings.
7.5.1.1.1 Four-Level Control Inputs
The DS160PR412 has five (EQ0, EQ1, GAIN, MODE, and RX_DET) 4-level inputs pins that are used to control
the configuration of the device. These 4-level inputs use a resistor divider to help set the 4 valid levels and
provide a wider range of control settings. External resistors must be of 10% tolerance or better. The EQ0, EQ1,
GAIN, and RX_DET pins are sampled at power-up only. The MODE pin can be exercised at device power up or
in normal operation mode.
表7-3. 4-Level Control Pin Settings
LEVEL
L0
SETTING
1 kΩ to GND
13 kΩ to GND
59 kΩ to GND
F (Float)
L1
L2
L3
7.5.1.2 SMBUS/I2C Register Control Interface
If MODE = L2 (SMBus / I2C slave control mode), the DS160PR412 is configured for best signal integrity through
a standard I2C or SMBus interface that may operate up to 400 kHz. The slave address of the DS160PR412 is
determined by the pin strap settings on the ADDR and MODE pins. The eight possible slave addresses (7-bit) for
each channel banks of the device are shown in 表 7-4. In SMBus/I2C modes the SCL, SDA pins must be pulled
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up to a 3.3 V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance. 4.7 kΩis
a good first approximation for a bus capacitance of 10 pF.
Refer to the DS160PR412/421 Programming Guide for details.
表7-4. SMBUS/I2C Slave Address Settings
MODE
L1
ADDR
L0
7-bit Slave Address Channels 0-1 7-bit Slave Address Channels 2-3
0x18
0x1A
0x1C
0x1E
0x20
0x22
0x24
0x26
0x19
0x1B
0x1D
0x1F
0x21
0x23
0x25
0x27
L1
L1
L1
L2
L1
L3
L2
L0
L2
L1
L2
L2
L2
L3
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The DS160PR412 is a high-speed linear repeater with integrated demux . The device extends the reach of a
differential channels impaired by loss from transmission media like PCBs and cables. It can be deployed in a
variety of different systems. The following sections outline typical applications and their associated design
considerations.
8.2 Typical Applications
The DS160PR412 is a PCI Express linear redriver that can also be configured as interface agnostic redriver by
disabling its RX detect feature. The device can be used in wide range of interfaces including:
• PCI Express
• Ultra Path Interconnect (UPI)
• SATA
• SAS
• Display Port
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8.2.1 PCIe x8 Lane Switching
The DS160PR412 and DS160PR421 and can be used in desktop motherboard applications to switch PCIe lanes
from a CPU in to one of the two PCIe CEM connectors. 图 8-1 shows a simplified schematic for the
configuration. Two DS160PR412 demultiplex eight TX channels from CPU into one of the two PCIe slots. On the
other hand two DS160PR421 multiplex eight RX channels from one of the two PCIe slots to CPU.
Mux selection
Two PR412
Float
SEL
RX_DET
X8 Slot
Linear
Driver
RXnP
RXnN
TXAnP
TXAnN
CTLE
8 TX Chan
8 Lanes
System Level
Power Control
1 of 4
Linear
Driver
PD
TXBnP
TXBnN
channels
GPIO mode
PCIe
Slot
A
MODE
pin strap control
for DC gain
1 kΩ
GAIN
GND
DS160PR412
Pin strap to
fine tune
EQ gain
EQ0
EQ1
PCIe Redriver Demux
settings
VCC
VREG1
0.1ꢀF
VREG2
VCC
0.1ꢀF
(2x)
0.1ꢀF
1ꢀF
Minimum
recommended
decoupling
Two PR421
Mux selection
CPU
(root
complex)
SEL
Float
RX_DET
Linear
Driver
TXnP
TXnN
RXAnP
RXAnN
CTLE
8 RX Chan
8 Lanes
1 of 4
channels
System Level
Power Control
RXBnP
RXBnN
CTLE
PD
PCIe
Slot
B
Optional pin strap
control for DC gain
GPIO mode
GAIN
MODE
DS160PR421
Pin strap to
fine tune
EQ gain
PCIe Redriver Mux
EQ0
EQ1
1 kΩ
GND
settings
VCC
VREG1
0.1ꢀF
VREG2
0.1ꢀF
VCC
Minimum
recommended
decoupling
1ꢀF
0.1ꢀF
(2x)
8 Lanes
X16 Slot
图8-1. Simplified Schematic for PCIe Lane Switching for PC Desktop Application
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8.2.1.1 Design Requirements
As with any high-speed design, there are many factors which influence the overall performance. The following
list indicates critical areas for consideration during design.
• Use 85 Ωimpedance traces when interfacing with PCIe CEM connectors. Length matching on the P and N
traces should be done on the single-ended segments of the differential pair.
• Use a uniform trace width and trace spacing for differential pairs.
• Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
• For Gen 3.0 and Gen 4.0, AC-coupling capacitors of 220 nF are recommended, set the maximum body size
to 0402, and add a cutout void on the GND plane below the landing pad of the capacitor to reduce parasitic
capacitance to GND.
• Back-drill connector vias and signal vias to minimize stub length.
• Use reference plane vias to ensure a low inductance path for the return current.
8.2.1.2 Detailed Design Procedure
In PCIe Gen 4.0 and Gen 3.0 applications, the specification requires Rx-Tx link training to establish and optimize
signal conditioning settings at 16 Gbps and 8 Gbps, respectively. In link training, the Rx partner requests a series
of FIR – pre-shoot and de-emphasis coefficients (10 Presets) from the Tx partner. The Rx partner includes 7-
levels (6 dB to 12 dB) of CTLE followed by a single tap DFE. The link training would pre-condition the signal,
with an equalized link between the root-complex and endpoint.
Note that there is no link training in PCIe Gen 1.0 (2.5 Gbps) or PCIe Gen 2.0 (5.0 Gbps) applications. The
DS160PR412 is placed in between the Tx and Rx. It helps extend the PCB trace reach distance by boosting the
attenuated signals with its equalization, which allows the user to recover the signal by the downstream Rx more
easily.
For operation in Gen 4.0 and Gen 3.0 links, the DS160PR412 transmit outputs are designed to pass the Tx
Preset signaling onto the Rx for the PCIe Gen 4.0 or Gen 3.0 link to train and optimize the equalization settings.
The suggested setting for the device is GAIN = L3 (default). Adjustments to the EQ setting should be performed
based on the channel loss to optimize the eye opening in the Rx partner. The Tx equalization presets or CTLE
and DFE coefficients in the Rx can also be adjusted to further improve the eye opening.
8.2.1.3 Pin-to-pin Passive versus Redriver Option
For eight lane PCIe lane muxing application a topology is illustrated where two DS160PR412 and two
DS160PR421 are used. There are system use cases where the PCIe link loss is low enough that a signal
conditioner such as linear redrivers may not be needed. In such use cases system engineers may consider
passive mux to achieve same lane muxing topology. The four channel passive mux/demux TMUXHS4412 is pin-
to-pin (p2p) compatible with the DS160PR412 and DS160PR421. This p2p component availability provides great
flexibility for system implementation engineers where the need for redriver is not completely clear. 图 8-2
illustrates p2p passive vs redriver option to implement PCIe lane switching.
PCIe Card
PCIe Card
x16
Slot
x16
Slot
x8
x8
Connector-B
RXB 8-ch
Connector-B
RXB 8-ch
x8
x8
RX 8-ch
RX 8-ch
TMUXHS4412
4 Ch 2:1 Mux
DS160PR421
4 Ch 2:1 redriver mux
CPU
CPU
TX 8-ch
TX 8-ch
TXB 8-ch
TXB 8-ch
TMUXHS4412
4 Ch 1:2 demux
DS160PR412
4 Ch 1:2 redriver demux
Pin-2-pin
h
c
h
h
c
h
c
-
PCIe Card
PCIe Card
c
-
-
-
8
8
8
8
XA
XA
T
RXA
T
RXA
x8
x8
Slot
Connector-A
Slot
Connector-A
x8
x8
Passive option
Redriver option
图8-2. Pin-to-pin passive vs redriver option for PCIe lane switching
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8.2.1.4 Application Curves
The DS160PR412 is a linear redriver that can be used to extend channel reach of a PCIe link. Normally, PCIe-
compliant TX and RX are equipt with signal-conditioning functions and can handle channel losses of up to 28 dB
at 8 GHz. In real implementation the channel reach is often lower. With the DS160PR412 in the link, the total
channel loss between a PCIe root complex and an end-point can be extended up to 42 dB at 8 GHz.
图8-3 shows an electric link that models a single channel of a PCIe link and eye diagrams measured at different
locations along the link. The source that models a PCIe Transmitter sends a 16 Gbps PRBS-15 signal with P7
presets. After a transmission channel with –30 dB at 8 GHz insertion loss, the eye diagram is fully closed. The
DS160PR412 with its CTLE set to the maximum (17 dB boost) together with the source TX equalization
compensates for the losses of the pre-channel (TL1) and opens the eye at the output of the device.
The post-channel (TL2) losses mandate the use of PCIe RX equalization functions such as CTLE and DFE that
are normally available in a PCIe-compliant receiver.
CPU / PCIe RC
16 Gbps, PRBS15
800mV
Pre-Cursor: 3.5 dB
Post-Cursor: -6 dB
PCIe
End Point
DUT
PCIe 4.0 Redriver
RX EQ = 15 (17 dB)
TL1
-30 dB @ 8 GHz
TL2
-15 dB @ 8 GHz
RX CTLE:
12 dB
图8-3. PCIe 4.0 Link Reach Extension Using the DS160PR412
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8.2.2 DisplayPort Application
The DS160PR412 can be used as a four channel DisplayPort (DP) redriver demux for data rates up to 20 Gbps.
To use the device in a non-PCIe application, the RX_DET pin must be pin-strapped to GND with 1 kΩ resistor
(L0).
The inverted DisplayPort HPD signal can be used to put the device into standby mode by using its PD pin. Note
in a DisplayPort link a sink can use HPD line to create an interrupt for its link partner source. If HPD signal is
used for power management an RC filter must be installed to filter out HPD interrupt signals.
The device is a linear redriver which is agnostic to DP link training. The DP link training negotiation between a
display source and sink stays effective through the device . The redriver becomes part of the electrical channel
along with passive traces, cables, and so forth, resulting into optimum source and sink parameters for best
electrical link.
图8-4 shows a simplified schematic for DisplayPort demultiplexing application using DS160PR412. Auxiliary and
Hot plug detect (HPD) are demuxed outside of DS160PR412. If system use case requires implementing DP
power states, the device must be controlled by the I2C or the pin-strap pins.
AUXAp
AUXAn
HPDA
For brevity AUX
biasing is not shown
AUXp
TS3A5223
AUXn
HPD
2-Ch 2:1 mux
AUXBp
AUXBn
HPDB
AUXAp
Demux control
AUXAn
HPDA
SEL
DisplayPort
Sink A
RX_DET
1kꢀ
GND
Linear
Driver
RXnP
RXnN
TXAnP
TXAnN
CTLE
DisplayPort
Source
3.3V
59kꢀ
Linear
Driver
1 of 4
TXBnP
TXBnN
AUXp
PD
channels
AUXn
HPD
DisplayPort
Sink B
AUXBp
0.1ꢁF
AUXBn
HPDB
GPIO mode
MODE
DS160PR412
100kꢀ
HPD
DP Main Link Redriver
1:2 Demux
Optional pin strap
control for DC gain
1 kΩ
GAIN
GND
EQ0
EQ1
Pin strap to fine tune
EQ gain settings
VREG1
0.1ꢁF
VREG2
0.1ꢁF
VCC
VCC
0.1ꢁF
(2x)
1ꢁF
Minimum
recommended
decoupling
图8-4. Simplified Schematic for DisplayPort Demultiplexer Application
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9 Power Supply Recommendations
Follow these general guidelines when designing the power supply:
1. The power supply should be designed to provide the operating conditions outlined in the recommended
operating conditions section in terms of DC voltage, AC noise, and start-up ramp time.
2. The DS160PR412 does not require any special power supply filtering, such as ferrite beads, provided that
the recommended operating conditions are met. Only standard supply decoupling is required. Typical supply
decoupling consists of a 0.1 µF capacitor per VCC pin, one 1.0 µF bulk capacitor per device, and one 10 µF
bulk capacitor per power bus that delivers power to one or more devices. The local decoupling (0.1 µF)
capacitors must be connected as close to the VCC pins as possible and with minimal path to the device
ground pad.
3. The DS160PR412 voltage regulator output pins require decoupling caps of 0.1 µF near each pins. The
regulator is only for internal use. Do not use to provide power to any external component.
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10 Layout
10.1 Layout Guidelines
The following guidelines should be followed when designing the layout:
1. Decoupling capacitors should be placed as close to the VCC pins as possible. Placing the decoupling
capacitors directly underneath the device is recommended if the board design permits.
2. High-speed differential signals TXnP/TXnN and RXnP/RXnN should be tightly coupled, skew matched, and
impedance controlled.
3. Vias should be avoided when possible on the high-speed differential signals. When vias must be used, take
care to minimize the via stub, either by transitioning through most/all layers or by back drilling.
4. GND relief can be used (but is not required) beneath the high-speed differential signal pads to improve
signal integrity by counteracting the pad capacitance.
5. GND vias should be placed directly beneath the device connecting the GND plane attached to the device to
the GND planes on other layers. This has the added benefit of improving thermal conductivity from the
device to the board.
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11 Layout Example
图11-1 shows DS160PR412 layout example.
图11-1. DS160PR412 layout example
图11-2 shows a layout illustration where two DS160PR412 and two DS160PR421 are used to switch 8 lanes
between two PCIe slots.
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图11-2. Layout example for PCIe lane muxing application
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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30-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS160PR412RUAR
DS160PR412RUAT
ACTIVE
ACTIVE
WQFN
WQFN
RUA
RUA
42
42
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
PR412
PR412
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RUA 42
9 x 3.5, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226504/A
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PACKAGE OUTLINE
RUA0042A
WQFN - 0.8 mm max height
S
C
A
L
E
1
.
8
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
A
B
PIN 1 INDEX AREA
9.1
8.9
0.8
0.6
C
SEATING PLANE
0.08 C
0.05
0.00
2.05 0.1
2X 1.5
SYMM
(0.1) TYP
EXPOSED
THERMAL PAD
21
18
17
22
SYMM
43
2X 8
7.55 0.1
0.3
0.2
1
38
42X
42
39
38X 0.5
0.1
C A B
0.5
0.3
42X
PIN 1 ID
0.05
4219139/A 03/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RUA0042A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.05)
SYMM
SEE SOLDER MASK
DETAIL
42X (0.6)
42X (0.25)
42
39
1
38X (0.5)
38
(3.525) TYP
(R0.05) TYP
(
0.2) TYP
VIA
1.17 TYP
SYMM
43
(7.55) (8.8)
17
22
18
21
(0.775)
TYP
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219139/A 03/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RUA0042A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.56) TYP
42X (0.6)
42X (0.25)
42
39
1
38X (0.5)
38
(R0.05) TYP
(0.585)
TYP
43
SYMM
(8.8)
12X (0.97)
22
17
21
18
12X (0.92)
SYMM
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 12X
EXPOSED PAD 43
69% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219139/A 03/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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