DRV8873SPWPT [TI]

40-V, 10-A H-bridge motor driver with integrated current sensing & current sense feedback | PWP | 24 | -40 to 125;


型号：	DRV8873SPWPT
厂家：	TEXAS INSTRUMENTS
描述：	40-V, 10-A H-bridge motor driver with integrated current sensing & current sense feedback \| PWP \| 24 \| -40 to 125
文件：	总58页 (文件大小：1727K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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DRV8873

SLVSET1 –AUGUST 2018

DRV8873 H-Bridge Motor Driver

1 Features

3 Description

The DRV8873 device is an integrated driver IC for

driving a brushed DC motor in industrial applications.

Two logic inputs control the H-bridge driver, which

consists of four N-channel MOSFETs that drive

motors bi-directionally with up to 10-A peak current.

The device operates from a single power supply and

supports a wide input supply range from 4.5 V to 38

•

H-Bridge Motor Driver

–

Drives One DC Motor, One Winding of a

Stepper Motor, or Solenoid Loads

•

4.5-V to 38-V Operating Voltage Range

10-A Peak Current Drive

Low HS + LS R_DS(ON)

–

150 mΩ at T_J= 25°C, 13.5 V

250 mΩ at T_J= 150°C, 13.5 V

A PH/EN or PWM interface allows simple interfacing

to controller circuits. Alternatively, independent half-

bridge control is available to drive two solenoid loads.

•

Current Mirror for Output Current Sensing

Configurable Control Interface

A current mirror allows the controller to monitor the

load current. This mirror approximates the current

through the high-side FETs, and does not require a

high-power resistor for sensing the current.

–

PH/EN

PWM (IN1/IN2)

Independent Half-Bridge Control

A low-power sleep mode is provided to achieve very-

low quiescent current draw by shutting down much of

the internal circuitry. Internal protection functions are

provided for undervoltage lockout, charge pump

faults, overcurrent protection, short-circuit protection,

open-load detection, and overtemperature. Fault

conditions are indicated on an nFAULT pin and

through the SPI registers.

•

Supports 1.8-V, 3.3-V, 5-V Logic Inputs

SPI or Hardware Interface Options

Low-Power Sleep Mode (10 µA)

Small Package and Footprint

–

24 HTSSOP PowerPAD™ IC Package

•

Protection Features

–

VM Undervoltage Lockout (UVLO)

Charge Pump Undervoltage (CPUV)

Overcurrent Protection (OCP)

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

DRV8873

HTSSOP (24)

7.70 mm × 4.40 mm

Output short to battery and short to ground

protection

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

–

Open Load Detection

Simplified Schematic

Thermal Shutdown (TSD)

Fault Condition Output (nFAULT / SPI)

4.5 to 38 V

DRV8873

2 Applications

PWM

•

ePOS and Currency Counters

ATMs (Automated Teller Machines)

Multi-Function Printers

H-Bridge Driver

DISABLE

SPI or HW

nFAULT

BDC

Current Sense

Current Regulation

Built-In Protection

Laser Beam Printers

Monitor

Factory Automation and Robotics

Motorized Window Blinds

Adjustable Desks and Beds

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DRV8873

SLVSET1 –AUGUST 2018

www.ti.com

Table of Contents

7.6 Register Maps......................................................... 35

Application and Implementation ........................ 40

8.1 Application Information............................................ 40

8.2 Typical Application .................................................. 40

Power Supply Recommendations...................... 46

9.1 Bulk Capacitance Sizing ......................................... 46

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 SPI Timing Requirements ......................................... 8

6.7 Typical Characteristics.............................................. 9

Detailed Description ............................................ 10

7.1 Overview ................................................................. 10

7.2 Functional Block Diagram ....................................... 11

7.3 Feature Description................................................. 13

7.4 Device Functional Modes........................................ 29

7.5 Programming........................................................... 30

10 Layout................................................................... 47

10.1 Layout Guidelines ................................................. 47

10.2 Layout Example .................................................... 47

11 Device and Documentation Support ................. 48

11.1 Documentation Support ....................................... 48

11.2 Receiving Notification of Documentation Updates 48

11.3 Community Resources.......................................... 48

11.4 Trademarks........................................................... 48

11.5 Electrostatic Discharge Caution............................ 48

11.6 Glossary................................................................ 48

12 Mechanical, Packaging, and Orderable

Information ........................................................... 48

12.1 Package Option Addendum .................................. 49

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

August 2018

September 2018

Initial release.

0.95

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SLVSET1 –AUGUST 2018

5 Pin Configuration and Functions

DRV8873H PWP PowerPAD Package

24-Pin HTSSOP

DRV8873S PWP PowerPAD Package

24-Pin HTSSOP

Top View

DVDD

nFAULT

MODE

GND

CPL

DVDD

nFAULT

SDO

GND

CPL

CPH

VCP

CPH

VCP

SDI

nITRIP

nOL

SCLK

OUT1

SRC

OUT2

nSCS

OUT1

SRC

OUT2

Thermal

Pad

Thermal

Pad

EN/IN1

PH/IN2

DISABLE

IPROPI1

nSLEEP

IPROPI2

EN/IN1

PH/IN2

DISABLE

IPROPI1

nSLEEP

IPROPI2

Not to scale

Pin Functions

NO.

TYPE⁽¹⁾

DESCRIPTION

NAME

DRV8873H

DRV8873S

Charge pump switching node. Connect a X7R capacitor with a value of 47 nF

between the CPH and CPL pins.

CPH

PWR

Charge pump switching node. Connect a X7R capacitor with a value of 47 nF

between the CPH and CPL pins.

CPL

Digital regulator. This pin is the 5-V internal digital-supply regulator. Bypass

this pin to GND with a 6.3-V, 1-µF ceramic capacitor.

DVDD

EN/IN1

Control Inputs. For details, see the Control Modes section. This pin has an

internal pulldown resistor to GND.

Bridge disable input. A logic high on this pin disables the H-bridge Hi-Z.

Internal pullup to DVDD.

DISABLE

GND

PWR

Ground pin

High-side FET current. The analog current proportional to the current flowing

in the half bridge.

IPROPI1

High-side FET current. The analog current proportional to the current flowing

in the half bridge.

IPROPI2

nITRIP

—

Internal current-regulation control pin (ITRIP). To enable the ITRIP feature,

do not connect this pin (or tie it to GND). To disable the ITRIP feature,

connect this pin to the DVDD pin.

Open-load diagnostic control pin. To run the open-load diagnostic at power

up, tie it to ground. Connect it to DVDD, open-load diagnostic will be

disabled.

nOL

—

MODE

OUT1

OUT2

—

Input mode pin. Sets the PH/EN, PWM, or independent-PWM mode.

Half-bridge output 1. Connect this pin to the motor or load.

Half-bridge output 2. Connect this pin to the motor or load.

(1) I = input, O = output, PWR = power, NC = no connect, OD = open-drain output, PP = push-pull output

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Pin Functions (continued)

NO.

TYPE⁽¹⁾

DESCRIPTION

NAME

DRV8873H

DRV8873S

Control inputs. For details, see the Control Modes section. This pin has an

internal pulldown resistor to GND.

PH/IN2

Serial clock input. Serial data is shifted out and captured on the

corresponding rising and falling edge on this pin.

SCLK

SDI

—

Serial data input. Data is captured on the falling edge of the SCLK pin.

Serial data output. Data is shifted out on the rising edge of the SCLK pin.

This is a push-pull output.

SDO

—

Slew rate adjust. This pin sets the slew rate of the H-bridge outputs.

Power FET source. Tie this pin to GND through a low-impedance path.

SRC

Charge pump output. Connect a 16-V, 1-µF ceramic capacitor from this pin to

the VM supply.

VCP

PWR

Power supply. This pin is the motor supply voltage. Bypass this pin to GND

with a 0.1-µF ceramic capacitor and a bulk capacitor.

Power supply. This pin is the motor supply voltage. Bypass this pin to GND

with a 0.1-µF ceramic capacitor and a bulk capacitor.

Fault indication pin. This pin is pulled logic low with a fault condition. This

open-drain output requires an external pullup resistor.

nFAULT

Serial chip select. An active low on this pin enables the serial interface

communications. Internal pullup to nSLEEP.

nSCS

—

nSLEEP

Sleep input. To enter a low-power sleep mode, set this pin logic low.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

Power supply voltage

Charge pump voltage

Charge pump switching pin

VCP, CPH

CPL

V_VM+ 5.7

V_VM

Internal logic regulator voltage DVDD

5.7

EN/IN1, PH/IN2, nSLEEP, DISABLE, nFAULT,

MODE, SR, SCLK, SDI, SDO, nSCS

Digital pin voltage

–0.3

5.7

V_TRIP

V_SRC

Analog pin voltage

IPROPI1, IPROPI2

–0.3

V_SRC– 1

5.5

0.3

H-Bridge source pin voltage

Phase node pin voltage

Open drain output current

Push-pull output current

Operating junction temperature

Storage temperature

OUTx

nFAULT

SDO

V_VM+ 1

°C

T_J

–40

150

T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

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6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

±2000

±750

±500

Electrostatic

V_(ESD)

Corner pins (1, 12, 13,

and 24)

Charged device model (CDM), per

discharge

JEDEC specification JESD22-C101, all pins⁽²⁾

Other pins

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

V_VM

V_I

Power supply voltage

4.5

Logic level input voltage

5.5

f_PWM

T_A

Applied PWM signal (EN/IN1, PH/IN2)

Operating ambient temperature

Operating junction temperature

100

125

150

kHz

°C

–40

T_J

°C

6.4 Thermal Information

DRV8873-Q1

THERMAL METRIC⁽¹⁾

PWP (HTSSOP)

UNIT

24 PINS

27.8

18.8

5.1

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

Ψ_JB

5.2

R_θJC(bot)

1.0

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. Typical limits apply for T_A= 25°C and V_VM= 13.5 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLIES (VM, DVDD)

V_VM

VM operating voltage

4.5

V_VM= 13.5 V; nSLEEP = 1; DISABLE

I_VM

VM operating supply current

I_VM(Q)

VM sleep mode supply current

Internal logic regulator voltage

Sleep time

V_VM= 13.5 V; nSLEEP = 0

µA

V_DVDD

t_(SLEEP)

t_(RESET)

2-mA load, V_VM> 5.5 V

4.7

5.3

nSLEEP low to start device shutdown

nSLEEP low to only clear fault registers

µs

nSLEEP reset pulse

nSLEEP high to device ready for input

signals

t_(WAKE)

t_on

Wake-up time

Turn-on time

1.5

VM > V_(UVLO); nSLEEP = 1, to output

transition

1.5

µs

t_(DISABLE)DISABLE deglitch time

DISABLE signal transition

2.5

CHARGE PUMP (VCP, CPH, CPL)

V_VCP

I_VCP

VCP operating voltage

VCP current

with respect to VM

V_VM= 13.5 V

V_VM+5

kHz

f_(VCP)

Charge pump switching frequency

V_VM> V_(UVLO); nSLEEP = 1

400

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Electrical Characteristics (continued)

Over recommended operating conditions unless otherwise noted. Typical limits apply for T_A= 25°C and V_VM= 13.5 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LOGIC-LEVEL INPUTS (EN/IN1, PH/IN2, nSLEEP, SCLK, SDI)

V_IL

Input logic-low voltage

Input logic-high voltage

Input logic hysteresis

0.8

5.3

V_IH

V_HYS

I_IL

1.6

150

µA

kΩ

Input logic-low current

Input logic-high current

Internal pulldown resistance

V_IN= 0 V

–5

I_IH

V_IN= 5 V

100

1.2

R_PD

to GND

SR = 000b; I_O= 1 A

SR = 001b; I_O= 1 A

SR = 010b; I_O= 1 A

SR = 011b; I_O= 1 A

SR = 100b; I_O= 1 A

SR = 101b; I_O= 1 A

SR = 110b; I_O= 1 A

SR = 111b; I_O= 1 A

1.6

2.6

3.4

Propagation delay (EN/IN1, PH/IN2

to OUTx = 50%)

t_pd

µs

4.1

5.2

7.8

13.3

LOGIC-LEVEL INPUT (DISABLE)

R_PU,DIS

V_IL,DIS

V_IH,DIS

Internal pull-up resistance

Input logic-low voltage

Input logic-high voltage

DISABLE to DVDD

100

450

kΩ

0.8

5.3

1.6

LOGIC-LEVEL INPUT (nSCS)

V_IL,nSCS

V_IH,nSCS

Input logic-low voltage

Input logic-high voltage

0.8

5.3

1.6

R_PU,nSCSInternal pull-up resistance

LOGIC-LEVEL INPUT (nSLEEP)

V_IL,SLEEPInput logic-low voltage

V_IH,SLEEPInput logic-high voltage

I_IH,SLEEPInput logic-high current

THREE-LEVEL INPUT (MODE)

nSCS to nSLEEP

kΩ

0.8

2.7

5.3

(1)

V_IN= 5 V; nSCS is High

80+I_SDO

µA

R_IN-1

R_IN-2

R_IN-3

Input mode 1

Input mode 2

Input mode 3

Tied to GND

Tied to DVDD

105

kΩ

190

PUSH-PULL OUTPUT (SDO)

R_PD,SDOInternal pull-down resistance

R_PU,SDOInternal pull-up resistance

OPEN DRAIN OUTPUT (nFAULT)

With respect to GND

Ω

With respect to nSLEEP

120

240

V_OL

I_OZ

Output logic-low voltage

I_O= 2 mA

V_O= 5 V

0.1

Output high-impedance leakage

–2

µA

MOTOR DRIVER OUTPUTS (OUT1, OUT2)

V_VM= 13.5 V; T_A= 25°C; T_J= 25°C

V_VM= 13.5 V; T_A= 25°C; T_J= 150°C

V_VM= 13.5 V; T_A= 25°C; T_J= 25°C

V_VM= 13.5 V; T_A= 25°C; T_J= 150°C

SR = 100b

125

R_DS(ON)

High-side FET on-resistance

mΩ

155

R_DS(ON)

t_(DEAD)

Low-side FET on-resistance

Output dead time

125

500

0.8

V_F(DIODE)Body diode forward voltage

I_O= 1 A

(1) SDO output current external to the device

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Electrical Characteristics (continued)

Over recommended operating conditions unless otherwise noted. Typical limits apply for T_A= 25°C and V_VM= 13.5 V

PARAMETER

TEST CONDITIONS

nSLEEP = 0

MIN

TYP

MAX

UNIT

I_SINK

Sink current when OUTx = Hi-Z

µA

nSLEEP = 1, DISABLE = 1

I_O= 1 A; Connect to GND

I_O= 1 A; R_(SR)= 22 kΩ ± 5% to GND

I_O= 1 A; R_(SR)= 68 kΩ ± 5% to GND

I_O= 1 A; No connect (Hi-Z)

I_O= 1 A; R_(SR)= 51 kΩ ± 5% to DVDD

I_O= 1 A; Connect to DVDD

I_O= 1 A; SR = 000b

340

53.2

18.3

Slew rate (H/W Device)

OUTx 10% to 90% changing

V/µs

7.9

2.6

53.2

I_O= 1 A; SR = 001b

I_O= 1 A; SR = 010b

18.3

I_O= 1 A; SR = 011b

Slew rate (SPI Device)

OUTx 10% to 90% changing

V/µs

I_O= 1 A; SR = 100b

10.8

7.9

5.3

2.6

I_O= 1 A; SR = 101b

I_O= 1 A; SR = 110b

I_O= 1 A; SR = 111b

CURRENT SENSE OUTPUTS (IPROPI1, IPROPI2)

Current mirror scaling

1100

A/A

I_O< 1 A

–50

–5

k_ERR

Current mirror scaling

I_O≥ 1 A

V_O= 2 V; SR = 000b

V_O= 2 V; SR = 111b

2.2

t_(IPROPI)

OUTx to IPROPI

µs

10.5

CURRENT REGULATION

ITRIP_LVL = 00b; V_VM= 13.5 V

ITRIP_LVL = 01b; V_VM= 13.5 V

ITRIP_LVL = 10b; V_VM= 13.5 V

ITRIP_LVL = 11b; V_VM= 13.5 V

TOFF = 00b

3.27

4.6

3.85

5.4

6.5

4.43

6.2

I_TRIP

Current limit threshold

5.5

7.5

5.95

8.1

TOFF = 01b

t_OFF

PWM off-time

µs

TOFF = 10b

TOFF = 11b

t_BLANK

PWM blanking time

PROTECTION CIRCUITS

VM falling; UVLO report

4.35

4.5

4.45

4.7

V_(UVLO)

VM undervoltage lockout

VM rising; UVLO recovery

t_(UVLO)

V_(RST)

VM UVLO falling deglitch time

VM UVLO reset

VM falling; UVLO report

µs

VM falling; UVLO report; device reset

V_VM= 12 V; T_A= 25°C; CPUV report

4.1

V_VCP(UV)Charge pump undervoltage

V_VM+ 2.25

I_(OCP)

Overcurrent protection trip level

Overcurrent deglitch time

t_(OCP)

µs

t_(RETRY)

Overcurrent retry time (H/W Device)

OCP_TRETRY = 00b

OCP_TRETRY = 01b

OCP_TRETRY = 10b

OCP_TRETRY = 11b

0.5

t_(RETRY)

Overcurrent retry time (SPI Device)

Open load active mode

V_OLA

150

300

450

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Electrical Characteristics (continued)

Over recommended operating conditions unless otherwise noted. Typical limits apply for T_A= 25°C and V_VM= 13.5 V

PARAMETER

TEST CONDITIONS

OL_DLY = 0b

MIN

TYP

0.3

1.2

MAX

UNIT

t_d(OL)

Open load diagnostic delay time

OL_DLY = 1b

I_OL

Open load current

°C

T_OTW

T_TSD

T_hys

Thermal warning temperature

Thermal shutdown temperature

Thermal shutdown hysteresis

Die temperature (T_J)

Die Temperature (T_J)

Die temperature (T_J)

140

165

150

175

160

185

6.6 SPI Timing Requirements

MIN

NOM

MAX

UNIT

t_(READY)

t_(CLK)

t_(CLKH)

t_(CLKL)

t_su(SDI)

t_h(SDI)

SPI ready, VM > V_(UVLO)

SCLK minimum period

SCLK minimum high time

SCLK minimum low time

SDI input setup time

100

SDI input hold time

t_d(SDO)

t_su(nSCS)

t_h(nSCS)

t_{(HI_nSCS)}

t_dis(nSCS)

SDO output delay time, SCLK high to SDO valid, C_L= 20 pF

nSCS input setup time

nSCS input hold time

nSCS minimum high time before active low

nSCS disable time, nSCS high to SDO high impedance

500

t_{(HI_nSCS)}

t_h(nSCS)

t_su(nSCS)

t_(CLK)

t_(CLKH)

t_(CLKL)

LSB

MSB

t_su(SDI)

t_h(SDI)

LSB

MSB

t_d(SDO)

t_dis(nSCS)

Figure 1. SPI Slave-Mode Timing Definition

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6.7 Typical Characteristics

160

140

120

100

-50

100

150

200

-50

100

150

200

Temperature (èC)

D001

D002

Figure 2. R_DS(on)vs Temperature

Figure 3. Operating Current (I_VM) vs Temperature

6.2

5.8

5.6

5.4

5.2

-50

100

150

200

-50

100

150

200

Temperature (èC)

D003

D004

ITRIP = 01b

Figure 5. ITRIP Current vs Temperature

Figure 4. Sleep Current (I_VM(Q)) vs Temperature

7.8

7.7

7.6

7.5

7.4

7.3

7.2

7.1

6.9

6.8

6.7

6.6

-50

100

150

200

-50

100

150

200

Temperature (èC)

D005

D006

ITRIP = 10b

Figure 6. ITRIP Current vs Temperature

ITRIP = 11b

Figure 7. ITRIP Current vs Temperature

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7 Detailed Description

7.1 Overview

The device is an integrated, 4.5-V to 38-V motor driver for industrial brushed-motor applications. The device is

capable of high output-current drive using low-R_DS(ON)integrated MOSFETs.

A standard 4-wire serial peripheral interface (SPI) decreases the device pin count by allowing the various device

settings and fault reporting to be managed through an external controller. Alternatively a hardware interface

option device is available for easy configuration with less detailed control of all device functions.

The device integrates a current mirror which provides an output current proportional to the current through the

high-side FETs. This feature allows the system to monitor the motor current without the need for a large high-

power resistor for current sensing. The device has a built-in current regulation feature with a fixed off-time

current-chopping scheme. The current-chopping level is selected through SPI in the SPI version of the device

and in the hardware version of the device is it a fixed value.

In addition to the high level of driver integration, the device provides a broad range of integrated protection

features. These features include power-supply undervoltage lockout (UVLO), charge-pump undervoltage lockout,

overcurrent faults, open-load detection, output short to battery and short to ground protection, and thermal

shutdown. Device faults are indicated by the nFAULT pin with detailed information available in the device

registers.

The device integrates a spread spectrum clocking feature for both the internal digital oscillator and internal

charge pump. This feature combined with output slew rate control minimizes the radiated emissions from the

device.

The device is available in a 24-pin HTSSOP package with a thermal pad.

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7.2 Functional Block Diagram

1 µF

DVDD

VCP

Power

1 µF

VCP

bulk

0.1 µF

CPH

Charge

Internal

OUT1

Pump

47 nF

Regulators

Predriver

CPL

IN1

IN2

BDC

VCP

Core

Logic

nSLEEP

OUT2

SRC

Predriver

DVDD

DISABLE

Control

Inputs

nSLEEP

V_TRIP

nOL

IPROPI1

IPROPI2

Protection

Undervoltage

Overcurrent

Thermal

R_SENSE-1

Current

Sense

Output

MODE

nITRIP

Open Load

R_SENSE-2

R_nFAULT

Output

nFAULT

GND

PPAD

Figure 8. Hardware Device Block Diagram

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Functional Block Diagram (continued)

1 µF

DVDD

VCP

Power

1 µF

VCP

CPH

bulk

0.1 µF

Charge

Pump

Internal

Regulators

OUT1

47 nF

Predriver

CPL

IN1

IN2

BDC

VCP

Core

Logic

Control

nSLEEP

OUT2

SRC

Inputs

Predriver

DVDD

DISABLE

nFAULT

R_nFAULT

V_TRIP

Output

IPROPI1

IPROPI2

Protection

nSLEEP

Undervoltage

Overcurrent

Thermal

R_SENSE-1

Current

Sense

Output

nSCS

SDI

SPI

nSLEEP

Open Load

R_SENSE-2

SDO

SCLK

GND

PPAD

Figure 9. Software Device Block Diagram

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7.3 Feature Description

Table 1 lists the recommended external components for the device.

Table 1. External Components

COMPONENT

C_VM1

PIN 1

PIN 2

GND

RECOMMENDED

0.1-µF ceramic capacitor rated for VM

Bulk capacitor rated for VM

C_VM2

GND

C_VCP

VCP

16-V, 1-µF ceramic capacitor

C_FLY

CPH

CPL

47-nF capacitor rated for VM

C_DVDD

DVDD

VCC⁽¹⁾

MODE

IPROPI1

IPROPI2

GND

6.3-V, 1-µF ceramic capacitor

R_nFAULT

R_MODE

R_SENSE-1

R_SENSE-2

nFAULT

GND or DVDD

GND

≥ 10-kΩ pullup resistor

Device hardware interface

Resistors to convert mirrored current into a voltage

GND

(1) VCC is not a pin on the device, but a VCC supply-voltage pullup is required for the open-drain output nFAULT.

7.3.1 Bridge Control

The device output has four N-channel MOSFETs configured in a H-bridge. The driver can be controlled using a

PH/EN, PWM, or independent half-bridge input mode. Table 2 lists the control mode configurations.

Table 2. Control Mode Configuration

HARDWARE DEVICE

MODE PIN

SPI DEVICE

MODE REGISTER

CONTROL MODE

00b

01b (default)

10b

PH/EN

PWM

200 kΩ ± 5% to GND

Not applicable

Independent half bridge

Input disabled, bridge Hi-Z

11b

In the hardware version of the device, the MODE pin determines the control interface and latches on power-up or

when exiting sleep mode. During the device power-up sequence, the DVDD pin is enabled first, and then the

MODE pin latches. Tying the MODE pin directly to ground sets the mode to phase and enable. Tying the MODE

pin to the DVDD pin, or an external 5 V rail, sets the mode to PWM. Connecting the MODE pin to ground with a

200 kΩ ± 5% resistor sets the mode to independent half-bridge where the two half-bridges can be independently

controlled by their respective input (INx) pins. Table 3 lists the different MODE pin settings.

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Table 3. DRV8873H MODE Pin Settings

CONNECTION

MODE

CIRCUIT

MODE

Connect to GND

Phase and Enable

MODE

200 kΩ ± 5% to GND

Independent half-bridge

R_MODE

DVDD

MODE

Connect to DVDD

PWM

In the SPI version of the device, the mode setting can be changed by writing to the MODE register in the IC1

control register because this device version has no dedicated MODE pin. The device mode gets latched when

the DISABLE signal transitions from high to low.

7.3.1.1 Control Modes

The device output consists of four N-channel MOSFETs that are designed to drive high current. The MOSFETs

are controlled by two logic inputs, EN/IN1 and PH/IN2, in three different input modes to support various

commutation and control methods, as shown in the logic tables (Table 4, Table 5, and Table 6). In the

Independent PWM mode, the fault handling is performed independently for each half bridge. For example, if an

overcurrent condition (OCP) is detected in half-bridge 1, only the half-bridge 1 output (OUT1) is disabled and

half-bridge 2 continues to operate based on the IN2 input.

Table 4. PH/EN Mode Truth Table

nSLEEP

DISABLE

EN/IN1

PH/IN2

OUT1

Hi-Z

OUT2

Hi-Z

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Table 5. PWM Mode Truth Table

nSLEEP

DISABLE

EN/IN1

PH/IN2

OUT1

Hi-Z

OUT2

Hi-Z

Table 6. Independent Mode Truth Table

nSLEEP

DISABLE

EN/IN1

PH/IN2

OUT1

Hi-Z

OUT2

Hi-Z

The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM)

for variable motor speed. When using PWM mode (MODE = 1), switching between driving and braking typically

is best. For example, to drive a motor forward with 50% of its maximum revolutions per minute (RPM), the IN1

pin is high and the IN2 pin is low during the driving period. During the other period in this example, the IN1 pin is

high and the IN2 pin is high.

SH2

SH1

Forward drive

High-side recirculation (brake)

Reverse drive

Figure 10. Half-Bridge Current Paths

In the Independent PWM mode, to independently put the outputs of the half bridge in the high-impedance (Hi-Z)

state, the OUT1_DIS or OUT2_DIS bit in the IC3 register must be set to 1b. Writing a logic 1 to the OUT1_DIS

bit disables the OUT1 output. Writing a logic 1 to the OUT2_DIS bit disables the OUT2 output. The default value

in these registers is 0b. The option to independently set the outputs of the half bridge in the Hi-Z state is not

available for the hardware version of the device.

7.3.1.2 Half-Bridge Operation

The device can be used to drive two solenoids or unidirectional brushed DC-motor loads instead of a brushed-

DC motor in full H-bridge configuration. Independent half-bridge control is preferred for operation in this mode;

however, using the PH/EN or PWM modes is not restricted if the correct driving and braking states can be

achieved.

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VCP

0.1 µF

bulk

OUT1

Predriver

BDC

VCP

OUT2

SRC

Predriver

BDC

Figure 11. Independent Half bridge Mode Driving Two Low-Side Loads

TI does not recommend tying the OUT1 and OUT2 pins together and drive a load. The half bridges may be out

of synchronization in this configuration and any mismatch in the input commands can momentarily result in shoot

through condition. This mismatch can be mitigated by adding an inductor in-line with the outputs.

If loads are connected between the OUTx and VM pins, the device can draw more current than specified in the

Electrical Characteristics table. To avoid this condition, TI recommends connecting loads in the configuration

shown in Figure 11.

Depending on how the loads are connected on the outputs pin, some of the features offered by the device could

have reduced functionality. For example, having a load between the OUTx and GND pins, as shown in

Figure 11, results in false trips of the open-load diagnosis in active-mode (OLA). Having a load tied between the

OUTx and VM pins restricts the use of internal current regulation because no means of measuring current

flowing through the load with the current mirror block is available. Table 7 lists these use cases.

Table 7. Control Mode Configuration

LOAD CONNECTIONS

FUNCTIONALITY

CURRENT REGULATION (I_TRIP)

NODE 1

OUTx

NODE 2

GND

OLA

Not Available

Operational

OUTx

Not Available

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7.3.1.3 Internal Current Sense and Current Regulation

The IPROPI pin outputs an analog current that is proportional to the current flowing in the H-bridge. The output

current is typically 1/1100 of the current in both high-side FETs. The IPROPI pin is derived from the current

through either of the high-side FETs. Because of this, the IPROPI pin does not represent the half bridge current

when operating in a fast decay mode or low-side slow decay mode. The IPROPI pin represents the H-bridge

current under forward drive, reverse drive, and high-side slow decay. The IPROPI output is delayed by

approximately 2 µs for the fastest slew-rate setting (43.2 V/µs) after the high-side FET is switched on.

HS1

SENSE_FET

1/1100 scaled

HS1

PWR_FET

OUT1

Current Sense

IPROPI1

and

Current Regulation

R_SENSE-1

HS2

SENSE_FET

1/1100 scaled

HS2

PWR_FET

OUT2

Current Sense

IPROPI2

and

Current Regulation

R_SENSE-2

Figure 12. Current-Sense Block Diagram

The selection of the external resistor should be such that the voltage on the IPROPI pin is less than 5 V.

Therefore the resistor must be sized less than this value based on Equation 1. The range of current that can be

monitored is from 100 mA to 10 A assuming the selected external resistor meets the calculated value from

Equation 1. If the current exceeds 10 A, the device could reach overcurrent protection (OCP) or overtemperature

shutdown (TSD). If OCP occurs, the device disables the internal MOSFETs and protects itself (for the hardware

version of the device) or based on the OCP_MODE setting (for the SPI version of the device). For guidelines on

selecting a sense resistor, see the Sense Resistor section.

R_(SENSE)= k × 5 V / I_O

where

•

k is the current mirror scaling factor, which is typically 1100.

I_Ois the maximum drive current to be monitored.

(1)

NOTE

Texas Instruments recommends the load current not exceed 8 A during normal operation.

If slew rate setting of 2.6 V/µs (SR = 111b) is used when the load current is about 8 A,

choose TOFF to be either 40 µs or 60 µs.

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The SPI version of the device limits the output current based on the trip level set in the SPI registers. In the

hardware version of the device, the current trip limit is set to 6.5 A. The current regulation feature is enabled by

default on both the outputs (OUT1 and OUT2). To disable current regulation in the hardware version of the

device, the nITRIP pin must be connected to DVDD. To disable current regulation in the SPI version of the

device, the DIS_ITRIP bits in the IC4 Control register must be written to. The bit settings are:

•

01b to disable current regulation only on the OUT1 pin

10b to disable current regulation only on the OUT2 pin

11b to disable current regulation on both the OUT1 and OUT2 pins

Table 8. Control Regulation Threshold

PARAMETER

ITRIP_LVL BIT

ITRIP_LVL = 00b

ITRIP_LVL = 01b

ITRIP_LVL = 10b

ITRIP_LVL = 11b

MIN

3.4

4.6

5.5

TYP

MAX

4.6

6.2

7.5

UNIT

5.4

6.5

I_TRIP

Current limit threshold

When the I_TRIPcurrent has been reached, the device enforces slow current decay by enabling both the high-side

FETs for a time of t_OFF. In the hardware version of the device, the t_OFFtime is 40 µs. The t_OFFtime is selectable

through SPI in the SPI version of the device, as shown in Table 9. The default setting is 01b (t_OFF= 40 µs).

Table 9. PWM Off Time Settings

PARAMETER

TOFF BIT

TOFF = 00b

TOFF = 01b

TOFF = 10b

TOFF = 11b

t_OFFDURATION

UNIT

µs

t_OFF

PWM off time

µs

I_TRIP

t_BLANK

Drive

t_DRIVE

Brake or Slow Decay

t_OFF

Drive

t_DRIVE

Brake or Slow Decay

t_OFF

Figure 13. Current Regulation Time Periods

When the t_OFFtime has elapsed and the current level falls below the current regulation (I_TRIP) level, the output is

re-enabled according to the inputs. If, after the t_OFFtime has elapsed the current is still higher than the I_TRIPlevel,

the device enforces another t_OFFtime period of the same duration.

The drive time (t_DRIVE) occurs until another ITRIP event is reached and depends heavily on the VM voltage, the

back-EMF of the motor, and the inductance of the motor. During the t_DRIVEtime, the current-sense regulator does

not enforce the ITRIP limit until the t_BLANKtime has elapsed. While in current regulation, the inputs can be toggled

to drive the load in the opposite direction to decay the current faster. For example, if the load was in forward

drive prior to entering current regulation it can only go into reverse drive when the driver enforces current

regulation.

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The IPROPI1 pin represents the current flowing through the HS1 MOSFET of half-bridge 1. The IPROPI2 pin

represents the current flowing through the HS2 MOSFET of half-bridge 2. To measure current with one sense

resistor, the IPROPI1 and IPROPI2 pins must be connected together with the R_SENSEresistor as shown in

Figure 14. In this configuration, the current-sense output is proportional to the sum of the currents flowing

through the both high-side FETs.

IPROPI1

Current-Sense

R_SENSE-1

Output

IPROPI2

GND

PPAD

Figure 14. Current Sense Output

7.3.1.4 Slew-Rate Control

The rise and fall times (t_rand t_f) of the outputs can be adjusted on the hardware version of the device by

changing the value of an external resistor connected from the SR pin to ground. On the SPI version of the

device, the slew rate can be adjusted through the SPI. The output slew rate is adjusted internally to the device by

controlling the ramp rate of the driven FET gate. The voltage or resistance on the SR pin sets the output rise and

fall times in the hardware version of the device.

Table 10. DRV8873H Slew Rate (SR) Pin Connections

CONNECTION

CIRCUIT

Connect to GND

53.2 V/µs

22 kΩ ± 5% to GND

34 V/µs

R_SR

68 kΩ ± 5% to GND

18.3 V/µs

R_SR

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Table 10. DRV8873H Slew Rate (SR) Pin Connections (continued)

CONNECTION

CIRCUIT

> 2 MΩ to GND (Hi-Z)

13 V/µs

DVDD

51 kΩ ± 5% to DVDD

7.9 V/µs

DVDD

Connect to DVDD

2.6 V/µs

Figure 15 shows the internal circuit block for the SR pin.

SLEW RATE

53.2 V/µs

V_REF

34 V/µs

DVDD

18.3 V/µs

13 V/µs

V_REF

7.9 V/µs

2.6 V/µs

V_REF

Figure 15. SR Block Diagram

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Table 11 lists the settings in the SPI register that set the output rise and fall times in the SPI version of the

device.

Table 11. DRV8873S Slew Rate Settings

RISE TIME (V/µs)

FALL TIME (V/µs)

000b

001b

010b

011b

100b

101b

110b

111b

53.2

18.3

10.8

7.9

10.8

7.9

5.3

2.6

The typical voltage on the SR pin is 3 V and is driven internally. Changing the resistor value on the SR pin

changes the slew-rate setting from approximately 2.6 V/µs to 53.2 V/µs. The recommended values for the

external resistor are shown in the Slew Rate section. If the SR pin is grounded then the slew rate is 53.2 V/µs.

Leaving the SR pin as a no-connect pin sets the slew rate to 13 V/µs. Tying it to the DVDD pin sets the slew rate

to 2.6 V/µs.

7.3.1.5 Dead Time

The dead time (t_(DEAD)) is measured as the time when the OUTx pin is in the Hi-Z state between turning off one

of the half bridge MOSFETs and turning on the other. For example, the output is in the Hi-Z state between

turning off the high-side MOSFET and turning on the low-side MOSFET, or turning on the high-side MOSFET

and turning off the low-side MOSFET.

IN1

IN2

OUT1

t_PD

t_(DEAD)

t_F

t_PD

t_(DEAD)

t_R

OUT2

t_PD

t_(DEAD)

t_R

t_PD

t_(DEAD)

t_F

Figure 16. Propagation Delay Time

If the output pin is measured during the t_DEADtime the voltage depends on the direction of the current. If the

current is leaving the pin, the voltage is a diode drop below ground. If the current is entering the pin, the voltage

is a diode drop above VM. The diode drop is associated with the body diode of the high-side or the low-side FET.

The dead time is dependent on the slew-rate setting because a portion of the FET gate ramp includes the

observable dead time.

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7.3.1.6 Propagation Delay

The propagation delay time (t_PD) is measured as the time between an input edge to an output change. This time

comprises two parts: an input deglitcher and output slewing delay. The input deglitcher prevents noise on the

input pins from affecting the output state. The adjustable slew rate also contributes to the propagation delay time.

For the fastest slew-rate setting, the t_PDtime is typically 1.5 µs, and for the slowest slew-rate setting, the t_PDtime

is typically 4.5 µs. For the output to change state during normal operation, one FET must first be turned off.

7.3.1.7 nFAULT Pin

The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. When a fault is

detected, the nFAULT line is logic low. For a 3.3-V pullup the nFAULT pin can be tied to the DVDD pin with a

resistor (see the Application and Implementation section). For a 5-V pullup, an external 5-V supply must be used.

Output

nFAULT

Figure 17. nFAULT Pin

During the device power-up sequence, or when exiting sleep mode, the nFAULT pin is held low until the digital

core is alive and functional. This low level signal on the nFAULT line does not represent a fault condition. The

signal can be used by the external MCU to determine when the digital core of the device is ready; however, this

does not mean that the device is ready to accept input commands via the INx pins.

7.3.1.8 nSLEEP as SDO Reference

The nSLEEP pin manages the state of the device. The device goes into sleep mode with a logic-low signal, and

comes out of sleep mode when the nSLEEP pin goes high. The signal level when the nSLEEP pin goes high

determines the logic level on the SDO output in the SPI version of the device. A 3.3-V signal on the nSLEEP pin

provides a 3.3-V output on the SDO output. A 5-V signal on the nSLEEP pin provides a 5-V output on the SDO

pin. If the sleep feature is not required, the nSLEEP pin can be connected to the MCU power supply. In that

case, when the MCU is powered-up, the motor driver device is also be powered-up.

DVDD

nSLEEP

Digital

Core

400 kꢀ

100 kꢀ

nSCS

Figure 18. nSCS and nSLEEP Circuit

In the SPI version of the device, if the nSLEEP reset pulse is used to clear faults, the SDO voltage reference is

not available for the duration of the nSLEEP reset pulse. No data can be transmitted on the SDO line for the

duration when the nSLEEP pin is held low. Therefore, TI recommends using the CLR_FLT bit in the IC3 control

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7.3.2 Motor Driver Protection Circuits

The device is fully protected against VM undervoltage conditions, charge-pump undervoltage conditions,

overcurrent events, and overtemperature events.

7.3.2.1 VM Undervoltage Lockout (UVLO)

If at any time the voltage on the VM pin falls below the UVLO-threshold voltage, V_(UVLO), for the voltage supply,

all the outputs (OUTx) are disabled, and the nFAULT pin is driven low. The charge pump is disabled in this

condition. The FAULT and UVLO bits are latched high in the SPI registers. Normal operation resumes (motor-

driver operation and nFAULT released) when the VM undervoltage condition is removed. The UVLO bit remains

set until it is cleared through the CLR_FLT bit or an nSLEEP reset pulse.

NOTE

During the power-up sequence VM must exceed V_(UVLO)recovery max limit in order to

power-up and function properly. After a successful power-up sequence, the device can

operate down to the V_(UVLO)report limit before going into the undervoltage lockout

condition.

7.3.2.2 VCP Undervoltage Lockout (CPUV)

If at any time the voltage on the VCP pin falls below the V_VCP(UV)voltage for the charge pump, all the outputs

(OUTx) are disabled, and the nFAULT pin is driven low. The charge pump remains active during this condition.

The FAULT and CPUV bits are latched high in the SPI registers. Normal operation resumes (motor-driver

operation and nFAULT released) when the VCP undervoltage condition is removed. The CPUV bit remains set

until it is cleared through the CLR_FLT bit or an nSLEEP reset pulse. This protection feature can be disabled by

setting the DIS_CPUV bit high.

7.3.2.3 Overcurrent Protection (OCP)

If the current in any FET exceeds the I_(ocp)limits for longer than the t_(OCP)time, all FETs in the half bridge are

disabled and the nFAULT pin is driven low. The charge pump remains active during this condition. The

overcurrent protection can operate in four different modes: latched shutdown, automatic retry, report only, and

disabled. In the independent PWM mode (MODE = 10b or MODE pin to ground with a 200-kΩ ± 5% resistor) the

fault handling is performed independently for each half-bridge based on the OCP mode selected. This protection

scheme protects the outputs from shorts to battery and shorts to ground.

7.3.2.3.1 Latched Shutdown (OCP_MODE = 00b)

In this mode, after an OCP event, all the outputs (OUTx) are disabled and the nFAULT pin are driven low. The

FAULT, OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal operation

resumes (motor-driver operation and nFAULT released) when the OCP condition is removed and a clear faults

command has been issued either through the CLR_FLT bit or an nSLEEP reset pulse. This mode is the default

mode for an OCP event for both the hardware version and SPI version of the device.

7.3.2.3.2 Automatic Retry (OCP_MODE = 01b)

In this mode, after an OCP event all the outputs (OUTx) are disabled and the nFAULT pin is driven low. The

FAULT, OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal operation

resumes automatically (motor-driver operation and nFAULT released) after the t_(RETRY)time has elapsed and the

fault condition is removed.

7.3.2.3.3 Report Only (OCP_MODE = 10b)

In this mode, no protective action is performed when an overcurrent event occurs. The overcurrent event is

reported by driving the nFAULT pin low and latching the FAULT, OCP, and corresponding MOSFET OCP bits

high in the SPI registers. The motor driver continues to operate. The external controller acts appropriately to

manage the overcurrent condition. The reporting is cleared (nFAULT released) when the OCP condition is

removed and a clear faults command has been issued either through the CLR_FLT bit or an nSLEEP reset

pulse.

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7.3.2.3.4 Disabled (OCP_MODE = 11b)

In this mode, no protective or reporting action is performed when an overcurrent event occurs. The device

continues to drive the load based on the input signals.

7.3.2.4 Open-Load Detection (OLD)

If the motor is disconnected from the device, an open-load condition is detected and the nFAULT pin is latched

low until a clear faults command is issued by the MCU either through the CLR_FLT bit or an nSLEEP reset

pulse. The fault also clears when the device is power cycled or comes out of sleep mode. The OLD test is

designed for applications that have capacitance less than 15 nF when the OL_DLY bit set to 0b and for less than

60 nF when the OL_DLY bit is set to 1b on the OUTx pins. This setting is equivalent to measuring the resistance

values listed in Table 12.

Table 12. Resistance for Open Load Detection

NODE 1

OUT1

OUTx

NODE 2

OUT2

RESISTANCE

2 kΩ

COMMENTS

12 kΩ

V_VM= 13.5 V

OUTx

GND

3 kΩ

Open load detection works in both standby mode (OLP) and active mode (OLA). OLP detects the presence of

the motor prior to commutating the motor. OLA detects the motor disconnection from the driver during

commutation.

7.3.2.4.1 Open-Load Detection in Passive Mode (OLP)

The open-load passive diagnostic (OLP) is different for the hardware and SPI version of the device. The OLP

test is available in all three modes of operation (PN/EN, PWM, and independent half-bridge). When the open-

load test is running, the internal power MOSFETs are disabled.

For the hardware version of the device, the OLP test is performed at power-up or after exiting sleep mode if the

nOL pin is left as a no connect pin (or tied to GND). If the nOL pin is tied to the DVDD pin (or an external 5-V

rail), the OLP test is not performed by the device.

For the SPI version of the device, the OLP test is performed when commanded. The following sequence shows

how to perform the OLP test directly after the device powers up:

1. Power up the device (DISABLE pin high).

2. Select the mode through SPI.

3. Wait for the t_(DISABLE)time to expire.

4. Write 1b to the EN_OL bit in the IC1 register.

5. Perform the OLP test.

–

If an open load (OL) is detected, the nFAULT pin is driven low, the FAULT and OLx bits are latched high.

When the OL condition is removed, a clear faults command must be issued by the MCU either through

the CLR_FLT bit or an nSLEEP reset pulse which resets the OLx register bit.

–

If an OL condition is not detected, the EN_OL bits return to the default setting (0b) after the t_d(OL)time

expires.

6. Set the DISABLE pin low so that the device drives the motor or load based on the input signals.

If an open-load diagnostic is performed at any other time, the following sequence must be followed:

1. Set the pin DISABLE high (to disable the half bridge outputs).

2. Wait for the t_(DISABLE)time to expire.

3. Write 1b to the EN_OL bit in the IC1 register.

4. Perform the OLP test.

–

If an OL condition is detected, the nFAULT pin is driven low, and the FAULT and OLx bits are latched

high. When the OL condition is removed, a clear faults command must be issued by the MCU either

through the CLR_FLT bit or an nSLEEP reset pulse which resets the OLx register bits.

–

If an OL condition is not detected, the EN_OL bits return to the default setting (0b) after the t_d(OL)time

expires.

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5. Set the DISABLE pin low so that the device drives the motor or load based on the input signals.

DVDD

OL1_PU

output

4 V

OUT1

1 V

OL1_PD

output

DVDD

Digital

Core

OL2_PU

output

4 V

OUT2

SRC

1 V

OL2_PD

output

Figure 19. Open-Load Detection Circuit

The EN_OL register maintains the written command until the diagnostic is complete. The signal on the DISABLE

pin must remain high for the entire duration of the test. While the OLP test is running, if the DISABLE pin goes

low, the OLP test is aborted to resume normal operation and no fault is reported. The OLP test is not performed

if the motor is energized.

The OLD test checks for a high-impedance connection on the OUTx pins. The diagnostic runs in two steps. First

the pullup current source is enabled. If a load is connected, the current passes through the pullup resistor and

the OLx_PU comparator output remains low. If an OL condition exists, the current through the pullup resistor

goes to 0 A and the OLx_PU comparator trips high. Second the pulldown current source is enabled. In the same

way, the OLx_PD comparator output either remains low to indicate that a load is connected, or trips high to

indicate an OL condition.

If both the OLx_PU and OLx_PD comparators report an OL condition, the OLx bit in the SPI register latches high

and the nFAULT line goes low to indicate an OL fault. When the OL condition is removed, a clear faults

command must be issued by the MCU either through the CLR_FLT bit or an nSLEEP reset pulse which resets

the OL1 and OL2 register bits. The charge pump remains active during this fault condition.

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7.3.2.4.2 Open-Load Detection in Active Mode (OLA)

Open load in active mode is detected when the OUT1 and OUT2 voltages do not exhibit overshoot greater than

the V_OLAover VM between the time the low-side FET is switched off and the high-side FET is switched on during

an output PWM cycle, as shown in Figure 20. An open load is not detected if the energy stored in the inductor is

high enough to cause an overshoot greater than the V_OLAover VM caused by the flyback current flowing through

the body diode of the high-side FET. The OLA diagnostic is disabled by default and can be enabled by writing a

1b to the EN_OLA bit in IC4 control register.

SH2

SH1

Detects OLD No OLD detected

if the diode V_F

drop < V_OLA

if the diode V_F

drop > V_OLA

Figure 20. Open-Load Active Mode Circuit

In PH/EN and PWM mode, the motor current decays by high-side recirculation. In independent PWM mode, the

motor can enter the brake state either by high-side or low-side recirculation. If the motor enters the brake state

using low-side recirculation, the diode V_Fvoltage of high-side FET is less than the V_OLAvoltage which flags an

open load fault even though the load is connected across the OUT1 and OUT2 pins. In this case, the OLA mode

should not be used. If high-side current recirculation is done with independent PWM mode, the OLA mode

functions properly.

NOTE

The OLA mode is functional only when high-side recirculation of the motor current occurs.

Depending on the operation conditions and external circuitry, such as the output

capacitors, an open load condition could be indicated even though the load is present.

This case might occur, for example, during a direction change or for small load currents

with respectively small PWM duty cycles. Therefore, TI recommends evaluating the open

load diagnosis only in known, suitable operating conditions and to ignore it otherwise.

To avoid inadvertently triggering the open load diagnosis, a failure counter is implemented. Three consecutive

occurrences of the internal open-load signal must occur, essentially three consecutive PWM pulses without

freewheeling detected, before an open load condition is reported by the nFAULT pin and in the SPI register.

In the hardware version of the device, OLA mode is active when the nOL pin if left as a no-connect pin or tied to

ground. If low-side current recirculation is done with independent PWM control, an open load condition is

detected even though the load is connected. To avoid this false trip, the OLD must be disabled by taking the nOL

pin high; however, both OLA and OLP diagnostics will be disabled.

7.3.2.5 Thermal Shutdown (TSD)

If the die temperature exceeds the thermal shutdown limit, the half bridge are disabled, and the nFAULT pin is

driven low. The charge pump remains active during this condition. In addition, the FAULT bit and TSD bit are

latched high. This protection feature cannot be disabled. The overtemperature protection can operate in two

different modes: latched shutdown and automatic recovery.

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7.3.2.5.1 Latched Shutdown (TSD_MODE = 0b)

In this mode, after a TSD event all the outputs (OUTx) are disabled and the nFAULT pin is driven low. The

FAULT and TSD bits are latched high in the SPI register. Normal operation resumes (motor-driver operation and

the nFAULT line released) when the TSD condition is removed and a clear faults command has been issued

either through the CLR_FLT bit or an nSLEEP reset pulse. This mode is the default mode for a TSD event in the

SPI version of the device.

7.3.2.5.2 Automatic Recovery (TSD_MODE = 1b)

In this mode, after a TSD event all the outputs (OUTx) are disabled and the nFAULT pin is driven low. The

FAULT and TSD bits are latched high in the SPI register. Normal operation resumes (motor-driver operation and

the nFAULT line released) when the junction temperature falls below the overtemperature threshold limit minus

the hysteresis (T_TSD– T_HYS). The TSD bit remains latched high indicating that a thermal event occurred until a

clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse. This mode is the

default mode for a TSD event in the hardware version of the device.

7.3.2.6 Thermal Warning (OTW)

If the die temperature exceeds the trip point of the thermal warning (T_OTW) the OTW bit is set in the registers of

SPI devices. The device performs no additional action and continues to function. When the die temperature falls

below the hysteresis point of the thermal warning, the OTW bit clears automatically. The OTW bit can also be

configured to report on the nFAULT pin, and set the FAULT bit in the SPI version of the device, by setting the

OTW_REP bit to 1b through the SPI registers. The charge pump remains active during this condition.

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Table 13. Fault Response

FAULT

CONDITION

CONFIGURATION

REPORT

HALF BRIDGE

LOGIC

RECOVERY

V_VM< V_(UVLO)

(maximum 4.45 V)

Automatic: V_VM> V_(UVLO)

(maximum 4.55 V)

VM undervoltage (UVLO)

—

nFAULT

Hi-Z

Reset

Automatic: V_VCP> V_VCP(UV)

(typical V_VM+ 2.25 V)

DIS_CPUV = 0b

nFAULT

Hi-Z

Active

Charge pump undervoltage

(CPUV)

V_VCP< V_VCP(UV)

(typical V_VM+ 2.25 V)

DIS_CPUV = 1b

OCP_MODE = 00b

OCP_MODE = 01b

OCP_MODE = 10b

OCP_MODE = 11b

EN_OLP = 1b

none

Active

Hi-Z

Active

No action

Latched: CLR_FLT/nSLEEP

Retry: t_(RETRY)

nFAULT

none

Hi-Z

I_O> I_(OCP)

(minimum 10 A)

Overcurrent (OCP)

Active

Hi-Z

No action

nFAULT

none

Latched: CLR_FLT/nSLEEP

No action

Open load (OLD)

No load detected

I_O> ITRIP_LVL

EN_OLA = 1b

ITRIP_REP = 0b

ITRIP_REP = 1b

TSD_MODE = 0b

Current regulation (ITRIPx)

nFAULT

No action

Latched: CLR_FLT/nSLEEP

T_J> T_TSD

(minimum 165°C)

Automatic:

T_J> T_TSD– T_HYS

(T_HYStypical 20°C)

Thermal shutdown (TSD)

Thermal Warning (OTW)

TSD_MODE = 1b

nFAULT

Hi-Z

Active

OTW_REP = 0b

OTW_REP = 1b

none

Active

No action

T_J> T_OTW

(minimum 140°C)

nFAULT

Automatic: T_J< T_OTW– T_HYS

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7.3.3 Hardware Interface

The hardware-interface device option lets the device be configured without a SPI, however not all of the

functionality is configurable. The following configuration settings are fixed for the hardware interface device

option:

•

CPUV is enabled

OCP_MODE is latched shutdown

TSD_MODE is automatic recovery

OL_DLY is 300 µs

ITRIP level is 6.5-A if current regulation is enabled by the nITRIP pin

OLA is activated when the open load diagnostic is enabled by the nOL pin

No option to independently set the outputs (OUTx) to the Hi-Z state

7.3.3.1 MODE (Tri-Level Input)

The MODE pin of the hardware version of the device determines the control interface and latches on power-up or

when exiting sleep mode. Table 14 lists the different control interfaces that can be set with the MODE pin.

Table 14. DRV8873H MODE Settings

MODE

CONTROL MODE

PH/EN

PWM

Hi-Z (200 kΩ ± 5% to GND)

Independent half bridge

When the MODE pin is latched on power-up or when exiting sleep mode; any additional changes to the signal at

the MODE pin are ignored by the device. To change the mode settings, a power cycle or sleep reset must be

performed on the device. To use the device in PWM mode, tie the MODE pin to either the DVDD pin or an

external 5-V rail. To use the device in independent half-bridge mode, the MODE pin must be connected to with a

200-kΩ ± 5% resistor (or left as a no connect). Tying the MODE pin to the GND pin puts the device in phase and

enable (PH/EN) mode.

7.3.3.2 Slew Rate

The rise and fall times of the outputs can be selected based on the configuration listed in Table 15 for the

hardware version of the device.

Table 15. Slew Rate Settings in H/W Device

SR PIN CONNECTION

Connect to GND

RISE TIME (V/µs)

FALL TIME (V/µs)

53.2

22 kΩ ± 5% to GND

68 kΩ ± 5% to GND

> 2MΩ to GND (Hi-Z)

51 kΩ ± 5% to DVDD

Connect to DVDD

18.3

7.9

2.6

7.9

2.6

7.4 Device Functional Modes

7.4.1 Motor Driver Functional Modes

7.4.1.1 Sleep Mode (nSLEEP = 0)

The nSLEEP pin sets the state of the device. When the nSLEEP pin is low, the device goes to a low-power sleep

mode. In sleep mode, all the internal MOSFETs are disabled, the charge pump is disabled, and the SPI is

disabled. The t_(SLEEP)time must elapse after a falling edge on the nSLEEP pin before the device enters sleep

mode. The device goes from sleep mode automatically if the nSLEEP pin is brought high. The t_(WAKE)time must

elapse before the device is ready for inputs.

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Device Functional Modes (continued)

7.4.1.2 Disable Mode (nSLEEP = 1, DISABLE = 1)

The DISABLE pin is used to enable or disable the half bridge in the device. When the DISABLE pin is high, the

output drivers are disabled in the Hi-Z state. In this mode, the open-load diagnostic can be performed for the SPI

version of the device because the SPI remains active.

7.4.1.3 Operating Mode (nSLEEP = 1, DISABLE = 0)

When the nSLEEP pin is high, the DISABLE pin is low, and VM > V_(UVLO), the device enters the active mode. The

t_(WAKE)time must elapse before the device is ready for inputs. In this mode, the charge pump and low-side gate

regulator are enabled.

7.4.1.4 nSLEEP Reset Pulse

In addition to the CLR_FLT bit in the SPI register, a latched fault can be cleared through a quick nSLEEP pulse.

This pulse must be greater than the nSLEEP deglitch time of 5 µs and shorter than 20 µs. If nSLEEP is low for

longer than 20 µs, the faults are cleared and the device may or may not shutdown, as shown in the timing

diagram (see Figure 21). This reset pulse resets any SPI faults and does not affect the status of the charge

pump or other functional blocks.

nSLEEP

50 µs

5 µs

20 µs

30 µs

60 µs

No Action. nSLEEP

low pulse is too short

(deglitch)

All faults cleared, device stays active

All faults cleared, device may or may not shutdown

Device shutdowns down (goes into sleep mode, faults cleared by default)

Device shutdowns down (sleep mode)

Figure 21. nSLEEP Reset Pulse

7.5 Programming

7.5.1 Serial Peripheral Interface (SPI) Communication

The SPI version of the device has full duplex, 4-wire synchronous communication. This section describes the SPI

protocol, the command structure, and the control and status registers. The device can be connected with the

MCU in the following configurations:

•

One slave device

Multiple slave devices in parallel connection

Multiple slave devices in series (daisy chain) connection

7.5.1.1 SPI Format

The SDI input data word is 16 bits long and consists of the following format:

•

1 read or write bit, W (bit 14)

5 address bits, A (bits 13 through 9)

8 data bits, D (bits 7 through 0)

The SDO output-data word is 16 bits long and the first 8 bits make up the Status Register (S1). The Report word

(R1) is the content of the register being accessed.

For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being

written to.

For a read command (W0 = 1), the response word is the data currently in the register being read

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Programming (continued)

Table 16. SDI Input Data Word Format

R/W

ADDRESS

DATA

B15

B14

B13

B12

B11

B10

Table 17. SDO Output Data Word Format

STATUS

REPORT

B15

B14

B13

B12

B11

B10

OTW UVLO CPUV OCP

TSD

OLD

7.5.1.2 SPI for a Single Slave Device

The SPI is used to set device configurations, operating parameters, and read out diagnostic information. The

device SPI operates in slave mode. The SPI input-data (SDI) word consists of a 16-bit word, with 8 bits

command and 8 bits of data. The SPI output data (SDO) word consists of 8 bits of status register with fault status

indication and 8 bits of register data. Figure 22 shows the data sequence between the MCU and the SPI slave

driver.

nSCS

SDI

SDO

Figure 22. SPI Transaction Between MCU and SPI version of the device

A valid frame must meet the following conditions:

•

The SCLK pin must be low when the nSCS pin goes low and when the nSCS pin goes high.

The nSCS pin should be taken high for at least 500 ns between frames.

When the nSCS pin is asserted high, any signals at the SCLK and SDI pins are ignored, and the SDO pin is

in the high-impedance state (Hi-Z).

•

Full 16 SCLK cycles must occur.

Data is captured on the falling edge of the clock and data is driven on the rising edge of the clock.

The most-significant bit (MSB) is shifted in and out first.

If the data word sent to SDI pin is less than 16 bits or more than 16 bits, a frame error occurs and the data

word is ignored.

•

For a write command, the existing data in the register being written to is shifted out on the SDO pin following

the 8-bit command data.

7.5.1.3 SPI for Multiple Slave Devices in Parallel Configuration

Multiple devices can be connected in parallel as shown in Figure 23. In this configuration, all the slave devices

can share the same SDI, SDO, and CLK lines from the micro-controller, but has dedicated chip-select pin (CSx)

for each device from the micro-controller.

The micro-controller activates the SPI of a given device via that device's chip-select input, the other devices

remain inactive for SPI transactions. This configuration helps reduce micro-controller resources for SPI

transactions if multiple slave devices are connected to the same micro-controller.

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Microcontroller

DRV8873_1

SPI

DRV8873_2

SPI

DRV8873_3

SPI

SDI1

SDO1

SDI2

SDO2

SDI3

SDO3

M-CS1

M-CS2

M-CS3

M-CLK

M-SDO

M-SDI

Figure 23. Three DRV8873S Devices Connected in Parallel Configuration

7.5.1.4 SPI for Multiple Slave Devices in Daisy Chain Configuration

The device can be connected in a daisy chain configuration to keep GPIO ports available when multiple devices

are communicating to the same MCU. Figure 24 shows the topology when three devices are connected in series.

Slave Device

(1)

Slave Device

(3)

Master

Device

Slave Device

(2)

SDO1 / SDI2

SDI1

SDO1 / SDI2

SDO3

M-SDO

M-nSCS

M-SCLK

M-SDI

Figure 24. Three DRV8873S Devices Connected in Daisy Chain

The first device in the chain receives data from the MCU in the following format for 3-device configuration: 2

bytes of header (HDRx) followed by 3 bytes of address (Ax) followed by 3 bytes of data (Dx).

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nSCS

HDR1

HDR2

HDR1

SDI1

HDR2

SDO1 / SDI2

HDR1

HDR2

HDR1

SDO2 / SDI3

SDO3

HDR2

All Address bytes

reach destination

All Data bytes

reach destination

Status response here

Reads executed here

Writes executed here

Figure 25. SPI Frame With Three DRV8873S Devices

After the data has been transmitted through the chain, the MCU receives the data string in the following format

for 3-device configuration: 3 bytes of status (Sx) followed by 2 bytes of header followed by 3 bytes of report (Rx).

nSCS

HDR1

HDR2

SDI

HDR1

HDR2

SDO

Figure 26. SPI Data Sequence for Three DRV8873S Devices

The header bytes contain information of the number of devices connected in the chain, and a global clear fault

command that will clear the fault registers of all the devices on the rising edge of the chip select (nSCS) signal.

Header values N5 through N0 are 6 bits dedicated to show the number of devices in the chain. Up to 63 devices

can be connected in series for each daisy chain connection.

The 5 LSBs of the HDR2 register are don’t care bits that can be used by the MCU to determine integrity of the

daisy chain connection. Header bytes must start with 1 and 0 for the two MSBs.

HDR 1

N4 N3

HDR 2

CLR

Don‘t care

No. of devices in the chain

1 = global FAULT clear

0 = don‘t care

(up to 2⁶œ 1= 63)

Figure 27. Header Bytes

The status byte provides information about the fault status register for each device in the daisy chain so that the

MCU does not have to initiate a read command to read the fault status from any particular device. This keeps

additional read commands for the MCU and makes the system more efficient to determine fault conditions

flagged in a device. Status bytes must start with 1 and 1 for the two MSBs.

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Header Bytes

(HDRx)

CLR

Status Byte

(Sx)

OTW

UVLO

CPUV

OCP

TSD

OLD

Address Byte

(Ax)

R/W

Data Byte

(Dx)

Figure 28. Contents of Header, Status, Address, and Data Bytes

When data passes through a device, it determines the position of itself in the chain by counting the number of

status bytes it receives followed by the first header byte. For example, in this 3-device configuration, device 2 in

the chain receives two status bytes before receiving the HDR1 byte which is then followed by the HDR2 byte.

From the two status bytes, the data can determine that its position is second in the chain. From the HDR2 byte,

the data can determine how many devices are connected in the chain. In this way, the data only loads the

relevant address and data byte in its buffer and bypasses the other bits. This protocol allows for faster

communication without adding latency to the system for up to 63 devices in the chain.

The address and data bytes remain the same with respect to a 1-device connection. The report bytes (R1

through R3), as shown in Figure 26, are the content of the register being accessed.

nSCS

SCLK

MSB

LSB

SDI

SDO

Capture

Point

Propagate

Point

Figure 29. SPI Transaction

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7.6 Register Maps

Table 18 lists the memory-mapped registers for the device. All register addresses not listed in Table 18 should

be considered as reserved locations and the register contents should not be modified.

Table 18. Memory Map

Name

Access

Type

Address

FAULT Status

DIAG Status

IC1 Control

IC2 Control

IC3 Control

IC4 Control

RSVD

OL1

FAULT

OL2

OTW

ITRIP1

UVLO

CPUV

OCP_H1

OCP

TSD

OLD

0x00

0x01

0x02

0x03

0x04

0x05

ITRIP2

OCP_L1

OCP_H2

OCP_L2

TOFF

SPI_IN

MODE

OCP_MODE

EN_IN1 PH_IN2

DIS_ITRIP

ITRIP_REP

CLR_FLT

RSVD

TSD_MODE

OTW_REP

LOCK

DIS_CPUV

EN_OLA

OCP_TRETRY

OUT1_DIS

OUT2_DIS

EN_OLP

OLP_DLY

ITRIP_LVL

Complex bit access types are encoded to fit into small table cells. Table 19 shows the codes that are used for

access types in this section.

Table 19. Access Type Codes

Access Type

Read Type

Code

Description

Read

Write Type

Write

Reset or Default Value

-n

Value after reset or the default

value

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7.6.1 Status Registers

The status registers are used to reporting warning and fault conditions. Status registers are read-only registers

Table 20 lists the memory-mapped registers for the status registers. All register offset addresses not listed in

Table 20 should be considered as reserved locations and the register contents should not be modified.

Table 20. Status Registers Summary Table

Address

0x00

FAULT status

DIAG status

Section

0x01

7.6.1.1 FAULT Status Register Name (address = 0x00)

FAULT status is shown in Figure 30 and described in Table 21.

Read-only

Figure 30. FAULT Status Register

RSVD

FAULT

OTW

R-0b

UVLO

R-0b

CPUV

R-0b

OCP

R-0b

TSD

R-0b

OLD

R-0b

Table 21. FAULT Status Register Field Descriptions

Bit

Field

Type

Default

Description

RSVD

FAULT

OTW

UVLO

CPUV

OCP

Reserved

Global FAULT status register. Compliments the nFAULT pin

Indicates overtemperature warning

Indicates UVLO fault condition

Indicates charge-pump undervoltage fault condition

Indicates an overcurrent condition

TSD

Indicates an overtemperature shutdown

Indicates an open-load detection

OLD

7.6.1.2 DIAG Status Register Name (address = 0x01)

DIAG status is shown in Figure 31 and described in Table 22.

Read-only

Figure 31. DIAG Status Register

OL1

R-0b

OL2

R-0b

ITRIP1

R-0b

ITRIP2

R-0b

OCP_H1

R-0b

OCP_L1

R-0b

OCP_H2

R-0b

OCP_L2

R-0b

Table 22. DIAG Status Register Field Descriptions

Bit

Field

Type

Default

Description

OL1

Indicates open-load detection on half bridge 1

Indicates open-load detection on half bridge 2

OL2

ITRIP1

Indicates the current regulation status of half bridge 1.

0b = Indicates output 1 is not in current regulation

1b = Indicates output 1 is in current regulation

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Table 22. DIAG Status Register Field Descriptions (continued)

Bit

Field

Type

Default

Description

ITRIP2

Indicates the current regulation status of half bridge 2.

0b = Indicates output 2 is not in current regulation

1b = Indicates output 2 is in current regulation

OCP_H1

OCP_L1

OCP_H2

OCP_L2

Indicates overcurrent fault on the high-side FET of half bridge 1

Indicates overcurrent fault on the low-side FET of half bridge 1

Indicates overcurrent fault on the high-side FET of half bridge 2

Indicates overcurrent fault on the low-side FET of half bridge 2

7.6.2 Control Registers

The IC control registers are used to configure the device. Status registers are read and write capable.

Table 23 lists the memory-mapped registers for the control registers. All register offset addresses not listed in

Table 23 should be considered as reserved locations and the register contents should not be modified.

Table 23. Control Registers Summary Table

Address

0x02

IC1 control

IC2 control

IC3 control

IC4 control

Section

0x03

0x04

0x05

7.6.2.1 IC1 Control Register (address = 0x02)

IC1 control is shown in Figure 32 and described in Table 24.

Read/Write

Figure 32. IC1 Control Register

TOFF

SPI_IN

R/W-0b

MODE

R/W-01b

R/W-100b

R/W-01b

Table 24. IC1 Control Register Field Descriptions

Bit

Field

Type

Default

Description

7-6

TOFF

R/W

01b

00b = 20 µs

01b = 40 µs

10b = 60 µs

11b = 80 µs

SPI_IN

R/W

0b = Outputs follow input pins (INx)

1b = Outputs follow SPI registers EN_IN1 and PH_IN2

4-2

100b

000b = 53.2-V/µs rise time

001b = 34-V/µs rise time

010b = 18.3-V/µs rise time

011b = 13-V/µs rise time

100b = 10.8-V/µs rise time

101b = 7.9-V/µs rise time

110b = 5.3-V/µs rise time

111b = 2.6-V/µs rise time

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Table 24. IC1 Control Register Field Descriptions (continued)

Bit

Field

Type

Default

Description

1-0

MODE

R/W

01b

00b = PH/EN

01b = PWM

10b = Independent half bridge

11b = Input disabled; bridge Hi-Z

7.6.2.2 IC2 Control Register (address = 0x03)

IC2 control is shown in Figure 33 and described in Table 25.

Read/Write

Figure 33. IC2 Control Register

ITRIP_REP

R/W-0b

TSD_MODE

R/W-0b

OTW_REP

R/W-0b

DIS_CPUV

R/W-0b

OCP_TRETRY

R/W-11b

OCP_MODE

R/W-00b

Table 25. IC2 Control Register Field Descriptions

Bit

Field

ITRIP_REP

Type

Default

Description

R/W

0b = ITRIP is not reported on nFAULT or the FAULT bit

1b = ITRIP is reported on nFAULT and the FAULT bit

TSD_MODE

R/W

0b = Overtemperature condition causes a latched fault

1b = Overtemperature condition causes an automatic recovery

fault

OTW_REP

R/W

0b = OTW is not reported on nFAULT or the FAULT bit

1b = OTW is reported on nFAULT and the FAULT bit

DIS_CPUV

0b = Charge pump undervoltage fault is enabled

1b = Charge pump undervoltage fault is disabled

3-2

OCP_TRETRY

11b

00b = Overcurrent retry time is 0.5 ms

01b = Overcurrent retry time is 1 ms

10b = Overcurrent retry time is 2 ms

11b = Overcurrent retry time is 4 ms

1-0

OCP_MODE

R/W

00b

00b = Overcurrent condition causes a latched fault

01b = Overcurrent condition causes an automatic retrying fault

10b = Overcurrent condition is report only but no action is taken

11b = Overcurrent condition is not reported and no action is

taken

7.6.2.3 IC3 Control Register (address = 0x04)

IC3 control is shown in Figure 34 and described in Table 26.

Read/Write

Figure 34. IC3 Control Register

CLR_FLT

R/W-0b

LOCK

OUT1_DIS

R/W-0b

OUT2_DIS

R/W-0b

EN_IN1

R/W-0b

PH_IN2

R/W-0b

R/W-100b

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Table 26. IC3 Control Register Field Descriptions

Bit

Field

Type

Default

Description

CLR_FLT

R/W

Write 1b to this bit to clear the fault bits. This bit is

automatically reset after a write.

6-4

LOCK

R/W

100b

Write 011b to this register to lock all register settings in the IC1

control register except to these bits and address 0x04, bit 7

(CLR_FLT)

Write 100b to this register to unlock all register settings in the

IC1 control register

OUT1_DIS

OUT2_DIS

R/W

Enabled only in the Independent PWM mode

0b = Half bridge 1 enabled

1b = Half bridge 1 disabled (Hi-Z)

Enabled only in the Independent PWM mode

0b = Half bridge 2 enabled

1b = Half bridge 2 disabled (Hi-Z)

EN_IN1

PH_IN2

R/W

EN/IN1 bit to control the outputs through SPI (when SPI_IN =

1b)

PH/IN2 bit to control the outputs through SPI (when SPI_IN =

1b)

7.6.2.4 IC4 Control Register (address = 0x05)

IC4 control is shown in Figure 35 and described in Table 27.

Read/Write

Figure 35. IC4 Control Register

RSVD

R/W-0b

EN_OLP

R/W-0b

OLP_DLY

R/W-0b

EN_OLA

R/W-0b

ITRIP_LVL

R/W-10b

DIS_ITRIP

R/W-00b

Table 27. IC4 Control Register Field Descriptions

Bit

Field

Type

Default

Description

RSVD

R/W

Reserved

EN_OLP

R/W

Write 1b to run open load diagnostic in standby mode. When

open load test is complete EN_OLP returns to 0b (status check)

OLP_DLY

EN_OLA

R/W

0b = Open load diagnostic delay is 300 µs

1b = Open load diagnostic delay is 1.2 ms

R/W

0b = Open load diagnostic in active mode is disabled

1b = Enable open load diagnostics in active mode

3-2

ITRIP_LVL

10b

00b = 4 A

01b = 5.4 A

10b = 6.5 A

11b = 7 A

1-0

DIS_ITRIP

R/W

00b

00b = Current regulation is enabled

01b = Current regulation is disabled for OUT1

10b = Current regulation is disabled for OUT2

11b = Current regulation is disabled for both OUT1 and OUT2

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The device is used mainly to drive a brushed DC motor. The on-board current regulation allows for limiting the

motor current during start-up and stall conditions. The design procedures in the Typical Application section

highlight how to use and configure the SPI version of the device.

8.2 Typical Application

Figure 36 shows the typical application schematic for the SPI version of the device.

1 …F

V_CC

DVDD

GND

10 kΩ

nFAULT

SDO

CPL

CPH

VCP

47 nF

SDI

V_VM

>10 …F

1 …F

SCLK

0.1 …F

nSCS

OUT1

SRC

OUT2

SPI

Device

EN/IN1

PH/IN2

DISABLE

IPROPI1

nSLEEP

IPROPI2

BDC

V_VM

0.1 …F

1.5 kΩ

Figure 36. Typical Application Schematic

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Typical Application (continued)

8.2.1 Design Requirements

Table 28 lists the example input parameters for the system design.

Table 28. Design Parameters

DESIGN PARAMETERS

Supply voltage

REFERENCE

EXAMPLE VALUE

13.5 V

Motor RMS current

I_RMS

2.5 A

Motor winding inductance

Motor current trip point

PWM frequency

2.9 mH

6.5 A

I_TRIP

f_PWM

10 kHz

1.5 kΩ

Sense resistor

R_SENSE

t_SR

Rise and fall times (slew rate)

1 µs

8.2.1.1 Motor Voltage

The motor voltage used depends on the ratings of the motor selected and the desired RPM. A higher voltage

spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage

also increases the rate of current change through the inductive motor windings.

8.2.1.2 Drive Current and Power Dissipation

The current path is through the high-side sourcing power driver, motor winding, and low-side sinking power

driver. The amount of current the device can drive depends on the power dissipation without going into thermal

shutdown. The amount of current that can be power dissipation losses in one source and sink power driver are

calculated in Equation 2.

P_D= (I_RMS)²× (R_{DS(on)High-side}+ R_{DS(on)Low-side}

)

(2)

The I_OUTcurrent is equal to the average current drawn by the DC motor. At 25°C ambient temperature, the power

dissipation becomes (2.5 A)²× (150 mΩ) = 0.94 W.

The temperature that the device reaches depends on the thermal resistance to the air and PCB. Soldering the

device PowerPAD to the PCB ground plane, with vias to the top and bottom board layers, is important to

dissipate heat into the PCB and reduce the device temperature. In the example used here, the device had an

effective thermal resistance R_θJAof 27.8°C/W. The junction temperature T_Jvalue becomes as shown in

Equation 3.

T_J= T_A+ (P_D× R_θJA) = 25°C + (0.94 W × 27.8°C/W) = 51°C

(3)

NOTE

The values of R_DS(on)increases with temperature, so as the device heats, the power

dissipation increases. This fact must be taken into consideration when sizing the heatsink.

At start-up and fault conditions, the current flowing through the motor is much higher than normal running current;

these peak currents and their duration must also be considered. High PWM frequency also results in higher

switching losses. Typically, switching the inputs at 100 kHz compared to 10 kHz causes 20% more power loss in

heat.

Power dissipation in the device is dominated by the power dissipated of the internal MOSFET resistance. The

maximum amount of power that can be dissipated in the device is dependent on ambient temperature and

heatsinking.

Total power dissipation for the device is composed of three main components. These are the quiescent supply

current dissipation, the power MOSFET switching losses, and the power MOSFET R_DS(ON)(conduction) losses.

While other factors may contribute additional power losses, these other items are typically insignificant compared

to the three main items.

P_TOT= P_VM+ P_SW+ P_D

(4)

P_VMcan be calculated from the nominal supply voltage (V_M) and the supply current (I_VM) in active mode.

P_VM= V_M× I_VM= 13.5 V × 5 mA = 67.5 mW

(5)

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P_SWcan be calculated from the nominal supply voltage (V_M), average output current (I_RMS), switching frequency

(f_PWM) and the device output rise and fall times (t_SR) time specifications.

P_SW= P_{SW_RISE}+ P_{SW_FALL}= 0.17 W + 0.17 W = 0.34 W

(6)

(7)

(8)

P_{SW_RISE}= 0.5 × V_M× I_RMS× t_SR× f_PWM= 0.5 × 13.5 V × 2.5 A × 1 µs × 10 kHz = 0.17 W

P_{SW_FALL}= 0.5 × V_M× I_RMS× t_SR× f_PWM= 0.5 × 13.5 V × 2.5 A × 1 µs × 10 kHz = 0.17 W

Therefore, total power dissipation (P_TOT) at 25°C ambient temperature becomes = P_VM+ P_SW+ P_D= 67.5 mW +

0.34 W + 0.94 W = 1.35 W

P_TOTmakes the junction temperature (T_J) of the device to be

T_J= T_A+ (P_TOT× R_θJA) = 25°C + (1.35 W × 27.8°C/W) = 63°C

(9)

The power dissipation from power MOSFET switching losses and quiescent supply current dissipation results is

approximately 12°C rise in the junction temperature (different between Equation 9 and Equation 3). Care must be

taken when doing the PCB layout and heatsinking the motor driver device so that the thermal characteristics are

properly managed.

Trace 0.22 × 34.5mm

at 0.65mm pitch

PTH via at 2.54mm pitch

Drill 300u; plate 18µ

Array to fit the copper area

PTH via at 1.2mm pitch

Drill 300µ; plate 18µ

3.2mm

Copper (Cu)

Dimension A

Area

(mm)

(cm²)

17.9

23.9

32.2

44.0

60.6

74.2

49.23

8.2mm

Figure 37. PCB Model (4-Layer PCB Shown, 2-Layer PCB Has No Vias)

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6.1

6.05

1oz

2oz

1oz

2oz

5.95

5.9

5.85

5.8

5.75

Copper Area (cm²)

D007

D008

Figure 38. 4-Layer PCB

Figure 39. 4-Layer PCB

Junction-to-Ambient Thermal Resistance vs Copper Area

Junction-to-Board Characterization Parameter vs Copper

Area

1oz

2oz

Copper Area (cm²)

D009

Dd0r1v08

Figure 40. 2-Layer PCB (No Vias)

Figure 41. 2-Layer PCB (No Vias)

Junction-to-Ambient Thermal Resistance vs Copper Area

Junction-to-Board Characterization Parameter vs Copper

Area

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8.2.1.3 Sense Resistor

For optimal performance, the sense resistor must have the following features:

•

Surface-mount device

Low inductance

Placed closely to the motor driver device

Use Equation 10 to calculate the power dissipation (P_D) of the sense resistor.

P_D= (I_(RMS)/ k)²× R_(SENSE)

(10)

In this example, for the RMS motor current is 2.5 A, the sense resistor of 1.5 kΩ dissipates approximately 7.5

mW of power. The power quickly increases with higher current levels. Resistors typically have a rated power

within some ambient temperature range, along with a derated power curve for high ambient temperatures. When

a PCB is shared with other components that generate heat, the system designer should add margin. Measuring

the actual sense resistor temperature in a final system is best.

8.2.2 Detailed Design Procedure

8.2.2.1 Thermal Considerations

The device has thermal shutdown (TSD) at 165°C (mininum). If the die temperature exceeds this TSD threshold,

the device will be disabled until the temperature drops below the temperature hysteresis level.

Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient

heatsinking, or too high of an ambient temperature.

8.2.2.2 Heatsinking

The PowerPAD package uses an exposed pad to remove heat from the device. For proper operation, this pad

must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,

this connection can be accomplished by adding a number of vias to connect the thermal pad to the ground plane.

On PCBs without internal planes, a copper area can be added on either side of the PCB to dissipate heat. If the

copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat

between top and bottom layers.

For details about how to design the PCB, refer to the PowerPAD™ Thermally Enhanced Package application

report, and the PowerPAD™ Made Easy application report, available at www.ti.com. In general, the more copper

area that can be provided, the more power can be dissipated.

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8.2.3 Application Curves

Figure 43. Current Regulation (ITRIP)

Figure 42. Overcurrent (OCP) Detection

Figure 44. ITRIP Across TOFF and Load Current

Figure 45. Motor Motion at Different Speeds

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9 Power Supply Recommendations

The device is designed to operate with an input voltage supply (VM) range from 4.5 V to 40 V. A 0.1-µF ceramic

capacitor rated for VM must be placed as close to the device as possible. Also, an appropriately sized bulk

capacitor must be placed on the VM pin.

9.1 Bulk Capacitance Sizing

Bulk capacitance sizing is an important factor in motor drive system design. It is beneficial to have more bulk

capacitance, while the disadvantages are increased cost and physical size.

The amount of local capacitance needed depends on a variety of factors including:

•

The highest current required by the motor system.

The capacitance of the power supply and the ability of the power supply to source current.

The amount of parasitic inductance between the power supply and motor system.

The acceptable voltage ripple.

The type of motor used (brushed DC, brushless DC, and stepper).

The motor braking method.

The inductance between the power supply and motor drive system limits the rate that current can change from

the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands

or dumps from the motor with a change in voltage. When sufficient bulk capacitance is used, the motor voltage

remains stable, and high current can be quickly supplied.

The data sheet provides a recommended value, but system-level testing is required to determine the appropriate

sized bulk capacitor.

Parasitic Wire

Inductance

Motor Drive System

Power Supply

Motor Driver

GND

Local

Bulk Capacitor

IC Bypass

Capacitor

Figure 46. Example Setup of Motor Drive System With External Power Supply

The voltage rating for bulk capacitors should be higher than the operating voltage to provide a margin for cases

when the motor transfers energy to the supply.

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10 Layout

10.1 Layout Guidelines

Each VM pin must be bypassed to ground using low-ESR ceramic bypass capacitors with recommended values

of 0.1 μF rated for VM. These capacitors should be placed as close to the VM pins as possible with a thick trace

or ground plane connection to the device GND pin.

Additional bulk capacitance is required to bypass the high current path. This bulk capacitance should be placed

such that it minimizes the length of any high current paths. The connecting metal traces should be as wide as

possible, with numerous vias connecting PCB layers. These practices minimize inductance and allow the bulk

capacitor to deliver high current.

Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 47 nF, rated for

VM, and be of type X5R or X7R. Additionally, place a low-ESR ceramic capacitor between the VCP and VM pins.

This capacitor should be 1 µF, rated for 16 V, and be of type X5R or X7R.

The current sense resistors should be placed as close as possible to the device pins to minimize trace

inductance between the device pin and resistors.

10.2 Layout Example

1 µF

0.1 µF

DVDD

nFAULT

SDO

GND

CPL

CPH

VCP

47 nF

1 µF

SDI

SCLK

nSCS

OUT1

SRC

EN/IN1

PH/EN2

DISABLE

IPROPI1

nSLEEP

IPROPI2

SRC

OUT2

0.1 µF

Figure 47. Layout Example

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following:

•

Texas Instruments, Calculating Motor Driver Power Dissipation application report

Texas Instruments, Daisy Chain Implementation for Serial Peripheral Interface application report

Texas Instruments, DRV8873x EVM User’s Guide

Texas Instruments, DRV8873x EVM GUI User's Guide

Texas Instruments, PowerPAD™ Thermally Enhanced Package application report

Texas Instruments, PowerPAD™ Made Easy application report

Texas Instruments, Understanding Motor Driver Current Ratings application report

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 Trademarks

PowerPAD, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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12.1 Package Option Addendum

12.1.1 Packaging Information

Package

Type

Package

Drawing

Package

Qty

Lead/Ball

Finish⁽³⁾

(1)

(2)

(4)

Orderable Device

Status

Pins

Eco Plan

MSL Peak Temp

Op Temp (°C)

Device Marking⁽⁵⁾⁽⁶⁾

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

space

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest

availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the

requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified

lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used

between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by

weight in homogeneous material)

space

(3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the

finish value exceeds the maximum column width.

space

(4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

space

(5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device

space

(6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief

on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third

parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for

release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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12.1.2 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

(mm)

Pin1

Quadrant

Device

Pins

SPQ

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TAPE AND REEL BOX DIMENSIONS

Width (mm)

Device

Package Type

Package Drawing Pins

SPQ

Length (mm) Width (mm)

Height (mm)

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10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

DRV8873HPWPR

DRV8873HPWPT

DRV8873SPWPR

DRV8873SPWPT

ACTIVE

HTSSOP

PWP

2000 RoHS & Green

250 RoHS & Green

2000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 125

8873H

NIPDAU

8873H

8873S

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF DRV8873 :

Automotive: DRV8873-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

GENERIC PACKAGE VIEW

PWP 24

4.4 x 7.6, 0.65 mm pitch

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224742/B

www.ti.com

PACKAGE OUTLINE

PWP0024J

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

6.6

6.2

TYP

0.1 C

PIN 1 INDEX

AREA

SEATING

22X 0.65

PLANE

7.9

7.7

7.15

NOTE 3

0.30

24X

4.5

4.3

0.19

0.1

C A B

SEE DETAIL A

(0.15) TYP

2X 2.08 MAX

NOTE 5

4X 0.3 MAX

4X 0.1 MAX

NOTE 5

0.25

GAGE PLANE

1.2 MAX

5.26

5.11

THERMAL

PAD

0.15

0.05

0.75

0.50

0 -8

DETAIL A

TYPICAL

3.20

3.05

4225860/A 04/2020

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may differ or may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

PWP0024J

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(3.4)

NOTE 9

(3.2)

METAL COVERED

BY SOLDER MASK

SYMM

24X (1.5)

24X (0.45)

SEE DETAILS

(R0.05) TYP

(5.26)

22X (0.65)

SYMM

(7.8)

NOTE 9

(1.2) TYP

SOLDER MASK

DEFINED PAD

(

0.2) TYP

VIA

(1.2) TYP

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 8X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

SOLDER MASK DETAILS

4225860/A 04/2020

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged

or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

PWP0024J

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(3.2)

BASED ON

0.125 THICK

STENCIL

METAL COVERED

BY SOLDER MASK

24X (1.5)

24X (0.45)

(R0.05) TYP

22X (0.65)

SYMM

(5.26)

BASED ON

0.125 THICK

STENCIL

SYMM

(5.8)

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 8X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

3.58 X 5.88

3.20 X 5.26 (SHOWN)

2.92 X 4.80

0.125

0.15

0.175

2.70 X 4.45

4225860/A 04/2020

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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