DRV8848 [TI]
具有电流调节功能的 18V、2A、H 桥电机驱动器;
| 型号： | DRV8848 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电流调节功能的 18V、2A、H 桥电机驱动器 电机 驱动 驱动器 |
| 文件： | 总29页 (文件大小：1036K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Reference
Design
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
DRV8848
ZHCSCX5A –OCTOBER 2014–REVISED NOVEMBER 2015
DRV8848 双路 H 桥电机驱动器
1 特性
3 说明
1
•
双路 H 桥电机驱动器
DRV8848 提供适用于家用电器和其他机电一体化应用
的双 H 桥 电机驱动器。该器件可用于驱动一个或两个
直流电机、一个双极性步进电机或其它负载。利用一个
简单的 PWM 接口便可轻松连接到控制器电路。
–
–
单通道/双通道刷式直流
步进
•
•
•
脉宽调制 (PWM) 控制接口
可选电流调节，具有 20μs 固定关断时间
每个 H 桥均提供高输出电流
每个 H 桥驱动器的输出块都包含配置为全 H 桥的 N 通
道和 P 通道功率 MOSFET，用于驱动电机绕组。每个
H 桥都含有一个调节电路，可通过固定关断时间斩波
方案调节绕组电流。DRV8848 能够从每个输出驱动高
达 2A 电流，在并联模式下驱动高达 4A 电流（正常散
热，12V 且 TA = 25°C 时）。
–
最大驱动器电流为 2A（12V 且
TA = 25°C 时）
–
并联模式下最大驱动器电流为 4A（12V 且
TA = 25°C 时）
•
•
•
•
工作电源电压范围为 4V 至 18V
3µA 低电流睡眠模式
低功耗睡眠模式可将部分内部电路关断，从而实现极低
的静态电流和功耗。这种睡眠模式可通过专用的
nSLEEP 引脚来设定。
散热增强型表面贴装封装
DRV8303 中的 特性
–
–
–
–
VM 欠压闭锁 (UVLO)
过流保护 (OCP)
还提供用于 UVLO、OCP、短路保护和过热保护的内
部保护功能。故障条件通过 nFAULT 引脚指示。
热关断 (TSD)
器件信息(1)
故障条件指示引脚 (nFAULT)
器件型号
DRV8848
封装
封装尺寸（标称值）
HTSSOP (16)
5.00mm x 6.40mm
2 应用
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
•
•
•
电器
通用刷式电机和步进电机
打印机
简化原理图
4 to 18 V
DRV8848
PWM
PWM
DC
M
1 A
1 A
Dual
H-Bridge
Motor
VREF
nFAULT
Driver
DC
M
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEL7
DRV8848
ZHCSCX5A –OCTOBER 2014–REVISED NOVEMBER 2015
www.ti.com.cn
目录
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 14
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 15
Power Supply Recommendations...................... 17
9.1 Bulk Capacitance Sizing ......................................... 17
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Typical Characteristics.............................................. 7
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 9
8
9
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 器件和文档支持 ..................................................... 19
11.1 社区资源................................................................ 19
11.2 商标....................................................................... 19
11.3 静电放电警告......................................................... 19
11.4 Glossary................................................................ 19
12 机械、封装和可订购信息....................................... 19
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (October 2014) to Revision A
Page
•
•
•
Updated unit for RDS(ON) .......................................................................................................................................................... 5
Corrected lines for Figure 6 ................................................................................................................................................. 10
已添加 社区资源 .................................................................................................................................................................. 19
2
Copyright © 2014–2015, Texas Instruments Incorporated
DRV8848
www.ti.com.cn
ZHCSCX5A –OCTOBER 2014–REVISED NOVEMBER 2015
5 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP
Top View
1
2
3
4
5
6
7
8
nSLEEP
AOUT1
AISEN
AOUT2
BOUT2
BISEN
16
15
14
13
12
11
10
9
AIN1
AIN2
VINT
GND
VM
VREF
BIN2
BIN1
GND
(PPAD)
BOUT1
nFAULT
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
AIN1
NO.
16
15
3
I
I
Bridge A input 1
Bridge A input 2
Winding A sense
Controls AOUT1; tri-level input
AIN2
Controls AOUT2; tri-level input
AISEN
AOUT1
AOUT2
BIN1
O
Connect to current sense resistor for bridge A, or GND if current regulation is not required
2
O
Winding A output
4
9
I
I
Bridge B input 1
Bridge B input 2
Winding B sense
Controls BOUT1; internal pulldown
BIN2
10
6
Controls BOUT2; internal pulldown
BISEN
BOUT1
BOUT2
O
Connect to current sense resistor for bridge A, or GND if current regulation is not required
7
O
Winding B output
5
13
PPAD
8
GND
PWR Device ground
Both the GND pin and device PowerPAD must be connected to ground
nFAULT
nSLEEP
VINT
OD
I
Fault indication pin Pulled logic low with fault condition; open-drain output requires external pullup
1
Sleep mode input
Internal regulator
Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown
14
—
Internal supply voltage; bypass to GND with 2.2-μF, 6.3-V capacitor
Connect to motor power supply; bypass to GND with a 0.1- and 10-μF (minimum) ceramic
capacitor rated for VM
VM
12
11
PWR Power supply
Full-scale current
Voltage on this pin sets the full scale chopping current; short to VINT if not supplying an
external reference voltage
VREF
I
reference input
External Components
COMPONENT
CVM
PIN 1
VM
PIN 2
RECOMMENDED
10-µF (minimum) ceramic capacitor rated for VM
0.1-µF ceramic capacitor rated for VM
6.3-V, 2.2-µF ceramic capacitor
GND
CVM
VM
GND
CVINT
VINT
VCC(1)
AISEN
BISEN
GND
RnFAULT
RAISEN
RBISEN
nFAULT
GND
>1 kΩ
Sense resistor, see Typical Application for sizing
Sense resistor, see Typical Application for sizing
GND
(1) VCC is not a pin on the DRV8848, but a VCC supply voltage pullup is required for open-drain output nFAULT; nFAULT may be pulled
up to VINT
Copyright © 2014–2015, Texas Instruments Incorporated
3
DRV8848
ZHCSCX5A –OCTOBER 2014–REVISED NOVEMBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range referenced with respect to GND (unless otherwise noted)
(1)
MIN
–0.3
MAX
UNIT
V
Power supply voltage (VM)
20
Power supply voltage ramp rate (VM)
0
2
3.6
V/µs
V
Internal regulator voltage (VINT)
–0.3
–0.3
–0.3
–0.3
–0.6
Analog input pin voltage (VREF)
3.6
V
Control pin voltage (AIN1, AIN2, BIN1, BIN2, nSLEEP, nFAULT)
Continuous phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2)
Continuous shunt amplifier input pin voltage (AISEN, BISEN)(2)
Peak drive current (AOUT1, AOUT2, BOUT1, BOUT2, AISEN, BISEN)
Operating junction temperature
7
V
VVM + 0.6
0.6
V
V
Internally limited
A
TJ
–40
–65
150
150
°C
°C
Tstg
Storage temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Transients of ±1 V for less than 25 ns are acceptable.
6.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
18
UNIT
VVM
VVREF
ƒPWM
IVINT
Irms
Power supply voltage range(1)
Reference rms voltage range(2)
Applied STEP signal
4
1
0
V
V
3.3
250
1
kHz
mA
A
VINT external load current
Motor rms current per H-bridge(3)
Operating ambient temperature
0
1
TA
–40
85
°C
(1) Note that RDS(ON) increases and maximum output current is reduced at VM supply voltages below 5 V.
(2) Operational at VREF between 0 and 1 V, but accuracy is degraded.
(3) Power dissipation and thermal limits must be observed.
6.4 Thermal Information
DRV8848
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
16 PINS
40.3
32.7
28.7
0.6
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
11.4
4.7
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2014–2015, Texas Instruments Incorporated
DRV8848
www.ti.com.cn
ZHCSCX5A –OCTOBER 2014–REVISED NOVEMBER 2015
6.5 Electrical Characteristics
TA = 25°C, over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VM, VINT)
VVM
VM operating voltage
4
2.5
0.5
18
V
VVM = 12 V, excluding winding current,
nSLEEP = 1
IVM
VM operating supply current
3.8
1.2
5.5
mA
IVMQ
tSLEEP
tWAKE
tON
VM sleep mode supply current
Sleep time
VVM = 12 V, nSLEEP = 0
3
1
μA
ms
ms
ms
V
nSLEEP = 0 to sleep mode
Wake time
nSLEEP = 1 to output transition
VVM > VUVLO rising to output transition
VVM > 4 V, IOUT = 0 A to 1 mA
1
Power-on time
VINT voltage
1
VINT
3.13
3.3
3.47
LOGIC-LEVEL INPUTS (BIN1, BIN2, NSLEEP)
VIL
VIH
VHYS
IIL
Input logic low voltage
Input logic high voltage
Input logic hysteresis
Input logic low current
Input logic high current
0
1.6
100
–1
0.7
5.5
V
V
mV
μA
μA
VIN = 0 V
1
IIH
VIN = 5 V
1
30
BIN1, BIN2
200
500
400
200
800
400
RPD
Pulldown resistance
Input deglitch time
Propagation delay
kΩ
nSLEEP
AIN1 or AIN2
ns
ns
ns
ns
tDEG
BIN1 or BIN2
AIN1 or AIN2 edge to output change
BIN1 or BIN2 edge to output change
tPROP
TRI-LEVEL INPUTS (AIN1, AIN2)
VIL
Tri-level input logic low voltage
0
0.7
5.5
V
V
VIZ
VIH
VHYS
IIL
Tri-level input Hi-Z voltage
Tri-level input logic high voltage
Tri-level input hysteresis
1.1
1.6
100
–30
1
V
mV
μA
μA
kΩ
kΩ
Tri-level input logic low current
Tri-level input logic high current
Tri-level pulldown resistance
Tri-level pullup resistance
VIN = 0 V
VIN = 5 V
To GND
To VINT
–1
30
IIH
RPD
RPU
170
340
CONTROL OUTPUTS (NFAULT)
VOL
IOH
Output logic low voltage
Output logic high leakage
IO = 5 mA
VO = 3.3 V
0.5
1
V
–1
–1
μA
MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)
VVM = 12 V, I = 0.5 A, TJ = 25°C
VVM = 12 V, I = 0.5 A, TJ = 85°C(1)
VVM = 12 V, I = 0.5 A, TJ = 25°C
VVM = 12 V, I = 0.5 A, TJ = 85°C(1)
VVM = 5 V, TJ = 25°C
550
660
350
420
RDS(ON)
High-side FET on-resistance
Low-side FET on-resistance
mΩ
mΩ
RDS(ON)
IOFF
Off-state leakage current
Output rise time
1
1
μA
ns
ns
ns
tRISE
tFALL
tDEAD
60
60
Output fall time
Output dead time
Internal dead time
200
PWM CURRENT CONTROL (VREF, AISEN, BISEN)
Externally applied VREF input
current
IREF
VVREF = 1 to 3.3 V
For 100% current step with VVREF = 3.3 V
μA
VTRIP
xISEN trip voltage
500
mV
(1) Not tested in production; limits are based on characterization data
Copyright © 2014–2015, Texas Instruments Incorporated
5
DRV8848
ZHCSCX5A –OCTOBER 2014–REVISED NOVEMBER 2015
www.ti.com.cn
Electrical Characteristics (continued)
TA = 25°C, over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
1.8
6.6
20
MAX
UNIT
μs
tBLANK
AISENSE
tOFF
Current sense blanking time
Current sense amplifier gain
Current control constant off time
Reference only
V/V
μs
PROTECTION CIRCUITS
VVM falling; UVLO report
VVM rising; UVLO recovery
2.9
3
VUVLO
VM undervoltage lockout
V
IOCP
tDEG
tOCP
Overcurrent protection trip level
Overcurrent deglitch time
2
A
2.8
1.6
160
50
μs
ms
°C
°C
Overcurrent protection period
Thermal shutdown temperature
Thermal shutdown hysteresis
(1)
TTSD
THYS
Die temperature TJ
Die temperature TJ
150
180
(1)
6.6 Timing Requirements
TA = 25°C, over recommended operating conditions unless otherwise noted
NO.
MIN
MAX
UNIT
1
2
3
4
5
6
t1
t2
t3
t4
tF
tR
Delay time, xIN1 to xOUT1
Delay time, xIN2 to xOUT1
Delay time, xIN1 to xOUT2
Delay time, xIN2 to xOUT2
Output rise time
100
100
100
100
50
600
600
600
600
150
150
ns
ns
ns
ns
ns
ns
Output fall time
50
xIN1
xIN2
80%
80%
2
1
4
xOUTx
xOUT1
xOUT2
z
z
z
z
20%
20%
3
5
6
Figure 1. Timing Diagram
6
Copyright © 2014–2015, Texas Instruments Incorporated
DRV8848
www.ti.com.cn
ZHCSCX5A –OCTOBER 2014–REVISED NOVEMBER 2015
6.7 Typical Characteristics
4.5
4
3.5
3
œ40°C
25°C
85°C
125°C
œ40°C
25°C
85°C
4
125°C
2.5
2
3.5
3
1.5
1
0.5
0
2.5
2
-0.5
0
5
10
15
20
0
5
10
15
20
VVM (V)
VVM (V)
D001
D002
Figure 2. IVM vs VVM
Figure 3. IVMQ vs VVM
1.8
1.6
1.4
1.2
1
1.8
1.6
1.4
1.2
1
œ40°C
25°C
85°C
125°C
4 V
12 V
18 V
0.8
0.6
0.4
0.2
0
0.8
0.6
0
5
10
15
20
-50
0
50
100
150
VVM (V)
TA (°C)
D003
D004
Figure 4. RDSON vs VVM
Figure 5. RDSON vs Temperature
Copyright © 2014–2015, Texas Instruments Incorporated
7
DRV8848
ZHCSCX5A –OCTOBER 2014–REVISED NOVEMBER 2015
www.ti.com.cn
7 Detailed Description
7.1 Overview
The DRV8848 is an integrated motor driver solution for two DC motors or a bipolar stepper motor. The device
integrates two H-bridges that use NMOS low-side drivers and PMOS high-side drivers and current sense
regulation circuitry. The DRV8848 can be powered with a supply range between 4 to 18 V and is capable of
providing an output current to 1-A rms.
A simple PWM interface allows easy interfacing to the controller circuit.
The current regulation uses a fixed off-time (tOFF) PWM scheme. The current regulation trip point is controlled by
the value of the sense resistor and the voltage applied to VREF.
A low-power sleep mode is included, which allows the system to save power when not driving the motor.
8
Copyright © 2014–2015, Texas Instruments Incorporated
DRV8848
www.ti.com.cn
ZHCSCX5A –OCTOBER 2014–REVISED NOVEMBER 2015
7.2 Functional Block Diagram
VM
VM
VINT
VM
Internal Ref and
Regs
2.2 µF
0.1 µF
10 µF
VREF
VM
VINT
AOUT1
AIN1
Gate
VINT
Drive
and
OCP
Step
Motor
DCM
VM
AIN2
BIN1
BIN2
AOUT2
AISEN
ISEN
optional
VREF
Logic
VM
VINT
nSLEEP
nFAULT
BOUT1
Gate
Drive
and
DCM
VM
OCP
Over-
Temp
BOUT2
BISEN
ISEN
optional
VREF
GND
PPAD
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 PWM Motor Drivers
DRV8848 contains two identical H-bridge motor drivers with current-control PWM circuitry. Figure 6 shows a
block diagram of the circuitry.
Copyright © 2014–2015, Texas Instruments Incorporated
9
DRV8848
ZHCSCX5A –OCTOBER 2014–REVISED NOVEMBER 2015
www.ti.com.cn
Feature Description (continued)
VM
OCP
VM
xOUT1
xIN1
xIN2
Pre-
drive
Step
Motor
xOUT2
PWM
OCP
xISEN
A=6.6
-
+
Optional
Internal
reference
VREF
Figure 6. PWM Motor Driver Circuitry
7.3.2 Bridge Control
Table 1 shows the logic for the inputs xIN1 and xIN2.
Table 1. Bridge Control
xIN1
xIN2
xOUT1
xOUT2
Function (DC Motor)
Coast (fast decay)
0
0
1
1
0
1
0
1
Z
L
Z
H
L
Reverse
H
L
Forward
L
Brake (slow decay)
SPACE
NOTE
Pins AIN1 and AIN2 are tri-level, so when they are left Hi-Z, they are not internally pulled
to logic low. When AIN1 or AIN2 are set to Hi-Z and not in parallel mode, the output driver
maintains the previous state.
10
Copyright © 2014–2015, Texas Instruments Incorporated
DRV8848
www.ti.com.cn
ZHCSCX5A –OCTOBER 2014–REVISED NOVEMBER 2015
7.3.3 Parallel Operation
The two drivers can be used in parallel to deliver twice the current to a single motor. To enter parallel mode,
AIN1 and AIN2 must be left Hi-Z during power-up or when exiting sleep mode (nSLEEP toggling from 0 to 1).
BIN1 and BIN2 are used to control the drivers. Tie AISEN and BISEN to a single sense resistor if current control
is desired. To exit parallel mode, AIN1 and AIN2 must be driven high or low and the device must be powered-up
or exit sleep mode. Figure 7 shows a block diagram of the device using parallel mode.
VM
AOUT1
AIN1
Gate
Drive
and
OCP
VM
AIN2
BIN1
AOUT2
AISEN
ISEN
BIN2
Controller
Logic
VM
nSLEEP
BOUT1
Gate
Drive
and
DCM
VM
OCP
BOUT2
BISEN
ISEN
optional
VREF
Figure 7. Parallel Mode Operation
7.3.4 Current Regulation
The current through the motor windings is regulated by a fixed-off-time PWM current regulation circuit. With DC
brushed motors, current regulation can be used to limit the stall current (which is also the startup current) of the
motor.
Current regulation works as follows:
When an H-bridge is enabled, current rises through the winding at a rate dependent on the supply voltage and
inductance of the winding. If the current reaches the current chopping threshold, the bridge disables the current
for a time tOFF before starting the next PWM cycle. Note that immediately after the current is enabled, the voltage
on the xISEN pin is ignored for a period of time (tBLANK) before enabling the current sense circuitry. This blanking
time also sets the minimum on-time of the PWM cycle.
Copyright © 2014–2015, Texas Instruments Incorporated
11
DRV8848
ZHCSCX5A –OCTOBER 2014–REVISED NOVEMBER 2015
www.ti.com.cn
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor,
connected to the xISEN pin, with a reference voltage. The reference voltage is derived from the voltage applied
to the VREF pin and it is VVREF / 6.6. The VREF pin can be tied, on board, to the 3.3 V – VINT pin, or it can be
externally forced to a desired VREF voltage.
The full scale chopping current in a winding is calculated as follows:
VVREF
IFS
=
6.6 ì RISENSE
where
•
•
•
IFS is the regulated current.
VVREF is the voltage on the VREF pin.
RISENSE is the resistance of the sense resistor.
(1)
Example: If VVREF is 3.3 V and a 500-mΩ sense resistor is used, the full-scale chopping current is 3.3 V / (6.6 ×
500 mΩ) = 1 A.
Note that if the current control is not needed, the xISEN pins may be connected directly to ground. In this case,
VREF should be connected to VINT.
7.3.5 Current Recirculation and Decay Modes
During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM
current chopping threshold is reached (see case 1 in Figure 8).
After the chopping current threshold is reached, the drive current is interrupted, but due to the inductive nature of
the motor, current must continue to flow for some period of time. This is called recirculation current. To handle
this recirculation current, the DRV8848 H-bridge operates in mixed decay mode.
Mixed decay is a combination of fast and slow decay modes. In fast decay mode, the opposite drivers are turned
on to allow the current to decay (see case 2 in Figure 8). If the winding current approaches zero, while in fast
decay, the bridge is disabled to prevent any reverse current flow. In slow decay mode, winding current is
recirculated by enabling both of the low-side FETs in the bridge (see case 3 in Figure 8). Mixed decay starts with
fast decay, then goes to slow decay. In DRV8848, the mixed decay ratio is 25% fast decay and 75% slow decay
(as shown in Figure 9).
12
Copyright © 2014–2015, Texas Instruments Incorporated
DRV8848
www.ti.com.cn
ZHCSCX5A –OCTOBER 2014–REVISED NOVEMBER 2015
xëa
1
2
3
5rive /urrent
Cast decay
1
2
xhÜÇ2
xhÜÇ1
{low decay
3
Figure 8. Decay Modes
PWM
ON
PWM OFF (tOFF
)
Mixed Decay
25%
Itrip
25% of tOFF
PWM CYCLE
Figure 9. Mixed Decay
7.3.6 Protection Circuits
The DRV8848 is fully protected against undervoltage, overcurrent, and overtemperature events.
7.3.6.1 OCP
An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive. If this
analog current limit persists for longer than the OCP deglitch time tOCP, all FETs in the H-bridge are disabled and
the nFAULT pin is driven low. The device remains disabled until the retry time tRETRY occurs. The OCP is
independent for each H-bridge.
Overcurrent conditions are detected independently on both high-side and low-side devices; that is, a short to
ground, supply, or across the motor winding all result in an OCP event. Note that OCP does not use the current
sense circuitry used for PWM current control, so OCP functions even without presence of the xISEN resistors.
Copyright © 2014–2015, Texas Instruments Incorporated
13
DRV8848
ZHCSCX5A –OCTOBER 2014–REVISED NOVEMBER 2015
www.ti.com.cn
7.3.6.2 TSD
If the die temperature exceeds safe limits TTSD, all FETs in the H-bridge are disabled and the nFAULT pin is
driven low. After the die temperature has fallen to a safe level, operation automatically resumes. The nFAULT pin
is released after operation has resumed.
7.3.6.3 UVLO
If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the
device is disabled, and all internal logic is reset. Operation resumes when VVM rises above the UVLO rising
threshold. The nFAULT pin is driven low during an undervoltage condition and is released after operation has
resumed.
Table 2. Fault Handling
INTERNAL
CIRCUITS
FAULT
ERROR REPORT
nFAULT unlatched
nFAULT unlatched
nFAULT unlatched
H-BRIDGE
Disabled
Disabled
Disabled
RECOVERY
VM undervoltage (UVLO)
Overcurrent (OCP)
Shut down
System and fault clears on recovery
System and fault clears on recovery and
motor is driven after time, tRETRY
Operating
Operating
Thermal shutdown (TSD)
System and fault clears on recovery
7.4 Device Functional Modes
The DRV8848 is active unless the nSLEEP pin is brought logic low. In sleep mode, the VINT regulator is
disabled and the H-bridge FETs are disabled Hi-Z. Note that tSLEEP must elapse after a falling edge on the
nSLEEP pin before the device is in sleep mode. The DRV8848 is brought out of sleep mode automatically if
nSLEEP is brought logic high. Note that tWAKE must elapse before the output change state after wake-up.
When VVM falls below the VM UVLO threshold (VUVLO), the output driver, internal logic, and VINT regulator are
reset.
Table 3. Functional Modes
MODE
CONDITION
H-BRIDGE
VINT
4 V < VVM < 18 V
nSLEEP pin = 1
Operating
Operating
Operating
4 V < VVM < 18 V
nSLEEP pin = 0
Sleep
Fault
Disabled
Disabled
Disabled
Any fault condition met
Depends on fault
14
Copyright © 2014–2015, Texas Instruments Incorporated
DRV8848
www.ti.com.cn
ZHCSCX5A –OCTOBER 2014–REVISED NOVEMBER 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8848 is used in stepper or brushed DC motor control.
8.2 Typical Application
The user can configure the DRV8848 with the following design procedure.
1
16
15
14
13
12
11
nSLEEP
AOUT1
AISEN
AOUT2
BOUT2
BISEN
AIN1
2
3
4
5
6
AIN2
VINT
GND
VM
500 mΩ
500 mΩ
5/a
2.2 µF
10 µF
DRV8848
0.1 µF
VM
GND
(PPAD)
5/a
VREF
7
8
10
9
BOUT1
BIN2
BIN1
nFAULT
10 kΩ
VCC
logic supply
Figure 10. Typical Application Schematic
8.2.1 Design Requirements
Table 4 gives design input parameters for system design.
Table 4. Design Parameters
DESIGN PARAMETER
Nominal supply voltage
REFERENCE
EXAMPLE VALUE
12 V
VVM
Supply voltage range
4 to 18 V
Motor winding resistance
Motor winding inductance
Target chopping current
Chopping current reference voltage
RL
LL
3 Ω/phase
330 µH/phase
500 mA
ICHOP
VVREF
3.3 V
Copyright © 2014–2015, Texas Instruments Incorporated
15
DRV8848
ZHCSCX5A –OCTOBER 2014–REVISED NOVEMBER 2015
www.ti.com.cn
8.2.2 Detailed Design Procedure
8.2.2.1 Current Regulation
The chopping current (ICHOP) is the maximum current driven through either winding. This quantity depends on the
sense resistor value (RXISEN).
VVREF
ICHOP
=
6.6 ì RXISEN
(2)
ICHOP is set by a comparator which compares the voltage across RXISEN to a reference voltage. Note that ICHOP
must follow Equation 3 to avoid saturating the motor.
VVM (V)
ICHOP (A) <
RL (W) + 2 ì RDS(ON) (W) + RXISEN (W)
where
•
•
VVM is the motor supply voltage.
RL is the motor winding resistance.
(3)
8.2.3 Application Curves
AIN1
Fast decay
Current trip point
AIN2
Slow decay
I Motor
Figure 11. Current Regulation
Figure 12. Stepper Mode Operation
16
Copyright © 2014–2015, Texas Instruments Incorporated
DRV8848
www.ti.com.cn
ZHCSCX5A –OCTOBER 2014–REVISED NOVEMBER 2015
9 Power Supply Recommendations
The DRV8848 is designed to operate from an input voltage supply (VVM) range between 4 and 18 V. Place a 0.1-
µF ceramic capacitor rated for VM as close to the DRV8848 as possible. In addition, the user must include a bulk
capacitor of at least 10 µF on VM.
9.1 Bulk Capacitance Sizing
Bulk capacitance sizing is an important factor in motor drive system design. It depends on a variety of factors
including:
•
•
•
•
•
•
Type of power supply
Acceptable supply voltage ripple
Parasitic inductance in the power supply wiring
Type of motor (brushed DC, brushless DC, stepper)
Motor startup current
Motor braking method
The inductance between the power supply and motor drive system limits the rate that current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. Size the bulk capacitance to meet acceptable voltage ripple
levels.
The data sheet provides a recommended minimum value, but system-level testing is required to determine the
appropriate-sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
œ
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 13. Setup of Motor Drive System With External Power Supply
Copyright © 2014–2015, Texas Instruments Incorporated
17
DRV8848
ZHCSCX5A –OCTOBER 2014–REVISED NOVEMBER 2015
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
Bypass the VM terminal to GND using a low-ESR ceramic bypass capacitor with a recommended value of 10 μF
rated for VM. Place this capacitor as close to the VM pin as possible with a thick trace or ground plane
connection to the device GND pin.
Bypass VINT to ground with a ceramic capacitor rated 6.3 V. Place this bypassing capacitor as close to the pin
as possible.
10.2 Layout Example
nSLEEP
AOUT1
AISEN
AIN1
AIN2
VINT
GND
VM
2.2 µF
AOUT2
BOUT2
BISEN
RAISEN
VREF
BIN2
BIN1
BOUT1
nFAULT
10 µF
RBISEN
Figure 14. Layout Recommendation
18
版权 © 2014–2015, Texas Instruments Incorporated
DRV8848
www.ti.com.cn
ZHCSCX5A –OCTOBER 2014–REVISED NOVEMBER 2015
11 器件和文档支持
11.1 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.2 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航栏。
版权 © 2014–2015, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8848PWP
ACTIVE
ACTIVE
HTSSOP
HTSSOP
PWP
PWP
16
16
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
DRV8848
DRV8848
DRV8848PWPR
2000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8848PWPR
HTSSOP PWP
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 16
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
DRV8848PWPR
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
PWP HTSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DRV8848PWP
16
90
530
10.2
3600
3.5
Pack Materials-Page 3
PACKAGE OUTLINE
PWP0016C
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
6.6
6.2
C
TYP
A
PIN 1 INDEX
AREA
0.1 C
SEATING
PLANE
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
B
0.19
0.1
C A B
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5
4X (0.3)
8
9
2X 0.23 MAX
NOTE 5
2.31
1.75
17
0.25
GAGE PLANE
1.2 MAX
0.15
0.05
0.75
0.50
0 -8
16
1
A
20
DETAIL A
TYPICAL
THERMAL
PAD
2.46
1.75
4224559/B 01/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016C
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(2.46)
16X (1.5)
METAL COVERED
BY SOLDER MASK
SYMM
1
16X (0.45)
16
(1.2) TYP
(2.31)
(R0.05) TYP
SYMM
17
(5)
NOTE 9
(0.6)
14X (0.65)
(
0.2) TYP
VIA
9
8
SOLDER MASK
DEFINED PAD
(1) TYP
SEE DETAILS
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
SOLDER MASK DETAILS
4224559/B 01/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016C
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.46)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
METAL COVERED
BY SOLDER MASK
1
16
16X (0.45)
(R0.05) TYP
SYMM
(2.31)
17
BASED ON
0.125 THICK
STENCIL
14X (0.65)
9
8
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.75 X 2.58
2.46 X 2.31 (SHOWN)
2.25 X 2.11
0.125
0.15
0.175
2.08 X 1.95
4224559/B 01/2019
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
DRV8849RHHR
35-V, 1.5-A quad H-bridge motor driver with smart tune and integrated current sensing | RHH | 36 | -40 to 125
TI
©2020 ICPDF网 联系我们和版权申明