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DRV8340-Q1

ZHCSJU7 –MAY 2019

DRV8340-Q1 12V/24V 汽车栅极驱动器单元 (GDU)，带有独立半桥控制装

置

1 特性

3 说明

1

•

具有符合面向汽车标准

温度等级 1：-40°C ≤ T_A≤ 125°C

3 个独立半桥栅极驱动器

DRV8340-Q1 器件是一款适用于三相应用的集成式栅

极驱动器。此器件具有三个半桥栅极驱动器，每个驱动

器都能够驱动高侧和低侧 N 沟道功率 MOSFET。专用

源极与漏极引脚支持对电磁阀应用进行独立 MOSFET

控制。DRV8340-Q1 使用集成式电荷泵为高侧

MOSFET 生成足够的栅极驱动电压，并使用线性稳压

器为低侧 MOSFET 生成足够的栅极驱动电压。此智能

栅极驱动架构支持高达 1A 的峰值栅极驱动拉电流和

2A 的峰值栅极驱动灌电流。DRV8340-Q1 可由单一电

源供电，支持适用于栅极驱动器的 5.5 至 60V 宽输入

电源电压范围。

–

•

–

专用源极 (SHx) 与漏极 (DLx) 引脚支持独立

MOSFET 控制

–

可驱动 3 个高侧和 3 个低侧 N 通道 MOSFET

(NMOS)

•

智能栅极驱动架构

–

可调转换率控制

1.5mA 至 1A 峰值源电流

3mA 至 2A 峰值灌电流

•

支持 100% 占空比的栅极驱动器电荷泵

提供 SPI (S) 和硬件 (H) 接口

6x、3x、1x 和独立的 PWM 模式

支持 3.3V 和 5V 逻辑输入

6x、3x、1x 和独立输入 PWM 模式可简化与控制器电

路的连接。栅极驱动器和器件的配置设置具有高度可配

置性，可通过 SPI 或硬件 (H/W) 接口实现。

提供了低功耗睡眠模式，实现较低的静态电流消耗。针

对欠压锁定、电荷泵故障、MOSFET 过流、MOSFET

短路、相位节点电源和接地短路、栅极驱动器故障和过

热情况提供内部保护功能。故障状况及故障详情可通过

SPI 器件型号的器件寄存器显示在 nFAULT 引脚上。

电荷泵输出可驱动反向电源保护 MOSFET

3.3V、30mA 线性稳压器

集成式保护特性

–

VM 欠压锁定 (UVLO)

电荷泵欠压 (CPUV)

电池短路 (SHT_BAT)

器件信息⁽¹⁾

接地短路 (SHT_GND)

MOSFET 过流保护 (OCP)

栅极驱动器故障 (GDF)

热警告和热关断 (OTW/OTSD)

故障状态指示器 (nFAULT)

器件型号

封装

封装尺寸（标称值）

DRV8340-Q1

HTQFP (48)

7.00mm × 7.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

简化原理图

2 应用

5.5 to 60 V

•

12V 与 24V 汽车电机控制应用

PWM

DRV8340-Q1

–

BLDC 和 BDC 电机模块

风扇和风机

Gate Drive

SPI or H/W

nFAULT

Three-Phase

Smart Gate Driver

M

燃油泵和水泵

Protection

3.3-V LDO

3.3 V

电磁阀驱动器

30 mA

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSDZ9

DRV8340-Q1

ZHCSJU7 –MAY 2019

www.ti.com.cn

8.6 Register Maps......................................................... 45

Application and Implementation ........................ 59

9.1 Application Information............................................ 59

9.2 Typical Application ................................................. 59

1

2

3

4

5

6

7

特性.......................................................................... 1

9

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 7

7.1 Absolute Maximum Ratings ...................................... 7

7.2 ESD Ratings.............................................................. 7

7.3 Recommended Operating Conditions....................... 8

7.4 Thermal Information.................................................. 8

7.5 Electrical Characteristics........................................... 9

7.6 SPI Timing Requirements ....................................... 14

7.7 Typical Characteristics............................................ 15

Detailed Description ............................................ 16

8.1 Overview ................................................................. 16

8.2 Functional Block Diagram ....................................... 17

8.3 Feature Description................................................. 18

8.4 Device Functional Modes........................................ 43

8.5 Programming........................................................... 43

10 Power Supply Recommendations ..................... 64

10.1 Power Supply Consideration in Generator Mode . 64

10.2 Bulk Capacitance Sizing ....................................... 64

11 Layout................................................................... 66

11.1 Layout Guidelines ................................................. 66

11.2 Layout Example .................................................... 67

12 器件和文档支持 ..................................................... 68

12.1 器件支持................................................................ 68

12.2 文档支持................................................................ 68

12.3 接收文档更新通知 ................................................. 68

12.4 社区资源................................................................ 68

12.5 商标....................................................................... 68

12.6 静电放电警告......................................................... 69

12.7 Glossary................................................................ 69

13 机械、封装和可订购信息....................................... 69

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

2019 年 5 月

*

初始发行版

PP

2

DRV8340-Q1

www.ti.com.cn

ZHCSJU7 –MAY 2019

5 Device Comparison Table

DEVICE

VARIANT⁽¹⁾

DRV8340H

DRV8340S

INTERFACE⁽¹⁾

Hardware

SPI

DRV8340-Q1

(1) For more information on the device name and device options, see the 器件命名规则 section.

6 Pin Configuration and Functions

DRV8340H PHP PowerPAD™ Package

48-Pin HTQFP With Exposed Thermal Pad

Top View

CPL

CPH

VCP

VM

1

36

35

34

33

32

31

30

29

28

27

26

25

ENABLE

RSVD

VDS

2

3

4

IDRIVE

MODE

nFAULT

NC

VDRAIN

GHA

SHA

DLA

5

6

Thermal

Pad

7

8

NC

GLA

SLA

9

NC

10

11

12

NC

Not to scale

Table 1. Pin Functions—DRV8340H

NAME

TYPE

DESCRIPTION

NO.

1

CPL

CPH

PWR

I

Charge pump switching node. Connect a flying capacitor between the CPH and CPL pins

Charge pump output. Connect a bypass capacitor between the VCP and VM pins

2

3

4

5

6

VCP

VM

Gate driver power supply input. Connect to the bridge power supply. Connect bypass capacitors VM and PGND pins

High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains

High-side gate driver output. Connect to the gate of the high-side power MOSFET

VDRAIN

GHA

O

3

DRV8340-Q1

ZHCSJU7 –MAY 2019

www.ti.com.cn

Table 1. Pin Functions—DRV8340H (continued)

TYPE

DESCRIPTION

NO.

NAME

High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used,

connect to GND

7

SHA

I

8

DLA

GLA

SLA

NC

I

O

Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain

Low-side gate driver output. Connect to the gate of the low-side power MOSFET

Low-side source sense input. Connect to the low-side power MOSFET source

No internal connection. This pin can be left floating or connected to system ground.

Low-side source sense input. Connect to the low-side power MOSFET source

Low-side gate driver output. Connect to the gate of the low-side power MOSFET

Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain

9

10

11

12

13

14

15

16

17

I

NC

I

NC

SLB

GLB

DLB

O

I

High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used,

connect to GND

18

SHB

I

19

20

GHB

GHC

O

High-side gate driver output. Connect to the gate of the high-side power MOSFET

High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used,

connect to GND

21

SHC

I

22

23

24

25

26

27

28

29

30

31

32

33

34

35

DLC

GLC

SLC

I

O

Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain

Low-side gate driver output. Connect to the gate of the low-side power MOSFET

Low-side source sense input. Connect to the low-side power MOSFET source

No internal connection. This pin can be left floating or connected to system ground.

Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor

PWM input mode setting. This pin is a 7-level input pin set by an external resistor

Gate drive output current setting. This pin is a 7-level input pin set by an external resistor

VDS monitor trip point setting. This pin is a 7-level input pin set by an external resistor

Reserved. Leave open.

I

NC

OD

I

NC

nFAULT

MODE

IDRIVE

VDS

RSVD

I

Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 20-μs (typ) low pulse can be

used to reset fault conditions

36

ENABLE

I

37

38

NC

No internal connection. This pin can be left floating or connected to system ground.

Device analog ground. Connect to system ground

AGND

PWR

3.3-V internal regulator output. Connect a bypass capacitor between the DVDD and AGND pins. This regulator can externally

source up to 30 mA.

39

40

DVDD

nDIAG

PWR

I

Control pin for open load diagnostic and offline short-to-battery and short-to-ground diagnostic. To enable the diagnostics at

device power-up, do not connect this pin (or tie it to ground). To disable the diagnostics, connect this pin to the DVDD pin.

41

42

43

44

45

46

47

48

INHA

INLA

INHB

INLB

INHC

INLC

PGND

NC

I

High-side gate driver control input. This pin controls the output of the high-side gate driver

Low-side gate driver control input. This pin controls the output of the low-side gate driver

High-side gate driver control input. This pin controls the output of the high-side gate driver

Low-side gate driver control input. This pin controls the output of the low-side gate driver

High-side gate driver control input. This pin controls the output of the high-side gate driver

Low-side gate driver control input. This pin controls the output of the low-side gate driver

Device power ground. Connect to system ground

I

PWR

NC

No connect. Do not connect anything to this pin

Thermal

Pad

—

PWR

Must be connected to ground

4

DRV8340-Q1

www.ti.com.cn

ZHCSJU7 –MAY 2019

DRV8340S PHP PowerPAD™ Package

48-Pin HTQFP With Exposed Thermal Pad

Top View

CPL

CPH

VCP

VM

1

36

35

34

33

32

31

30

29

28

27

26

25

ENABLE

nSCS

SCLK

SDI

2

3

4

VDRAIN

GHA

SHA

DLA

5

SDO

nFAULT

NC

6

Thermal

Pad

7

8

NC

GLA

SLA

9

NC

10

11

12

NC

Not to scale

Table 2. Pin Functions—DRV8340S

TYPE

DESCRIPTION

NO.

1

NAME

CPL

PWR

Charge pump switching node. Connect a flying capacitor between the CPH and CPL pins

Charge pump output. Connect a bypass capacitor between the VCP and VM pins

2

CPH

VCP

3

Gate driver power supply input. Connect to the bridge power supply. Connect bypass capacitors between the VM and PGND

pins

4

VM

PWR

5

6

VDRAIN

GHA

I

High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains

High-side gate driver output. Connect to the gate of the high-side power MOSFET

O

High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used,

connect to GND

7

SHA

I

8

DLA

GLA

SLA

NC

I

Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain

Low-side gate driver output. Connect to the gate of the low-side power MOSFET

Low-side source sense input. Connect to the low-side power MOSFET source

No internal connection. This pin can be left floating or connected to system ground.

Low-side source sense input. Connect to the low-side power MOSFET source

9

O

10

11

12

13

14

15

I

NC

I

NC

SLB

5

DRV8340-Q1

ZHCSJU7 –MAY 2019

www.ti.com.cn

Table 2. Pin Functions—DRV8340S (continued)

TYPE

DESCRIPTION

NO.

16

NAME

GLB

O

I

Low-side gate driver output. Connect to the gate of the low-side power MOSFET

Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain

17

DLB

High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used,

connect to GND

18

SHB

I

19

20

GHB

GHC

O

High-side gate driver output. Connect to the gate of the high-side power MOSFET

High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used,

connect to GND

21

SHC

I

22

23

24

25

26

27

28

29

30

31

32

33

34

35

DLC

GLC

SLC

NC

I

Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain

O

Low-side gate driver output. Connect to the gate of the low-side power MOSFET

Low-side source sense input. Connect to the low-side power MOSFET source

I

NC

OD

PP

I

No internal connection. This pin can be left floating or connected to system ground.

Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor

Serial data output. Data is shifted out on the rising edge of the SCLK pin. VSDO determines logic level on the output

Serial data input. Data is captured on the falling edge of the SCLK pin

NC

nFAULT

SDO

SDI

SCLK

nSCS

I

Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin

Serial chip select. A logic low on this pin enables serial interface communication

I

Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 20-μs (typ) low pulse can be

used to reset fault conditions

36

ENABLE

I

37

38

NC

No internal connection. This pin can be left floating or connected to system ground.

Device analog ground. Connect to system ground

AGND

PWR

3.3-V internal regulator output. Connect a bypass capacitor between the DVDD and AGND pins. This regulator can externally

source up to 30 mA.

39

40

DVDD

VSDO

PWR

Supply pin for SDO output. Connect to 5-V or 3.3-V depending on the desired logic level. Connect a bypass capacitors

between VSDO and AGND

41

42

43

44

45

46

47

48

INHA

INLA

INHB

INLB

INHC

INLC

PGND

NC

I

High-side gate driver control input. This pin controls the output of the high-side gate driver

Low-side gate driver control input. This pin controls the output of the low-side gate driver

High-side gate driver control input. This pin controls the output of the high-side gate driver

Low-side gate driver control input. This pin controls the output of the low-side gate driver

High-side gate driver control input. This pin controls the output of the high-side gate driver

Low-side gate driver control input. This pin controls the output of the low-side gate driver

Device power ground. Connect to system ground

I

PWR

NC

No connect. Do not connect anything to this pin

Thermal

Pad

—

PWR

Must be connected to ground

6

DRV8340-Q1

www.ti.com.cn

ZHCSJU7 –MAY 2019

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

GATE DRIVER

Power supply pin voltage (VM)

–0.3

–10

65

V

Voltage differential between ground pins (AGND, BGND, DGND, PGND)

MOSFET drain sense pin voltage (VDRAIN)

Charge pump pin voltage (CPH, VCP)

0.3

65

V_VM+ 13.5

V_VM

Charge-pump negative-switching pin voltage (CPL)

Internal logic regulator pin voltage (DVDD)

Voltage difference between VM and VDRAIN

3.8

10

Digital pin voltage (ENABLE, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI, SDO, VDS,

nDIAG)

–0.3

5.75

V

Continuous high-side gate drive pin voltage (GHx)

Transient 200-ns high-side gate drive pin voltage (GHx)

High-side gate drive pin voltage with respect to SHx (GHx)

Continuous high-side source sense pin voltage (SHx, DLx)

Transient 200-ns high-side source sense pin voltage (SHx, DLx)

Continuous high-side source sense pin voltage (SHx, DLx)

Transient 200-ns high-side source sense pin voltage (SHx, DLx)

Continuous low-side gate drive pin voltage (GLx)

Gate drive pin source current (GHx, GLx)

–5⁽²⁾

–7

V_VCP+ 0.5

13.5

V

–0.3

–5⁽²⁾

–7

V

V_VM+ 5

V_VM+ 7

V_DRAIN+ 5

V_DRAIN+ 7

15

V

–5⁽²⁾

V

–7

V

–0.5

V

Internally limited

A

Gate drive pin sink current (GHx, GLx)

Internally limited

A

Continuous low-side source sense pin voltage (SLx)

Transient 200-ns low-side source sense pin voltage (SLx)

Push-pull output buffer reference voltage (VSDO)

Push-pull output current (SDO)

–1

–3

1

3

V

–0.3

0

5.75

10

V

mA

V

Open drain pullup voltage (nFAULT)

–0.3

0

5.75

10

Open drain output current (nFAULT)

mA

°C

Operating junction temperature, T_J

–40

–65

150

Storage temperature, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Continuous high-side gate pin (GHx) and phase node pin voltage (SHx) should be limited to –2 V minimum for an absolute maximum of

65 V on VM. At 60 V and below, the full specification of –5 V continuous on GHx and SHx is allowable.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

V

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Electrostatic

discharge

V_(ESD)

All pins

Charged-device model (CDM), per AEC Q100-

011

Corner pins (1, 10, 11, 20, 21, 30, 31, and 40)

±750

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7

DRV8340-Q1

ZHCSJU7 –MAY 2019

www.ti.com.cn

UNIT

7.3 Recommended Operating Conditions

MIN

MAX

GATE DRIVER

(1)

Power supply voltage (VM) Continuous

5.5

50

60

V

V_VM

(2)

Power supply voltage (VM) Transient over voltage

Input voltage (ENABLE, IDRIVE, INHx, INLx, MODE, nSCS, SCLK, SDI, VDS, VSDO,

nDIAG)

V_I

0

5.5

V

f_PWM

Applied PWM signal (INHx, INLx)

High-side average gate-drive current (GHx)

Low-side average gate-drive current (GLx)

External load current (DVDD)

0

200⁽³⁾

25⁽³⁾

30⁽³⁾

5.5

kHz

mA

V

I_{GATE_HS}

I_{GATE_LS}

I_DVDD

V_SDO

V_OD

0

Push-pull voltage (SDO)

3

Open drain pullup voltage (nFAULT)

Operating ambient temperature

0

5.5

V

T_A

–40

125

°C

(1) Operation at VM = 5.5V only when coming from higher VM. The minimum VM voltage for startup is greater than V_UVLO(rising) voltage.

(2) VM recommended operating condition for electrical characteristic table. Product life time depends on VM voltage. The device is intended

for 12–V and 24–V battery automotive system with life-time nominal voltage of 5.5 V - 50 V. The device can be operated during

additional overvoltage events as specified in ISO16750-2:2012

(3) Power dissipation and thermal limits must be observed

7.4 Thermal Information

DRV8340-Q1

THERMAL METRIC⁽¹⁾

PHP (HTQFP)

UNIT

48 PINS

26.5

16.3

6.7

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

6.8

R_θJC(bot)

1.0

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8

DRV8340-Q1

www.ti.com.cn

ZHCSJU7 –MAY 2019

7.5 Electrical Characteristics

Over recommended operating conditions 5.5 ≤ V_VM≤ 60 V (unless otherwise noted). Typical limits apply for V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLIES (DVDD, VCP, VM)

V_VM= 24 V, ENABLE = 3.3 V, INHx/INLx = 0 V, SHx = 0

V

I_VM

VM operating supply current

12

16

mA

µA

ENABLE = 0 V, V_VM= 24 V, T_A= 25°C

ENABLE = 0 V, V_VM= 24 V, T_A= 125°C

ENABLE = 0 V period to reset faults

ENABLE = 3.3 V to outputs ready, V_VM> V_UVLO

ENABLE = 0 V to device sleep mode

V_VM> 6 V, I_DVDD= 0 to 30 mA

20

50

43

1

I_VMQ

VM sleep mode supply current

t_RST

Reset pulse time

Turnon time

4.4

µs

ms

V

(1)

t_WAKE

t_SLEEP

Turnoff time

1

3

3.3

11

9

3.6

12.5

10

8

V_DVDD

DVDD regulator voltage

V_VM= 5.5 to 6 V, I_DVDD= 0 to 20 mA

V_VM= 13 V, I_VCP= 0 to 25 mA

V

8.4

6.3

5.4

4

V_VM= 10 V, I_VCP= 0 to 20 mA

VCP operating voltage

with respect to VM

V_VCP

V

V_VM= 8 V, I_VCP= 0 to 15 mA

7

V_VM= 5.5 V, I_VCP= 0 to 5 mA

5

6

LOGIC-LEVEL INPUTS (CAL, ENABLE, INHx, INLx, SCLK, SDI)

V_IL

Input logic low voltage

Input logic high voltage

Input logic hysteresis

0

0.7

5.5

V

V_IH

1.6

V_HYS

182

mV

V_VIN= 0 V; INHx, INLx, SDI(IDRIVE), SCLK(VDS),

ENABLE

I_IL

Input logic low current

–5

5

µA

I_IH

Input logic high current

Pulldown resistance

V_VIN= 5 V; INHx, INLx, SDI(IDRIVE), SCLK(VDS)

V_VIN= 5 V; ENABLE

50

80

90

110

200

110

µA

kΩ

I_IH

R_PD

To AGND; INHx, INLx, SDI(IDRIVE), SCLK(VDS)

To AGND; ENABLE

50

30

100

60

INHx/INLx input buffer and digital core propagation

delay. Dead time is excluded.

t_PD

Propagation delay

105

ns

LOGIC LEVEL INPUT (nSCS)

V_IL,nSCS

V_IH,nSCS

R_PU,nSCS

Input logic low voltage

0

1.6

25

0.7

5.5

90

V

Input logic high voltage

Pullup resistance

To DVDD

50

kΩ

SEVEN-LEVEL H/W INPUTS (MODE, IDRIVE, VDS)

V_I1

V_I2

V_I3

V_I4

V_I5

V_I6

Input mode 1 voltage

Input mode 2 voltage

Input mode 3 voltage

Input mode 4 voltage

Input mode 5 voltage

Input mode 6 voltage

Tied to AGND

0

0.5

V

18 kΩ ± 5% tied to AGND

75 kΩ ± 5% tied to AGND

Hi-Z ( > 1.5 MΩ )

1.1

1.65

2.2

75 kΩ ± 5% tied to DVDD

18 kΩ ± 5% tied to DVDD

2.8

MODE : 0.47 kΩ ± 5% tied to DVDD

VDS, IDRIVE : Tied to DVDD

V_I7

Input mode 7 voltage

3.3

V

R_PU

R_PD

Pullup resistance

Internal pullup to DVDD

35

73

125

kΩ

Pulldown resistance

Internal pulldown to AGND

PUSH-PULL OUTPUT (SDO)

To VSDO = 5 V

To VSDO = 3.3 V

To GND

40

60

30

90

120

50

R_PU,SDOInternal pullup

Ω

R_PD,SDO

Internal pulldown

OPEN DRAIN OUTPUT (nFAULT)

V_OL

I_OZ

Output logic low voltage

Output high impedance leakage

I_O= 5 mA

V_O= 5 V

0.15

9

V

–1

µA

GATE DRIVERS (GHx, GLx)

(1) Does not include OLP/Shorts diagnostic delay time in the H/W device

9

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ZHCSJU7 –MAY 2019

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Electrical Characteristics (continued)

Over recommended operating conditions 5.5 ≤ V_VM≤ 60 V (unless otherwise noted). Typical limits apply for V_VM= 24 V

PARAMETER

TEST CONDITIONS

V_VM= 13 V, I_VCP= 0 to 25 mA, GHx no output load

V_VM= 10 , I_VCP= 0 to 20 mA, GHx no output load

V_VM= 8 V, I_VCP= 0 to 15 mA, GHx no output load

V_VM= 5.5 V, I_VCP= 0 to 5 mA, GHx no output load

V_VM= 12 V, I_VCP= 0 to 25 mA, GLx no output load

V_VM= 10 V, I_VCP= 0 to 20 mA, GLx no output load

V_VM= 8 V, I_VCP= 0 to 15 mA, GLx no output load

V_VM= 5.5 V, I_VCP= 0 to 5 mA, GLx no output load

DEAD_TIME = 00b

MIN

8.4

6.3

5.4

4

TYP

MAX

12.5

10

UNIT

11

9

High-side gate drive voltage

with respect to SHx

V_GSH

V

7

8

5

6

9

11

12

9.9

7.9

5.4

10.0

8.0

10.1

8.1

5.6

Low-side gate drive voltage

with respect to PGND

V_GSL

V

5.5

500

1000

2000

4000

1000

500

1000

2000

3000

20

DEAD_TIME = 01b

SPI Device

Gate drive

dead time

t_DEAD

DEAD_TIME = 10b

ns

DEAD_TIME = 11b

H/W Device

SPI Device

H/W Device

TDRIVE = 00b

TDRIVE = 01b

TDRIVE = 10b

TDRIVE = 11b

Peak current

gate drive time

t_DRIVE

ns

µs

t_{DRIVE_MAX}

Peak current gate drive max time

IDRIVEP_Hx = 0000b, 0001b, 0010b, 0011b

10

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Electrical Characteristics (continued)

Over recommended operating conditions 5.5 ≤ V_VM≤ 60 V (unless otherwise noted). Typical limits apply for V_VM= 24 V

PARAMETER

TEST CONDITIONS

IDRIVEP_Hx = 0000b (GHx), V_VM= 24 V

IDRIVEP_Lx = 0000b (GLx), V_VM= 24 V

IDRIVEP_Hx = 0001b (GHx), V_VM= 24 V

IDRIVEP_Lx = 0001b (GLx), V_VM= 24 V

IDRIVEP_Hx = 0010b (GHx), V_VM= 24 V

IDRIVEP_Lx = 0010b (GLx), V_VM= 24 V

MIN

0.45

0.81

1.05

1.17

1.5

TYP

1.5

2.7

3.5

3.9

5

MAX

3.0

5.4

7

UNIT

7.8

10

1.95

6.5

13

IDRIVEP_Hx or IDRIVEP_Lx = 0011b (GHx/GLx), V_VM

24 V

=

3

4.5

10

15

20

30

IDRIVEP_Hx or IDRIVEP_Lx = 0100b (GHx/GLx), V_VM

24 V

IDRIVEP_Hx or IDRIVEP_Lx = 0101b (GHx/GLx), V_VM

24 V

15

50

100

IDRIVEP_Hx or IDRIVEP_Lx = 0110b (GHx/GLx), V_VM

24 V

18

60

120

IDRIVEP_Hx or IDRIVEP_Lx = 0111b (GHx/GLx), V_VM

24 V

19.5

76

65

130

SPI Device

IDRIVEP_Hx or IDRIVEP_Lx = 1000b (GHx/GLx), V_VM

24 V

200

210

260

265

735

800

935

1000

400

IDRIVEP_Hx or IDRIVEP_Lx = 1001b (GHx/GLx), V_VM

24 V

79.8

98.8

100.7

279.3

304

420

IDRIVEP_Hx or IDRIVEP_Lx = 1010b (GHx/GLx), V_VM

24 V

520

Peak source

gate current

I_DRIVEP

mA

IDRIVEP_Hx or IDRIVEP_Lx = 1011b (GHx/GLx), V_VM

24 V

530

IDRIVEP_Hx or IDRIVEP_Lx = 1100b (GHx/GLx), V_VM

24 V

1470

1600

1870

2000

IDRIVEP_Hx or IDRIVEP_Lx = 1101b (GHx/GLx), V_VM

24 V

IDRIVEP_Hx or IDRIVEP_Lx = 1110b (GHx/GLx), V_VM

24 V

355.3

380

IDRIVEP_Hx or IDRIVEP_Lx = 1111b (GHx/GLx), V_VM

24 V

IDRIVE = Tied to AGND (GHx), V_VM= 24 V

0.45

0.81

1.5

2.7

5

3.0

5.4

10

IDRIVE = Tied to AGND (GLx), V_VM= 24 V

IDRIVE = 18 kΩ ± 5% tied to AGND (GHx), V_VM= 24 V

IDRIVE = 18 kΩ ± 5% tied to AGND (GLx), V_VM= 24 V

1.95

6.5

13

IDRIVE = 75 kΩ ± 5% tied to AGND (GHx/GLx), V_VM= 24

V

3

18

76

10

60

20

120

400

H/W Device

IDRIVE = Hi-Z (GHx/GLx), V_VM= 24 V

IDRIVE = 75 kΩ ± 5% tied to DVDD (GHx/GLx), V_VM= 24

V

200

IDRIVE = 18 kΩ ± 5% tied to DVDD (GHx/GLx), V_VM= 24

V

98.8

380

260

520

IDRIVE = Tied to DVDD (GHx/GLx), V_VM= 24 V

1000

2000

11

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ZHCSJU7 –MAY 2019

www.ti.com.cn

Electrical Characteristics (continued)

Over recommended operating conditions 5.5 ≤ V_VM≤ 60 V (unless otherwise noted). Typical limits apply for V_VM= 24 V

PARAMETER

TEST CONDITIONS

IDRIVEN_Hx or IDRIVEN_Lx = 0000b, V_VM= 24 V

IDRIVEN_Hx or IDRIVEN_Lx = 0001b, V_VM= 24 V

IDRIVEN_Hx or IDRIVEN_Lx = 0010b, V_VM= 24 V

IDRIVEN_Hx or IDRIVEN_Lx = 0011b, V_VM= 24 V

IDRIVEN_Hx or IDRIVEN_Lx= 0100b, V_VM= 24 V

IDRIVEN_Hx or IDRIVEN_Lx = 0101b, V_VM= 24 V

IDRIVEN_Hx or IDRIVEN_Lx = 0110b, V_VM= 24 V

IDRIVEN_Hx or IDRIVEN_Lx = 0111b, V_VM= 24 V

IDRIVEN_Hx or IDRIVEN_Lx = 1000b, V_VM= 24 V

IDRIVEN_Hx or IDRIVEN_Lx = 1001b, V_VM= 24 V

IDRIVEN_Hx or IDRIVEN_Lx = 1010b, V_VM= 24 V

IDRIVEN_Hx or IDRIVEN_Lx = 1011b, V_VM= 24 V

IDRIVEN_Hx or IDRIVEN_Lx = 1100b, V_VM= 24 V

IDRIVEN_Hx or IDRIVEN_Lx = 1101b, V_VM= 24 V

IDRIVEN_Hx or IDRIVEN_Lx = 1110b, V_VM= 24 V

IDRIVEN_Hx or IDRIVEN_Lx = 1111b, V_VM= 24 V

IDRIVE = Tied to AGND, V_VM= 24 V

MIN

0.9

2.09

3

TYP

MAX

5.4

12.6

18

UNIT

3

7

10

6

20

36

9

30

54

30

36

39

120

126

156

159

441

480

561

600

0.9

3

100

120

130

400

420

520

530

1470

1600

1870

2000

3

180

216

234

720

756

936

954

2646

2880

3366

3600

5.4

18

SPI Device

Peak sink

gate current

I_DRIVEN

mA

IDRIVE = 18 kΩ ± 5% tied to AGND, V_VM= 24 V

IDRIVE = 75 kΩ ± 5% tied to AGND, V_VM= 24 V

IDRIVE = Hi-Z, V_VM= 24 V

10

6

20

36

H/W Device

36

120

156

600

0.45

1.05

1.5

3

120

400

520

2000

1.5

3.5

5

216

720

936

3600

3.8

7

IDRIVE = 75 kΩ ± 5% tied to DVDD, V_VM= 24 V

IDRIVE = 18 kΩ ± 5% tied to DVDD, V_VM= 24 V

IDRIVE = Tied to DVDD, V_VM= 24 V

IDRIVEP_Hx = 0000b, V_VM= 24 V

IDRIVEP_Hx = 0001b, V_VM= 24 V

SPI Device

H/W Device

SPI Device

H/W Device

IDRIVEP_Hx = 0010b, V_VM= 24 V

10

IDRIVEP_Hx = 0011b, V_VM= 24 V

10

20

Gate holding source

current after t_DRIVE

I_HOLDP

All other IDRIVE settings, V_VM= 24 V

4.5

0.45

1.5

3

15

30

mA

IDRIVE tied to AGND, V_VM= 24 V

1.5

5

3.8

10

IDRIVE = 18 kΩ ± 5% tied to AGND, V_VM= 24 V

IDRIVE = 75 kΩ ± 5% tied to AGND, V_VM= 24 V

All other IDRIVE settings, V_VM= 24 V

10

20

4.5

0.9

2

15

30

IDRIVEP_Hx = 0000b, V_VM= 24 V

3

5.4

12.6

18

IDRIVEP_Hx = 0001b, V_VM= 24 V

7

IDRIVEP_Hx = 0010b, V_VM= 24 V

3

10

IDRIVEP_Hx = 0011b, V_VM= 24 V

6

20

36

Gate holding sink

current after t_DRIVE

I_HOLDN

All other IDRIVE settings, V_VM= 24 V

9

30

54

mA

IDRIVE tied to AGND, V_VM= 24 V

0.9

3

5.4

18

IDRIVE = 18 kΩ ± 5% tied to AGND, V_VM= 24 V

IDRIVE = 75 kΩ ± 5% tied to AGND, V_VM= 24 V

All other IDRIVE settings, V_VM= 24 V

10

6

20

36

9

30

54

IDRIVEP_Hx = 0000b, 0001b, 0010b, 0011b, V_VM= 24 V

All other IDRIVE settings, V_VM= 24 V

9

30

54

mA

A

Gate strong pulldown current

(GHx to SHx and GLx to PGND)

I_STRONG

0.6

2

3.6

280

R_OFF

Gate hold off resistor

GHx to SHx

150

kΩ

GLx to PGND

PROTECTION CIRCUITS

VM falling, UVLO report

VM rising, UVLO recovery

5.2

5.4

5.9

2.9

V_UVLO

VM undervoltage lockout

V

V_UVLO,DVDD

V_{UVLO_HYS}

DVDD undervoltage lockout

VM undervoltage hysteresis

V

Rising to falling threshold

200

mV

12

DRV8340-Q1

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ZHCSJU7 –MAY 2019

Electrical Characteristics (continued)

Over recommended operating conditions 5.5 ≤ V_VM≤ 60 V (unless otherwise noted). Typical limits apply for V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_{UVLO_DEG}

V_CPUV

VM undervoltage deglitch time

VM falling, UVLO report

11.5

µs

V_VM

1.4

+

V_VM

+

V_VM+

3.1

Charge pump undervoltage lockout

High-side gate clamp

VCP falling, CPUV report

V

2.5

Positive clamping voltage

Negative clamping voltage

DLx – VDRAIN

15

16.5

–0.7

300

2.5

19

V_{GS_CLAMP}

150

430

500

Open load active mode detection

threshold

V_OLA

I_OL

mV

mA

SLx – SHx, –1 < SLx < 0

Open load current

OLP_SHRT_DLY = 00b

OLP_SHRT_DLY = 01b

OLP_SHRT_DLY = 10b

OLP_SHRT_DLY = 11b

After t_WAKEand t_SHORTSelapse

OLP_SHRT_DLY = 00b

OLP_SHRT_DLY = 01b

OLP_SHRT_DLY = 10b

OLP_SHRT_DLY = 11b

After t_WAKEelapses

0.25

1.25

5

SPI Device

Open load passive

diagnostic delay

t_OLP

ms

11.5

5

H/W Device

0.1

0.5

Offline short-to-

battery and short-to-

GND diagnostic delay

SPI Device

H/W Device

t_SHORTS

2

4.4

2

VDS_LVL = 0000b

0.01

0.08

0.15

0.2

0.06

0.13

0.2

0.11

0.18

0.25

0.32

0.38

0.52

0.61

0.69

0.77

0.86

1.07

1.29

1.46

1.66

1.88

2.07

0.11

0.18

0.32

0.69

1.29

2.07

VDS_LVL = 0001b

VDS_LVL = 0010b

VDS_LVL = 0011b

0.26

0.31

0.45

0.53

0.6

VDS_LVL = 0100b

0.24

0.38

0.45

0.51

0.59

0.64

0.81

0.97

1.14

1.34

1.52

1.69

0.01

0.08

0.2

VDS_LVL = 0101b

VDS_LVL = 0110b

VDS_LVL = 0111b

SPI Device

VDS_LVL = 1000b

0.68

0.75

0.94

1.13

1.3

VDS_LVL = 1001b

VDS_LVL = 1010b

V_DSovercurrent

trip voltage

V_{VDS_OCP}

VDS_LVL = 1011b

V

VDS_LVL = 1100b

VDS_LVL = 1101b

1.5

VDS_LVL = 1110b

1.7

VDS_LVL = 1111b

1.88

0.06

0.13

0.26

0.6

VDS = Tied to AGND

VDS = 18 kΩ ± 5% tied to AGND

VDS = 75 kΩ ± 5% tied to AGND

VDS = Hi-Z

H/W Device

0.51

0.97

1.69

VDS = 75 kΩ ± 5% tied to DVDD

VDS = 18 kΩ ± 5% tied to DVDD

VDS = Tied to DVDD

OCP_DEG=000b

1.13

1.88

Disabled

2.5

OCP_DEG = 001b

4.75

6.75

8.75

10.25

11.5

16.5

20.5

4.75

OCP_DEG = 010b

OCP_DEG = 011b

V_DSand V_SENSE

overcurrent deglitch

time

SPI Device

H/W Device

t_{OCP_DEG}

OCP_DEG = 100b

µs

OCP_DEG = 101b

OCP_DEG = 110b

OCP_DEG = 111b

13

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ZHCSJU7 –MAY 2019

www.ti.com.cn

Electrical Characteristics (continued)

Over recommended operating conditions 5.5 ≤ V_VM≤ 60 V (unless otherwise noted). Typical limits apply for V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TRETRY = 00b

2

TRERTY = 01b

4

Overcurrent fault retry

time

t_RETRY

SPI Device

ms

TRETRY = 10b

6

TRETRY = 11b

8

T_HYS

Thermal hysteresis

Die temperature, T_J

20

170

150

°C

T_OTSD

T_OTW

Thermal shutdown temperature

Thermal warning temperature

150

130

188

169

7.6 SPI Timing Requirements

Over recommended operating conditions unless otherwise noted. Typical limits apply for V_VM= 24 V

MIN

NOM

MAX

UNIT

ms

ns

t_READY

t_CLK

SPI ready after enable

VM > UVLO, ENABLE = 3.3 V

1

SCLK minimum period

100

50

20

30

t_CLKH

SCLK minimum high time

SCLK minimum low time

SDI input data setup time

SDI input data hold time

SDO output data delay time

nSCS input setup time

ns

t_CLKL

ns

t_{SU_SDI}

t_{H_SDI}

ns

t_{D_SDO}

t_{SU_nSCS}

t_{H_nSCS}

t_{HI_nSCS}

t_{DIS_nSCS}

SCLK high to SDO valid, C_L= 20 pF

nSCS high to SDO high impedance

30

ns

50

ns

nSCS input hold time

ns

nSCS minimum high time before active low

nSCS disable time

500

ns

10

ns

t_{HI_nSCS}t_{SU_nSCS}

t_{H_nSCS}

nSCS

SCLK

t_CLK

t_CLKH

t_CLKL

X

MSB

LSB

X

SDI

t_{SU_SDI}

t_{H_SDI}

Z

MSB

LSB

Z

SDO

t_{D_SDO}

t_{DIS_nSCS}

图 1. SPI Slave Mode Timing Diagram

14

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ZHCSJU7 –MAY 2019

7.7 Typical Characteristics

13.5

13.25

13

30

25

20

15

10

5

12.75

12.5

12.25

12

Ta -40

Ta 125

11.75

11.5

11.25

11

T_A= -40°C

T_A= 25°C

T_A= 125°C

10.75

10.5

0

5

10 15 20 25 30 35 40 45 50 55 60

VM (V)

5

15

25

35

VM (V)

45

55 60

D001

D002

No PWM Switching

ENABLE = 0 V

图 2. VM Operating Supply Current

图 3. VM Sleep Mode Supply Current

10

15

Ta = -40

Ta = 25

Ta = 125

8

6

4

2

12

9

6

3

I_VCP= 0mA

I_VCP= 12.5mA

I_VCP= 25mA

0

13

0

21

29

37

VM (V)

45

53

60

3

6

9

12

15

I_VCP(mA)

D003

D004

T_A= 25°C

VM = 8 V

图 4. VCP w.r.t VM over VM voltage > 13 V

图 5. VCP w.r.t VM over output load I_VCP

15

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ZHCSJU7 –MAY 2019

www.ti.com.cn

8 Detailed Description

8.1 Overview

The DRV8340-Q1 device is an integrated gate driver for three-phase motor driver automotive applications. These

devices decrease system complexity by integrating three independent half-bridge gate drivers, charge pump, and

linear regulator for the supply voltages of the high-side and low-side gate drivers.. A standard serial peripheral

interface (SPI) provides a simple method for configuring the various device settings and reading fault diagnostic

information through an external controller. Alternatively, a hardware interface (H/W) option allows for configuring

the most common settings through fixed external resistors.

The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 1-A

source, 2-A sink peak currents. A doubler charge pump generates the supply voltage of the high-side gate drive.

This charge pump architecture regulates the VCP output voltage for driving high-side power MOSFET. The

supply voltage of the low-side gate driver is generated using a linear regulator from the VM power supply that

regulates for driving low-side power MOSFET. A Smart Gate Drive architecture provides the ability to

dynamically adjust the strength of the gate drive output current which lets the gate driver control the V_DS

switching speed of the power MOSFET. This feature lets the user remove the external gate drive resistors and

diodes, reducing the component count in the bill of materials (BOM), cost, and area of the printed circuit board

(PCB). The architecture also uses an internal state machine to protect against short-circuit events in the gate

driver, control the half-bridge dead time, and protect against dV/dt parasitic turnon of the external power

MOSFET.

In addition to the high level of device integration, the DRV8340-Q1 device provides a wide range of integrated

protection features. These features include power supply undervoltage lockout (UVLO), charge pump

undervoltage lockout (CPUV), V_DSovercurrent monitoring (OCP), gate driver short-circuit detection (GDF), and

overtemperature shutdown (OTW and OTSD). Fault events are indicated by the nFAULT pin with detailed

information available in the SPI registers on the SPI device version.

16

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ZHCSJU7 –MAY 2019

8.2 Functional Block Diagram

VM

VDRAIN

GHA

VM

VCP

HS

VCP

1 …F

>10 …F 4.7 …F

SHA

DLA

VCP

Charge

Pump

CPH

CPL

47 nF

VGLS

LS

GLA

SLA

VGLS

Linear

Regulator

Gate Driver

VM

30 mA

DVDD

AGND

PGND

VCP

HS

DVDD

Linear

Regulator

GHB

1 …F

SHB

DLB

Power

VGLS

LS

Digital

Core

ENABLE

INHA

GLB

SLB

Gate Driver

INLA

VM

VCP

HS

Smart Gate

Drive

GHC

INHB

Protection

SHC

DLC

INLB

Control

Inputs

VGLS

LS

INHC

INLC

GLC

VCC

nFAULT

Gate Driver

Fault Output

R

MODE

nFAULT

SLC

IDRIVE

VDS

图 6. Block Diagram for DRV8340H

17

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ZHCSJU7 –MAY 2019

www.ti.com.cn

Functional Block Diagram (接下页)

VM

VDRAIN

GHA

VM

VCP

HS

VCP

>10 …F 4.7 …F 1 …F

SHA

DLA

VCP

CPH

Charge

Pump

VGLS

LS

47 nF

CPL

GLA

SLA

VGLS

Linear

Gate Driver

Regulator

VM

30 mA

DVDD

AGND

PGND

VCP

HS

DVDD

Linear

Regulator

1 …F

GHB

Power

SHB

DLB

VCC

VGLS

LS

Digital

Core

VSDO

GLB

SLB

0.1 …F

ENABLE

Gate Driver

INHA

VM

Smart Gate

Drive

VCP

HS

INLA

INHB

INLB

GHC

Protection

Control

Inputs

SHC

DLC

VGLS

LS

GLC

INHC

INLC

VCC

PU

Gate Driver

Fault Output

R

VSDO

SDI

SPI

nFAULT

SDO

SLC

SCLK

DVDD

nSCS

图 7. Block Diagram for DRV8340S

8.3 Feature Description

8.3.1 Three Phase Smart Gate Drivers

The DRV8340-Q1 device integrates three, half-bridge gate drivers, each capable of driving high-side and low-

side N-channel power MOSFETs. A doubler charge pump provides the correct gate bias voltage to the high-side

MOSFET across a wide operating voltage range in addition to providing 100% support of the duty cycle. An

internal linear regulator provides the gate bias voltage for the low-side MOSFETs. The half-bridge gate drivers

can be used in combination to drive a three-phase motor or separately to drive other types of loads.

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Feature Description (接下页)

The DRV8340-Q1 device implements a Smart Gate Drive architecture which allows the user to dynamically

adjust the gate drive current without requiring external resistors to limit the gate current. Additionally, this

architecture provides a variety of protection features for the external MOSFETs including automatic dead time

insertion, prevent of parasitic dV/dt gate turnon, and gate fault detection.

8.3.1.1 PWM Control Modes

The DRV8340-Q1 device provides eight different PWM control modes in the SPI device and seven different

modes in the H/W device to support various commutation and control methods. Texas Instruments does not

recommend changing the MODE pin or PWM_MODE register during operation of the power MOSFETs. Set all

INHx and INLx pins to logic low before making a MODE pin or PWM_MODE register change. 表 3 shows the

different mode settings for the SPI device. The MODE bit setting of 100b is not available in the H/W device.

表 3. 6x PWM Mode Truth Table

H/W DEVICE

Tied to AGND

18 kΩ to AGND

75 kΩ to AGND

Hi-Z

SPI DEVICE

000b

MODE SETTINGS

6x PWM

001b

3x PWM

010b

1x PWM

011b

Independent half-bridge (for all three half-bridges)

Phases A and B are independent half-bridges, Phase C is independent FET

Phases B and C are independent half-bridges, Phase A is independent FET

Phases A is independent half-bridge, Phase B and C are independent FET

Independent MOSFET (for all three half-bridges)

Not Available

75 kΩ to DVDD

18 kΩ to DVDD

0.47 kΩ to DVDD

100b

101b

110b

111b

8.3.1.1.1 6x PWM Mode (PWM_MODE = 000b or MODE Pin Tied to AGND)

In 6x PWM mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The

corresponding INHx and INLx signals control the output state as listed in 表 4.

表 4. 6x PWM Mode Truth Table

INLx

INHx

GLx

L

GHx

SHx + DLx

0

1

0

1

0

1

L

H

L

Hi-Z

H

L

H

L

Hi-Z

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6-PWM

INHA

INLA

INHB

INLB

INHC

INLC

MCU PWM

图 8. 6-PWM Mode

8.3.1.1.2 3x PWM Mode (PWM_MODE = 001b or MODE Pin = 18 kΩ to AGND)

In 3x PWM mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx

pin is used to put the half bridge in the Hi-Z state. If the Hi-Z state is not required, tie all INLx pins to logic high.

The corresponding INHx and INLx signals control the output state as listed in 表 5.

表 5. 3x PWM Mode Truth Table

INLx

INHx

GLx

L

GHx

L

SHx + DLx

0

1

X

0

1

Hi-Z

L

H

L

H

3-PWM

INHA

MCU PWM

INLA

INHB

INLB

INHC

INLC

图 9. 3-PWM Mode

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8.3.1.1.3 1x PWM Mode (PWM_MODE = 010b or MODE Pin = 75 kΩ to AGND)

In 1x PWM mode, the DRV8340-Q1 device uses 6-step block commutation tables that are stored internally. This

feature allows for a three-phase BLDC motor to be controlled using one PWM sourced from a simple controller.

The PWM is applied on the INHA pin and determines the output frequency and duty cycle of the half-bridges.

The half-bridge output states are managed by the INLA, INHB, and INLB pins which are used as state logic

inputs. The state inputs can be controlled by an external controller or connected directly to the digital outputs of

the Hall effect sensor from the motor (INLA = HALL_A, INHB = HALL_B, INLB = HALL_C). The 1x PWM mode

usually operates with synchronous rectification (low-side MOSFET recirculation); however, the mode can be

configured to use asynchronous rectification (MOSFET body diode freewheeling) on SPI devices. This

configuration is set using the 1PWM_COM bit in the SPI registers.

The INHC input controls the direction through the 6-step commutation table which is used to change the direction

of the motor when Hall effect sensors are directly controlling the state of the INLA, INHB, and INLB inputs. Tie

the INHC pin low if this feature is not required.

The INLC input brakes the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs

when the INLC pin is pulled low. This brake is independent of the state of the other input pins. Tie the INLC pin

high if this feature is not required. In the SPI device, the brake and coast mode can also be selected by the

1PWM_BRAKE register (see 表 22).

表 6. Synchronous 1x PWM Mode

LOGIC AND HALL INPUTS

INHC = 0

GATE DRIVE OUTPUTS⁽¹⁾

INHC = 1

PHASE A

PHASE B PHASE C

STATE

DESCRIPTION

INLA

INHB

INLB

INLA

INHB

INLB

GHA

GLA

GHB

GLB

GHC

GLC

Stop

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

L

PWM

L

!PWM

L

Stop

Align

L

H

L

H

Align

1

2

3

4

5

6

PWM

!PWM

L

H

B → C

A → C

A → B

C → B

C → A

B → A

PWM

L

!PWM

L

H

L

H

PWM

L

!PWM

L

H

L

H

PWM

!PWM

(1) !PWM is the inverse of the PWM signal.

表 7. Asynchronous 1x PWM Mode 1PWM_COM = 1 (SPI Only)

LOGIC AND HALL INPUTS

GATE DRIVE OUTPUTS

PHASE B PHASE C

INHC = 0

INHC = 1

PHASE A

STATE

DESCRIPTION

INLA

INHB

INLB

INLA

INHB

INLB

GHA

GLA

L

GHB

GLB

L

GHC

GLC

L

Stop

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

L

PWM

L

Stop

Align

L

H

L

H

L

Align

1

2

3

4

5

6

L

PWM

L

B → C

A → C

A → B

C → B

C → A

B → A

PWM

L

H

L

PWM

L

H

L

PWM

L

图 10 and 图 11 show the different possible configurations in 1x PWM mode.

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INHA

INLA

INHB

INLB

INHC

INLC

INHA

INLA

INHB

INLB

INHC

INLC

MCU_PWM

PWM

MCU_PWM

MCU_GPIO

PWM

H

STATE0

STATE1

STATE2

DIR

STATE0

STATE1

STATE2

DIR

H

BLDC Motor

H

MCU_GPIO

nBRAKE

MCU_GPIO

nBRAKE

图 10. 1x PWM—Simple Controller

图 11. 1x PWM—Hall Effect Sensor

8.3.1.1.4 Independent Half-Bridge PWM Mode (PWM_MODE = 011b or MODE Pin is > 1.5 MΩ to AGND or Hi-Z)

In independent half-bridge PWM mode, the INHx pin controls each half-bridge independently and supports two

output states: low or high. The corresponding INHx and INLx signals control the output state as listed in 表 8.

The INLx pin is used to change the half-bridge to high impedance. If the high-impedance (Hi-Z) state is not

required, tie all INLx pins logic high.

表 8. Independent Half-Bridge Mode Truth Table

INLx

INHx

GLx

L

GHx

L

0

1

X

0

1

H

L

H

8.3.1.1.5 Phases A and B are Independent Half-Bridges, Phase C is Independent FET (MODE = 100b)

In this mode, phases A and B are independent half-bridge control, with independent fault handling and dead time

enforcement by the device. Phase C is independent FET mode where the dead time inserted by the device is

bypassed and both MOSFETs can be turned-on at the same time. This mode is not available in the H/W version.

8.3.1.1.6 Phases B and C are Independent Half-Bridges, Phase A is Independent FET (MODE = 101b or MODE Pin is

75 kΩ to DVDD)

In this mode, phases B and C are independent half-bridge control, with independent fault handling and dead time

enforcement by the device. Phase A is independent FET mode where the dead time inserted by the device is

bypassed and both MOSFETs can be turned-on at the same time.

8.3.1.1.7 Phases A is Independent Half-Bridge, Phases B and C are Independent FET (MODE = 110b or MODE Pin is

18 kΩ to DVDD)

In this mode, phase A is independent half-bridge control, with dead time enforcement by the device. Phases B

and C are independent FET mode where the dead time is bypassed and both MOSFETs in a given phase can

be turned-on at the same time. Fault handling is also done independently for each FET in phases B and C.

8.3.1.1.8 Independent MOSFET Drive Mode (PWM_MODE = 111b or MODE Pin = 0.47 kΩ to DVDD)

In independent MOSFET drive mode, the INHx and INLx pins control the outputs, GHx and GLx, respectively.

This control mode lets the DRV8340-Q1 device drive separate high-side and low-side loads with each half-

bridge. These types of loads include unidirectional brushed DC motors, solenoids, and low-side and high-side

switches. In this mode, turning on both the high-side and low-side MOSFETs at the same time in a given half-

bridge gate driver is possible to use the device as a high-side or low-side driver. The dead time (t_DEAD) is

bypassed in the mode and must be inserted by the external MCU.

表 9. Independent PWM Mode Truth Table

INLx

INHx

GLx

L

GHx

L

0

1

0

1

0

1

L

H

L

H

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图 12 shows how the DRV8340-Q1 device can be used to connect a high-side load and a low-side load at the

same time with one half-bridge and drive the loads independently. In this mode, the VDS monitors are active for

both the MOSFETs to protect from an overcurrent condition.

Disable

+

V_DS

œ

VM

VDRAIN

VCP

GHx

Load

HS

INHx

SHx

VGLS

INLx

GLx

LS

Load

Gate Driver

Disable

SLx/SPx

+

V_DS

œ

图 12. Independent PWM High-Side and Low-Side Drivers

If the half-bridge is used to implement only a high-side or low-side driver, using the VDS monitors to help protect

from an overcurrent condition is possible as shown in 图 13 or 图 14. The unused gate driver can stay

disconnected.

+

V_DS

œ

VM

VDRAIN

VCP

HS

VCP

HS

GHx

SHx

GHx

SHx

Load

INHx

INLx

INHx

INLx

VGLS

LS

VGLS

LS

GLx

Load

Gate Driver

SLx/SPx

Gate Driver

SLx/SPx

+

V_DS

œ

图 13. One High-Side Driver

图 14. One Low-Side Driver

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图 15 shows how the DRV8340-Q1 device can be used to connect a solenoid load where both the high-side and

low-side MOSFETs can be turned on at the same time to drive the load without causing shoot-through. TI

recommends having the external diodes for current recirculation. If a half-bridge is not used, the gate pins (GHx

and GLx) can stay unconnected and the sense pins (SHx and DLx) can be tied directly or with a resistor to GND.

VDRAIN

HS_VSD

+

GHx

SHx

GHx

SHx

GHx

SHx

œ

PH_B

PH_C

PH_A

DLx

GLx

DLx

GLx

DLx

GLx

LS_VSD

+

œ

SLx

图 15. Solenoid Drive Configuration

8.3.1.2 Device Interface Modes

The DRV8340-Q1 device supports two different interface modes (SPI and hardware) to let the end application

design for either flexibility or simplicity. The two interface modes share the same four pins, allowing the different

versions to be pin-to-pin compatible. This compatibility lets application designers evaluate with one interface

version and potentially switch to another with minimal modifications to their circuit design and layout.

8.3.1.2.1 Serial Peripheral Interface (SPI)

The SPI devices support a serial communication bus that lets an external controller send and receive data with

the DRV8340-Q1 device. This support lets the external controller configure device settings and read detailed

fault information. The interface is a four wire interface using the SCLK, SDI, SDO, and nSCS pins which are

described as follows:

•

The SCLK pin is an input that accepts a clock signal to determine when data is captured and propagated on

the SDI and SDO pins.

•

The SDI pin is the data input.

The SDO pin is the data output. The SDO pin has a push-pull output structure.

The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the

DRV8340-Q1 device.

For more information on the SPI, see the SPI Communication section.

8.3.1.2.2 Hardware Interface

Hardware interface devices convert the four SPI pins into four resistor-configurable inputs which are IDRIVE,

MODE, and VDS. This conversion lets the application designer configure the most common device settings by

tying the pin logic high or logic low, or with a simple pullup or pulldown resistor. This removes the requirement for

an SPI bus from the external controller. General fault information can still be obtained through the nFAULT pin.

•

The IDRIVE pin configures the gate drive current strength.

The MODE pin configures the PWM control mode.

The VDS pin configures the voltage threshold of the V_DSovercurrent monitors.

For more information on the hardware interface, see the Pin Diagrams section.

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SCLK

SDI

SPI

Hardware

Interface

DVDD

IDRIVE

VSDO

DVDD

SDO

MODE

VDS

DVDD

nSCS

R_VDS

图 16. SPI

图 17. Hardware Interface

8.3.1.3 Gate Driver Voltage Supplies

The voltage supply for the high-side gate driver is created using a doubler charge pump that operates from the

VM voltage supply input. The charge pump lets the gate driver correctly bias the high-side MOSFET gate with

respect to the source across a wide input supply voltage range. The charge pump is regulated to keep a fixed

output voltage V_VCPand supports an average output current I_{GATE_HS}. The charge pump is continuously

monitored for undervoltage events to prevent under-driven MOSFET conditions. The charge pump requires a

ceramic capacitor between the VM and VCP pins to act as the storage capacitor. Additionally, a flying capacitor

is required between the CPH and CPL pins.

VM

C_VCP

VCP

CPH

VM

Charge

Pump

Control

C_FLY

CPL

图 18. Charge Pump Architecture

The voltage supply of the low-side gate driver is created using a linear regulator that operates from the VM

voltage supply input. The linear regulator lets the gate driver correctly bias the low-side MOSFET gate with

respect to ground. The linear regulator output is V_GSLand supports an output current I_{GATE_LS}

.

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8.3.1.4 Smart Gate Drive Architecture

The DRV8340-Q1 gate drivers use an adjustable, complimentary, push-pull topology for both the high-side and

low-side drivers. This topology allows for both a strong pullup and pulldown of the external MOSFET gates.

Gate Drive (Internal)

MOSFET (External)

V_GATE

V_DRAIN

OFF

ON

OFF

I_SOURCE

OFF

图 19. Charge Pump Architecture

Additionally, the gate drivers use a Smart Gate Drive architecture to provide additional control of the external

power MOSFETs, additional steps to protect the MOSFETs, and optimal tradeoffs between efficiency and

robustness. This architecture is implemented through two components called IDRIVE and TDRIVE which are

described in the IDRIVE: MOSFET Slew-Rate Control section and TDRIVE: MOSFET Gate Drive Control

section. 图 20 shows the high-level functional block diagram of the gate driver.

The IDRIVE gate drive current and TDRIVE gate drive time should be initially selected based on the parameters

of the external power MOSFET used in the system and the desired rise and fall times (see the Application and

Implementation section).

The high-side gate driver also implements a Zener clamp diode to help protect the external MOSFET gate from

overvoltage conditions in the case of external short-circuit events on the MOSFET.

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VCP

VGLS

Linear

Regulator

VGLS

INHx

INLx

VM

AGND

Control

Inputs

GHx

SHx

Level

Shifters

150 kꢀ

+

^GSœ

V

VGLS

Digital

Core

GLx

SLx

Level

Shifters

150 kꢀ

+

^GSœ

V

PGND

AGND

图 20. Gate Driver Block Diagram

8.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control

The IDRIVE component implements adjustable gate drive current to control the MOSFET V_DSslew rates. The

MOSFET V_DSslew rates are a critical factor for optimizing radiated emissions, energy, and duration of diode

recovery spikes, dV/dt gate turnon resulting in shoot-through, and switching voltage transients related to

parasitics in the external half-bridge. The IDRIVE component operates on the principal that the MOSFET V_DS

slew rates are predominately determined by the rate of gate charge (or gate current) delivered during the

MOSFET Q_GDor Miller charging region. By letting the gate driver adjust the gate current, the gate driver can

effectively control the slew rate of the external power MOSFETs.

The IDRIVE component lets the DRV8340-Q1 device dynamically switch between gate drive currents either

through a register setting on SPI devices or the IDRIVE pin on hardware interface devices. The SPI devices

provide 16 I_DRIVEsettings ranging from 1.5-mA to 1-A source and 3-mA to 2-A sink. Hardware interface devices

provide 7 I_DRIVEsettings within the same ranges. The setting of the gate drive current is delivered to the gate

during the turnon and turnoff of the external power MOSFET for the t_DRIVEduration. After the MOSFET turnon or

turnoff, the gate driver switches to a smaller hold current (I_HOLD) to improve the gate driver efficiency. In the event

of an overcurrent condition, the IDRIVE component is automatically decreased to help prevent device damage.

For additional details on the IDRIVE settings, see the Register Maps section for the SPI devices and the Pin

Diagrams section for the hardware interface devices.

8.3.1.4.2 TDRIVE: MOSFET Gate Drive Control

The TDRIVE component is an integrated gate drive state machine that provides automatic dead time insertion

through handshaking between the high-side and low-side gate drivers, parasitic dV/dt gate turnon prevention,

and MOSFET gate fault detection.

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The first component of the TDRIVE state machine is automatic dead time insertion. Dead time is period of time

between the switching of the external high-side and low-side MOSFETs to make sure that they do not cross

conduct and cause shoot-through. The DRV8340-Q1 device uses V_GSvoltage monitors to measure the MOSFET

gate-to-source voltage and determine the correct time to switch instead of relying on a fixed time value. This

feature lets the dead time of the gate driver adjust for variation in the system such as temperature drift and

variation in the MOSFET parameters. An additional digital dead time (t_DEAD) can be inserted and is adjustable

through the registers on SPI devices.

The second component of the TDRIVE state machine is parasitic dV/dt gate turnon prevention. To implement this

component, the TDRIVE state machine enables a strong pulldown current (I_STRONG) on the opposite MOSFET

gate whenever a MOSFET is switching. The strong pulldown occurs for the TDRIVE duration. This feature helps

remove parasitic charge that couples into the MOSFET gate when the voltage half-bridge switch node slews

rapidly.

The third component implements a gate-fault detection scheme to detect pin-to-pin solder defects, a MOSFET

gate failure, or a MOSFET gate stuck-high or stuck-low voltage condition. This implementation is done with a pair

of V_GSgate-to-source voltage monitors for each half-bridge gate driver. When the gate driver receives a

command to change the state of the half-bridge it starts to monitor the gate voltage of the external MOSFET. If,

at the end of the t_DRIVEperiod, the V_GSvoltage has not increased the correct threshold, the gate driver reports a

fault. To make sure that a false gate drive fault (GDF) is not detected, a t_DRIVEtime should be selected that is

longer than the time required to charge or discharge the MOSFET gate. The t_DRIVEtime does not increase the

PWM time and will terminate if another PWM command is received while active. In the SPI device, for IDRIVE bit

settings of 0000b, 0001b, 0010b, and 0011b, a longer t_DRIVEtime of 20-µs is automatically selected by the

TDRIVE_MAX bit. If the 20-µs t_DRVIEtime is not required, write a 0 to the TDRIVE_MAX bit to disable it and set

the t_DRIVEtime by the TDRIVE bits. For all other IDRIVE settings, writing to the TDRIVE_MAX bit is disabled. This

option is not available in the H/W device.

For additional details on the TDRIVE settings, see the Register Maps section for SPI devices and the Pin

Diagrams section for hardware interface devices. 图 21 shows an example of the TDRIVE state machine in

operation.

V

INHx

V

INLx

V

GHx

t_DEAD

I_HOLD

t_DEAD

I

t

I

HOLD

DRIVE

STRONG

I

GHx

I

t

I

HOLD

DRIVE

V

GLx

t_DEAD

I_HOLD

I

t

I

HOLD

DRIVE

STRONG

I

HOLD

DRIVE

t

DRIVE

图 21. TDRIVE State Machine

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8.3.1.4.3 Propagation Delay

The propagation delay time (t_pd) is measured as the time between an input logic edge to a detected output

change. This time has three parts consisting of the digital input deglitcher delay, the digital propagation delay,

and the delay through the analog gate drivers.

The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate

drivers. To support multiple control modes and dead time insertion, a small digital delay is added as the input

command propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to

the overall propagation delay of the device.

8.3.1.4.4 MOSFET V_DSMonitors

The gate drivers implement adjustable V_DSvoltage monitors to detect overcurrent or short-circuit conditions on

the external power MOSFETs. When the monitored voltage is greater than the V_DStrip point (V_{VDS_OCP}) for

longer than the deglitch time (t_OCP), an overcurrent condition is detected and action is taken according to the

device V_DSfault mode.

The high-side V_DSmonitors measure the voltage between the VDRAIN and SHx pins.The low-side V_DSmonitor

measures between the DLx and SLx pins.

The V_{VDS_OCP}threshold is programmable from 0.06 V to 1.88 V. For additional information on the V_DSmonitor

levels, see the Register Maps section for SPI devices and in the Pin Diagrams section hardware interface device.

VM

VDRAIN

+

V

+

^DSœ

V

^DSœ

V

VDS_OCP

GHx

SHx

GLx

+

^DSœ

+

^DSœ

V

VDS_OCP

SLx

PGND

图 22. DRV8340-Q1 V_DSMonitors

8.3.1.4.5 VDRAIN Sense Pin

The DRV8340-Q1 device provides a separate sense pin for the common point of the high-side MOSFET drain.

This pin is called VDRAIN. This pin lets the sense line for the overcurrent monitors (VDRAIN) and the power

supply (VM) stay separate and prevent noise on the VDRAIN sense line. This separation also lets

implementation of a small filter on the gate driver supply (VM) or insertion of a boost converter to support lower

voltage operation if desired. Care must still be used when designing the filter or separate supply because VM is

still the reference point for the VCP charge pump that supplies the high-side gate drive voltage (V_GSH). The VM

supply must not drift too far from the VDRAIN supply to avoid violating the V_GSvoltage specification of the

external power MOSFETs.

8.3.1.4.6 nFAULT Pin

The nFAULT pin has an open-drain output and should be pulled up to a 5 V or 3.3 V supply. When a fault is

detected, the nFAULT line is logic low. For a 3.3-V pullup the nFAULT pin can be tied to the DVDD pin with a

resistor (refer to the Application and Implementation section). For a 5-V pullup an external 5-V supply must be

used.

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Output

nFAULT

图 23. nFAULT Pin

During the power-up sequence, or when going from sleep mode, the digital core of the device is enabled to a VM

voltage of approximately 3.3 V and the device is fully operational after VM exceeds 5.5 V. After the digital core is

alive if the VM does not exceed 5.5 V within 100-µs the device will flag a UVLO fault. In the H/W device, the

nFAULT pin is driven low. In the SPI device, the FAULT and ULVO bits will be latched high

8.3.2 DVDD Linear Voltage Regulator

A 3.3-V, 30-mA linear regulator is integrated into the DRV8340-Q1 device and is available for use by external

circuitry. This regulator can provide the supply voltage for a low-power MCU or other circuitry supporting low

current. The output of the DVDD regulator should be bypassed near the DVDD pin with a X5R or X7R, 1-µF, 6.3-

V ceramic capacitor routed directly back to the adjacent AGND ground pin.

The DVDD nominal, no-load output voltage is 3.3 V. When the DVDD load current exceeds 30 mA, the regulator

functions like a constant-current source. The output voltage drops significantly with a current load greater than 30

mA.

VM

REF

+

œ

DVDD

AGND

3.3 V, 30 mA

0.1 …F

图 24. DVDD Linear Regulator Block Diagram

Use 公式 1 to calculate the power dissipated in the device by the DVDD linear regulator.

P = V_VM- V_DVDDì I

(

)

DVDD

(1)

(2)

For example, at a V_VMof 24 V, drawing 20 mA out of DVDD results in a power dissipation as shown in 公式 2.

P = 24 V - 3.3 V ì 20 mA = 414 mW

(

)

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8.3.3 Pin Diagrams

图 25 shows the input structure for the logic level pins, INHx, INLx, ENABLE, nSCS, SCLK, and SDI. The input

can be driven with a voltage or external resistor.

DVDD

STATE

V_IH

RESISTANCE

Tied to DVDD

Tied to AGND

INPUT

Logic High

Logic Low

V_IL

100 kꢀ

图 25. Logic-Level Input Pin Structure

图 26 shows the structure of the seven level input pins, MODE, IDRIVE and VDS, on hardware interface devices.

The input can be set with an external resistor.

IDRIVE

1/2 A

VDS

MODE

Disabled

Independent MOSFET

+

œ

STATE

V_I7

RESISTANCE

Ph A as Ind. Half bridge

Ph B & Ph C as Ind. FET

260 / 520 mA

200 / 400 mA

60 / 120 mA

10 / 20 mA

5 / 10 mA

1.88 V

1.13 V

0.60 V

0.26 V

0.13 V

0.06 V

0.47 kΩ ± 5%

to DVDD (1)

+

DVDD

œ

18 kꢀ 5%

to DVDD

V_I6

V_I5

V_I4

V_I3

V_I2

V_I1

Ph B & Ph C as Ind. Half

bridge, Ph A as Ind. FET

+

75 kꢀ 5%

to DVDD

73 kꢀ

œ

Independent

Half-Bridge

Hi-Z (>1.5 MΩ

to AGND)

73 kꢀ

+

75 kꢀ 5%

to AGND

œ

1x PWM

3x PWM

6x PWM

18 kΩ ±5%

to AGND

+

Tied to AGND

œ

+

œ

1.5 / 3 mA

(1)

图 26. Seven Level Input Pin Structure

图 27 shows the structure of the open-drain output pin, nFAULT. The open-drain output requires an external

pullup resistor to function correctly.

(1) V_I7requires a 0.47 kΩ resistor to DVDD for MODE input pin. VDS and IDRIVE pins can be directly tied to DVDD.

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DVDD

R

PU

STATE

No Fault

Fault

STATUS

Inactive

Active

OUTPUT

Active

Inactive

图 27. Open-Drain Output Pin Structure

8.3.4 Gate Driver Protective Circuits

The DRV8340-Q1 device is protected against VM undervoltage, charge pump undervoltage, MOSFET VDS

overcurrent, gate driver shorts, and overtemperature events. The DRV8340-Q1 device also provides a detection

mechanism for open-load, offline short-to-supply, and offline short-to-ground conditions. When a fault occurs, the

individual fault bit is set high along with the global FAULT bit in the FAULT status register for the SPI device. The

FAULT bit is OR’ed with all the other individual status bits. In the H/W device, only the nFAULT pin is driven low

during a fault condition. Some of the protection and detection features can be disabled through SPI in the SPI

device, or the nDIAG pin in the H/W device

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8.3.4.1 VM Supply Undervoltage Lockout (UVLO)

If at any time the input supply voltage on the VM pin falls lower than the V_UVLOthreshold, all of the external

MOSFETs are disabled, the charge pump is disabled, and the nFAULT pin is driven low. The FAULT and

VM_UVLO bits are also latched high in the registers on SPI devices. Normal operation starts again (gate driver

operation and the nFAULT pin is released) when the VM undervoltage condition clears. The VM_UVLO bit stays

set until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (t_RST).

8.3.4.2 VCP Charge Pump Undervoltage Lockout (CPUV)

If at any time the voltage on the VCP pin (charge pump) falls lower than the CPUV threshold voltage of the

charge pump, all of the external MOSFETs are disabled and the nFAULT pin is driven low. The FAULT and

CPUV bits are also latched high in the registers in the SPI device. Normal operation starts again (gate driver

operation and the nFAULT pin is released) when the VCP undervoltage condition is removed. The FAULT and

CPUV bits stay set until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (t_RST). Setting the

DIS_CPUV bit high on the SPI devices disables this protection feature. If the DIS_CPUV bit is set high and a

charge pump undervoltage condition occurs, the device keeps operating but the CPUV fault bit is set high in the

SPI register until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (t_RST). CPUV protection cannot

be disabled in the H/W device.

8.3.4.3 MOSFET V_DSOvercurrent Protection (VDS_OCP)

A MOSFET overcurrent event is sensed by monitoring the VDS voltage drop across the external MOSFET

R_DS(on). If the voltage across an enabled MOSFET exceeds the V_{VDS_OCP}threshold for longer than the t_{OCP_DEG}

deglitch time, a VDS_OCP event is recognized and action is done according to the OCP_MODE. On hardware

interface devices, the V_{VDS_OCP}threshold is set with the VDS pin, the t_{OCP_DEG}is fixed at 4 μs, and the

OCP_MODE is configured for latched shutdown but can be disabled by tying the VDS pin to DVDD. In the SPI

device, the V_{VDS_OCP}threshold is set through the VDS_LVL SPI register, the t_{OCP_DEG}is set through the

OCP_DEG bits in the SPI register, and the OCP_MODE bit can operate in four different modes: V_DSlatched

shutdown, V_DSautomatic retry, V_DSreport only, and V_DSdisabled.

8.3.4.3.1 V_DSLatched Shutdown (OCP_MODE = 00b)

After a VDS_OCP event in this mode, all external MOSFETs are disabled and the nFAULT pin is driven low. The

FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal

operation starts again (gate driver operation and the nFAULT pin is released) when the VDS_OCP condition

clears and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (t_RST).

This is the default mode in both the H/W and SPI device options.

8.3.4.3.2 V_DSAutomatic Retry (OCP_MODE = 01b)

After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.

The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal

operation starts again automatically (gate driver operation and the nFAULT pin is released) after the t_RETRYtime

elapses. The FAULT, VDS_OCP, and MOSFET OCP bits stay latched until the t_RETRYperiod expires.

8.3.4.3.3 V_DSReport Only (OCP_MODE = 10b)

No protective action occurs after a VDS_OCP event in this mode. The overcurrent event is reported by driving

the nFAULT pin low and latching the FAULT, VDS_OCP, and corresponding MOSFET OCP bits high in the SPI

registers. The gate drivers continue to operate as usual. The external controller manages the overcurrent

condition by acting appropriately. The reporting clears (nFAULT pin is released) when the VDS_OCP condition

clears and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (t_RST).

8.3.4.3.4 V_DSDisabled (OCP_MODE = 11b)

No action occurs after a VDS_OCP event in this mode. The VDS overcurrent monitor is disabled for all three

half-bridges at the same time and the DIS_VDS_x bits are locked. In the H/W device, VDS_OCP is disabled for

all three half-bridges at the same time through the VDS pin.

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8.3.4.4 Gate Driver Fault (GDF)

The GHx and GLx pins are monitored such that if the voltage on the external MOSFET gate does not increase or

decrease after the t_DRIVEtime, a gate driver fault is detected. This fault may be encountered if the GHx or GLx

pins are shorted to the PGND, SHx, SLx, or VM pins. Additionally, a gate driver fault may be encountered if the

selected IDRIVE setting is not sufficient to turn on the external MOSFET within the t_DRIVEperiod. After a gate

drive fault is detected, all external MOSFETs are disabled and the nFAULT pin driven low. In addition, the

FAULT, GDF, and corresponding VGS bits are latched high in the SPI registers. Normal operation starts again

(gate driver operation and the nFAULT pin is released) when the gate driver fault condition is removed and a

clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (t_RST). In the SPI

device, setting the DIS_GDF bit high disables this protection feature. If DIS_GDF bit is set high and a gate drive

fault occurs, the device keeps operating but the appropriate VGS fault bit is set high in the SPI register until

cleared through the CLR_FLT bit or an ENABLE pin reset pulse (t_RST). GDF cannot be disabled in the H/W

device option.

Gate driver faults can indicate that the selected IDRIVE or t_DRIVEsettings are too low to slew the external

MOSFET in the desired time. Increasing either the IDRIVE or t_DRIVEsetting can resolve gate driver faults in these

cases. Alternatively, if a gate-to-source short occurs on the external MOSFET, a gate driver fault is reported

because of the MOSFET gate not turning on. The t_DRIVEtime also refers to the GDF fault blanking time.

Fault handling is done as follows based on the MODE setting:

•

In 6x, 3x, and 1x PWM modes a GDF fault in one of the external MOSFETs turns off all the MOSFETs.

In independent half-bridge mode (MODE = 011b or MODE pin is Hi-Z) a GDF fault in one half-bridge only

disables both the MOSFETs in that half-bridge. The MOSFETs in the other half-bridges operate as

commanded.

•

In independent MOSFET mode (MODE = 111b or MODE pin tied to DVDD) a GDF fault in a MOSFET only

disables that particular MOSFET. All the other MOSFETs operate as commanded. The same fault handling

scheme applies for MODE = 100b, 101b, and 110b.

•

A GDF fault in phases set as Independent half-bridge disables both MOSFETs in that particular phase.

A GDF fault in phases set as Independent FET mode disables the MOSFET where the fault occurred.

8.3.4.5 Thermal Warning (OTW)

If the die temperature exceeds the trip point of the thermal warning (T_OTW), the OTW bit is set in the registers of

SPI devices. The device performs no additional action and continues to function. When the die temperature falls

lower than the hysteresis point of the thermal warning, the OTW bit clears automatically. The OTW bit can also

be configured to report on the nFAULT pin by setting the OTW_REP bit to 1 through the SPI registers. OTW is

not available in the H/W device.

8.3.4.6 Thermal Shutdown (OTSD)

If the die temperature exceeds the trip point of the thermal shutdown limit (T_OTSD), all the external MOSFETs are

disabled, the charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and OTSD

bits are latched high. This protection feature cannot be disabled. The overtemperature protection can operate in

two different modes.

8.3.4.6.1 Latched Shutdown (OTSD_MODE = 0b)

In latched shutdown mode, after a OTSD event, normal operation starts again (motor driver operation and the

nFAULT line released) when the OTSD condition is removed and a clear faults command has been issued either

through the CLR_FLT bit or an nSLEEP reset pulse. This is the default mode for a OTSD event in the SPI

device.

When the DRV8340-Q1 device hits thermal shutdown, the OTSD and FAULT bits are latched in the SPI register.

Clearing the fault through the CLR_FLT bit or an nSLEEP reset pulse will clear the OSTD and FAULT bits. When

the DRV8340-Q1 device hits thermal shutdown, the device will disable the charge pump without triggering

CPUV. The charge pump will be enabled again when the OTSD and FAULT bits are cleared through the

CLR_FLT bit or an nSleep reset Pulse.

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8.3.4.6.2 Automatic Recovery (OTSD_MODE = 1b)

In automatic recovery mode, after a OTSD event, normal operation starts again (motor driver operation and the

nFAULT line released) when the junction temperature falls to less than the overtemperature threshold limit minus

the hysteresis (T_OTSD– T_HYS). The OTSD bit stays latched high indicating that a thermal event occurred until a

clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse. This is the default

mode for a OTSD event in the H/W device.

8.3.4.7 Open Load Detection (OLD)

If the load is disconnected from the device, an open load is detected and the nFAULT pin is latched low. In the

DRV8340-Q1 device, The FAULT, OL_SHT, and the corresponding open load (OL_PH_x) bits in the SPI register

are latched high. When the open-load condition is removed, and the MCU clears the fault through either the

CLR_FLT bit or an ENABLE-pin reset pulse (t_RST), the device is ready to drive the motor based on the input

commands.

8.3.4.7.1 Open Load Detection in Passive Mode (OLP)

In open load detection in passive mode, open load diagnosis is performed without the motor in motion. If the

motor is disconnected from the device an open load is detected and the nFAULT pin will latch low until a clear

faults command is issued by the MCU either through the CLR_FLT bit or an ENABLE reset pulse. The fault also

clears when the device is power cycled or comes out of sleep mode. OLP is designed for applications having

capacitance less than the values listed in 表 11 between motor phase pins to ground.

表 11. Open Load Passive Diagnostic Run-Time

Capacitance (nF)

OLP_SHTS_DLY (ms)

5

0.25

1.25

5

26

110

270

11.5

When the open load test is running, all external MOSFETs are disabled. For the H/W device option, at power-up

or after going from sleep mode, the offline short-to-supply (SHT_BAT) and short-to-ground (SHT_GND)

diagnostics run first followed by the OLP diagnostic if the nDIAG pin is left as no connect or tied to GND. If the

nDIAG pin is tied to DVDD (or an external 3.3 V) the open load test is not performed. If a short condition is

detected, the OLP diagnostic is not run (see Offline Shorts Diagnostics). If a short condition and open load

occurs on a given phase at device power-up, for example, only the short condition is reported on the nFAULT pin

and through the SPI fault register. In the SPI device option the OLP test is performed when commanded through

SPI. If both short and OLP diagnostics are enabled simultaneously and a short condition is detection, only the

short condition is reported on the nFAULT pin and through the SPI fault register.

The sequence to perform open load diagnostics in passive mode is as follows:

1. Device powered up (ENABLE = 1).

2. Mode is selected by SPI.

3. Hi-Z all three half-bridges by turning-off all the external MOSFETs.

4. Write a 1 to the EN_OLP bit in the SPI register and OLP is performed.

–

If an open load is detected, the nFAULT pin is driven low, and the FAULT bit, the OLD bit, and the

respective OL_PH_x bit are latched high. When the open load condition is removed, a clear faults

command must be issued by the MCU either through the CLR_FLT bit or an ENABLE reset pulse which

resets the OL_PH_x register bit and causes the nFAULT pin to go high.

–

If open load is not detected, the EN_OLP bits return to default setting (0b) after t_OLexpires.

The EN_OLP register keeps the written command until the diagnostic is complete. The half bridges must stay in

Hi-Z state for the entire duration of the test. While open load diagnostic is running, if an input change occurs or

the EN_OLP bit is set low, the open load test is aborted to start normal operation again, and no fault is reported.

OLP should not be performed if the motor is energized.

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The open load detection checks for a high impedance connection on the motor phase pins (SHx or DLx). The

diagnostic has two major steps as listed in the OLP Steps section. The sequencing of the pullup and pulldown

current varies depending on the load connections. 图 28 a simplified H-bridge configuration as an example for

open load detection.

VDRAIN

V_ref

+

OL1_PU

output

œ

OLx_PU

SHx / DLx

VDRAIN

SHx / DLx

V_ref

+

OL1_PU

output

œ

SLx

OLx_PD

图 28. Circuit for Open Load Detection in Passive Mode

8.3.4.7.1.1 OLP Steps

The OLP algorithm list is as follows:

•

The pullup current source is enabled. If a load is connected, current passes through the pullup resistor and

the OLx_PU comparator output stays low. If an open load condition occurs, the current through the pullup

resistor goes 0 and the OLx_PU comparator trips high.

•

The pulldown current source is enabled. In the same way, the OLx_PD comparator output either stays low to

indicate load-connected, or trips high to indicate an open load condition.

If both the OLx_PU and OLx_PD comparators report an open load, the OL_PH_x bit in the SPI register

latches high, and the nFAULT line goes low, to indicate an OL fault.

When the OL condition is removed, a clear faults command must be issued by the micro-controller either through

the CLR_FLT bit or an ENABLE reset pulse which resets open load register bits. The charge pump stays active

during this fault condition. The load connections shown in 图 29 are not supported OLP.

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VDRAIN

HS_VSD

VDRAIN

+

GHx

SHx

œ

VM

DLx

GLx

IPD

IPU

LS_VSD

+

œ

SLx

图 29. Load Configurations Not Supported

8.3.4.7.2 Open Load Detection in Active Mode (OLA)

An open load in active mode is disabled by default in the SPI device and can be enabled independently per half-

bridge by writing a 1 to the EN_OLA_x bit. In the H/W device, OLA runs if the nDIAG pin is left as unconnected

or tied to GND. OLA is detected when the motor gets disconnected from the driver when it is commutating. 图 30

shows a simplified H-bridge configuration for OLA implementation during high-side current recirculation. When

the voltage drop across the body diode of the MOSFET does not exhibit overshoot greater than the VOLA over

VM between the time the low-side FET is switched off and the high side FET is switched on during an output

PWM cycle. An open load is not detected if the energy stored in the inductor is high enough to cause an

overshoot greater than the V_OLAover VM caused by the fly-back current flowing through the body diode of the

high-side FET.

VM

SH2

DL2

SH2

DL2

SH2

DL2

SH1

DL1

SH1

DL1

SH1

DL1

œ

+

Detects OLD if the

diode V_Fdrop < V_OLA

No OLD detected if the

diode V_Fdrop > V_OLA

图 30. Circuit for Open Load Detection in Active Mode

注

Depending on the operating conditions and on external circuitry, such as the output

capacitors, an open load could be reported even though the load is present. This case

might occur during a direction change or for small load currents respectively small PWM

duty cycles. Therefore, TI recommends evaluating the open load diagnosis only in known

suitable operating conditions and to ignore it otherwise.

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The device has a failure counter to avoid inadvertent triggering of the open load active diagnosis. Three

consecutive occurrences of the internal open load signal must occur, essentially three consecutive PWM pulses

without freewheeling detected, before an open load is reported through the nFAULT pin and in the respective

SPI register.

In the SPI device, depending on the load configuration and the PWM sequence, OLA on one phase can latch all

three OL_PH_x bits high. In that case, the OLP diagnostic can be initiated to determine which phase has the

open load condition. The load connections shown in 图 29 are not supported by OLA.

For OLA to function correctly, place capacitors between the motor phase node and GND. This capacitor is

required for BLDC, bi-directional BDC and unidirectional BDC motors at the phase node. If a solenoid load is

connected, as shown in 图 15, the capacitor is not required. Size the capacitors according 公式 3. Make sure that

the capacitor (C_phase) is placed on the PCB.

V_THì C_rss

V_OLA(min)

C_phase

í

- C_oss

where

•

V_THis the threshold voltage of the MOSFET.

V_OLA(min)is 150 mV.

(3)

The values of C_rssand C_ossof the MOSFETs should be used for 0-V V_DS. Derating of C_phasemust be considered

when selecting the capacitance.

8.3.4.8 Offline Shorts Diagnostics

The device detects short-to-battery and short-to-ground conditions when the motor is not commutating. These

offline diagnostics can be activated in the SPI device by setting the EN_SHT_TST bit high. Both the short-to-

battery and short-to-ground diagnostics run when the EN_SHT_TST bit is set high. In the H/W device, these

diagnostics run at power-up or when going from the sleep mode if the nDIAG pin is left unconnected or tied to

GND. To disable the diagnostics in the H/W device, connect the nDIAG pin to the DVDD supply (or an external

3.3 V or 5 V rail). The short-to-supply diagnostic runs first (see Offline Short-to-Supply Diagnostic (SHT_BAT))

followed by the short-to-ground diagnostic (see Offline Short-to-Ground Diagnostic (SHT_GND)). In the SPI

device, the duration for this diagnostics is selected through the OLP_SHTS_DLY register. In the H/W device, the

duration is fixed to 2 ms.

8.3.4.8.1 Offline Short-to-Supply Diagnostic (SHT_BAT)

When the EN_SHT_TST bit is set high, all the pulldown current sources on the DLx pins are enabled. The

voltage across each pulldown source is individually measured and compared to an internal threshold (V_TH). If the

voltage across any of the current sources exceeds V_TH, the DRV8340-Q1 device flags that as a fault condition.

The nFAULT pin is driven low, and in the SPI device the FAULT, OL_SHT, and the corresponding SHT_BAT_x

bit is set. 图 31 shows the internal circuit for the short to battery detection.

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VDRAIN

GHA

GHB

SHA

GHC

Short to Ground

(SHT_GND)

Diagnostic Circuit

SHB

SHC

DLC

DLB

GLC

DLA

GLB

GLC

V_TH

图 31. Offline Short-to-Supply Detection Circuit

In the SPI device, depending on the load configuration, SHT_BAT on one phase can latch all three SHT_BAT_x

bits high. To determine which phase has a short-to-supply fault condition, the external MOSFETs can be enabled

and the appropriate VDS_Lx fault bit is latched indicating the faulty phase node. SHT_BAT is not supported for

load configurations shown in 图 29.

8.3.4.8.2 Offline Short-to-Ground Diagnostic (SHT_GND)

When the EN_SHT_TST bit is set high, all the pullup current sources on the SHx pins are enabled. The voltage

across each pullup source is individually measured and compared to an internal threshold (V_TH). If the voltage

across any of the current sources exceeds V_TH, the DRV8340-Q1 device flags that as a fault condition. The

nFAULT pin is driven low, and in the SPI device the FAULT, OL_SHT, and the corresponding SHT_GND_x bit is

set. 图 32 shows the internal circuit for the short-to-ground detection.

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VDRAIN

GHA

GHB

SHA

V_TH

GHC

SHB

SHC

DLC

DLB

GLC

DLA

GLB

Short to Supply

(SHT_BAT)

Diagnostic Circuit

GLC

图 32. Offline Short-to-Ground Detection Circuit

In the SPI device, depending on the load configuration, SHT_GND on one phase can latch all three SHT_GND_x

bits high. To determine which phase has a short-to-ground fault condition, the external MOSFETs can be

enabled and the appropriate VDS_Hx fault bit is latched indicating the faulty phase node. SHT_GND is not

supported for load configurations shown in 图 29.

8.3.4.9 Reverse Supply Protection

The circuit in 图 33 can be implemented to help protect the system from reverse supply conditions. This circuit

requires the following additional components:

•

N-channel MOSFET

NPN BJT

Diode

10-kΩ and 43-kΩ resistors

The VCP voltage with respect to VM supplies the gate-source voltage of N-channel MOSFET, and the voltage

V_VCPdepends on VM voltage. The characteristics of N-Channel MOSFET (e.g. gate threshold voltage) and the

VM voltage range of the system need to be reviewed by the system integrator.

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V_BAT

43 kꢀ

10 kꢀ

47 nF

1 µF

0.1 µF

+

Bulk

10 µF (min)

CPL

CPH

VCP

VM

VDRAIN

GHA

SHA

DLA

GLA

SLA

VM

GHB

SHB

DLB

GLB

SLB

VM

GHC

SHC

DLC

GLC

SPC

SNC

R

SEN

图 33. Reverse Supply Protection

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8.4 Device Functional Modes

8.4.1 Gate Driver Functional Modes

8.4.1.1 Sleep Mode

The ENABLE pin manages the state of the DRV8340-Q1 device. When the ENABLE pin is low, the device goes

to a low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are disabled, the

charge pump is disabled, the DVDD regulator is disabled, and the SPI bus is disabled. The t_SLEEPtime must

elapse after a falling edge on the ENABLE pin before the device goes to sleep mode. The device comes out of

sleep mode automatically if the ENABLE pin is pulled high. The t_WAKEtime must elapse before the device is

ready for inputs.

In sleep mode and when V_VM< V_UVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are

pulled to the SHx pin by an internal resistor and the low-side gate pins, GLx, are pulled to the PGND pin by an

internal resistor.

8.4.1.2 Operating Mode

When the ENABLE pin is high and the V_VMvoltage is greater than the V_UVLOvoltage, the device goes to

operating mode. The t_WAKEtime must elapse before the device is ready for inputs. In this mode the charge pump,

low-side gate regulator, DVDD regulator, and SPI bus are active.

8.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)

In the case of device latched faults, the DRV8340-Q1 device goes to a partial shutdown state to help protect the

external power MOSFETs and system.

When the fault condition clears, the device can go to the operating state again by either setting the CLR_FLT SPI

bit on SPI devices or issuing a result pulse to the ENABLE pin on either interface variant. The ENABLE reset

pulse (t_RST) consists of a high-to-low-to-high transition on the ENABLE pin. The low period of the sequence

should fall with the t_RSTtime window or else the device will start the complete shutdown sequence. The reset

pulse has no effect on any of the regulators, device settings, or other functional blocks

8.5 Programming

This section applies only to the DRV8340-Q1 SPI devices.

8.5.1 SPI Communication

8.5.1.1 SPI

On DRV8340-Q1 SPI devices, an SPI bus is used to set device configurations, operating parameters, and read

out diagnostic information. The SPI operates in slave mode and connects to a master controller. The SPI input

data (SDI) word consists of a 16-bit word, with an 8-bit command and 8 bits of data. The SPI output data (SDO)

word consists of 8-bit register data. The first 8 bits are don’t care bits.

A valid frame must meet the following conditions:

•

The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.

The nSCS pin should be pulled high for at least 400 ns between words.

When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is

placed in the Hi-Z state.

•

Data is captured on the falling edge of the SCLK pin and data is propagated on the rising edge of the SCLK

pin.

•

The most significant bit (MSB) is shifted in and out first.

A full 16 SCLK cycles must occur for transaction to be valid.

If the data word sent to the SDI pin is less than or more than 16 bits, a frame error occurs and the data word

is ignored.

•

For a write command, the existing data in the register being written to is shifted out on the SDO pin following

the 8-bit command data.

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Programming (接下页)

8.5.1.1.1 SPI Format

The SDI input data word is 16 bits long and consists of the following format:

•

1 read or write bit, W (bit B15)

7 address bits, A (bits B14 through B8)

8 data bits, D (bits B7 through B0)

The SDO output data word is 16 bits long and the first 5 bits are don't care bits. The data word is the content of

the register being accessed.

For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being

written to.

For a read command (W0 = 1), the response word is the data currently in the register being read.

表 12. SDI Input Data Word Format

R/W

B15

W0

ADDRESS

B11

DATA

B4

D4

B14

0

B13

0

B12

A4

B10

A2

B9

A1

B8

A0

B7

D7

B6

D6

B5

D5

B3

D3

B2

D2

B1

D1

B0

D0

A3

表 13. SDO Output Data Word Format

R/W

B15

W0

DON'T CARE

DATA

B14

X

B13

X

B12

X

B11

X

B10

X

B9

X

B8

X

B7

D7

B6

D6

B5

D5

B4

D4

B3

D3

B2

D2

B1

D1

B0

D0

nSCS

SCLK

SDI

X

Z

MSB

LSB

X

Z

SDO

Capture

Point

Propagate

Point

图 34. SPI Slave Timing Diagram

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8.6 Register Maps

This section applies only to the DRV8340-Q1 SPI devices.

注

Do not modify reserved registers or addresses not listed in the register map (). Writing to

these registers may have unintended effects. For all reserved bits, the default value is 0.

To help prevent erroneous SPI writes from the master controller, set the LOCK bits to lock

the SPI registers.

表 14. DRV8340-Q1 Register Map

Register

Name

Access Addres

7

6

5

4

3

2

1

0

Type

s

FAULT Status

FAULT

RSVD

GDF

CPUV

UVLO

OCP

OTW

OTSD

VDS_LA

OL_SHT

VDS_HA

R

0x00

DIAG Status

A

SHT_GND SHT_BAT_

_A

OL_PH_A

VGS_LA

VGS_HA

R

0x01

0x02

0x03

0x04

0x05

A

DIAG Status

B

SHT_GND SHT_BAT_

_B

RSVD

OL_PH_B

OL_PH_C

VGS_LB

VGS_LC

VGS_HB

VGS_HC

VDS_LB

VDS_LC

VDS_HB

VDS_HC

B

DIAG Status

C

SHT_GND SHT_BAT_

R

_C

C

1PWM_CO 1PWM_DI

IC1 Control

IC2 Control

CLR_FLT

PWM_MODE

1PWM_BRAKE

RW

M

R

OTSD_MO

DE

EN_SHT_

TST

EN_OLA_ EN_OLA_ EN_OLA_

OLP_SHTS_DLY

EN_OLP

C

B

A

IC3 Control

IC4 Control

IC5 Control

IC6 Control

IC7 Control

IC8 Control

IDRIVEP_LA

IDRIVEP_LB

IDRIVEP_LC

VDS_LVL_LA

VDS_LVL_LB

VDS_LVL_LC

IDRIVEP_HA

RW

0x06

0x07

0x08

0x09

0x0A

0x0B

IDRIVEP_HB

IDRIVEP_HC

VDS_LVL_HA

VDS_LVL_HB

VDS_LVL_HC

TDRIVE_M

AX

IC9 Control

IC10 Control

IC11 Control

COAST

RSVD

TRETRY

LOCK

DEAD_TIME

TDRIVE

OCP_DEG

RW

0x0C

0x0D

0x0E

DIS_CPUV DIS_GDF

DIS_VDS_ DIS_VDS_ DIS_VDS_

OTW_REP

CBC

OCP_MODE

C

B

A

IC12 Control

IC13 Control

IC14 Control

RSVD

RW

0x0F

0x10

0x11

RSVD

Complex bit access types are encoded to fit into small table cells. 表 15 shows the codes that are used for

access types in this section.

表 15. Status Registers Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Reset or Default Value

-n

Value after reset or the default value

8.6.1 Status Registers

表 16 lists the memory-mapped registers for the status registers. All register offset addresses not listed in 表 16

should be considered as reserved locations and the register contents should not be modified.

The status registers are used to reporting warning and fault conditions. Status registers are read-only registers.

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表 16. Status Registers Summary Table

Address

0x00

Register Name

FAULT Status

DIAG Status A

DIAG Status B

DIAG Status C

Section

Go

0x01

0x02

0x03

8.6.1.1 FAULT Status Register (Address = 0x00) [reset = 0x00]

FAULT Status is shown in 图 35 and described in 表 17.

图 35. FAULT Status Register

7

6

5

4

3

2

1

0

FAULT

R-0b

GDF

R-0b

CPUV

R-0b

UVLO

R-0b

OCP

R-0b

OTW

R-0b

OTSD

R-0b

OL_SHT

R-0b

表 17. FAULT Status Register Field Descriptions

Bit

Field

Type

Default

Description

7

FAULT

R

0b

Logic OR of FAULT status registers

Indicates gate drive fault condition

6

5

4

3

2

1

0

GDF

R

0b

CPUV

UVLO

OCP

Indicates charge pump undervoltage fault condition

Indicates undervoltage lockout fault condition

Indicated overcurrent fault condition either by VDS

Indicates overtemperature warning

OTW

OTSD

OL_SHT

Indicates overtemperature shutdown

Indicates open load detection, or offline short-to-supply or GND

detection

8.6.1.2 DIAG Status A Register (Address = 0x01) [reset = 0x00]

DIAG Status A is shown in 图 36 and described in 表 18.

图 36. DIAG Status A Register

7

6

5

4

3

2

1

0

RSVD

R-0b

SHT_GND_A

R-0b

SHT_BAT_A

R-0b

OL_PH_A

R-0b

VGS_LA

R-0b

VGS_HA

R-0b

VDS_LA

R-0b

VDS_HA

R-0b

表 18. DIAG Status A Register Field Descriptions

Bit

Field

Type

R

Default

0b

Description

7

6

RSVD

Reserved.

SHT_GND_A

SHT_BAT_A

OL_PH_A

VGS_LA

R

0b

Indicates offline short-to-ground fault in Phase A

Indicates offline short to battery fault in Phase A

Indicates open load fault in Phase A

5

4

3

2

1

0

R

0b

Indicates gate drive fault on the A low-side MOSFET

VGS_HA

Indicates gate drive fault on the A high-side MOSFET

Indicates VDS overcurrent fault on the A low-side MOSFET

Indicates VDS overcurrent fault on the A high-side MOSFET

VDS_LA

VDS_HA

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8.6.1.3 DIAG Status B Register (Address = 0x02) [reset = 0x00]

DIAG Status B is shown in 图 37 and described in 表 19.

图 37. DIAG Status B Register

7

6

5

4

3

2

1

0

RSVD

R-0b

SHT_GND_B

R-0b

SHT_BAT_B

R-0b

OL_PH_B

R-0b

VGS_LB

R-0b

VGS_HB

R-0b

VDS_LB

R-0b

VDS_HB

R-0b

表 19. DIAG Status B Register Field Descriptions

Bit

Field

Type

R

Default

0b

Description

7

6

RSVD

Reserved

SHT_GND_B

SHT_BAT_B

OL_PH_B

VGS_LB

R

0b

Indicates offline short-to-ground fault in Phase B

Indicates offline short to battery fault in Phase B

Indicates open load fault in Phase B

5

4

3

2

1

0

R

0b

Indicates gate drive fault on the B low-side MOSFET

Indicates gate drive fault on the B high-side MOSFET

Indicates VDS overcurrent fault on the B low-side MOSFET

Indicates VDS overcurrent fault on the B high-side MOSFET

VGS_HB

VDS_LB

VDS_HB

8.6.1.4 DIAG Status C Register (address = 0x03) [reset = 0x00]

DIAG Status C iss shown in 图 38 and described in 表 20.

图 38. DIAG Status C Register

7

6

5

4

3

2

1

0

RSVD

R-0b

SHT_GND_C

R-0b

SHT_BAT_C

R-0b

OL_PH_C

R-0b

VGS_LC

R-0b

VGS_HC

R-0b

VDS_LC

R-0b

VDS_HC

R-0b

表 20. DIAG Status C Register Field Descriptions

Bit

Field

Type

R

Default

0b

Description

7

6

RSVD

Reserved

SHT_GND_C

SHT_BAT_C

OL_PH_C

VGS_LC

R

0b

Indicates offline short-to-ground fault in Phase C

Indicates offline short to battery fault in Phase C

Indicates open load fault in Phase C

5

4

3

2

1

0

R

0b

Indicates gate drive fault on the C low-side MOSFET

VGS_HC

Indicates gate drive fault on the C high-side MOSFET

Indicates VDS overcurrent fault on the C low-side MOSFET

Indicates VDS overcurrent fault on the C high-side MOSFET

VDS_LC

VDS_HC

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8.6.2 Control Registers

表 21 lists the memory-mapped registers for the control registers. All register offset addresses not listed in 表 21

should be considered as reserved locations and the register contents should not be modified.

The IC control registers are used to configure the device. Control registers are read and write capable.

表 21. Control Registers Summary Table

Address

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

Register Name

IC1 Control

IC2 Control

IC3 Control

IC4 Control

IC5 Control

IC6 Control

IC7 Control

IC8 Control

IC9 Control

IC10 Control

IC11 Control

IC12 Control

IC13 Control

IC14 Control

Section

Go

8.6.2.1 IC1 Control Register (Address = 0x04) [reset = 0x00]

IC1 Control is shown in 图 39 and described in 表 22.

图 39. IC1 Control Register

7

6

5

4

3

2

1

0

CLR_FLT

R/W-0b

PWM_MODE

R/W-000b

1PWM_COM

R/W-0b

1PWM_DIR

R/W-0b

1PWM_BRAKE

R/W-00b

表 22. IC1 Control Field Descriptions

Bit

Field

Type

Default

Description

7

CLR_FLT

R/W

0b

Write a 1 to this bit to clear all latched fault bits. This bit

automatically resets after being written

6-4

PWN_MODE

R/W

000b

000b = 6x PWM mode

001b = 3x PWM mode

010b = 1x PWM mode

011b = Independent half-bridge (for all phases)

100b = Phases A and B are independent half-bridges, Phase C

is independent FET

101b = Phases B and C are independent half-bridges, Phase A

is independent FET

110b = Phase A is independent half-bridge, Phases B and C are

independent FET

111b =Independent FET (for all phases)

3

2

1PWM_COM

1PWM_DIR

R/W

0b

0b = 1x PWM mode uses synchronous rectification

1b = 1x PWM mode uses asynchronous rectification (diode

freewheeling)

In 1x PWM mode this bit is OR’ed with the INHC (DIR) input

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表 22. IC1 Control Field Descriptions (接下页)

Bit

Field

1PWM_BRAKE

Type

Default

Description

1-0

R/W

00b

00b = Outputs follow commanded inputs

01b = Turn on all three low-side MOSFETs

10b = Turn on all three high-side MOSFETs

11b = Turn off all six MOSFETs (coast)

8.6.2.2 IC2 Control Register (address = 0x05) [reset = 0x40]

IC2 Control is shown in 图 40 and described in 表 23.

图 40. IC2 Control Register

7

6

5

4

3

2

1

0

OTSD_MODE

R/W-0b

OLP_SHTS_DLY

R/W-10b

EN_SHT_TST

R/W-0b

EN_OLP

R/W-0b

EN_OLA_C

R/W-0b

EN_OLA_B

R/W-0b

EN_OLA_A

R/W-0b

表 23. IC2 Control Field Descriptions

Bit

Field

Type

Default

Description

0b = Overtemperature condition will cause a latched fault

1b Overtemperature condition will cause an automatic

7

OTSD_MODE

R/W

0b

=

recovery when the fault condition is removed

6-5

OLP_SHTS_DLY

R/W

10b

00b = OLP delay is 0.25 ms and Shorts test delay is 0.1 ms

01b = OLP delay is 1.25 ms and Shorts test delay is 0.5 ms

10b = OLP delay is 5 ms and Shorts test delay is 2 ms

11b = OLP delay is 11.5 ms and Shorts test delay is 4.4 ms

4

3

EN_SHT_TST

EN_OLP

R/W

0b

Write a 1 to enable offline short to battery and ground diagnoses

Write a 1 to enable open load diagnostic in standby mode.

When open load test is complete EN_OLP returns to the default

setting

2

1

0

EN_OLA_C

EN_OLA_B

EN_OLA_A

R/W

0b

Write a 1 to enable open load active diagnostic on Phase C

Write a 1 to enable open load active diagnostic on Phase B

Write a 1 to enable open load active diagnostic on Phase A

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8.6.2.3 IC3 Control Register (Address = 0x06) [reset = 0xFF]

IC3 Control is shown in 图 41 and described in 表 24.

图 41. IC3 Control Register

7

6

5

4

3

2

1

0

IDRIVEP_LA

R/W-1111b

IDRIVEP_HA

R/W-1111b

表 24. IC3 Control Field Descriptions

Bit

Field

IDRIVEP_LA

Type

Default

Description

7-4

R/W

1111b

0000b = 1.5 mA

0001b = 3.5 mA

0010b = 5 mA

0011b = 10 mA

0100b = 15 mA

0101b = 50 mA

0110b = 60 mA

0111b = 65 mA

1000b = 200 mA

1001b = 210 mA

1010b = 260 mA

1011b = 265 mA

1100b = 735 mA

1101b = 800 mA

1110b = 935 mA

1111b = 1000 mA

3-0

IDRIVEP_HA

R/W

1111b

0000b = 1.5 mA

0001b = 3.5 mA

0010b = 5 mA

0011b = 10 mA

0100b = 15 mA

0101b = 50 mA

0110b = 60 mA

0111b = 65 mA

1000b = 200 mA

1001b = 210 mA

1010b = 260 mA

1011b = 265 mA

1100b = 735 mA

1101b = 800 mA

1110b = 935 mA

1111b = 1000 mA

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8.6.2.4 IC4 Control Register (Address = 0x07) [reset = 0xFF]

IC4 Control is shown in 图 42 and described in 表 25.

图 42. IC4 Control Register

7

6

5

4

3

2

1

0

IDRIVEP_LB

R/W-1111b

IDRIVEP_HB

R/W-1111b

表 25. IC4 Control Field Descriptions

Bit

Field

IDRIVEP_LB

Type

Default

Description

7-4

R/W

1111b

0000b = 1.5 mA

0001b = 3.5 mA

0010b = 5 mA

0011b = 10 mA

0100b = 15 mA

0101b = 50 mA

0110b = 60 mA

0111b = 65 mA

1000b = 200 mA

1001b = 210 mA

1010b = 260 mA

1011b = 265 mA

1100b = 735 mA

1101b = 800 mA

1110b = 935 mA

1111b = 1000 mA

3-0

IDRIVEP_HB

R/W

1111b

0000b = 1.5 mA

0001b = 3.5 mA

0010b = 5 mA

0011b = 10 mA

0100b = 15 mA

0101b = 50 mA

0110b = 60 mA

0111b = 65 mA

1000b = 200 mA

1001b = 210 mA

1010b = 260 mA

1011b = 265 mA

1100b = 735 mA

1101b = 800 mA

1110b = 935 mA

1111b = 1000 mA

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8.6.2.5 IC5 Control Register (Address = 0x08) [reset = 0xFF]

IC5 Control is shown in 图 43 and described in 表 26.

图 43. IC5 Control Register

7

6

5

4

3

2

1

0

IDRIVEP_LC

R/W-1111b

IDRIVEP_HC

R/W-1111b

表 26. IC5 Control Field Descriptions

Bit

Field

IDRIVEP_LC

Type

Default

Description

7-4

R/W

1111b

0000b = 1.5 mA

0001b = 3.5 mA

0010b = 5 mA

0011b = 10 mA

0100b = 15 mA

0101b = 50 mA

0110b = 60 mA

0111b = 65 mA

1000b = 200 mA

1001b = 210 mA

1010b = 260 mA

1011b = 265 mA

1100b = 735 mA

1101b = 800 mA

1110b = 935 mA

1111b = 1000 mA

3-0

IDRIVEP_HC

R/W

1111b

0000b = 1.5 mA

0001b = 3.5 mA

0010b = 5 mA

0011b = 10 mA

0100b = 15 mA

0101b = 50 mA

0110b = 60 mA

0111b = 65 mA

1000b = 200 mA

1001b = 210 mA

1010b = 260 mA

1011b = 265 mA

1100b = 735 mA

1101b = 800 mA

1110b = 935 mA

1111b = 1000 mA

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8.6.2.6 IC6 Control Register (Address = 0x09) [reset = 0x99]

IC6 Control is shown in 图 44 and described in 表 27.

图 44. IC6 Control Register

7

6

5

4

3

2

1

0

VDS_LVL_LA

R/W-1001b

VDS_LVL_HA

R/W-1001b

表 27. IC6 Control Field Descriptions

Bit

Field

VDS_LVL_LA

Type

Default

Description

7-4

R/W

1001b

0000b = 0.06 V

0001b = 0.13 V

0010b = 0.2 V

0011b = 0.26 V

0100b = 0.31 V

0101b = 0.45 V

0110b = 0.53 V

0111b = 0.6 V

1000b = 0.68 V

1001b = 0.75 V

1010b = 0.94 V

1011b = 1.13 V

1100b = 1.3 V

1101b = 1.5 V

1110b = 1.7 V

1111b = 1.88 V

3-0

VDS_LVL_HA

R/W

1001b

0000b = 0.06 V

0001b = 0.13 V

0010b = 0.2 V

0011b = 0.26 V

0100b = 0.31 V

0101b = 0.45 V

0110b = 0.53 V

0111b = 0.6 V

1000b = 0.68 V

1001b = 0.75 V

1010b = 0.94 V

1011b = 1.13 V

1100b = 1.3 V

1101b = 1.5 V

1110b = 1.7 V

1111b = 1.88 V

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8.6.2.7 IC7 Control Register (Address = 0x0A) [reset = 0x99]

IC7 Control is shown in 图 45 and described in 表 28.

图 45. IC7 Control Register

7

6

5

4

3

2

1

0

VDS_LVL_LB

R/W-1001b

VDS_LVL_HB

R/W-1001b

表 28. IC7 Control Field Descriptions

Bit

Field

VDS_LVL_LB

Type

Default

Description

7-4

R/W

1001b

0000b = 0.06 V

0001b = 0.13 V

0010b = 0.2 V

0011b = 0.26 V

0100b = 0.31 V

0101b = 0.45 V

0110b = 0.53 V

0111b = 0.6 V

1000b = 0.68 V

1001b = 0.75 V

1010b = 0.94 V

1011b = 1.13 V

1100b = 1.3 V

1101b = 1.5 V

1110b = 1.7 V

1111b = 1.88 V

3-0

VDS_LVL_HB

R/W

1001b

0000b = 0.06 V

0001b = 0.13 V

0010b = 0.2 V

0011b = 0.26 V

0100b = 0.31 V

0101b = 0.45 V

0110b = 0.53 V

0111b = 0.6 V

1000b = 0.68 V

1001b = 0.75 V

1010b = 0.94 V

1011b = 1.13 V

1100b = 1.3 V

1101b = 1.5 V

1110b = 1.7 V

1111b = 1.88 V

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8.6.2.8 IC8 Control Register (Address = 0x0B) [reset = 0x99]

IC8 control is shown in 图 46 and described in 表 29.

图 46. IC8 Control Register

7

6

5

4

3

2

1

0

VDS_LVL_LC

R/W-1001b

VDS_LVL_HC

R/W-1001b

表 29. IC8 Control Field Descriptions

Bit

Field

VDS_LVL_LC

Type

Default

Description

7-4

R/W

1001b

0000b = 0.06 V

0001b = 0.13 V

0010b = 0.2 V

0011b = 0.26 V

0100b = 0.31 V

0101b = 0.45 V

0110b = 0.53 V

0111b = 0.6 V

1000b = 0.68 V

1001b = 0.75 V

1010b = 0.94 V

1011b = 1.13 V

1100b = 1.3 V

1101b = 1.5 V

1110b = 1.7 V

1111b = 1.88 V

3-0

VDS_LVL_HC

R/W

1001b

0000b = 0.06 V

0001b = 0.13 V

0010b = 0.2 V

0011b = 0.26 V

0100b = 0.31 V

0101b = 0.45 V

0110b = 0.53 V

0111b = 0.6 V

1000b = 0.68 V

1001b = 0.75 V

1010b = 0.94 V

1011b = 1.13 V

1100b = 1.3 V

1101b = 1.5 V

1110b = 1.7 V

1111b = 1.88 V

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8.6.2.9 IC9 Control Register (Address = 0x0C) [reset = 0x2F]

IC9 Control is shown in 图 47 and described in 表 30.

图 47. IC9 Control Register

7

6

5

4

3

2

1

0

COAST

R/W-0b

TRETRY

R/W-01b

DEAD_TIME

R/W-01b

TDRIVE_MAX

R/W-1b

TDRIVE

R/W-11b

表 30. IC9 Control Field Descriptions

Bit

Field

Type

Default

Description

7

COAST

R/W

0b

Write a 1 to this bit to put all the MOSFETs in the Hi-Z state

6-5

TRETRY

R/W

01b

00b = 2 ms

01b = 4 ms

10b = 6 ms

11b = 8 ms

4-3

DEAD_TIME

R/W

01b

00b = 500 ns

01b = 1000 ns

10b = 2000 ns

11b = 4000 ns

2

TDRIVE_MAX

TDRIVE

R/W

1b

Write a 0 to this bit to disable the maximum t_DRIVEtime of 20 µs.

This bit is automatically enabled when IDRIVE = 0000b, 0001b,

0010b, or 0011b is selected

1-0

11b

00b = 500 ns peak gate-current drive time

01b = 1000 ns peak gate-current drive time

10b = 2000 ns peak gate-current drive time

11b = 3000 ns peak gate-current drive time

8.6.2.10 IC10 Control Register (Address = 0x0D) [reset = 0x61]

IC10 Control is shown in 图 48 and described in 表 31.

图 48. IC10 Control Register

7

6

5

4

3

2

1

0

LOCK

DIS_CPUV

R/W-0b

DIS_GDF

R/W-0b

OCP_DEG

R/W-001b

R/W-011b

表 31. IC10 Control Field Descriptions

Bit

Field

Type

Default

Description

7-5

LOCK

R/W

011b

Write 110b to lock the settings by ignoring further register writes

except to these bits and address 0x04h bit 7 (CLR_FLT). Writing

any sequence other than 110b has no effect when unlocked.

Write 011b to this register to unlock all registers. Writing any

sequence other than 011b has no effect when locked.

4

3

DIS_CPUV

DIS_GDF

R/W

0b

0b = Charge-pump undervoltage lockout fault is enabled

1b = Charge-pump undervoltage lockout fault is disabled

0b = Gate drive fault is enabled

1b = Gate drive fault is disabled

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表 31. IC10 Control Field Descriptions (接下页)

Bit

Field

OCP_DEG

Type

Default

Description

2-0

R/W

001b

000b = 2.5 µs

001b = 4.75 µs

010b = 6.75 µs

011b = 8.75 µs

100b = 10.25 µs

101b = 11.5 µs

110b = 16.5 µs

111b = 20.5 µs

8.6.2.11 IC11 Control Register (Address = 0x0E) [reset = 0x00]

IC11 Control is shown in 图 49 and described in 表 32.

图 49. IC11 Control Register

7

6

5

4

3

2

1

0

RSVD

R/W-0b

OTW_REP

R/W-0b

CBC

DIS_VDS_C

R/W-0b

DIS_VDS_B

R/W-0b

DIS_VDS_A

R/W-0b

OCP_MODE

R/W-00b

R/W-0b

表 32. IC11 Control Field Descriptions

Bit

Field

Type

Default

Description

7

RSVD

R/W

0b

Reserved

6

OTW_REP

R/W

0b

0b = Overtemperature warning is not reported on nFAULT

1b = Overtemperature warning is reported on nFAULT

5

4

CBC

R/W

0b

00b

In retry OCP_MODE, for both VDS_OCP, the fault is

automatically cleared when a PWM input is given

DIS_VDS_C

DIS_VDS_B

DIS_VDS_A

OCP_MODE

Write a 1 to this bit to disable VDS_OCP for MOSFETs in Phase

C

3

Write a 1 to this bit to disable VDS_OCP for MOSFETs in Phase

B

2

Write a 1 to this bit to disable VDS_OCP for MOSFETs in Phase

A

1-0

00b = Overcurrent causes a latched fault

01b = Overcurrent causes an automatic retrying fault

10b = Overcurrent is report only but no action is taken

11b = Overcurrent is not reported and no action is taken

8.6.2.12 IC12 Control Register (Address = 0x0F) [reset = 0x2A]

IC12 Control is shown in and described in .

图 50. IC12 Control Register

7

6

5

4

3

2

1

0

RSVD

R/W-0b

RSVD

R/W-0b

RSVD

R/W-10b

表 33. IC12 Control Field Descriptions

Bit

7

Field

Type

R/W

Default

0b

Description

RSVD

Reserved. Keep the default value 0b.

6

0b

Reserved.

5-4

10b

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表 33. IC12 Control Field Descriptions (接下页)

Bit

3-2

1-0

Field

Type

R/W

Default

10b

Description

Reserved.

RSVD

10b

8.6.2.13 IC13 Control Register (Address = 0x10) [reset = 0x7F]

IC13 Control is shown in and described in .

图 51. IC13 Control Register

7

6

5

4

3

2

1

0

RSVD

R/W-0b

RSVD

R/W-1b

RSVD

R/W-11b

表 34. IC13 Control Field Descriptions

Bit

7

Field

Type

R/W

Default

0b

Description

Reserved

RSVD

6

1b

5-4

3-2

1-0

11b

8.6.2.14 IC14 Control Register (Address = 0x10) [reset = 0x00]

IC14 Control is shown in and described in .

图 52. IC14 Control Register

7

6

5

4

3

2

1

0

RSVD

R/W-0b

RSVD

R/W-0b

RSVD

R/W-0b

RSVD

R/W-0b

RSVD

R/W-0b

RSVD

R/W-0b

R/W-00b

表 35. IC14 Control Field Descriptions

Bit

7-6

5

Field

Type

R/W

Default

00b

0b

Description

Reserved

RSVD

4

0b

3

0b

2

0b

1

0b

0

0b

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9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The DRV8340-Q1 device is primarily used in applications for three-phase brushless DC motor control. The

design procedures in the Typical Application section highlight how to use and configure the DRV8340-Q1 device.

9.2 Typical Application

9.2.1 Primary Application

The DRV8340-Q1 SPI device is used in this application example.

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Typical Application (接下页)

VCC

C_VSDO

3.3 V, 30 mA

C_DVDD

1

2

36

35

34

33

32

31

30

29

28

27

26

25

ENABLE

CPL

CPH

C_FLY

nSCS

SCLK

SDI

3

VCP

VM

C_VCP

4

VCC

+

5

C_VM1

C_VM2

C_VM3

VDRAIN

GHA

SHA

DLA

VDRAIN

GHA

SHA

DLA

GLA

SLA

NC

SDO

nFAULT

NC

R_nFAULT

6

GND

(PAD)

7

8

NC

9

NC

GLA

10

11

12

NC

SLA

NC

VM

+

VM

+

VDRAIN

GHB

GHC

GHA

SHB

DLB

SHA

DLA

SHC

DLC

C

B

A

GLB

SLB

GLA

SLA

GLC

SLC

图 53. Primary Application Schematic

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Typical Application (接下页)

9.2.1.1 Design Requirements

lists the example input parameters for the system design.

表 36. Design Parameters

EXAMPLE DESIGN PARAMETER

Nominal supply voltage

Supply voltage range

REFERENCE

EXAMPLE VALUE

24 V

8 V to 45 V

V_VM

MOSFET part number

CSD18536KCS

83 nC (typical) at V_VGS= 10 V

14 nC (typical)

1000 ns

MOSFET total gate charge

MOSFET gate to drain charge

Target output rise time

Q_g

Q_gd

t_r

PWM Frequency

ƒ_PWM

I_max

I_SENSE

I_RMS

T_A

10 kHz

Maximum motor current

Winding sense current range

Motor RMS current

100 A

–40 A to +40 A

28.3 A

System ambient temperature

–40°C to 125°C

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 External MOSFET Support

The DRV8340-Q1 MOSFET support is based on the capacity of the charge pump and PWM switching frequency

of the output. For a quick calculation of MOSFET driving capacity, use 公式 4 and 公式 5 for three phase BLDC

motor applications.

Trapezoidal 120° Commutation: I_VCP> Q_g× ƒ_PWM

where

•

ƒ_PWMis the maximum desired PWM switching frequency.

I_VCPis the charge pump capacity, which depends on the VM pin voltage.

The multiplier based on the commutation control method, may vary based on implementation.

(4)

(5)

Sinusoidal 180° Commutation: I_VCP> 3 × Q_g× ƒ_PWM

9.2.1.2.1.1 Example

If a system with a V_VMvoltage of 8 V (I_VCP= 15 mA) uses a maximum PWM switching frequency of 10 kHz, then

the charge pump can support MOSFETs using trapezoidal commutation with a Q_gless than 750 nC, and

MOSFETs using sinusoidal commutation with a Q_gless than 250 nC.

9.2.1.2.2 IDRIVE Configuration

The strength of the gate drive current, I_DRIVE, is selected based on the gate-to-drain charge of the external

MOSFETs and the target rise and fall times at the outputs. If I_DRIVEis selected to be too low for a given

MOSFET, then the MOSFET may not turn on completely within the t_DRIVEtime and a gate drive fault may be

asserted. Additionally, slow rise and fall times result in higher switching power losses. TI recommends adjusting

these values in the system with the required external MOSFETs and motor to determine the best possible setting

for any application.

The I_DRIVEPand I_DRIVENcurrent for both the low-side and high-side MOSFETs are independently adjustable on

SPI devices through the SPI registers. On hardware interface devices, both source and sink settings are selected

at the same time on the IDRIVE pin.

For MOSFETs with a known gate-to-drain charge Q_gd, desired rise time (t_r), and a desired fall time (t_f), use 公式

6 and 公式 7 to calculate the value of I_DRIVEPand I_DRIVEN(respectively).

I_DRIVEP> Q_gdì t_r

(6)

I_DRIVEN= 2 ì I_DRIVEP

(7)

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9.2.1.2.2.1 Example

Use 公式 8 to calculate the value of I_DRIVEPfor a gate-to-drain charge of 14 nC and a rise time from 100 to 300

ns.

12 nC

I_DRIVEP

=

14 mA

1000 ns

(8)

Select an I_DRIVEPvalue that is close to 14 mA which will set the I_DRIVENvalue close to 28 mA. For this example,

the value of I_DRIVEPwas selected as 15 mA.

9.2.1.2.3 V_DSOvercurrent Monitor Configuration

The V_DSmonitors are configured based on the worst-case motor current and the R_DS(on)of the external

MOSFETs as shown in 公式 9.

V_{DS_OCP}> I_maxì R_DS(on)max

(9)

9.2.1.2.3.1 Example

The goal of this example is to set the V_DSmonitor to trip at a current greater than 100 A. According to the

CSD18536KCS 60 V N-Channel NexFET™ Power MOSFET data sheet, the R_DS(on)value is 1.8 times higher at

175°C, and the maximum R_DS(on)value at a V_GSof 10 V is 1.6 mΩ. From these values, the approximate worst-

case value of R_DS(on)is 1.8 × 1.6 mΩ = 2.88 mΩ.

Using 公式 9 with a value of 2.88 mΩ for R_DS(on)and a worst-case motor current of 100 A, 公式 10 shows the

calculated the value of the V_DSmonitors.

V_{DS _ OCP}> 100 A ì 2.88 mW

V_{DS _ OCP}> 0.288 V

(10)

For this example, the value of V_{DS_OCP}was selected as 0.31 V.

The SPI devices allow for adjustment of the deglitch time for the V_DSovercurrent monitor. The deglitch time can

be set to 2 µs, 4 µs, 6 µs, 8 µs, 10 µs, 12 µs, 16 µs, or 20 µs.

9.2.1.2.4 Design consideration of low-side gate drive (IDRIVE, GLx, SLx)

The VGLS linear regulator of low-side gate driver is biased with respect to AGND. Since the external FET is

referenced to bridge ground, any difference between the two grounds may cause the effective gate-source

voltage on the low-side MOSFET to increase during high current switching events.

Steps can be taken during the design stage to reduce the severity of this effect

•

Avoid excessively fast switching transients in the bridge ( <100ns slew rates on the phase node)

Ensure low inductance between SLx pin to MOSFET ground

Ensure low inductance in the path from GLx pin to MOSFET Gate . As a guidance, the below relationships 公

式 11 may be used to estimate the highest V_GSLexpected. The 1V term in the equation is required for

additional margin.

I_D²_RIVEP

V_{GSL _ SWITCHING}= V_GSL+1V +

ìL_gate

Q_g

where

•

V_{GSL_SWITCHING}is the effective gate-source voltage on the low-side MOSFET

•

V_GSLis the low-side gate drive voltage with no output load of GLx

I_DRIVEPis the peak source gate current

Q_gis the total gate charge of MOSFET

L_gateis the parasitic inductance in the path from GLx pin to MOSFET gate

(11)

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9.2.1.2.5 External Components

lists the recommended external components.

表 37. External Components

COMPONENT

C_FLY

PIN 1

CPH

VCP

VM

PIN 2

CPL

RECOMMENDED

47-nF ceramic capacitor X5R or X7R rated for VM⁽¹⁾

(1)

C_VCP

VM

1-µF ceramic capacitor X5R or X7R rated for VCP – VM

0.1-µF ceramic capacitor X5R or X7R rated for VM⁽¹⁾

4.7-µF ceramic capacitor X5R or X7R rated for VM⁽¹⁾

> 10-µF electrolytic capacitor rated for VM⁽¹⁾

C_VM1

PGND

AGND

C_VM2

VM

C_VM3

VM

C_DVDD

DVDD

1-µF ceramic capacitor X5R or X7R rated for DVDD⁽¹⁾

0.1-µF ceramic capacitor X5R or X7R rated for VSDO⁽¹⁾. DRV8340S

only

C_VSDO

VSDO

AGND

VCC⁽²⁾

R_nFAULT

nFAULT

2.5 – 10 kΩ pulled up the MCU I/O (VCC) power supply

(1) The effective capacitance of ceramic capacitors varies with DC operating voltage and temperature. As a rule of thumb, expect the

effective capacitance to decrease by as much as 50% at the extremes of the operating voltage. The system designer must review the

capacitor characteristics and select the component accordingly.

(2) The VCC pin is not a pin on the DRV8340-Q1 device, but a VCC supply voltage pullup is required for the open-drain output, nFAULT.

These pins can also be pulled up to DVDD.

9.2.1.3 Application Curves

(1)

图 54. Device Power Up Sequence Waveform

图 55. BLDC Motor Commutation

(1) SOC is available for DRV8343-Q1.

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10 Power Supply Recommendations

The DRV8340-Q1 device is designed to operate from an input voltage supply (VM) range from 6 V to 60 V.

10.1 Power Supply Consideration in Generator Mode

When the motor shaft of BLDC or PMSM motor is turned by an external force, the motor windings will generate a

voltage on the motor inputs. This condition is known as generator mode or motor back-drive. In the generator

mode, a positive voltage can be observed on SHx pins of the device. If there is a switch between VDRAIN and

VM (SW_VDRAINin 图 56 ) and the following conditions exist in the system, the absolute max voltage of VCP with

respect to VM needs to be reviewed;

•

Generator mode

SW_VDRAINis off

VM and VCP are low voltage (e.g. VM = 0V)

If SHx voltage (V_SHx) exceeds VCP voltage, the VCP voltage starts following V_SHxbecause of the device internal

diodes D1 and D2 (or D3). If VCP - VM voltage exceeds the absolute max voltage of DRV8340-Q1, the ESD

diode D4 starts conducting and results in a big current from SHx to VM through the diodes D2, D1 and D4. To

avoid this condition, it is recommended to add an external diode D_{VDRAIN_VM}between VDRAIN and VM.

SW_VDRAIN

12-V or 24-V

Battery

Optional

VM

VCP

DRV8340-Q1

D_{VDRAN_VM}

ESD

VDRAIN

D4

D1

D2

GHx

Level

shifter

INHx

external

force

D3

SHx

V_SHx

M

VGLS

GLx

SLx

Level

shifter

INLx

GND

图 56. Power Supply Consideration in Generator mode

10.2 Bulk Capacitance Sizing

Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally

beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The

amount of local capacitance depends on a variety of factors including:

•

The highest current required by the motor system

The power supply's type, capacitance, and ability to source current

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Bulk Capacitance Sizing (接下页)

•

The amount of parasitic inductance between the power supply and motor system

The acceptable supply voltage ripple

Type of motor (brushed DC, brushless DC, stepper)

The motor startup and braking methods

The inductance between the power supply and motor drive system will limit the rate current can change from the

power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or

dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage

stays stable and high current can be quickly supplied.

The data sheet provides a recommended minimum value, but system level testing is required to determine the

appropriate sized bulk capacitor.

Parasitic Wire

Inductance

Motor Drive System

Power Supply

VM

+

Motor Driver

œ

GND

Local

Bulk Capacitor

IC Bypass

Capacitor

图 57. Motor Drive Supply Parasitics Example

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11 Layout

11.1 Layout Guidelines

Bypass the VM pin to the PGND pin using a low-ESR ceramic bypass capacitor C_VM1. Place this capacitor as

close to the VM pin as possible with a thick trace or ground plane connected to the PGND pin. Additionally,

bypass the VM pin using a bulk capacitor rated for VM. This component can be electrolytic. This capacitance

must be at least 10 µF.

Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk

capacitance should be placed such that it minimizes the length of any high current paths through the external

MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB

layers. These practices minimize inductance and let the bulk capacitor deliver high current.

Place a low-ESR ceramic capacitor C_FLYbetween the CPL and CPH pins. Additionally, place a low-ESR ceramic

capacitor C_VCPbetween the VCP and VM pins.

Bypass the DVDD pin to the AGND pin with C_DVDD. Place this capacitor as close to the pin as possible and

minimize the path from the capacitor to the AGND pin.

The VDRAIN pin can be shorted directly to the VM pin. However, if a significant distance is between the device

and the external MOSFETs, use a dedicated trace to connect to the common point of the drains of the high-side

external MOSFETs. Do not connect the SLx pins directly to PGND. Instead, use dedicated traces to connect

these pins to the sources of the low-side external MOSFETs. These recommendations offer more accurate V_DS

sensing of the external MOSFETs for overcurrent detection.

Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of

the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx

pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the

low-side MOSFET source back to the PGND pin.

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11.2 Layout Example

S

G

D

G

S

24

NC 37

23 GLC

22 DLC

21 SHC

20 GHC

19 GHB

18 SHB

17 DLB

16 GLB

15 SLB

14 NC

AGND 38

DVDD 39

VSDO 40

INHA 41

INLA 42

INHB 43

INLB 44

INHC 45

INLC 46

PGND 47

NC 48

D

G

S

Thermal Pad

13

NC

S

G

D

S

G

D

G

S

图 58. Layout Example

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12 器件和文档支持

12.1 器件支持

12.1.1 器件命名规则

下图显示了说明完整器件名称的图例：

DRV83 (4) (0) (S) (Q) (PHP) (R) (Q1)

Prefix

DRV83 œ Three Phase Brushless DC

Qualified to use in

automotive environment

Tape and Reel

R œ Tape and Reel

T œ Small Tape and Reel

Series

4 œ 60 V device

Package

PHP œ 7 × 7 × 1 mm QFP

Operating Temperature

Q œ N40C to 125C

Sense amplifiers

0 œ No sense amplifiers

3 œ Three current sense amplifiers

Interface

S œ SPI

H œ Hardware

12.2 文档支持

12.2.1 相关文档

•

德州仪器 (TI)，《AN-1149 开关电源布局指南》应用报告

德州仪器 (TI)，《DRV834x-Q1 增强型故障检测》TI 技术手册{

德州仪器 (TI)，《采用 BLDC 电机的电动自行车硬件设计注意事项》

德州仪器 (TI)，《开关电源布局指南》

德州仪器 (TI)，《采用 MSP430™ 的传感器式三相 BLDC 电机控制》应用报告

德州仪器 (TI)，《TI 电机栅极驱动器的 IDRIVE 和 TDRIVE 认知》应用报告

12.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.5 商标

PowerPAD, NexFET, MSP430, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

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12.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

69

GENERIC PACKAGE VIEW

PHP 48

7 x 7, 0.5 mm pitch

TQFP - 1.2 mm max height

QUAD FLATPACK

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4226443/A

www.ti.com

PACKAGE OUTLINE

TM

PHP0048C

PowerPAD TQFP - 1.2 mm max height

SCALE 1.900

PLASTIC QUAD FLATPACK

7.2

6.8

B

NOTE 3

37

48

PIN 1 ID

1

36

7.2

6.8

9.2

TYP

8.8

NOTE 3

12

25

13

24

A

0.27

48X

44X 0.5

0.17

0.08

C A B

4X 5.5

1.2 MAX

C

SEATING PLANE

SEE DETAIL A

0.08

(0.13)

TYP

13

24

12

25

0.25

(1)

GAGE PLANE

4.6

3.6

49

0.75

0.45

0.15

0.05

0 -7

A

16

36

DETAIL A

TYPICAL

1

48

37

4X (0.115)NOTE5

4.6

3.6

4226381/A 11/2020

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MS-026.

5. Feature may not be present.

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EXAMPLE BOARD LAYOUT

TM

PHP0048C

PowerPAD TQFP - 1.2 mm max height

PLASTIC QUAD FLATPACK

(

6.5)

NOTE 10

(4.6)

SYMM

48

37

SOLDER MASK

DEFINED PAD

48X (1.6)

1

36

48X (0.3)

SYMM

49

(4.6)

(1.1 TYP)

(8.5)

44X (0.5)

12

25

(R0.05) TYP

(

0.2) TYP

VIA

METAL COVERED

BY SOLDER MASK

13

24

(1.1 TYP)

SEE DETAILS

(8.5)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

METAL UNDER

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4226381/A 11/2020

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,

Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged

or tented.

10. Size of metal pad may vary due to creepage requirement.

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EXAMPLE STENCIL DESIGN

TM

PHP0048C

PowerPAD TQFP - 1.2 mm max height

PLASTIC QUAD FLATPACK

(4.6)

BASED ON

0.125 THICK STENCIL

SEE TABLE FOR

SYMM

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

48

37

48X (1.6)

1

36

48X (0.3)

(8.5)

(4.6)

SYMM

49

BASED ON

0.125 THICK

STENCIL

44X (0.5)

12

25

(R0.05) TYP

METAL COVERED

BY SOLDER MASK

24

13

(8.5)

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:8X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

5.14 X 5.14

4.6 X 4.6 (SHOWN)

4.2 X 4.2

0.125

0.150

0.175

3.89 X 3.89

4226381/A 11/2020

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DRV8340HPHPRQ1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类 12V 至 24V 三相智能栅极驱动器 \| PHP \| 48 \| -40 to 125 栅极驱动驱动器
文件：	总78页 (文件大小：1682K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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