DRV8306HRSMR [TI]
最大 40V 含传感器梯形控制三相 BLDC 智能栅极驱动器 | RSM | 32 | -40 to 125;
| 型号： | DRV8306HRSMR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 最大 40V 含传感器梯形控制三相 BLDC 智能栅极驱动器 | RSM | 32 | -40 to 125 电动机控制 栅极驱动 传感器 驱动器 |
| 文件： | 总47页 (文件大小：2924K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DRV8306
ZHCSHZ0A –APRIL 2018–REVISED JULY 2018
DRV8306 38V 无刷直流电机控制器
1 特性
3 说明
1
•
6V 至 38V、三个半桥栅极驱动器，集成了 3 个霍
尔比较器
DRV8306 器件是一款集成式栅极驱动器，适用于三相
无刷直流 (BLDC) 电机 应用。此器件具有三个半桥栅
极驱动器，每个驱动器都能够驱动高侧和低侧 N 沟道
功率 MOSFET。DRV8306 器件使用集成电荷泵为高
侧 MOSFET 生成合适的栅极驱动电压，并使用线性稳
压器为低侧 MOSFET 生成合适的栅极驱动电压。智能
栅极驱动架构支持高达 150mA 的峰值栅极驱动拉电流
和 300mA 的峰值栅极驱动灌电流以及 15mA rms 栅极
驱动电流能力。
–
–
–
–
40V 绝对最大额定值
针对 12V 和 24V 直流电源轨进行了全面优化
驱动高侧和低侧 N 沟道 MOSFET
支持 100% PWM 占空比
•
智能栅极驱动架构
–
通过可调压摆率控制实现更出色的 EMI 和 EMC
性能
–
通过 VGS 握手和最小死区时间插入方法避免击
穿
此器件为梯形 BLDC 电机提供内部 120° 换向。
DRV8306 器件具有三个霍尔比较器，它们使用来自霍
尔元件的输入进行内部换向。可通过 PWM 引脚对电
机相电压的占空比进行调整。通过额外提供的制动
(nBRAKE) 和方向 (DIR) 引脚可制动 BLDC 电机和设
置电机方向。使用提供的 3.3V、30mA 低压降 (LDO)
稳压器可为外部控制器和霍尔元件供电。此外提供额外
的 FGOUT 信号来衡量换向频率。该信号可用于实现
BLDC 电机的闭环控制。
–
–
15mA 至 150mA 峰值拉电流
30mA 至 300mA 峰值灌电流
•
•
通过霍尔传感器集成了换向
–
–
–
120° 梯形电流控制
支持低成本霍尔元件
通过转速输出信号 (FGOUT) 实现闭环速度控制
集成栅极驱动器电源
–
–
高侧电荷泵
提供了低功耗睡眠模式，以通过关断大部分的内部电路
实现较低的静态电流消耗。针对欠压锁定、电荷泵故
障、MOSFET 过流、MOSFET 短路、栅极驱动器故障
和过热等情况，提供内部保护功能。故障情况通过
nFAULT 引脚指示。
低侧线性稳压器
•
•
•
•
•
•
逐周期电流限制
支持 1.8V、3.3V 和 5V 逻辑输入
低功耗睡眠模式
3.3V、30mA 线性稳压器
紧凑型 VQFN 封装和外形尺寸
集成式保护 特性
器件信息(1)
器件型号
DRV8306
封装
VQFN (32)
封装尺寸（标称值）
–
–
–
–
–
–
VM 欠压闭锁 (UVLO)
电荷泵欠压 (CPUV)
4.00mm × 4.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
MOSFET 过流保护 (OCP)
栅极驱动器故障 (GDF)
热关断 (OTSD)
简化原理图
6 to 38 V
故障状态指示器 (nFAULT)
PWM
H/W
Smart Gate
Drive
DRV8306
2 应用
M
3 ½ -H Bridge
Smart Gate Driver
•
•
•
•
•
•
BLDC 电机模块
Current
Sense
nFAULT
服务机器人
Current Limit
真空吸尘器
Built-In Protection
无人机、机器人和遥控玩具
白色家电
Hall Sensors
ATM 和点钞机
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSE38
DRV8306
ZHCSHZ0A –APRIL 2018–REVISED JULY 2018
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 8
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 25
8
9
Application and Implementation ........................ 26
8.1 Application Information............................................ 26
8.2 Typical Application ................................................. 29
Power Supply Recommendations...................... 34
9.1 Bulk Capacitance Sizing ......................................... 34
10 Layout................................................................... 35
10.1 Layout Guidelines ................................................. 35
10.2 Layout Example .................................................... 36
11 器件和文档支持 ..................................................... 37
11.1 器件支持................................................................ 37
11.2 文档支持................................................................ 37
11.3 接收文档更新通知 ................................................. 37
11.4 社区资源................................................................ 37
11.5 商标....................................................................... 37
11.6 静电放电警告......................................................... 37
11.7 术语表 ................................................................... 38
12 机械、封装和可订购信息....................................... 38
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (April 2018) to Revision A
Page
•
已更改 数据表状态从预告信息更改成了生产数据 ................................................................................................................... 1
2
Copyright © 2018, Texas Instruments Incorporated
DRV8306
www.ti.com.cn
ZHCSHZ0A –APRIL 2018–REVISED JULY 2018
5 Pin Configuration and Functions
RSM Package
32-Pin VQFN With Exposed Thermal Pad
Top View
CPH
VCP
1
2
3
4
5
6
7
8
24
ENABLE
VDS
23
22
21
20
19
18
17
VM
IDRIVE
nFAULT
HNA
VDRAIN
GHA
Thermal
Pad
SHA
HPA
GLA
HNB
ISEN
HPB
Not to scale
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
AGND
CPH
NO.
25
1
PWR
PWR
PWR
I
Device analog ground. Connect to system ground.
Charge-pump switching node. Connect a X5R or X7R, 22-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
Charge-pump switching node. Connect a X5R or X7R, 22-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
Direction pin for setting the direction of the motor rotation to clockwise or counterclockwise. Internal pulldown resistor.
CPL
32
29
DIR
3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins. This regulator
can source up to 30 mA externally.
DVDD
26
24
PWR
I
Gate driver enable. When this pin is logic low the device enters a low-power sleep mode. A 15 to 40-µs low pulse can be used to reset
fault conditions.
ENABLE
FGOUT
GHA
GHB
GHC
GLA
28
5
OD
Outputs a commutation zero crossing signal generated from Hall sensors.
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
11
12
7
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB
9
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC
14
20
18
16
19
17
15
22
8
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
HNA
I
Hall element negative input. Noise filter capacitors may be desirable, connected between the positive and negative Hall inputs.
Hall element negative input. Noise filter capacitors may be desirable, connected between the positive and negative Hall inputs.
Hall element negative input. Noise filter capacitors may be desirable, connected between the positive and negative Hall inputs.
Hall element positive input. Noise filter capacitors may be desirable, connected between the positive and negative Hall inputs.
Hall element positive input. Noise filter capacitors may be desirable, connected between the positive and negative Hall inputs.
Hall element positive input. Noise filter capacitors may be desirable, connected between the positive and negative Hall inputs.
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
Current sense for pulse-by-pulse current limit. Connect to low-side current sense resistor.
Device power ground. Connect to system ground.
HNB
I
HNC
HPA
I
I
HPB
I
HPC
I
IDRIVE
ISEN
PGND
I
I
31
PWR
(1) PWR = power, I = input, O = output, OD = open-drain
Copyright © 2018, Texas Instruments Incorporated
3
DRV8306
ZHCSHZ0A –APRIL 2018–REVISED JULY 2018
www.ti.com.cn
Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
PWM
SHA
NO.
27
6
I
PWM input for motor control. Set the output voltage and switching frequency of the phase voltage of the motor.
High-side source sense input. Connect to the high-side power MOSFET source.
I
SHB
10
13
2
I
High-side source sense input. Connect to the high-side power MOSFET source.
SHC
I
High-side source sense input. Connect to the high-side power MOSFET source.
VCP
PWR
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins.
High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains.
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VDRAIN
VDS
4
I
I
23
Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or
equal to 10-uF local capacitance between the VM and PGND pins.
VM
3
PWR
nBRAKE
nFAULT
30
21
I
Causes motor to brake. Internal pulldown resistor.
OD
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.5
–0.3
–0.3
–0.3
–0.3
–0.3
0
MAX
40
UNIT
V
Power supply voltage (VM)
Voltage differential between any ground pin (AGND, DGND, PGND)
Internal logic regulator voltage (DVDD)
0.5
V
3.8
V
MOSFET voltage sense (VDRAIN)
40
V
Charge pump voltage (VCP, CPH)
VM + 13.5
VM
V
Charge pump negative switching pin voltage (CPL)
Digital pin voltage (PWM, DIR, nBRAKE, nFAULT, ENABLE, VDS, IDRIVE, FGOUT)
Open drain output current range (nFAULT, FGOUT)
Continuous high-side gate pin voltage (GHX)
Pulsed 200 ns high-side gate pin voltage (GHX)
High-side gate voltage with respect to SHX (GHX)
Continuous phase node pin voltage (SHX)
Pulsed 200 ns phase node pin voltage (SHX)
Continuous low-side gate pin voltage (GLX)
Pulsed 200 ns low-side gate pin voltage (GLX)
Gate pin source current (GHX, GLX)
V
5.75
V
5
mA
V
–2
VCP + 0.5
VCP + 0.5
13.5
-5
V
–0.3
–2
V
VM + 2
VM + 2
13.5
V
-5
V
–1
V
-5
13.5
V
Internally limited
Internally limited
A
Gate pin sink current (GHX, GLX)
A
Hall sensor input terminal voltage (HPA, HPB, HPC, HNA, HNB, HNC)
Junction temperature, TJ
0
DVDD
150
V
–40
–65
°C
°C
Storage temperature, Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001
±2000
(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101
±500
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000
V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.
4
Copyright © 2018, Texas Instruments Incorporated
DRV8306
www.ti.com.cn
ZHCSHZ0A –APRIL 2018–REVISED JULY 2018
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
6
MAX
UNIT
V
VVM
Power supply voltage range
38
VI
Logic level input voltage range
0
5.5
V
(1)
fPWM
IGATE_HS
IGATE_LS
IDVDD
fHALL
VOD
Applied PWM signal (PWM)
200
kHz
mA
mA
mA
kHz
V
(1)
(1)
(1)
High-side average gate drive current (GHX)
Low-side average gate drive current (GLX)
DVDD external load current
15
15
30
Hall sensor input frequency
0
0
30
Open drain pull up voltage (nFAULT, FGOUT)
Open drain output current (nFAULT, FGOUT)
Operating ambient temperature
5.5
5
IOD
0
mA
°C
TA
–40
125
(1) Power dissipation and thermal limits must be observed
6.4 Thermal Information
DRV8306
THERMAL METRIC(1)
RSM (VQFN)
32 PINS
32.6
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
29.3
11.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJB
11.9
RθJC(bot)
2.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
at VVM = 6 to 38 V over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLIES (VM, DVDD)
IVM
VM operating supply current
VVM = 24 V; ENABLE = 1; PWM = 0 V
ENABLE = 0; VVM = 24 V, TA = 25°C
ENABLE = 0, VVM = 24 V, TA = 125°C
ENABLE = 0 V period to reset faults
ENABLE = 0 V to driver tri-stated
5
8
40
mA
µA
20
IVMQ
VM sleep mode supply current
100
40
tRST
Reset pulse time
Sleep time
15
µs
µs
tSLEEP
200
VVM > VUVLO; ENABLE = 3.3 V to output
transistion
tWAKE
Wake-up time
1
ms
V
VDVDD
Internal logic regulator voltage
IDVDD = 0 to 30 mA
2.9
3.3
3.6
CHARGE PUMP (VCP, CPH, CPL)
VM = 12 to 38 V; IVCP = 0 to 15 mA
VM = 10 V; IVCP = 0 to 10 mA
VM = 8 V; IVCP = 0 to 5 mA
7
6.5
5
10
7.5
6
11.5
9.5
VCP operating voltage with respect
to VM
VVCP
V
7.5
VM = 6 V; IVCP = 0 to 1 mA
3.8
4.3
6.5
LOGIC-LEVEL INPUTS (PWM, DIR, nBRAKE)
VIL
Input logic low voltage
Input logic high voltage
Input logic hysteresis
Input logic low current
0
1.5
100
–1
0.8
5.5
V
V
VIH
VHYS
IIL
mV
µA
VPIN (Pin Voltage) = 0 V
1
Copyright © 2018, Texas Instruments Incorporated
5
DRV8306
ZHCSHZ0A –APRIL 2018–REVISED JULY 2018
www.ti.com.cn
MAX UNIT
Electrical Characteristics (continued)
at VVM = 6 to 38 V over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VPIN (Pin Voltage) = 5 V
MIN
TYP
IIH
Input logic high current
100
µA
Pulldown resistance (PWM, DIR,
nBRAKE)
RPD
Internal pulldown to AGND
100
kΩ
LOGIC-LEVEL INPUTS (ENABLE)
VIL
VIH
VHYS
IIL
Input logic low voltage
Input logic high voltage
Input logic hysteresis
Input logic low current
Input logic high current
0
1.5
100
–10
–5
0.6
5.5
V
V
mV
µA
µA
VPIN (Pin Voltage) = 0 V
VPIN (Pin Voltage) = 5 V
10
5
IIH
SEVEN-LEVEL INPUTS (IDRIVE, VDS)
VI1
VI2
VI3
VI4
VI5
VI6
VI7
Input mode 1 voltage
Input mode 2 voltage
Input mode 3 voltage
Input mode 4 voltage
Input mode 5 voltage
Input mode 6 voltage
Input mode 7 voltage
Tied to AGND
0
0.5
V
V
V
V
V
V
V
18 kΩ ± 5% to AGND
75 kΩ ± 5% to AGND
Hi-Z
1.1
1.65
2.2
75 kΩ ± 5% to DVDD
18 kΩ ± 5% to DVDD
Tied to DVDD
2.8
3.3
OPEN-DRAIN OUTPUTS (nFAULT, FGOUT)
VOL
IOZ
Output logic low voltage
Output logic high current
IOD = 2 mA
VOD = 5 V
0.1
1
V
–1
µA
GATE DRIVERS (GHX, SHX, GLX)
VVM = 12 to 38 V; IHS_GATE = 0 to 15 mA
VVM = 10 V; IHS_GATE = 0 to 10 mA
VVM = 8 V; IHS_GATE = 0 to 5 mA
VVM = 6 V; IHS_GATE = 0 to 1 mA
VVM = 12 to 38 V; ILS_GATE = 0 to 15 mA
VVM = 10 V; ILS_GATE = 0 to 10 mA
VVM = 8 V; ILS_GATE = 0 to 5 mA
VVM = 6 V; ILS_GATE = 0 to 1 mA
7
6.5
5
10
7.5
6
11.5
8.5
7
High-side VGS gate drive (gate-to-
source)
VGHS
V
V
3.8
7.5
5.5
3.5
3
4.3
10
6.5
12.5
9.5
8.5
6.5
7.5
6
Low-side VGS gate drive (gate-to-
source)
VGSL
4.3
120
4000
15
tDEAD
tDRIVE
Output dead time
ns
ns
Peak gate drive time
IDRIVE tied to AGND
IDRIVE 18 kΩ (±5%) to AGND
IDRIVE 75 kΩ (±5%) to AGND
IDRIVE Hi-Z ( > 500 kΩ to AGND)
IDRIVE 75 kΩ (±5%) to DVDD
IDRIVE 18 kΩ (±5%) to DVDD
IDRIVE tied to DVDD
45
60
Peak source gate current (high-side
and low-side)
IDRIVEP
90
mA
105
135
150
30
IDRIVE tied to AGND
IDRIVE 18 kΩ (±5%) to AGND
IDRIVE 75 kΩ (±5%) to AGND
IDRIVE Hi-Z ( > 500 kΩ to AGND)
IDRIVE 75 kΩ (±5%) to DVDD
IDRIVE 18 kΩ (±5%) to DVDD
IDRIVE tied to DVDD
90
120
180
210
270
300
Peak sink gate current (high-side
and low-side)
IDRIVEN
mA
6
Copyright © 2018, Texas Instruments Incorporated
DRV8306
www.ti.com.cn
ZHCSHZ0A –APRIL 2018–REVISED JULY 2018
Electrical Characteristics (continued)
at VVM = 6 to 38 V over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Source current after tDRIVE
MIN
TYP
15
MAX UNIT
IHOLD
FET holding current
mA
Sink current after tDRIVE
30
ISTRONG
ROFF
tPD
FET hold-off strong pulldown
FET gate hold-off resistor
Propagation delay
GHX and GLX
300
150
180
mA
GHX to SHX and GLX to PGND
PWM transition to GHX/GLX transition
kΩ
250
ns
HALL SENSOR INPUTS (HPX, HNX)
VHYS
ΔVHYS
VID
Hall comparator hysteresis voltage
20
-5
30
40
5
mV
mV
mV
V
Hall comparator hysteresis
difference
Between A, B and C
HPX = HNX = 0 V
Hall comparator input differential
50
1.5
–1
Hall comparator input common
mode voltage CM range
VCM
3.5
1
II
Input leakage current
Hall deglitch time
µA
µs
tHDEG
5
CYCLE-BY-CYCLE CURRENT LIMIT (ISEN)
Voltage limit across RSENSE for the
current limiter
VLIMIT
0.225
0.25
5
0.275
V
Time that VLIMIT is ignored from the
start of the PWM cycle
tBLANK
µs
PROTECTION CIRCUITS
VM falling, UVLO report
VM rising, UVLO recovery
Rising to falling threshold
VM falling, UVLO report
With respect to VM
5.4
5.6
5.8
6
VUVLO
VM undervoltage lockout
V
VUVLO_HYS
tUVLO_DEG
VCPUV
VM undervoltage hysteresis
VM undervoltage deglitch time
Charge pump undervoltage
200
10
mV
µs
V
2.4
Positive clamping voltage
Negative clamping voltage
VDS tied to AGND
10.5
15
VGS_CLAMP
Gate drive clamping voltage
V
–0.6
0.15
0.24
0.4
VDS 18 kΩ (±5%) to AGND
VDS 75 kΩ (±5%) to AGND
VDS Hi-Z ( > 500 kΩ to AGND)
VDS 75 kΩ (±5%) to DVDD
VDS 18 kΩ (±5%) to DVDD
VDS tied to DVDD
VDS_OCP
VDS overcurrent trip voltage
0.6
V
0.9
1.8
Disabled
1.8
VSEN_OCP
tOCP_DEG
VSENSE overcurrent trip voltage
1.7
1.9
V
VDS and VSENSE overcurrent
deglitch time
4.5
µs
tRETRY
TOTSD
THYS
Overcurrent retry time
Thermal shutdown temperature
Thermal hysteresis
4
170
20
ms
°C
°C
Die temperature Tj
Die temperature Tj
150
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6.6 Typical Characteristics
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
VVM = 6 V
TA = -40èC
TA = 25èC
TA = 125èC
VVM = 12 V
VVM = 24 V
VVM = 38 V
0
5
10
15
20
25
30
35
40
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage (V)
Temperature (èC)
D001
D002
图 1. Supply Current Over Supply Voltage
图 2. Supply Current Over Temperature
100
100
90
80
70
60
50
40
30
20
10
0
TA = -40èC
TA = 25èC
TA = 125èC
VVM = 6 V
90
80
70
60
50
40
30
20
10
0
VVM = 12 V
VVM = 24 V
VVM = 38 V
0
5
10
15
20
25
30
35
40
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage (V)
Temperature (èC)
D003
D004
图 3. Sleep Current Over Supply Voltage
图 4. Sleep Current Over Temperature
3.5
3.4
3.3
3.2
3.1
3
3.5
3.4
3.3
3.2
3.1
3
2.9
2.8
2.7
2.6
2.5
2.9
2.8
2.7
2.6
2.5
TA = -40èC
TA = -40èC
TA = 25èC
TA = 25èC
TA = 125èC
TA = 125èC
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Supply Voltage (V)
Supply Voltage (V)
D005
D006
IDVDD = 0 mA
图 5. DVDD Voltage Over Supply Voltage
IDVDD = 30 mA
图 6. DVDD Voltage Over Supply Voltage
8
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Typical Characteristics (接下页)
12
12
10
8
10
8
6
6
4
4
VVM = 6 V
VVM = 8 V
VVM = 10 V
VVM = 12 V
VVM = 6 V
VVM = 8 V
VVM = 10 V
VVM = 12 V
2
2
0
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
-40
-20
0
20
40
60
80
100 120 140
Load Current (mA)
Temperature (èC)
D007
D008
图 7. VCP Voltage Over Load
图 8. VCP Voltage Over Temperature
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7 Detailed Description
7.1 Overview
The DRV8306 device is an integrated 6-V to 38-V gate driver for three-phase motor-drive applications. The
device reduces system component count, cost, and complexity by integrating three independent half-bridge gate
drivers, charge pump, and linear low-dropout (LDO) regulator for the high-side and low-side gate-driver supply
voltages. A hardware interface (H/W) option allows for configuring the most commonly used settings through
fixed external resistors.
The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 150-
mA source and 300-mA sink peak currents with a 15-mA average output current. The high-side gate drive supply
voltage is generated using a doubler charge-pump architecture that regulates the VCP output to VVM + 10 V. The
low-side gate drive supply voltage is generated using a linear regulator from the VM power supply that regulates
to 10 V. A smart gate-drive architecture provides the ability to adjust the output gate-drive current strength
allowing for the gate driver to control the power MOSFET VDS switching speed. This allows for the removal of
external gate drive resistors and diodes reducing BOM component count, cost, and PCB area. The architecture
also uses an internal state machine to protect against gate-drive short-circuit events, control the half-bridge dead
time, and protect against dV/dt parasitic turnon of the external power MOSFET.
The DRV8306 device also integrates three Hall comparators for rotor position sensing using the Hall elements.
This input is used for electronically commutating the BLDC motor in trapezoidal mode. This device also has a
3.3-V LDO regulator which can be powered up to loads up to 30 mA.
In addition to the high level of device integration, the DRV8306 device provides a wide range of integrated
protection features. These features include power-supply undervoltage lockout (UVLO), charge-pump
undervoltage lockout (CPUV), VDS and VSENSE overcurrent monitoring (OCP), gate-driver short-circuit detection
(GDF), and overtemperature shutdown (OTSD). Fault events are indicated by the nFAULT pin.
The DRV8306 device is available in a 0.4-mm pin pitch, VQFN surface-mount package. The VQFN package size
is 4-mm × 4-mm.
10
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7.2 Functional Block Diagram
VM
+
1 …F
bulk
VM
VM
VDRAIN
VM
VCP
HS
Power
GHA
SHA
1 …F
VCP
VCP
CPH
Charge
VGLS
LS
Pump
22 nF
CPL
GLA
30 mA
DVDD
AGND
3.3-V LDO
VGLS LDO
Gate Driver
1 …F
VM
DVDD
VCP
HS
GHB
SHB
ENABLE
PWM
VGLS
LS
GLB
Digital
Core
Hall
A
Hall
B
Hall
C
DIR
Control
Inputs
Gate Driver
nBRAKE
VDS
VM
VCP
HS
GHC
SHC
IDRIVE
FGOUT
VGLS
LS
GLC
Outputs
Gate Driver
nFAULT
PGND
ISEN
VLIMIT
+
œ
RSENSE
PWM Limiter
-
+
VOCP
Sense OCP
HPA
HNA
+
Hall_A
Optional
œ
HPB
HNB
+
Hall_B
Hall_C
Optional
Optional
œ
HPC
HNC
+
œ
Differential
Comparators
PPAD
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7.3 Feature Description
表 1 lists the recommended values of the external components for the gate driver.
表 1. DRV8306 Gate-Driver External Components
COMPONENTS
CVM1
PIN 1
VM
PIN 2
PGND
RECOMMENDED
X5R or X7R, 0.1-µF, VM-rated capacitor
≥ 10-µF, VM-rated capacitor
CVM2
VM
PGND
CVCP
VCP
VM
X5R or X7R, 16-V, 1-µF capacitor
X5R or X7R, VM-rated capacitor, 22-nF capacitor
X5R or X7R, 1-µF, 6.3-V capacitor
Pullup resistor
CSW
CPH
CPL
CDVDD
RnFAULT
RPWM
DVDD
VCC(1)
PWM
nBRAKE
DIR
AGND
nFAULT
AGND or DVDD
AGND or DVDD
AGND or DVDD
AGND or DVDD
AGND or DVDD
DRV8306 hardware interface
DRV8306 hardware interface
DRV8306 hardware interface
DRV8306 hardware interface
DRV8306 hardware interface
RBRK
RDIR
RIDRIVE
RVDS
IDRIVE
VDS
(1) The VCC pin is not a pin on the DRV8306 device, but a VCC supply-voltage pullup is required for the open-drain output nFAULT and
SDO. These pins can also be pulled up to DVDD.
7.3.1 Three Phase Smart Gate Drivers
The DRV8306 device integrates three, half-bridge gate drivers, each capable of driving high-side and low-side N-
channel power MOSFETs. A doubler charge pump provides the proper gate bias voltage to the high-side
MOSFET across a wide operating voltage range in addition to providing 100% duty-cycle support. An internal
linear regulator provides the gate-bias voltage for the low-side MOSFETs.
The DRV8306 device implements a smart gate-drive architecture which lets the user dynamically adjust the gate
drive current (through the IDRIVE pin) without requiring external gate current limiting resistors. Additionally, this
architecture provides a variety of protection features for the external MOSFETs including automatic dead-time
insertion, parasitic dV/dt gate turnon prevention, and gate-fault detection.
7.3.1.1 PWM Control Mode (1x PWM Mode)
The DRV8306 device provides a 1x PWM control mode for driving the BLDC motor into trapezoidal current-
control mode. The DRV8306 device uses 6-step block commutation tables that are stored internally. This feature
lets a three-phase BLDC motor be controlled using a single PWM sourced from a simple controller. The PWM is
applied on the PWM pin and determines the output frequency and duty cycle of the half-bridges.
The half-bridge output states are managed by the HPA, HNA, HPB, HNB, HPC and HNC pins which are used as
state logic inputs. The state inputs are the position feedback of the BLDC motor. The device always operates
with synchronous rectification.
The DIR pin controls the direction of BLDC motor in either clockwise or counter-clockwise direction. Tie the DIR
pin low if this feature is not required.
The nBRAKE input halts the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs
when it is pulled low. This brake is independent of the states of the other input pins. Tie the nBRAKE pin high if
this feature is not required.
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表 2. Synchronous 1x PWM Mode
HALL INPUTS
DIR = 0
HALL_A HALL_B HALL_C HALL_A HALL_B HALL_C
GATE-DRIVE OUTPUTS
DIR = 1
PHASE A
PHASE B
PHASE C
STATE
DESCRIPTION
GHA
GLA
GHB
GLB
GHC
GLC
Stop
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
0
1
0
0
1
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
1
0
0
0
1
1
1
0
0
0
1
L
PWM
L
L
!PWM
L
L
L
L
L
Stop
Align
L
H
L
H
Align
1
2
3
4
5
6
PWM
!PWM
L
L
H
H
B → C
A → C
A → B
C → B
C → A
B → A
PWM
PWM
L
!PWM
!PWM
L
L
L
H
L
L
L
L
H
PWM
PWM
L
!PWM
!PWM
L
L
H
L
L
L
H
PWM
!PWM
图 9 shows the configuration in 1x PWM mode.
DRV8306
H
PWM
MCU_PWM
H
M
DIR
MCU_GPIO
MCU_GPIO
H
nBRAKE
HPA
HNA
HPB
HNB
HPC
HNC
图 9. 1x PWM Mode
7.3.1.2 Hardware Interface Mode
The DRV8306 device supports a hardware interface mode for simple end-application design. In this hardware
interface device, the VDS overcurrent limit and the gate drive current levels can be configured through the
resistor-configurable inputs, IDRIVE and VDS. This feature lets the application designer configure the most
commonly used device settings by tying the pin logic high or logic low, or with a simple pullup or pulldown
resistor.
The IDRIVE pin configures the gate drive current strength. The VDS pin configures the voltage threshold of the
VDS overcurrent monitors.
For more information on the hardware interface, see the Pin Diagrams section.
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DVDD
DVDD
DVDD
IDRIVE
Hardware
Interface
VDS
RVDS
图 10. Sample Configuration of Hardware Interface
7.3.1.3 Gate Driver Voltage Supplies
The high-side gate-drive voltage supply is created using a doubler charge pump that operates from the VM
voltage supply input. The charge pump lets the gate driver correctly bias the high-side MOSFET gate with
respect to its source across a wide input supply voltage range. The charge pump is regulated to maintain a fixed
output voltage of VVM + 10 V and supports an average output current of 15 mA. When the VVM voltage is less
than 12 V, the charge pump operates in full doubler mode and generates VVCP = 2 × VVM – 1.5 V when unloaded.
The charge pump is continuously monitored for undervoltage to prevent under-driven MOSFET conditions. The
charge pump requires a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VM and VCP pins to act as the
storage capacitor. Additionally, a X5R or X7R, 22-nF, VM-rated ceramic capacitor is required between the CPH
and CPL pins to act as the flying capacitor.
VM
VM
1 …F
VCP
CPH
VM
Charge
Pump
22 nF
Control
CPL
图 11. Charge Pump Architecture
The low-side gate drive voltage is created using a linear low-dropout (LDO) regulator that operates from the VM
voltage supply input. The LDO regulator allows the gate driver to properly bias the low-side MOSFET gate with
respect to ground. The LDO regulator output is fixed at 10 V and supports an output current of 15 mA. The LDO
regulator is monitored for undervoltage to prevent under-driven MOSFET conditions.
14
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7.3.1.4 Smart Gate Drive Architecture
The DRV8306 gate drivers use an adjustable, complimentary, push-pull topology for both the high-side and low-
side drivers. This topology allows for both a strong pullup and pulldown of the external MOSFET gates.
Additionally, the gate drivers use a smart gate-drive architecture to provide additional control of the external
power MOSFETs, take additional steps to protect the MOSFETs, and allow for optimal tradeoffs between
efficiency and robustness. This architecture is implemented through two components called IDRIVE and TDRIVE
which are detailed in the IDRIVE: MOSFET Slew-Rate Control section and TDRIVE: MOSFET Gate Drive
Control section. 图 12 shows the high-level functional block diagram of the gate driver.
The IDRIVE gate-drive current and TDRIVE gate-drive time should be initially selected based on the parameters
of the external power MOSFET used in the system and the desired rise and fall times (see the Application and
Implementation section).
The high-side gate driver also implements a Zener clamp diode to help protect the external MOSFET gate from
overvoltage conditions in the case of external short-circuit events on the MOSFET.
VCP
VM
GHx
SHx
Level
Shifters
150 kꢀ
+
V
GSœ
Logic
VGLS
GLx
Level
Shifters
150 kꢀ
PGND
+
V
GSœ
图 12. Gate Driver Block Diagram
7.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
The IDRIVE component implements adjustable gate-drive current to control the MOSFET VDS slew rates. The
MOSFET VDS slew rates are a critical factor for optimizing radiated emissions, energy and duration of diode
recovery spikes, dV/dt gate turnon leading to shoot-through, and switching voltage transients related to parasitics
in the external half-bridge. The IDRIVE component operates on the principal that the MOSFET VDS slew rates
are predominately determined by the rate of gate charge (or gate current) delivered during the MOSFET QGD or
Miller charging region. By allowing the gate driver to adjust the gate current, it can effectively control the slew
rate of the external power MOSFETs.
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The IDRIVE component allows the DRV8306 device to dynamically switch between gate drive currents through
an IDRIVE pin. This hardware interface devices provides seven IDRIVE settings from 15-mA to 150-mA (source)
and 30-mA to 300-mA (sink). The gate drive current setting is delivered to the gate during the turnon and turnoff
of the external power MOSFET for the tDRIVE duration. After the MOSFET turnon or turnoff, the gate driver
switches to a smaller hold current (IHOLD) to improve the gate driver efficiency. Additional details on the IDRIVE
settings are described in the Pin Diagrams section.
7.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
The TDRIVE component is an integrated gate-drive state machine that provides automatic dead time insertion
through switching handshaking, parasitic dV/dt gate turnon prevention, and MOSFET gate-fault detection.
The first component of the TDRIVE state machine is automatic dead-time insertion. Dead time is period of time
between the switching of the external high-side and low-side MOSFETs to ensure that they do not cross conduct
and cause shoot-through. The DRV8306 device uses VGS voltage monitors to measure the MOSFET gate-to-
source voltage and determine the proper time to switch instead of relying on a fixed time value. This feature
allows the gate-driver dead time to adjust for variation in the system such as temperature drift and variation in the
MOSFET parameters. An additional digital dead time (tDEAD) is inserted on top of the gate-driver dead time and is
fixed for the DRV8306 device.
The second component focuses on prevention of parasitic dV/dt gate turnon. To implement this feature, the
TDRIVE state machine enables a strong pulldown current (ISTRONG) on the opposite MOSFET gate whenever a
MOSFET is switching. The strong pulldown last for the TDRIVE duration. This feature helps remove parasitic
charge that couples into the MOSFET gate when the half-bridge switch-node voltage slews rapidly.
The third component implements a gate-fault detection scheme to detect pin-to-pin solder defects, a MOSFET
gate failure, or a MOSFET gate stuck-high or stuck-low voltage condition. This implementation is done with a pair
of VGS gate-to-source voltage monitors for each half-bridge gate driver. When the gate driver receives a
command to change the state of the half-bridge it begins to monitor the gate voltage of the external MOSFET. If
the VGS voltage has not reached the proper threshold at the end of the tDRIVE period, the gate driver reports a
fault. To ensure that a false fault is not detected, the user must ensure that the tDRIVE time is longer than the time
required to charge or discharge the MOSFET gate (this setting can be configured indirectly using the IDRIVE
pin). The tDRIVE time does not increase the PWM time and will terminate if another PWM command is received
while active. Additional details on the TDRIVE settings are described in the Pin Diagrams section for hardware
interface devices.
图 13 shows an example of the TDRIVE state machine in operation.
PWM
tPD
tPD
tDEAD
tDEAD
VGHX
IDRIVE
IHOLD
IHOLD
ISTRONG
ISTRONG
IGHX
IHOLD
IDRIVE
tDEAD
tDEAD
VGLX
IDRIVE
IHOLD
ISTRONG
ISTRONG
IGLX
IHOLD
IHOLD
IDRIVE
tDRIVE
tDRIVE
图 13. TDRIVE State Machine
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7.3.1.4.3 Gate Drive Clamp
A clamping structure limits the gate drive output voltage to the VGS,CLAMP voltage to help protect the external
high-side MOSFETs from gate overvoltage damage. The positive voltage clamp is realized using a series of
diodes. The negative voltage clamp uses the body diodes of the internal pulldown gate driver as shown in 图 14.
VGHS
VM
IREVERSE
GHx
VGS > VCLAMP
ICLAMP
SHx
Predriver
VGLS
VGS negative
GLx
RSENSE
PGND
图 14. Gate Drive Clamp
7.3.1.4.4 Propagation Delay
The propagation delay time (tpd) is measured as the time between an PWM logic edge detected to the GHX /
GLX transition as shown in 图 13. This time comprises three parts consisting of the digital input deglitcher delay,
the digital propagation delay, and the delay through the analog gate drivers.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate
drivers. To support multiple control modes and dead time insertion, a small digital delay is added as the input
command propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to
the overall propagation delay of the device.
In order for the output to change state during normal operation, one MOSFET must first be turned off. The
MOSFET gate is ramped down according to the IDRIVE setting, and the observed propagation delay ends when
the MOSFET gate falls below the threshold voltage.
7.3.1.4.5 MOSFET VDS Monitors
The gate drivers implement adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on
the external power MOSFETs. When the monitored voltage is greater than the VDS trip point (VVDS_OCP) for
longer than the deglitch time (tOCP), an overcurrent condition is detected and the driver enters into the VDS
automatic-retry mode.
The high-side VDS monitors measure the voltage between the VDRAIN and SHx pins and the low side VDS
monitors measure the voltage between the SHx and ISEN pins. The VVDS_OCP threshold is programmable from
0.15 V to 1.8 V. Additional information on the VDS monitor levels are described in the Pin Diagrams section.
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DRV8306
High-Side VDS OCP Monitor
+
VM
VDRAIN
œ
GHx
SHx
GLx
+
VDS,OCP
œ
Low-Side VDS OCP Monitor
+
œ
ISEN
+
VDS,OCP
RSENSE
œ
PGND
图 15. DRV8306 VDS Monitors
7.3.1.4.6 VDRAIN Sense Pin
The DRV8306 device provides a separate sense pin for the common point of the high-side MOSFET drain. This
pin is called VDRAIN. This pin allows the sense line for the overcurrent monitors (VDRAIN) and the power supply
(VM) to remain separate and prevent noise on the VDRAIN sense line. This separation also allows for a small
filter to be implemented on the gate driver supply (VM) or to insert a boost converter to support lower voltage
operation if desired. Care must still be taken when the filter or separate supply is designed because VM is still
the reference point for the VCP charge pump that supplies the high-side gate drive voltage (VGSH). The VM
supply must not drift too far from the VDRAIN supply to avoid violating the VGS voltage specification of the
external power MOSFETs.
7.3.2 DVDD Linear Voltage Regulator
A 3.3-V, 30-mA linear regulator is integrated into the DRV8306 device and is available for use by external
circuitry. This regulator can provide the supply voltage for a low-power microcontroller or other low-current
supporting circuitry. The output of the DVDD regulator should be bypassed near the DVDD pin with a X5R or
X7R, 1-µF, 6.3-V ceramic capacitor routed directly back to the adjacent AGND ground pin.
The DVDD nominal, no-load output voltage is 3.3 V. When the DVDD load current exceeds 30 mA, the regulator
functions like a constant-current source. The output voltage drops significantly with a current load greater than 30
mA.
VM
+
REF
3.3 V, 30 mA
maximum
DVDD
AGND
œ
1 …F
图 16. DVDD Linear Regulator Block Diagram
Use 公式 1 to calculate the power dissipated in the device because of the DVDD linear regulator.
P = VVM - VDVDD ì I
DVDD
(1)
For example, at VVM = 24 V, drawing 20 mA out of DVDD results in a power dissipation as shown in 公式 2.
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P = 24 V - 3.3 V ì 20 mA = 414 mW
(2)
7.3.3 Pulse-by-Pulse Current Limit
The current-limit circuit activates if the voltage detected across the low-side sense resistor (ISEN pin) exceeds
the VLIMIT voltage. This feature restricts motor current to less than the VLIMIT voltage divided by the RSENSE
resistance.
注
The current-limit circuit is ignored immediately after the PWM signal goes active for a short
blanking time to prevent false trips of the current-limit circuit.
If the current limit activates, the high-side FET is disabled until the beginning of the next PWM cycle. Because
the synchronous rectification is always enabled, when the current limit activates, the low-side FET is activated
while the high-side FET is disabled.
VM
X
X
X
PWM
PWM
Ph_C
Ph_A
Ph_B
RSENSE
图 17. Bridge Operation in Normal Mode (Current Limit Not Active)
VM
X
X
X
X
Ph_C
Ph_A
Ph_B
Low-Side
Recirculation
Mode
RSENSE
图 18. Bridge Operation in Current Limit Mode (Current Limit Active)
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PWM
ILIMIT
Bridge Operating in
Brake Mode
IBRIDGE
图 19. Pulse-by-Pulse Current-Limit Operation
7.3.4 Hall Comparators
Three comparators are provided to process the raw signals from the Hall effect transducers to commutate the
motor. The Hall comparators sense zero crossings of the differential inputs and pass the information to digital
logic. The Hall comparators have hysteresis, and their detect threshold is centered at 0. The hysteresis is defined
as shown in 图 20.
In addition to the hysteresis, the Hall inputs are deglitched with a circuit that ignores any extra Hall transitions for
a period of tHDEG after sensing a valid transition. Ignoring these transitions for the tHDEG time prevents PWM noise
from being coupled into the Hall inputs, which can result in erroneous commutation.
If excessive noise is still coupled into the Hall comparator inputs, adding capacitors between the positive and
negative inputs of the Hall comparators may be required. The ESD protection circuitry on the Hall inputs
implements a diode to the DVDD pin. Because of this diode, the voltage on the Hall inputs should not exceed the
DVDD voltage.
Because the DVDD pin is disabled in standby mode (ENABLE inactive), the Hall inputs should not be driven by
external voltages in standby mode. If the Hall sensors are powered externally, the supply to the Hall sensors
should be disabled if the DRV8306 device is put into standby mode. In addition, the Hall sensor power supply
should be powered up after enabling the motor otherwise an invalid Hall state may cause a delay in motor
operation.
Hall Differential
Voltage (VID/2)
VHYS/2
Hall Comparator
Common Mode
Voltage (VCM
)
Hall Comparator
Output (Internal)
tHDEG (Hall
Deglitch Time)
图 20. Hall Comparators
20
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7.3.5 FGOUT Signal
The DRV8306 device also has an open-drain FGOUT signal that can be used for the closed-loop speed control
of BLDC motor. This signal includes the information of all three Hall-elements inputs as shown in 图 21.
Hall Input
(HPA, HNA)
Hall Input
(HPB, HNB)
Hall Input
(HPC, HNC)
Hall Output
(Internal Hall_A)
Hall Output
(Internal Hall_B)
Hall Output
(Internal Hall_C)
FGOUT
Time
图 21. FGOUT Signal
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7.3.6 Pin Diagrams
图 22 shows the input structure for the logic-level pins, PWM, DIR and nBRAKE. The input can be driven with a
voltage or external resistor.
DVDD
STATE
VIH
RESISTANCE
Tied to DVDD
Tied to AGND
INPUT
Logic High
Logic Low
VIL
RPD
图 22. Logic-Level Input Pin Structure (PWM, DIR, and nBRAKE)
图 23 shows the input structure for the logic-level pin, ENABLE pin. The input can be driven with a voltage or
external resistor. The VEXT represents the external voltage.
5 V
RPU2
Latch
VEXT
STATE
VIH
RESISTANCE
Tied to VEXT
Tied to AGND
INPUT
RPU1
Logic High
Logic Low
VIL
图 23. Logic-Level Input Pin Structure (ENABLE)
图 24 shows the structure of the open-drain output pin, nFAULT. The open-drain output requires an external
pullup resistor to function properly.
VEXT
R
PU
STATE
No Fault
Fault
STATUS
Inactive
Active
OUTPUT
Active
Inactive
图 24. Open-Drain Output Pin Structure
22
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图 25 shows the structure of the seven level input pins, IDRIVE and VDS. The input can be set with an external
resistor.
IDRIVE
VDS
150/300 mA
Disabled
+
œ
VOLTAGE
VI7
RESISTANCE
Tied to DVDD
135/270 mA
105/210 mA
90/180 mA
60/120 mA
45/90 mA
1.8 V
0.9 V
0.6 V
0.4 V
0.24 V
0.15 V
DVDD
+
DVDD
œ
18 kꢀ ± 5%
to DVDD
VI6
VI5
VI4
VI3
VI2
VI1
+
75 kꢀ ± 5%
to DVDD
73 kꢀ
œ
Hi-Z (>500 kΩ
to AGND)
73 kꢀ
+
75 kꢀ ± 5%
to AGND
œ
18 kΩ ±5%
to AGND
+
Tied to AGND
œ
+
œ
15/30 mA
图 25. Seven Level Input Pin Structure
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7.3.7 Gate-Driver Protective Circuits
The DRV8306 device is fully protected against VM undervoltage, charge pump undervoltage, MOSFET VDS
overcurrent, gate driver shorts, and overtemperature events.
表 3. Fault Action and Response
FAULT
CONDITION
REPORT
GATE DRIVER
LOGIC
RECOVERY
Automatic:
VVM > VUVLO
VM undervoltage
(UVLO)
VVM < VUVLO
nFAULT
Hi-Z
Disabled
Charge pump
undervoltage
(CPUV)
Automatic:
VVCP > VCPUV
VVCP < VCPUV
nFAULT
Hi-Z
Active
Retry:
tRETRY
VDS overcurrent
(VDS_OCP)
VDS > VVDS_OCP
nFAULT
nFAULT
nFAULT
nFAULT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Active
Active
Active
Active
VSENSE overcurrent
(SEN_OCP)
Retry:
tRETRY
VSP > VSEN_OCP
Latched:
ENABLE Pulse
Gate driver fault
(GDF)
Gate voltage stuck > tDRIVE
TJ > TOTSD
Automatic:
TJ < TOTSD – THYS
Thermal shutdown
(OTSD)
7.3.7.1 VM Supply Undervoltage Lockout (UVLO)
If at any time the input supply voltage on the VM pin falls below the VUVLO threshold, all of the external MOSFETs
are disabled, the charge pump is disabled, and the nFAULT pin is driven low. Normal operation resumes (gate
driver operation and the nFAULT pin is released) when the VM undervoltage condition is removed.
7.3.7.2 VCP Charge-Pump Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin (charge pump) falls below the VCPUV threshold voltage of the charge
pump, all of the external MOSFETs are disabled and the nFAULT pin is driven low. Normal operation resumes
(gate-driver operation and the nFAULT pin is released) when the VCP undervoltage condition is removed.
7.3.7.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
A MOSFET overcurrent event is sensed by monitoring the VDS voltage drop across the external MOSFET RDS(on)
.
If the voltage across an enabled MOSFET exceeds the VVDS_OCP threshold for longer than the tOCP_DEG deglitch
time, a VDS_OCP event is recognized. The VVDS_OCP threshold is set with the VDS pin, the tOCP_DEG is fixed at
4.5 µs, and the driver operates with fixed for 4-ms automatic retry in an OCP event, but can be disabled by tying
the VDS pin to DVDD.
7.3.7.4 VSENSE Overcurrent Protection (SEN_OCP)
Three-phase bridge overcurrent is also monitored by sensing the voltage drop across the external current-sense
resistor with the ISEN pin. If at any time the voltage on the ISEN input of the current-sense amplifier exceeds the
VSEN_OCP threshold for longer than the tOCP_DEG deglitch time, a SEN_OCP event is recognized. The VSEN,OCP
threshold is fixed at 1.8 V, tOCP_DEG is fixed at 4 µs, and, during the OCP event, the driver operates with fixed
tRETRY for 4-ms automatic retry.
7.3.7.5 Gate Driver Fault (GDF)
The GHx and GLx pins are monitored such that if the voltage on the external MOSFET gate does not increase or
decrease after the tDRIVE time, a gate driver fault is detected. This fault may be encountered if the GHx or GLx
pins are shorted to the PGND, SHx, or VM pins. Additionally, a gate driver fault may be encountered if the
selected IDRIVE setting is not sufficient to turn on the external MOSFET within the tDRIVE period. After a gate drive
fault is detected, all external MOSFETs are disabled and the nFAULT pin is driven low. Normal operation
resumes (gate driver operation and the nFAULT pin is released) when the gate driver fault condition is removed.
Gate driver faults can indicate that the selected IDRIVE or tDRIVE settings are too low to slew the external MOSFET
in the desired time. Increasing either the IDRIVE or tDRIVE setting can resolve gate driver faults in these cases.
Alternatively, if a gate-to-source short occurs on the external MOSFET, a gate driver fault is reported because of
the MOSFET gate not turning on.
24
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7.3.7.6 Thermal Shutdown (OTSD)
If the die temperature exceeds the trip point of the thermal shutdown limit (TOTSD), all the external MOSFETs are
disabled, the charge pump is shut down, and the nFAULT pin is driven low. Normal operation resumes (gate
driver operation and the nFAULT pin is released) when the overtemperature condition is removed. This
protection feature cannot be disabled.
7.4 Device Functional Modes
7.4.1 Gate Driver Functional Modes
7.4.1.1 Sleep Mode
The ENABLE pin manages the state of the DRV8306 device. When the ENABLE pin is low, the device goes to a
low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are disabled, the
charge pump is disabled, and the DVDD regulator is disabled. The tSLEEP time must elapse after a falling edge on
the ENABLE pin before the device goes to the sleep mode. The device goes from the sleep mode automatically
if the ENABLE pin is pulled high. The tWAKE time must elapse before the device is ready for inputs.
In sleep mode and when VVM < VUVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are
pulled to the SHx pin by an internal resistor and the low-side gate pins, GLx, are pulled to the PGND pin by an
internal resistor.
注
During power up and power down of the device through the ENABLE pin, the nFAULT pin
is held low as the internal regulators are enabled or disabled. After the regulators have
enabled or disabled, the nFAULT pin is automatically released. The duration that the
nFAULT pin is low does not exceed the tSLEEP or tWAKE time.
7.4.1.2 Operating Mode
When the ENABLE pin is high or left floating and VVM > VUVLO, the device goes to the operating mode. The tWAKE
time must elapse before the device is ready for inputs. In this mode the charge pump, low-side gate regulator,
and DVDD regulator are active. The hardware inputs (IDRIVE and VDS) are latched during the wake-up time
(tWAKE). Any further change to these pins is ignored unless a power-up cycle or an ENABLE pin transition after
sleep mode occurs.
7.4.1.3 Fault Reset (ENABLE Reset Pulse)
In the case of device-latched faults, the DRV8306 device goes to driver Hi-Z state to help protect the external
power MOSFETs and system.
When the fault condition is removed the device can go back to the operating state by issuing a result pulse to the
ENABLE pin on either interface variant. The ENABLE reset pulse (tRST) consists of a high-to-low-to-high
transition on the ENABLE pin. The low period of the sequence should fall with the tRST time window or else the
device will begin the complete shutdown sequence. The reset pulse has no effect on any of the regulators,
device settings, or other functional blocks
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8306 device is primarily used in three-phase brushless DC motor-control applications. The design
procedures in the Typical Application section highlight how to use and configure the DRV8306 device.
8.1.1 Hall Sensor Configuration and Connection
The combinations of Hall sensor connections in this section are common connections.
8.1.1.1 Typical Configuration
The Hall sensor inputs on the DRV8306 device can interface with a variety of Hall sensors. Typically, a Hall
element is used, which outputs a differential signal on the order of 100 mV. To use this type of sensor, the DVDD
regulator can be used to power the Hall sensor. 图 26 shows the connections.
DVDD
INP
OUTN
OUTP
HPx
HNx
Hall Sensor
INN
Hall
Comparator
Optional
图 26. Typical Hall Sensor Configuration
Because the amplitude of the Hall-sensor output signal is very low, capacitors are often placed across the Hall
inputs to help reject noise coupled from the motor. Capacitors with a value of 1 nF to 100 nF are typically used.
8.1.1.2 Open Drain Configuration
Some motors use digital Hall sensors with open-drain outputs. These sensors can also be used with the
DRV8306 device, with the addition of a few resistors as shown in 图 27.
DVDD
1 to
1 to
4.7 kΩ
4.7 kΩ
VCC
HPx
HNx
Hall Sensor
GND
+
OUT
Hall
Comparator
œ
To Other
HNx Inputs
图 27. Open-Drain Hall Sensor Configuration
26
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Application Information (接下页)
The negative (HNx) inputs are biased to DVDD / 2 by a pair of resistors between the DVDD pin and ground. For
open-collector Hall sensors, an additional pullup resistor to the VREG pin is required on the positive (HPx) input.
Again, the DVDD output can usually be used to supply power to the Hall sensors.
8.1.1.3 Series Configuration
Hall elements are also connected in series or parallel depending upon the Hall sensor current/voltage
requirement. 图 28 shows the series connection of Hall sensors powered via the DRV8306 internal LDO (DVDD).
This configuration is used if the current requirement per Hall sensor is high (>10 mA)
DVDD
RSE
(Optional)
INP
HPA
HNA
Hall
Sensor
+
OUTN
OUTN
OUTN
OUTP
OUTP
OUTP
Hall
Comparator
INN
œ
INP
HPB
HNB
Hall
Sensor
+
Hall
Comparator
INN
œ
INP
HPC
HNC
Hall
Sensor
+
Hall
Comparator
INN
GND
œ
图 28. Hall Sensor Connected in Series Configuration
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Application Information (接下页)
8.1.1.4 Parallel Configuration
图 29 shows the parallel connection of Hall sensors which is powered by the DVDD. This configuration can be
used if the current requirement per Hall sensor is low (<10 mA).
DVDD
RSE
INP
HPA
HNA
Hall
Sensor
+
OUTN
OUTN
OUTN
OUTP
Hall
Comparator
INN
GND
œ
INP
HPB
HNB
Hall
Sensor
+
OUTP
Hall
Comparator
INN
GND
œ
INP
HPC
HNC
Hall
Sensor
+
OUTP
GND
Hall
Comparator
INN
œ
图 29. Hall Sensors Connected in Parallel Configuration
28
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8.2 Typical Application
8.2.1 Primary Application
Power and Charge Pump
VM
3.3 V, 30 mA
DVDD
AGND
VM
GND
1 µF
Three Phase Inverter
VM
GND
Gate Driver
BLDC Motor with
Hall Elements
VDD
Power
GND
GP-O
GHA
SHA
GLA
DIR
GP-O
GP-I
GP-I
BRK
FGOUT
nFAULT
ENABLE
GHB
SHB
GLB
DVDD
GP-O
GPIO
PWM
Module
PWM_Out
PWM
GHC
SHC
GLC
VDS
IDRIVE
Hardwired
with VDD
and GND
Microcontroller
Smart Gate Drive
100 mA, 200 mA
(Fully Protected)
Hall
A
Hall
B
Hall
C
Current Sense
for OCP,
Current
Sense
RSENSE
ISEN
Current Limit
HPA, HNA
HPB, HNB
HPC, HNC
Hall
Comparators
DRV8306
图 30. Primary Application Schematic
8.2.1.1 Design Requirements
表 4 lists the example input parameters for the system design.
表 4. Design Parameters
EXAMPLE DESIGN PARAMETER
Nominal supply voltage
Supply voltage range
REFERENCE
EXAMPLE VALUE
24 V
VVM
8 V to 38 V
MOSFET part number
CSD18514Q5A
29 nC (typical) at VVGS = 10 V
5 nC (typical)
100 to 300 ns
50 to 150 ns
45 kHz
MOSFET total gate charge
MOSFET gate to drain charge
Target output rise time
Target output fall time
Qg
Qgd
tr
tf
PWM frequency
ƒPWM
Imax
ISENSE
IRMS
PSENSE
TA
Maximum motor current
Winding sense current range
Motor RMS current
50 A
–20 A to +20 A
14.14 A
Sense resistor power rating
System ambient temperature
2 W
–20°C to +105°C
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 External MOSFET Support
The DRV8306 MOSFET support is based on the charge-pump capacity and output PWM switching frequency.
For a quick calculation of MOSFET driving capacity, use 公式 3 for three-phase BLDC motor applications.
Trapezoidal 120° Commutation:IVCP > Qg × ƒPWM
where
•
•
•
ƒPWM is the maximum desired PWM switching frequency.
IVCP is the charge pump capacity, which depends on the VM pin voltage.
The multiplier based on the commutation control method, may vary based on implementation.
(3)
8.2.1.2.1.1 Example
If a system at VVM = 8 V (IVCP = 15 mA) uses a maximum PWM switching frequency of 45 kHz, then the charge-
pump can support MOSFETs using trapezoidal commutation with a Qg < 333 nC. When the VM voltage (VVM) is
8 V, the maximum DRV8306 gate drive voltage (VGSH) is 7.3 V. Therefore, at 7.3-V gate drive, the target FET
(part number CSD18514Q5A) only has a gate charge of approximately 22 nC. Therefore, with this FET, the
system can have an adequate margin.
8.2.1.2.2 IDRIVE Configuration
The gate drive current strength, IDRIVE, is selected based on the gate-to-drain charge of the external MOSFETs
and the target rise and fall times at the outputs. If IDRIVE is selected to be too low for a given MOSFET, then the
MOSFET may not turn on completely within the tDRIVE time and a gate drive fault may be asserted. Additionally,
slow rise and fall times will lead to higher switching power losses. TI recommends adjusting these values in the
system with the required external MOSFETs and motor to determine the best possible setting for any application.
The IDRIVEP and IDRIVEN current for both the low-side and high-side MOSFETs are selected simultaneously on the
IDRIVE pin.
For MOSFETs with a known gate-to-drain charge Qgd, desired rise time (tr), and a desired fall time (tf), use 公式
4 and 公式 5 to calculate the value of IDRIVEP and IDRIVEN (respectively).
Qgd
IDRIVEP
=
tr
(4)
(5)
Qgd
tf
IDRIVEN
=
8.2.1.2.2.1 Example
Use 公式 6 and 公式 7 to calculate the value of IDRIVEP1 and IDRIVEP2 (respectively) for a gate to drain charge of 5
nC and a rise time from 100 to 300 ns.
5 nC
IDRIVEP1
=
= 50 mA
100 ns
5 nC
(6)
(7)
IDRIVEP2
=
= 16.67 mA
300 ns
Select a value for IDRIVEP that is between 16.67 mA and 50 mA. For this example, the value of IDRIVEP was
selected as 45-mA source.
Use 公式 8 and 公式 9 to calculate the value of IDRIVEN1 and IDRIVEN2 (respectively) for a gate to drain charge of 5
nC and a fall time from 50 to 150 ns.
5 nC
IDRIVEN1
=
= 100 mA
50 ns
(8)
5 nC
IDRIVEN2
=
= 33.33 mA
150 ns
(9)
30
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Select a value for IDRIVEN that is between 33.33 mA and 100 mA. For this example, the value of IDRIVEN was
selected as 90-mA sink.
8.2.1.2.3 VDS Overcurrent Monitor Configuration
The VDS monitors are configured based on the worst-case motor current and the RDS(on) of the external
MOSFETs as shown in 公式 10.
VDS _ OCP > Imax ì RDS(on)max
(10)
8.2.1.2.3.1 Example
The goal of this example is to set the VDS monitor to trip at a current greater than 50 A. According to the
CSD18514Q5A 40 V N-Channel NexFET™ Power MOSFET data sheet, the RDS(on) value is 1.8 times higher at
175°C, and the maximum RDS(on) value at a VGS of 10 V is 4.9 mΩ. From these values, the approximate worst-
case value of RDS(on) is 1.8 × 4.9 mΩ = 8.82 mΩ.
Using 公式 10 with a value of 8.82 mΩ for RDS(on) and a worst-case motor current of 50 A, 公式 11 shows the
calculated the value of the VDS monitors.
VDS_OCP > 50 A ì 8.82 mW
VDS_OCP > 0.441 V
(11)
For this example, the value of VDS_OCP was selected as 0.51 V.
The deglitch time for the VDS overcurrent monitor is fixed at 4 µs.
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8.2.1.3 Application Curves
图 31. IDRIVE Maximum Setting
图 32. IDRIVE Minimum Setting
图 33. Gate Drive 80% Duty Cycle
图 34. Gate Drive 20% Duty Cycle
图 35. Motor Operation at 80% PWM Duty
图 36. Motor Operation at 20% PWM Duty
32
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图 37. Hall Operation (Digital Hall Sensors Connected)
图 38. VLIMIT Operation
图 39. Motor Starting With PWM Duty Change
图 40. Motor Starting With Supply Voltage Change
图 41. Motor Performance at Speed Change
图 42. Motor Performance at Load Change
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9 Power Supply Recommendations
The DRV8306 device is designed to operate from an input voltage supply (VM) range from 6 V to 38 V. A 0.1-µF
ceramic capacitor rated for VM must be placed as close to the device as possible. In addition, a bulk capacitor
must be included on the VM pin but can be shared with the bulk bypass capacitance for the external power
MOSFETs. Additional bulk capacitance is required to bypass the external half-bridge MOSFETs and should be
sized according to the application requirements.
9.1 Bulk Capacitance Sizing
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The
amount of local capacitance depends on a variety of factors including:
•
•
•
•
•
•
The highest current required by the motor system
The power supply's type, capacitance, and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable supply voltage ripple
Type of motor (brushed DC, brushless DC, stepper)
The motor startup and braking methods
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet provides a recommended minimum value, but system level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
œ
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
图 43. Motor Drive Supply Parasitics Example
34
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10 Layout
10.1 Layout Guidelines
Bypass the VM pin to the PGND pin using a low-ESR ceramic bypass capacitor with a recommended value of
0.1 µF. Place this capacitor as close to the VM pin as possible with a thick trace or ground plane connected to
the PGND pin. Additionally, bypass the VM pin using a bulk capacitor rated for VM. This component can be
electrolytic. This capacitance must be at least 10 µF.
Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk
capacitance should be placed such that it minimizes the length of any high current paths through the external
MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB
layers. These practices minimize inductance and let the bulk capacitor deliver high current.
Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 47 nF, rated for
VM, and be of type X5R or X7R. Additionally, place a low-ESR ceramic capacitor between the VCP and VM pins.
This capacitor should be 1 µF, rated for 16 V, and be of type X5R or X7R.
Bypass the DVDD pin to the AGND pin with a 1-µF low-ESR ceramic capacitor rated for 6.3 V and of type X5R
or X7R. Place this capacitor as close to the pin as possible and minimize the path from the capacitor to the
AGND pin.
The VDRAIN pin can be shorted directly to the VM pin. However, if a significant distance is between the device
and the external MOSFETs, use a dedicated trace to connect to the common point of the drains of the high-side
external MOSFETs. Do not connect the SLx pins directly to PGND. Instead, use dedicated traces to connect
these pins to the sources of the low-side external MOSFETs. These recommendations offer more accurate VDS
sensing of the external MOSFETs for overcurrent detection.
Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of
the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx
pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the
low-side MOSFET source back to the PGND pin.
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10.2 Layout Example
S
S
S
G
D
D
D
D
GND
D
D
D
D
G
S
S
S
GND
D
D
D
D
G
S
S
S
16
15
14
13
12
11
10
9
HNC
HPC
GLC
SHC
GHC
GHB
SHB
GLB
25
26
AGND
DVDD
DVDD
PWM
PWM 27
FGOUT
DIR
FGOUT
DIR
28
29
Thermal Pad
nBRAKE
nBRAKE 30
S
S
S
G
D
D
D
D
PGND
CPL
31
32
S
S
S
G
D
D
D
D
D
D
D
D
G
S
S
S
GND
图 44. Layout Example
36
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11 器件和文档支持
11.1 器件支持
11.1.1 器件命名规则
下图显示了说明完整器件名称的图例：
(6)
(RSN) (R)
DRV83
Prefix
Tape and Reel
DRV83 œ Three Phase Brushless DC
R œ Tape and Reel
T œ Small Tape and Reel
Package
RSN œ 4 × 4 × 0.75 mm QFN
Series
6 œ 40 V device
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
•
•
•
•
•
德州仪器 (TI)，《AN-1149 开关电源布局指南》应用报告
德州仪器 (TI)，《DRV8306EVM 用户指南》
德州仪器 (TI)，《采用 BLDC 电机的高效真空吸尘器硬件设计注意事项》应用报告
德州仪器 (TI)，《采用 BLDC 电机的电动自行车硬件设计注意事项》应用报告
德州仪器 (TI)，《工业电机驱动解决方案指南》
德州仪器 (TI)，《开关电源布局指南》应用报告
德州仪器 (TI)，《采用 TI 智能栅极驱动技术进行电机驱动保护》TI 技术手册
德州仪器 (TI)，《QFN/SON PCB 连接》应用报告
德州仪器 (TI)，《采用 TI 智能栅极驱动技术缩减电机驱动 BOM 和 PCB 面积》TI 技术手册
德州仪器 (TI)，《采用 MSP430™ 的传感器式三相 BLDC 电机控制》应用报告
德州仪器 (TI)，《TI 电机栅极驱动器的 IDRIVE 和 TDRIVE 认知》应用报告
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
NexFET, MSP430, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
版权 © 2018, Texas Instruments Incorporated
37
DRV8306
ZHCSHZ0A –APRIL 2018–REVISED JULY 2018
www.ti.com.cn
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
38
版权 © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8306HRSMR
DRV8306HRSMT
ACTIVE
VQFN
VQFN
RSM
32
32
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
DRV
8306H
ACTIVE
RSM
NIPDAU
DRV
8306H
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8306HRSMR
DRV8306HRSMT
VQFN
VQFN
RSM
RSM
32
32
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV8306HRSMR
DRV8306HRSMT
VQFN
VQFN
RSM
RSM
32
32
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RSM 32
4 x 4, 0.4 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224982/A
www.ti.com
PACKAGE OUTLINE
RSM0032B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
B
4.1
3.9
A
0.45
0.25
0.25
0.15
PIN 1 INDEX AREA
DETAIL
OPTIONAL TERMINAL
TYPICAL
4.1
3.9
(0.1)
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2.8 0.05
2X 2.8
(0.2) TYP
4X (0.45)
28X 0.4
9
16
SEE SIDE WALL
DETAIL
8
17
EXPOSED
THERMAL PAD
2X
SYMM
33
2.8
24
0.25
32X
1
SEE TERMINAL
DETAIL
0.15
0.1
C A B
25
32
PIN 1 ID
(OPTIONAL)
0.05
SYMM
0.45
0.25
32X
4219108/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.8)
SYMM
32
25
32X (0.55)
1
32X (0.2)
24
(
0.2) TYP
VIA
(1.15)
SYMM
33
(3.85)
28X (0.4)
17
8
(R0.05)
TYP
9
16
(1.15)
(3.85)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219108/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.715)
4X ( 1.23)
(R0.05) TYP
25
32
32X (0.55)
1
24
32X (0.2)
(0.715)
(3.85)
33
SYMM
28X (0.4)
17
8
METAL
TYP
16
9
SYMM
(3.85)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 33:
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219108/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
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的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE
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