DRV8300UDIPWR [TI]
100-V max, simple three-phase gate driver with bootstrap diodes and enhanced UVLO protection | PW | 20 | -40 to 125;
| 型号： | DRV8300UDIPWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 100-V max, simple three-phase gate driver with bootstrap diodes and enhanced UVLO protection | PW | 20 | -40 to 125 |
| 文件： | 总34页 (文件大小：2949K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV8300U
ZHCSQZ4A –JULY 2022 –REVISED OCTOBER 2022
DRV8300U：100V 三相BLDC 栅极驱动器
1 特性
3 说明
• 100V 三相半桥栅极驱动器
DRV8300U 是一款 100V 三相半桥栅极驱动器，能够
驱动高侧和低侧 N 沟道功率 MOSFET。DRV8300UD
使用集成自举二极管和外部电容为高侧 MOSFET 生成
合适的栅极驱动电压。GVDD 用于为低侧 MOSFET 生
成栅极驱动电压。栅极驱动架构支持高达 750mA 的峰
值拉电流和1.5A 的灌电流。
– 驱动N 沟道MOSFET (NMOS)
– 栅极驱动器电源(GVDD)：5-20V
– MOSFET 电源(SHx) 支持高达100V 的电压
• 集成自举二极管(DRV8300UD 器件)
• 支持反相和同相INLx 输入
• 自举栅极驱动架构
相位引脚 SHx 能够承受显著的负电压瞬变；而高侧栅
极驱动器电源 BSTx 和 GHx 能够支持更高的正电压瞬
变 (125V) 绝对最大值，从而提高系统的鲁棒性。较小
的传播延迟和延迟匹配参数可尽可能降低死区时间要
求，从而进一步提高效率。通过GVDD 和BST 欠压锁
定为低侧和高侧提供欠压保护。
– 750mA 拉电流
– 1.5A 灌电流
• 支持由高达15 节串联电池供电的应用
• 支持标准MOSFET 的更高BSTUV（8V 典型值）
和GVDDUV（7.6V 典型值）阈值
• SHx 引脚具有低漏电流（小于55µA）
• 绝对最大BSTx 电压高达125V
• SHx 引脚瞬态负压可达-22V
• 内置跨导保护
• 针对QFN 封装型号，可通过DT 引脚调节死区时间
• 针对TSSOP 封装型号，固定插入200ns 死区时间
• 支持3.3V 和5V 逻辑输入（绝对最大值为20V）
• 4ns 典型传播延迟匹配
器件信息(1)
封装尺寸（标称值）
器件型号
封装
TSSOP (20)
TSSOP (20)
VQFN (24)
DRV8300UDPW
DRV8300UDIPW
DRV8300UDRGE
6.40mm × 4.40mm
6.40mm × 4.40mm
4.00mm × 4.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 紧凑型QFN 和TSSOP 封装
• 具有电源块的高效系统设计
• 集成保护特性
PVDD
GVDD
DBx
BSTA, BSTB, BSTC
GVDD
– BST 欠压锁定(BSTUV)
INHA
INHB
INHC
GHA, GHB, GHC
SHA, SHB, SHC
– GVDD 欠压(GVDDUV)
MCU
2 应用
DRV8300D
INLA
INLB
INLC
GLA, GLB. GLC
• 电动自行车、电动踏板车和电动汽车
• 风扇、泵和伺服驱动器
GND
Repeated for 3
phases
• 无刷直流(BLDC) 电机模块和PMSM
• 无线园艺和电动工具、割草机
• 无线真空吸尘器
• 无人机、机器人和遥控玩具
• 工业和物流机器人
DRV8300UD 的简化原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSGY3
DRV8300U
ZHCSQZ4A –JULY 2022 –REVISED OCTOBER 2022
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Table of Contents
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................15
9 Application and Implementation..................................16
9.1 Application Information............................................. 16
9.2 Typical Application.................................................... 17
10 Power Supply Recommendations..............................20
11 Layout...........................................................................21
11.1 Layout Guidelines................................................... 21
11.2 Layout Example...................................................... 21
12 Device and Documentation Support..........................22
12.1 接收文档更新通知................................................... 22
12.2 支持资源..................................................................22
12.3 Trademarks.............................................................22
12.4 Electrostatic Discharge Caution..............................22
12.5 术语表..................................................................... 22
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings Comm....................................................6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics.............................................7
7.6 Timing Diagrams.........................................................9
7.7 Typical Characteristics................................................9
8 Detailed Description......................................................11
8.1 Overview................................................................... 11
8.2 Functional Block Diagram.........................................12
Information.................................................................... 22
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (July 2022) to Revision A (October 2022)
Page
• 将器件状态更新为“量产数据”......................................................................................................................... 1
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5 Device Comparison Table
Integrated Bootstrap
Diode
GLx polarity with
Deadtime
Device Variants
Package
respect to INLx Input
DRV8300UD
DRV8300UDI
DRV8300UD
Yes
Yes
Yes
Inverted
Non-Inverted
Fixed
Fixed
20-Pin TSSOP
24-Pin VQFN
Non-Inverted or Inverted
Variable
表5-1. DRV8300 vs DRV8300U comparison
Parameters
DRV8300
4.6-V (typ)
4.35-V (typ)
4.2-V (typ)
4-V (typ)
DRV8300U
GVDDUV rising
GVDDUV falling
BSTUV rising
BSTUV falling
8.3-V (typ)
8-V (typ)
8-V (typ)
7.6-V(typ)
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6 Pin Configuration and Functions
INLA
INLB
1
2
3
4
5
6
18 SHA
17
16
BSTB
GHB
DRV8300
INLC
GVDD
15 SHB
PowerPAD
14
MODE
GND
BSTC
13
GHC
图6-1. DRV8300UD RGE Package 24-Pin VQFN With Exposed Thermal Pad Top View
表6-1. Pin Functions—24-Pin DRV8300U Devices
PIN
TYPE(1)
DESCRIPTION
NAME
BSTA
BSTB
BSTC
NO.
20
O
O
O
Bootstrap output pin. Connect capacitor between BSTA and SHA
Bootstrap output pin. Connect capacitor between BSTB and SHB
Bootstrap output pin. Connect capacitor between BSTC and SHC
17
14
Deadtime input pin. Connect resistor to ground for variable deadtime, fixed deadtime when left it
floating
DT
21
I
GHA
GHB
GHC
GLA
19
16
13
11
10
9
O
O
O
O
O
O
I
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
GLB
GLC
INHA
INHB
INHC
INLA
INLB
INLC
22
23
24
1
I
I
I
2
I
3
I
Mode Input controls polarity of GLx compared to INLx inputs.
MODE
5
I
Mode pin floating: GLx output polarity same(Non-Inverted) as INLx input
Mode pin to GVDD: GLx output polarity inverted compared to INLx input
NC
7, 8
6
NC
No internal connection. This pin can be left floating or connected to system ground.
GND
SHA
SHB
SHC
PWR Device ground.
18
15
12
I
I
I
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
Gate driver power supply input. Connect a X5R or X7R, GVDD-rated ceramic and greater then or equal
to 10-uF local capacitance between the GVDD and GND pins.
GVDD
4
PWR
(1) PWR = power, I = input, O = output, NC = no connection
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1
2
3
4
5
6
INHA
20
19
18
17
16
15
14
13
12
11
BSTA
INHB
INHC
GHA
SHA
BSTB
GHB
INLA
INLB
INLC
GVDD
GND
GLC
DRV8300
SHB
BSTC
GHC
7
8
SHC
GLA
9
GLB
10
图6-2. DRV8300UD, DRV8300UDI PW Package 20-Pin TSSOP Top View
表6-2. Pin Functions—20-Pin DRV8300U Devices
PIN
NAME
BSTA
BSTB
BSTC
GHA
TYPE1
DESCRIPTION
NO.
20
17
14
19
16
13
11
10
9
O
O
O
O
O
O
O
O
O
I
Bootstrap output pin. Connect capacitor between BSTA and SHA
Bootstrap output pin. Connect capacitor between BSTB and SHB
Bootstrap output pin. Connect capacitor between BSTC and SHC
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
GHB
GHC
GLA
GLB
GLC
INHA
INHB
INHC
INLA
1
2
I
3
I
4
I
INLB
5
I
INLC
GND
6
I
8
PWR Device ground.
SHA
18
15
12
I
I
I
High-side source sense input. Connect to the high-side power MOSFET source.
SHB
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
SHC
Gate driver power supply input. Connect a X5R or X7R, GVDD-rated ceramic and greater then or equal
to 10-uF local capacitance between the GVDD and GND pins.
GVDD
7
PWR
1. PWR = power, I = input, O = output, NC = no connection
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
-0.3
-0.3
-0.3
-0.3
-22
MAX UNIT
Gate driver regulator pin voltage
Bootstrap pin voltage
GVDD
21.5
125
V
V
BSTx
Bootstrap pin voltage
BSTx with respect to SHx
21.5
V
Logic pin voltage
INHx, INLx, MODE, DT
VGVDD+0.3
125
V
High-side gate drive pin voltage
High-side gate drive pin voltage
Transient 500-ns high-side gate drive pin voltage
Low-side gate drive pin voltage
Transient 500-ns low-side gate drive pin voltage
High-side source pin voltage
Ambient temperature, TA
GHx
V
GHx with respect to SHx
-0.3
-5
22
V
GHx with respect to SHx
22
V
GLx
GLx
SHx
-0.3
-5
VGVDD+0.3
VGVDD+0.3
110
V
V
-22
V
125
°C
°C
°C
–40
–40
–65
Junction temperature, TJ
150
Storage temperature, Tstg
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
7.2 ESD Ratings Comm
VALUE
±1000
±250
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
8.7
-2
NOM
MAX UNIT
VGVDD
VSHx
Power supply voltage
GVDD
SHx
20
85
V
V
High-side source pin voltage
Transient 2µs high-side source pin
voltage
VSHx
SHx
-22
85
V
VBST
VBST
VIN
Bootstrap pin voltage
Bootstrap pin voltage
Logic input voltage
PWM frequency
BSTx
5
5
0
0
105
20
V
V
BSTx with respect to SHx
INHx, INLx, MODE, DT
INHx, INLx
GVDD
200
V
fPWM
kHz
Slew rate on SHx pin (DRV8300UD and
DRV8300UDI)
VSHSL
2
1
V/ns
µF
Capacitor between BSTx and SHx
(DRV8300UD and DRV8300UDI)
(1)
CBOOT
TA
TJ
Operating ambient temperature
Operating junction temperature
125
150
°C
°C
–40
–40
(1) Current flowing through boot diode (DBOOT) needs to be limited for CBOOT > 1µF
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7.4 Thermal Information
DRV8300U
THERMAL METRIC(1)
PW (TSSOP)
20 PINS
97.4
RGE (VQFN)
24 PINS
49.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
Rθ
38.3
42.5
JC(top)
RθJB
ΨJT
Junction-to-board thermal resistance
48.8
4.3
26.5
2.2
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
48.4
26.4
ΨJB
Rθ
Junction-to-case (bottom) thermal resistance
N/A
11.5
°C/W
JC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
8.7 V ≤VGVDD ≤20 V, –40°C ≤TJ ≤150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (GVDD, BSTx)
GVDD standby mode current
INHx = INLX = 0; VBSTx = VGVDD
400
400
2
800
825
4
1400
1400
7
µA
µA
µA
µA
IGVDD
INHx = INLX = Switching @20kHz; VBSTx
= VGVDD; NO FETs connected
GVDD active mode current
Bootstrap pin leakage current
ILBSx
VBSTx = VSHx = 85V; VGVDD = 0V
INHx = Switching@20kHz
Bootstrap pin active mode transient
leakage current
ILBS_TRAN
30
105
220
Bootstrap pin active mode leakage
static current
ILBS_DC
ILSHx
INHx = High
30
30
85
55
150
80
µA
µA
INHx = INLX = 0; VBSTx - VSHx = 12V;
VSHx = 0 to 85V
High-side source pin leakage current
LOGIC-LEVEL INPUTS (INHx, INLx, MODE)
VIL_MODE
VIL
VIH_MODE
VIH
VHYS_MODE
VHYS
Input logic low voltage
Input logic low voltage
Input logic high voltage
Input logic high voltage
Input hysteresis
Mode pin
0.6
0.8
V
V
INLx, INHx pins
Mode pin
3.7
2.0
V
INLx, INHx pins
Mode pin
V
1600
40
2000
100
2400
260
mV
mV
Input hysteresis
INLx, INHx pins
VPIN (Pin Voltage) = 0 V; INLx in non-
inverting mode
-1
5
0
20
1
30
µA
µA
µA
µA
IIL_INLx
INLx Input logic low current
INLx Input logic high current
VPIN (Pin Voltage) = 0 V; INLx in inverting
mode
VPIN (Pin Voltage) = 5 V; INLx in non-
inverting mode
5
20
30
IIH_INLx
VPIN (Pin Voltage) = 5 V; INLx in inverting
mode
0
0.5
1.5
IIL
INHx, MODE Input logic low current VPIN (Pin Voltage) = 0 V;
INHx, MODE Input logic high current VPIN (Pin Voltage) = 5 V;
-1
5
0
20
1
30
µA
µA
IIH
RPD_INHx
RPD_INLx
RPU_INLx
RPD_MODE
INHx Input pulldown resistance
INLx Input pulldown resistance
INLx Input pullup resistance
To GND
120
120
120
120
200
200
200
200
280
280
280
280
kΩ
kΩ
kΩ
kΩ
To GND, INLx in non-inverting mode
To INT_5V, INLx in inverting mode
To GND
MODE Input pulldown resistance
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8.7 V ≤VGVDD ≤20 V, –40°C ≤TJ ≤150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GATE DRIVERS (GHx, GLx, SHx, SLx)
IGLx = -100 mA; VGVDD = 12V; No FETs
connected
VGHx_LO
VGHx_HI
VGLx_LO
VGLx_HI
High-side gate drive low level voltage
0
0.3
0
0.15
0.6
0.35
1.2
V
V
V
V
High-side gate drive high level
voltage (VBSTx - VGHx
IGHx = 100 mA; VGVDD = 12V; No FETs
connected
)
IGLx = -100 mA; VGVDD = 12V; No FETs
connected
Low-side gate drive low level voltage
0.15
0.6
0.35
1.2
Low-side gate drive high level voltage IGHx = 100 mA; VGVDD = 12V; No FETs
0.3
(VGVDD - VGHx
)
connected
IDRIVEP_HS
IDRIVEN_HS
IDRIVEP_LS
IDRIVEN_LS
High-side peak source gate current
High-side peak sink gate current
Low-side peak source gate current
Low-side peak sink gate current
GHx-SHx = 12V
GHx-SHx = 0V
GLx = 12V
400
850
400
850
750
1500
750
1200
2100
1200
2100
mA
mA
mA
mA
GLx = 0V
1500
INHx, INLx to GHx, GLx; VGVDD = VBSTx
VSHx > 8V; SHx = 0V, No load on GHx
and GLx
-
tPD
Input to output propagation delay
70
125
±4
180
30
ns
ns
GHx turning OFF to GLx turning ON, GLx
turning OFF to GHx turning ON; VGVDD
Matching propagation delay per
phase
=
tPD_match
-30
VBSTx - VSHx > 8V; SHx = 0V, No load on
GHx and GLx
GHx/GLx turning ON to GHy/GLy turning
Matching propagation delay phase to ON, GHx/GLx turning OFF to GHy/GLy
tPD_match
-30
±4
30
ns
phase
turning OFF; VGVDD = VBSTx - VSHx > 8V;
SHx = 0V, No load on GHx and GLx
CLOAD = 1000 pF; VGVDD = VBSTx - VSHx
8V; SHx = 0V
>
tR_GLx
tR_GHx
tF_GLx
tF_GHx
GLx rise time (10% to 90%)
GHx rise time (10% to 90%)
GLx fall time (90% to 10%)
GHx fall time (90% to 10%)
10
10
5
24
24
12
12
50
50
30
30
ns
ns
ns
ns
CLOAD = 1000 pF; VGVDD = VBSTx - VSHx
8V; SHx = 0V
>
>
>
CLOAD = 1000 pF; VGVDD = VBSTx - VSHx
8V; SHx = 0V
CLOAD = 1000 pF; VGVDD = VBSTx - VSHx
8V; SHx = 0V
5
DT pin floating
150
150
215
215
280
280
ns
ns
ns
ns
DT pin connected to GND
40 kΩ between DT pin and GND
400 kΩ between DT pin and GND
tDEAD
Gate drive dead time
150
200
260
1500
2000
2600
Minimum input pulse width on INHx,
INLx that changes the output on
GHx, GLx
tPW_MIN
40
70
150
ns
BOOTSTRAP DIODES(DRV8300UD, DRV8300UDI)
IBOOT = 100 µA
IBOOT = 100 mA
0.45
2
0.7
2.3
0.85
3.1
V
V
VBOOTD
Bootstrap diode forward voltage
Bootstrap dynamic resistance
RBOOTD
IBOOT = 100 mA and 80 mA
11
15
25
Ω
(ΔVBOOTD/ΔIBOOT
PROTECTION CIRCUITS
)
Supply rising
8
7.8
8.3
8
8.6
8.25
360
V
V
Gate Driver Supply undervoltage
lockout (GVDDUV)
VGVDDUV
Supply falling
VGVDDUV_HYS Gate Driver Supply UV hysteresis
Rising to falling threshold
295
330
mV
Gate Driver Supply undervoltage
deglitch time
tGVDDUV
5
10
13
µs
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8.7 V ≤VGVDD ≤20 V, –40°C ≤TJ ≤150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Boot Strap undervoltage lockout
Supply rising
7.5
8
8.7
V
(VBSTx - VSHx
Boot Strap undervoltage lockout
(VBSTx - VSHx
)
VBSTUV
Supply falling
6.9
7.6
8.4
V
)
VBSTUV_HYS
tBSTUV
Bootstrap UV hysteresis
Rising to falling threshold
250
5.5
400
10
850
22
mV
µs
Bootstrap undervoltage deglitch time
7.6 Timing Diagrams
INHx/INLx
GHx/GLx
50%
50%
tPD
tPD
图7-1. Propagation Delay(tPD
)
INHx
INLx
GHx
GLx
tPD_match
tPD_match
图7-2. Propagation Delay Match (tPD_match
)
7.7 Typical Characteristics
1150
1100
1050
1000
950
1150
1100
1050
1000
950
VGVDD = 5 V
VGVDD = 12 V
VGVDD = 20 V
900
900
850
850
800
TJ = -40C
800
750
700
TJ = 25C
TJ = 150C
750
-40 -20
0
20
40
60
80 100 120 140 160
4
6
8
10
12
14
16
18
20
Junction Temperature (C)
GVDD Voltage (V)
图7-4. Supply Current Over Temperature
图7-3. Supply Current Over GVDD Voltage
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图7-6. Bootstrap Diode Forward Voltage over
图7-5. Bootstrap Resistance Over GVDD Voltage
GVDD Voltage
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8 Detailed Description
8.1 Overview
The DRV8300U family of devices is a gate driver for three-phase motor drive applications. These devices
decrease system component count, saves PCB space and cost by integrating three independent half-bridge
gate drivers and optional bootstrap diodes.
DRV8300U supports external N-channel high-side and low-side power MOSFETs and can drive 750-mA source,
1.5-A sink peak currents with total combined 30-mA average output current. The DRV8300U family of devices
are available in 0.5-mm pitch QFN and 0.65-mm pitch TSSOP surface-mount packages. The QFN size is 4 × 4
mm (0.5-mm pin pitch) for the 24-pin package, and TSSOP body size is 6.5 × 4.4 mm (0.65-mm pin pitch) for the
20-pin package.
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8.2 Functional Block Diagram
GVDD
CGVDD
PVDD
GVDD
HS
BSTA
GHA
SHA
CBSTA
RGHA
INHA
HS
INT_5V
GVDD
LS
INLA/INLA
RGLA
GLA
LS
MODE**
Gate Driver
GVDD
BSTB
GHB
SHB
PVDD
CBSTB
RGHB
HS
HS
INHB
INT_5V
Input logic
control
GVDD
LS
INLB/INLB
RGLB
GLB
LS
Shoot-
Through
Prevention
MODE**
Gate Driver
GVDD
PVDD
BSTC
GHC
SHC
CBSTC
RGHC
INHC
HS
HS
INT_5V
GVDD
LS
Gate Driver
INLC/INLC
RGLC
GLC
LS
MODE**
DT**
MODE**
GND
PowerPAD
** QFN-24 Package
图8-1. Block Diagram for DRV8300UD
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8.3 Feature Description
8.3.1 Three BLDC Gate Drivers
The DRV8300U integrates three half-bridge gate drivers, each capable of driving high-side and low-side N-
channel power MOSFETs. Input on GVDD provides the gate bias voltage for the low-side MOSFETs. The high
voltage is generated using bootstrap capacitor and GVDD supply. The half-bridge gate drivers can be used in
combination to drive a three-phase motor or separately to drive other types of loads.
8.3.1.1 Gate Drive Timings
8.3.1.1.1 Propagation Delay
The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output
change. This time has two parts consisting of the input deglitcher delay and the delay through the analog gate
drivers.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate
drivers. The analog gate drivers have a small delay that contributes to the overall propagation delay of the
device.
8.3.1.1.2 Deadtime and Cross-Conduction Prevention
In the DRV8300U, high-side and low-side inputs operate independently, with an exception to prevent cross
conduction when high and low side are turned ON at same time. The DRV8300U turns OFF high-side and low-
side output to prevent shoot through when the both high-side and low-side inputs are at logic HIGH at same
time.
The DRV8300U also provides option to insert additional deadtime to prevent the external high-side and low-side
MOSFET from switching on at the same time. In the devices with DT pin (QFN package), deadtime can be
linearly adjusted between 200 ns to 2000 ns by configuring resistor value between DT and GND. When the DT
pin is left floating, fixed deadtime of 200 nS (typical value) is inserted. The value of resistor can be calculated
using 方程式1.
&A=@PEIA (J5)
4&6(GÀ) =
5
(1)
In the devices without DT pin (TSSOP package), fixed deadtime of 200 ns (typical value) is inserted to prevent
high and low side gate output turning ON at same time.
INHx/INLx Inputs
INHx
INLx
GHx/GLx outputs
GHx
GLx
DT
DT
Cross
Conduction
Prevention
图8-2. Cross Conduction Prevention and Deadtime Insertion
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8.3.1.2 Mode (Inverting and non inverting INLx)
The DRV8300U has flexibility of accepting different kind of inputs on INLx. In the devices with MODE pin (QFN
package), the DRV8300U provides option of configuring the GLx outputs to be inverted or non-inverted
compared to polarity of signal on INLx pins. When the MODE pin is left floating, the INLx is configured to be in
non-inverting mode and GLx output is in phase with respect to INLx (see 图 8-3), whereas when the MODE pin
is connected to GVDD, GLx output is out of phase with respect to INLx (see 图 8-4). In devices without MODE
pin (TSSOP package device), there are different device option available for inverting and non inverting inputs
(see 节5).
INHx
INLx
GHx
GLx
DT
DT
DT
图8-3. Non-Inverted INLx inputs
INHx
INLx
GHx
GLx
DT
DT
DT
图8-4. Inverted INLx inputs
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8.3.2 Pin Diagrams
图 8-5 shows the input structure for the logic level pins INHx, INLx. INHx and non-inverted INLx has passive pull
down, so when inputs are floating the output the gate driver will be pulled low. 图 8-6 shows the input structure
for the inverted INLx pins. The inverted INLx has passive pull up, so when inputs are floating the output of the
low-side gate driver will be pulled low.
INT_5V
INPUT
INPUT
200 kꢀ
Logic High
Logic Low
Logic High
Logic Low
INHx
INLx
INLx
200 kꢀ
图8-6. Inverted INLx Logic-Level Input Pin
图8-5. INHx and non-inverted INLx Logic-Level
Structure
Input Pin Structure
8.3.3 Gate Driver Protective Circuits
The DRV8300U is protected against BSTx undervoltage and GVDD undervoltage events.
表8-1. Fault Action and Response
FAULT
CONDITION
GATE DRIVER
RECOVERY
Automatic:
VBSTx > VBSTUV and low to high
PWM edge detected on INHx pin
VBSTx undervoltage
(BSTUV)
VBSTx < VBSTUV
GHx - Hi-Z
GVDD undervoltage
(GVDDUV)
Automatic:
VGVDD > VGVDDUV
VGVDD < VGVDDUV
Hi-Z
8.3.3.1 VBSTx Undervoltage Lockout (BSTUV)
The DRV8300U has separate voltage comparator to detect undervoltage condition for each phases. If at any
time the voltage on the BSTx pin falls lower than the VBSTUV threshold, high side external MOSFETs of that
particular phase is disabled by disabling (Hi-Z) GHx pin. Normal operation starts again when the BSTUV
condition clears and low to high PWM edge is detected on INHx input of the same phase that BSTUV condition
was detected. BSTUV protection ensures that high-side MOSFETs are not driven when the BSTx pins has lower
value.
8.3.3.2 GVDD Undervoltage Lockout (GVDDUV)
If at any time the voltage on the GVDD pin falls lower than the VGVDDUV threshold voltage, all of the external
MOSFETs are disabled. Normal operation starts again when the GVDDUV condition clears. GVDDUV protection
ensures that external MOSFETs are not driven when the GVDD input is at lower value.
8.4 Device Functional Modes
The DRV8300U is in operating (active) mode, whenever the GVDD and BST pins are higher than the UV
threshold (GVDD > VGVDDUVand VBSTX > VBSTUV). In active mode, the gate driver output GHx and GLX will
follow respective inputs INHx and INLx.
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The DRV8300U family of devices is primarily used in applications for three-phase brushless DC motor control.
The design procedures in the 节9.2 section highlight how to use and configure the DRV8300U.
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9.2 Typical Application
GVDD
GVDD
GND
CGVDD
PVDD
External
Supply
GND
BSTA
CBSTA
RGHA
GHA
SHA
RGLA
INHA
INLA
GLA
INHB
INLB
PWM
MCU
PVDD
BSTB
INHC
INLC
CBSTB
RGHB
GHB
SHB
RGLB
DRV8300D
GLB
PVDD
GVDD
BSTC
BSTC
CBSTC
RGHC
MODE**
GHC
SHC
GND or Floating
GHC
SHC
DT**
RGLC
GLC
** QFN-24 Package
GLC
INA+
INA-
INB+ INC+
R
R
INB-
INC-
R
N-
INx+
INx-
N-
N+
R
R
IN-
N+
œ
OUT
IN+
+
Reference
Voltage
V
REF
R
Current Sense Amplifier 1x or 3x
+
œ
图9-1. Application Schematic
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9.2.1 Design Requirements
表9-1 lists the example design input parameters for system design.
表9-1. Design Parameters
EXAMPLE DESIGN PARAMETER
REFERENCE
EXAMPLE VALUE
MOSFET
-
CSD19532Q5B
12 V
Gate Supply Voltage
Gate Charge
VGVDD
QG
48 nC
9.2.2 Bootstrap Capacitor and GVDD Capacitor Selection
The bootstrap capacitor must be sized to maintain the bootstrap voltage above the undervoltage lockout for
normal operation. 方程式2 calculates the maximum allowable voltage drop across the bootstrap capacitor:
¿8$56: = 8)8&& F8$116&F8
$5678
(2)
=12 V –0.85 V –4.5 V = 6.65 V
where
• VGVDD is the supply voltage of the gate drive
• VBOOTD is the forward voltage drop of the bootstrap diode
• VBSTUV is the threshold of the bootstrap undervoltage lockout
In this example the allowed voltage drop across bootstrap capacitor is 6.65 V. It is generally recommended that
ripple voltage on both the bootstrap capacitor and GVDD capacitor should be minimized as much as possible.
Many of commercial, industrial, and automotive applications use ripple value between 0.5 V to 1 V.
The total charge needed per switching cycle can be estimated with 方程式3:
+.$5_64#05
3616 = 3) +
B
59
(3)
=48 nC + 220 μA/20 kHz = 50 nC + 11 nC = 59 nC
where
• QG is the total MOSFET gate charge
• ILBS_TRAN is the bootstrap pin leakage current
• fSW is the is the PWM frequency
The minimum bootstrap capacitor an then be estimated as below assuming 1V ΔVBSTx
:
3
%
=
616W
$56_/+0
¿8
$56:
(4)
= 59 nC / 1 V = 59 nF
The calculated value of minimum bootstrap capacitor is 59 nF. It should be noted that, this value of capacitance
is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater than calculated
value to allow for situations where the power stage may skip pulse due to various transient conditions. It is
recommended to use a 100 nF bootstrap capacitor in this example. It is also recommenced to include enough
margin and place the bootstrap capacitor as close to the BSTx and SHx pins as possible.
%
)8&&
R 10 × %$56:
(5)
= 10*100 nF= 1 μF
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For this example application choose 1 µF CGVDD capacitor. Choose a capacitor with a voltage rating at least
twice the maximum voltage that it will be exposed to because most ceramic capacitors lose significant
capacitance when biased. This value also improves the long term reliability of the system.
9.2.3 Application Curves
GHA
GHA
SHA
SHA
GLA
GLA
图9-2. Gate voltages, SHx rising with 15 ohm gate
图9-3. Gate voltages, SHx falling with 15 ohm gate
resistor and CSD19532Q5B MOSFET
resistor and CSD19532Q5B MOSFET
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10 Power Supply Recommendations
The DRV8300U is designed to operate from an input voltage supply (GVDD) range from 4.8 V to 20 V. A local
bypass capacitor should be placed between the GVDD and GND pins. This capacitor should be located as close
to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is recommended to
use two capacitors across GVDD and GND: a low capacitance ceramic surface-mount capacitor for high
frequency filtering placed very close to GVDD and GND pin, and another high capacitance value surfacemount
capacitor for device bias requirements. In a similar manner, the current pulses delivered by the GHx pins are
sourced from the BSTx pins. Therefore, capacitor across the BSTx to SHx is recommended, it should be high
enough capacitance value capacitor to deliver GHx pulses
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11 Layout
11.1 Layout Guidelines
• Low ESR/ESL capacitors must be connected close to the device between GVDD and GND and between
BSTx and SHx pins to support high peak currents drawn from GVDD and BSTx pins during the turn-on of the
external MOSFETs.
• To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a
good quality ceramic capacitor must be connected between the high side MOSFET drain and ground.
• In order to avoid large negative transients on the switch node (SHx) pin, the parasitic inductances between
the source of the high-side MOSFET and the source of the low-side MOSFET must be minimized.
• In order to avoid unexpected transients, the parasitic inductance of the GHx, SHx, and GLx connections must
be minimized. Minimize the trace length and number of vias wherever possible. Minimum 10 mil and typical
15 mil trace width is recommended.
• Resistance between DT and GND must be place as close as possible to device
• Place the gate driver as close to the MOSFETs as possible. Confine the high peak currents that charge and
discharge the MOSFET gates to a minimal physical area by reducing trace length. This confinement
decreases the loop inductance and minimize noise issues on the gate terminals of the MOSFETs.
• In QFN package device variants, NC pins can be connected to GND to increase ground conenction between
thermal pad and external ground plane.
• Refer to sections General Routing Techniques and MOSFET Placement and Power Stage Routing in
Application Report
11.2 Layout Example
BSTx capacitor close
to device
DT resistor
close to device
GVDD capacitor
close to device
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8300UDIPWR
DRV8300UDPWR
DRV8300UDRGER
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
VQFN
PW
PW
20
20
24
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
8300UDI
Samples
Samples
Samples
NIPDAU
NIPDAU
8300UD
8300UD
RGE
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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2-Nov-2022
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Nov-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8300UDIPWR
DRV8300UDPWR
DRV8300UDRGER
TSSOP
TSSOP
VQFN
PW
PW
20
20
24
3000
3000
3000
330.0
330.0
330.0
16.4
16.4
12.4
6.95
6.95
4.25
7.1
7.1
1.6
1.6
8.0
8.0
8.0
16.0
16.0
12.0
Q1
Q1
Q2
RGE
4.25
1.15
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Nov-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV8300UDIPWR
DRV8300UDPWR
DRV8300UDRGER
TSSOP
TSSOP
VQFN
PW
PW
20
20
24
3000
3000
3000
356.0
356.0
367.0
356.0
356.0
367.0
35.0
35.0
35.0
RGE
Pack Materials-Page 2
PACKAGE OUTLINE
PW0020A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
5.85
6.6
6.4
NOTE 3
10
B
11
0.30
20X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.5)
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
11
10
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
20X (1.5)
SYMM
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
RGE0024B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
0.5
0.3
PIN 1 INDEX AREA
4.1
3.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
(0.2) TYP
2.45 0.1
7
12
EXPOSED
SEE TERMINAL
DETAIL
THERMAL PAD
13
6
2X
SYMM
25
2.5
18
1
0.3
24X
20X 0.5
0.2
19
24
0.1
C A B
SYMM
24X
PIN 1 ID
(OPTIONAL)
0.05
0.5
0.3
4219013/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.45)
SYMM
24
19
24X (0.6)
1
18
24X (0.25)
(R0.05)
TYP
25
SYMM
(3.8)
20X (0.5)
13
6
(
0.2) TYP
VIA
7
12
(0.975) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219013/A 05/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.08)
(0.64) TYP
19
24
24X (0.6)
1
25
18
24X (0.25)
(R0.05) TYP
SYMM
(0.64)
TYP
(3.8)
20X (0.5)
13
6
METAL
TYP
7
12
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219013/A 05/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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