DRV8243HQRXYRQ1 [TI]
DRV8243-Q1 Automotive H-Bridge Driver with Integrated Current Sense and Diagnostics;型号: | DRV8243HQRXYRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | DRV8243-Q1 Automotive H-Bridge Driver with Integrated Current Sense and Diagnostics |
文件: | 总77页 (文件大小:4034K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DRV8243-Q1
SLVSG23 – AUGUST 2021
DRV8243-Q1 Automotive H-Bridge Driver with Integrated Current Sense and
Diagnostics
1 Features
3 Description
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
Functional Safety-Capable
– Documentation available to aid functional safety
system design
40 V Abs Max, 4.5 V to 35 V operating range
VQFN-HR package: RON_LS + RON_HS: 84 mΩ
HVSSOP package: RON_LS + RON_HS: 98 mΩ
IOUT Max = 12 A
PWM frequency operation up to 25 KHz with
automatic dead time assertion
Configurable slew rate and spread spectrum
clocking for low electromagnetic interference (EMI)
Integrated current sense (eliminates shunt resistor)
Proportional load current output on IPROPI pin
Configurable current regulation
Protection / Diagnostic features with configurable
fault reaction (latched or retry)
– Load diagnostics in both the off-state and on-
state to detect open load and short circuit
– Voltage monitoring on supply (VM)
– Over current protection
The DRV824x-Q1 family of devices is a fully
integrated H-bridge driver intended for a wide range
of automotive applications. The device can be
configured as a single full-bridge driver or as two
independent half-bridge drivers. Designed in Texas
Instruments' proprietary BiCMOS high power process
technology node, this monolithic family of devices in
a power package offer excellent power handling and
thermal capability while providing compact package
size, ease of layout, EMI control, accurate current
sense, robustness, and diagnostic capability. This
family also has identical pin function with scalable
RON (current capability) to support different loads.
•
•
•
•
•
•
•
•
•
•
•
The devices integrate a N-channel H-bridge, charge
pump regulator, high-side current sensing and
regulation, current proportional output, and protection
circuitry. A low-power sleep mode is provided to
achieve low quiescent current. The devices offer
voltage monitoring and load diagnostics as well
as protection features against over current and
over temperature. Fault conditions are indicated
on nFAULT pin. The devices are available in
two interface variants - hardware (HW) and SPI.
SPI interface device has two variant choices, "P"
for externally supplied logic supply, and "S" for
internally generated logic supply. The SPI variant
offers more flexibility in device configuration and fault
observability.
– Over temperature detection
– Fault indication on nFAULT pin
Supports 3.3-V, 5-V logic inputs
Low sleep current - 1μA typical at 25°C
SPI or Hardware interface variant option
Configurable modes to operate the device as:
•
•
•
•
– Single full bridge using PWM or PH/EN mode
– Two half-bridges using Independent mode
Device comparison table shows the complete
family
Typical loads include unidirectional and
bidirectional brushed DC motors, solenoids, relays
and other inductive or resistive loads.
Device Information(1)
PART NUMBER
DRV8243-Q1
DRV8243-Q1
PACKAGE
VQFN-HR (14)
HVSSOP (28)
BODY SIZE (nominal)
•
•
3 mm X 4.5 mm
3 mm X 7.3 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet
2 Applications
4.5 - 35 V
•
•
•
•
•
•
Automotive brushed DC motors, Solenoid drivers
Door modules , mirror modules, and seat modules
Body control module (BCM)
E-Shifter
Gas engine systems
On board charger
nSLEEP
DRV824X-Q1
Driver Control
nFAULT
Full Bridge
Driver
SPI (SPI variant)
CONFIG pins
(HW variant)
Diagnos cs
Current Sense
IPROPI
ADC
Current Regula on
Built-in Protec on
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
DRV8243-Q1
SLVSG23 – AUGUST 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................3
6 Pin Configuration and Functions...................................6
6.1 HW Variant..................................................................6
6.2 SPI Variant..................................................................8
7 Specifications................................................................ 11
7.1 Absolute Maximum Ratings...................................... 11
7.2 ESD Ratings..............................................................11
7.3 Recommended Operating Conditions.......................12
7.4 Thermal Information..................................................12
7.5 Electrical Characteristics...........................................12
7.6 SPI Timing Requirements......................................... 19
7.7 Switching Waveforms................................................21
8 Detailed Description......................................................28
8.1 Overview...................................................................28
8.2 Functional Block Diagram.........................................29
8.3 Feature Description...................................................32
8.4 Device Functional States.......................................... 45
8.5 Programming - SPI Variant Only...............................47
8.6 Register Map - SPI Variant Only...............................52
9 Application and Implementation..................................59
9.1 Application Information............................................. 59
9.2 Typical Application.................................................... 60
10 Power Supply Recommendations..............................64
10.1 Bulk Capacitance Sizing......................................... 64
11 Layout...........................................................................65
11.1 Layout Guidelines................................................... 65
11.2 Layout Example...................................................... 65
12 Device and Documentation Support..........................66
12.1 Documentation Support.......................................... 66
12.2 Receiving Notification of Documentation Updates..66
12.3 Community Resources............................................66
12.4 Trademarks.............................................................66
13 Mechanical, Packaging, and Orderable
Information.................................................................... 66
13.1 Tape and Reel Information......................................73
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
August 2021
*
Initial release.
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5 Device Comparison
Table 5-1 summarizes the RON and package differences between devices in the DRV824X-Q1 family.
Table 5-1. Device Comparison
BODY SIZE
(nominal)
PART NUMBER
(LS + HS) RON
IOUT MAX
PACKAGE
Variants
DRV8243-Q1
DRV8243-Q1
DRV8244-Q1
DRV8244-Q1
DRV8245-Q1
DRV8245-Q1
84 mΩ
98 mΩ
47 mΩ
60 mΩ
32 mΩ
40 mΩ
12 A
12 A
21 A
21 A
32 A
32 A
VQFN-HR (14)
HVSSOP (28)
VQFN-HR (16)
HVSSOP (28)
VQFN-HR (16)
HTSSOP (28)
3 mm X 4.5 mm
3 mm X 7.3 mm
3 mm X 6 mm
HW, SPI "S"
HW, SPI "S", SPI "P"
HW, SPI "S"
3 mm X 7.3 mm
3.5 mm X 5.5 mm
4.4 mm X 9.7 mm
HW, SPI "S", SPI "P"
HW, SPI "S"
HW, SPI "S", SPI "P"
Table 5-2 summarizes the feature differences between the SPI and HW interface variants in the DRV824X-Q1
family. In general, the SPI variant offers more configurability, bridge control options, diagnostic feedback,
redundant driver shutoff, improved Pin FMEA and additional features. In addition, the SPI device has an
additional "P" variant that supports an external low voltage supply to the device which replaces the internal
supply generated from the VM supply. This "P" variant avoids device brown out (reset of device) during VM
under voltage transients.
Table 5-2. SPI Variant vs HW Variant Comparison
FUNCTION
HW "H" Variant
SPI "S" & "P" Variant
Bridge control
Pin only
Individual pin "and/or" register bit with pin
status indication(Refer Register Pin control)
nSLEEP pin control from MCU
Necessary
Can be tied off high at the pin if SLEEP
function is not required
Slew rate
6 levels
8 levels
Over current protection (OCP)
Fixed at the highest setting
3 choices for thresholds, 4 choices for filter
time
ITRIP regulation
5 levels with disable & fixed TOFF
time
7 levels with disable & indication, with
programmable TOFF time
Individual fault reaction configuration between retry or Not supported, either all latched or
Supported
latched behavior
all retry
Detailed fault logging and device status feedback
Not supported, nFAULT pin
monitoring necessary
Supported, nFAULT pin monitoring optional
VM over voltage
On-state (Active) diagnostics
Fixed
4 threshold choices
Supported for high-side loads
Supported
Not supported
Not supported
Not supported
Not supported
Not supported
Spread spectrum clocking (SSC)
External logic supply to the device
Additional driver states in PWM mode
Hi-Z for individual half-bridge in Independent mode
Supported only in the "P" variant
Supported
Supported (SPI register only)
Note
There are some functional improvements as well as parametric corrections between the pre-
production samples and final production devices. These differences are summarized in the feature
changes table and errata table. The sample types can be differentiated visually by their package
symbolization. Pre-production samples are pre-fixed with a "P" on the package symbolization.
Additionally, for the SPI variant, it is possible to electrically differentiate between the samples by
reading the DEVICE_ID register byte (refer to Table 5-5).
Table 5-3 summarizes the feature changes between the pre-production samples and final production devices.
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Table 5-3. Feature Changes Between Pre-Production and Production Samples
Feature
Pre-Production Samples
Final Product
Parallel mode removed. Use the DRV814X equivalent
device for this.
Parallel Mode
Parallel mode available
DRV824X: SR = [1.6 12* 18* 23 28 33 38 43] V/usec
HW only 6 choices only
DRV824X: SR = [1.6 4* 8* 12 18 23 33 43] V/usec
*Additional settings in SPI variant only
Slew Rate
*Additional settings in SPI variant only
OCP limit in DRV8243
Set at 9 A min
Increased to 12 A
VTRIP = [DIS 2.97 2.64 2.31 1.98 1.65* 1.41* 1.18] V
*Additional settings in SPI only
ITRIP regulation levels VTRIP = [DIS 2.97 2.64 2.31 1.98 1.65] V
DRVOFF_SEL, EN_IN1_SEL, PH_IN2_SEL
When SPI_IN is unlocked, the input pins, DRVOFF,
SPI variant only - Reg / EN_IN1 and PH_IN2, become don’t care and the
introduced to configure the logical combination
(AND/OR) of each of the three input pins (DRVOFF,
EN/IN1, PH/IN2) with their register bit counterparts,
when SPI_IN is unlocked. (Refer Register Pin control)
Pin control
output is controlled by their equivalent register bits
only.
[IN1 IN2] = [H H] => HiZ, [L L] => Brake. This
eliminates risk for direction reversal for a short to GND
or Open in PWM mode.
PWM truth table
[IN1 IN2] = [L L] => HiZ, [H H] => Brake
Changes allow for efficient diagnostic monitoring, in
addition to support extended configurability
1. STATUS2 byte added for DRVOFF_STAT and
ACTIVE bit indication
SPI variant only - Register
map expansion
2. OLP_CMP moved to STATUS2 with a redundant
ACTIVE bit replacing OLP_CMP in the STATUS1
3. CONFIG4 byte added to accommodate
configurability for OCP control and output control
through input pins & their equivalent register bits
As listed in the register map section
1. SPI variant - Feature enabled by default
2. HW variant - Feature always enabled
1. SPI variant - Feature disabled by default
2. HW variant - Feature always disabled
Spread spectrum clocking
Added 2 bits of OCP_SEL to lower OCP threshold and
2 bits of OCP_TSEL to change the OCP filter time.
Over current protection Fixed thresholds
Additional SPI "P" variant – nSLEEP/VIO pin function
changed to external VDD input as logic supply
SPI "P" variant
Not available
Thresholds swapped in half-bridge operation to enable
differentiation between short and open for a half-bridge
use case during off-state diagnostics (OLP)
Can't differentiate between open and short for a half-
bridge use case during off-state diagnostics (OLP)
OLP CMP reference
Processes write commands for
Improved feature to process write commands for
1. length = 16 SCLKs for regular SPI frame or
1. length ≥ 16 SCLKs for regular SPI frame or
SPI variant only – Frame
length error
2. length ≥ 16 + “N” x 16 SCLKs for daisy chain SPI 2. length = 16 + “N” x 16 SCLKs for daisy chain SPI
frame, where N = number of peripherals
frame, where N = number of peripherals
Only shorter lengths are rejected with SPI_ERR
All other lengths are rejected with SPI_ERR
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Table 5-4. Errata Fixes Between Pre-Production and Production Samples
Errata
Pre-Production Samples
Final Product
Fixed the mean shift to ensure 10% resistor
(datasheet target) is OK for use on the
CONFIG pins as per datasheet
HW variant only - Mean shift in determining
the resistance to GND at the CONFIG pins
Recommend to use 1% resistor on the
CONFIG pins to ensure expected behavior
Digital input pin - hysteresis is lower than
expected
Hysteresis measured: [Min/ Typ/ Max] = [30/ Fixed to meet datasheet target of: [Min/ Typ/
60/ 90] mV
Max] = [70/ 100/ 150] mV
ITRIP regulation accuracy – lower than
expected
VTRIP threshold comparison could be ~ +/-
12%
Fixed to meet datasheet target of < +/- 10%
Over current protection threshold mean shift
of high-side FET for DRV8245 closer to the
lower threshold
Fixed the mean value so that min OCP is
always > 32 A(datasheet target)
OCP of HSx FET could be as low as 28 A
Table 5-5. Differentiating Between Pre-Production and Production Samples
Pre-Production Samples
Final Product
Device
Package Symbolization
DEVICE_ID Register
Not applicable
Not applicable
Not applicable
0 x 30
Package Symbolization
DEVICE_ID Register
Not applicable
Not applicable
Not applicable
0 x 32
DRV8243H-Q1
DRV8244H-Q1
DRV8245H-Q1
DRV8243S-Q1
DRV8244S-Q1
DRV8245S-Q1
DRV8243P-Q1
DRV8244P-Q1
DRV8245P-Q1
P8243X
P8244X
P8245X
P8243X
P8244X
P8245X
8243H
8244H
8245H
8243S
8244S
8245S
8243P
8244P
8245P
0 x 40
0 x 42
0 x 50
0 x 52
Not available
0 x 36
Not available
Not available
0 x 46
0 x 56
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6 Pin Configuration and Functions
6.1 HW Variant
6.1.1 HVSSOP (28) package
1
2
3
4
5
SR
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ITRIP
MODE
nFAULT
IPROPI
nSLEEP
VM
DIAG
PH/IN2
EN/IN1
DRVOFF
VM
6
VM
7
VM
VM
VM
8
9
OUT1
OUT1
OUT2
OUT2
10
11
12
13
14
OUT1
GND
GND
OUT2
GND
GND
GND
GND
Figure not drawn to scale
Figure 6-1. DRV8243H-Q1 HW variant in HVSSOP (28) package
Table 6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
Device configuration pin for Slew Rate control . For details, refer to Slew Rate in the Device
Configuration section.
1
SR
I
I
Device configuration pin for load type indication and fault reaction configuration. For details,
refer to DIAG in the Device Configuration section.
2
DIAG
3
4
5
PH/IN2
EN/IN1
I
I
I
Controller input pin for bridge operation. For details, see the Bridge Control section.
Controller input pin for bridge operation. For details, see the Bridge Control section.
Controller input pin for bridge Hi-Z. For details, see the Bridge Control section.
DRVOFF
Power supply. This pin is the motor supply voltage. Must combine with the rest of VM pins
(6 total) to support device current capability. Bypass this pin to GND with a 0.1-µF ceramic
capacitor and a bulk capacitor.
6, 7, 8, 21,
22, 23
VM
P
Half-bridge output 1. Connect this pin to the motor or load. Must combine with the rest of
OUT1 pins (3 total) to support device current capability.
9, 10, 11
OUT1
GND
P
12, 13, 14,
15, 16, 17
Ground pin. Must combine with the rest of GND pins (6 total) to support device current
capability.
G
Half-bridge output 2. Connect this pin to the motor or load. Must combine with the rest of
OUT2 pins (3 total) to support device current capability.
18, 19, 20
OUT2
nSLEEP
IPROPI
P
I
24
25
Controller input pin for SLEEP. For details, see the Bridge Control section.
Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration
section.
I/O
Fault indication to the controller. For details, refer to nFAULT in the Device Configuration
section.
26
nFAULT
OD
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Table 6-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
27
MODE
I
I
Device configuration pin for MODE. For details, refer to the Device Configuration section.
Device configuration pin for ITRIP level for high-side current limiting. For details, refer to
ITRIP in the Device Configuration section.
28
ITRIP
(1) I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output
6.1.2 VQFN-HR (14) package
PH/IN2
nFAULT
10
9
nFAULT
PH/IN2
1
2
3
10
9
1
2
3
EN/IN1
IPROPI
EN/IN1
IPROPI
8
8
DRVOFF
nSLEEP
TOP VIEW
nSLEEP
DRVOFF
BOTTOM VIEW
VM
OUT1
GND
VM
4
VM
4
VM
7
5
7
5
OUT1
GND
OUT2
GND
OUT2
GND
6
6
GND
GND GND GND
GND GND GND GND
Figure not drawn to scale
Figure 6-2. DRV8243H-Q1 HW variant in VQFN-HR (14) package
Table 6-2. Pin Functions
PIN
TYPE (1)
DESCRIPTION
NO.
NAME
Fault indication to the controller. For details, refer to nFAULT in the Device Configuration
section.
1
nFAULT
OD
Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration
section.
2
3
4
IPROPI
nSLEEP
VM
I/O
I
Controller input pin for SLEEP . For details, see the Bridge Control section.
Power supply. This pin is the motor supply voltage. Bypass this pin to GND with a 0.1-µF
ceramic capacitor and a bulk capacitor.
P
5
6
OUT2
GND
P
G
P
I
Half-bridge output 2. Connect this pin to the motor or load.
Ground pin
7
OUT1
Half-bridge output 1. Connect this pin to the motor or load.
Controller input pin for bridge Hi-Z. For details, see the Bridge Control section.
Controller input pin for bridge operation. For details, see the Bridge Control section.
Controller input pin for bridge operation. For details, see the Bridge Control section.
8
DRVOFF
EN/IN1
PH/IN2
9
I
10
I
Device configuration pin for load type indication and fault reaction configuration. For details,
refer to DIAG in the Device Configuration section.
11
DIAG
I
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Table 6-2. Pin Functions (continued)
PIN
TYPE (1)
DESCRIPTION
NO.
NAME
Device configuration pin for Slew Rate control . For details, refer to Slew Rate in the Device
Configuration section.
12
SR
I
Device configuration pin for ITRIP level for high-side current limiting. For details, refer to
ITRIP in the Device Configuration section.
13
14
ITRIP
I
I
MODE
Device configuration pin for MODE. For details, refer to the Device Configuration section.
(1) I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output
6.2 SPI Variant
6.2.1 HVSSOP (28) package
1
2
3
4
5
1
2
3
4
5
SCLK
nSCS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SCLK
nSCS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SDI
SDI
SDO
SDO
nFAULT
IPROPI
VDD
VM
nFAULT
IPROPI
nSLEEP
VM
PH/IN2
EN/IN1
DRVOFF
VM
PH/IN2
EN/IN1
DRVOFF
VM
6
6
VM
VM
7
7
VM
VM
VM
VM
VM
VM
8
8
9
9
OUT1
OUT1
OUT1
OUT1
OUT2
OUT2
OUT2
OUT2
10
11
12
13
14
10
11
12
13
14
OUT1
GND
OUT1
GND
OUT2
GND
OUT2
GND
GND
GND
GND
GND
GND
GND
GND
GND
Figure not drawn to scale
Figure not drawn to scale
Figure 6-3. DRV8243S-Q1 SPI variant in HVSSOP (28) package
Table 6-3. Pin Functions
PIN
TYPE (1)
DESCRIPTION
NO.
1
NAME
SCLK
I
I
I
I
I
SPI - Serial Clock input.
2
nSCS
SPI - Chip Select. An active low on this pin enables the serial interface communication.
Controller input pin for bridge operation. For details, see the Bridge Control section.
Controller input pin for bridge operation. For details, see the Bridge Control section.
Controller input pin for bridge Hi-Z. For details, see the Bridge Control section.
3
PH/IN2
EN/IN1
DRVOFF
4
5
Power supply. This pin is the motor supply voltage. Must combine with the rest of VM pins
(6 total) to support device current capability. Bypass this pin to GND with a 0.1-µF ceramic
capacitor and a bulk capacitor.
6, 7, 8, 21,
22, 23
VM
P
P
Half-bridge output 1. Connect this pin to the motor or load. Must combine with the rest of
OUT1 pins (3 total) to support device current capability.
9, 10, 11
OUT1
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NO.
Table 6-3. Pin Functions (continued)
PIN
TYPE (1)
DESCRIPTION
NAME
12, 13, 14,
15, 16, 17
Ground pin. Must combine with the rest of GND pins (6 total) to support device current
capability.
GND
G
P
Half-bridge output 2. Connect this pin to the motor or load. Must combine with the rest of
OUT2 pins (3 total) to support device current capability.
18, 19, 20
OUT2
"S" variant: Controller input pin for SLEEP. For details, see the Bridge Control section. Also
VIO logic level for SDO.
nSLEEP
VDD
I
24
P
"P" variant: Logic power supply to the device.
Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration
section.
25
26
IPROPI
I/O
Fault indication to the controller. For details, refer to nFAULT in the Device Configuration
section.
nFAULT
OD
27
28
SDO
SDI
PP
I
SPI - Serial Data Output. Data is updated at the rising edge of SCLK.
SPI - Serial Data Input. Data is captured at the falling edge of SCLK.
(1) I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output
6.2.2 VQFN-HR (14) package
PH/IN2
nFAULT
10
9
nFAULT
PH/IN2
1
2
3
10
9
1
2
3
EN/IN1
IPROPI
EN/IN1
IPROPI
8
8
DRVOFF
nSLEEP
TOP VIEW
nSLEEP
DRVOFF
BOTTOM VIEW
VM
OUT1
GND
VM
4
VM
4
VM
7
5
7
5
OUT1
GND
OUT2
GND
OUT2
GND
6
6
GND
GND GND GND
GND GND GND GND
Figure not drawn to scale
Figure 6-4. DRV8243S-Q1 SPI variant in VQFN-HR (14) package
Table 6-4. Pin Functions
PIN
TYPE (1)
DESCRIPTION
NO.
NAME
Fault indication to the controller. For details, refer to nFAULT in the Device Configuration
section.
1
nFAULT
IPROPI
nSLEEP
OD
O
I
Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration
section.
2
3
Controller input pin for SLEEP. For details, see the Bridge Control section. Also VIO logic
level for SDO.
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Table 6-4. Pin Functions (continued)
PIN
TYPE (1)
DESCRIPTION
NO.
NAME
Power supply. This pin is the motor supply voltage. Bypass this pin to GND with a 0.1-µF
ceramic capacitor and a bulk capacitor.
4
VM
P
5
6
OUT2
GND
P
Half-bridge output 2. Connect this pin to the motor or load.
Ground pin
G
7
OUT1
DRVOFF
EN/IN1
PH/IN2
nSCS
SCLK
SDI
P
Half-bridge output 1. Connect this pin to the motor or load.
Controller input pin for bridge Hi-Z. For details, see the Bridge Control section.
Controller input pin for bridge operation. For details, see the Bridge Control section.
Controller input pin for bridge operation. For details, see the Bridge Control section.
SPI - Chip Select. An active low on this pin enables the serial interface communication.
SPI - Serial Clock input.
8
I
9
I
10
11
12
13
14
I
I
I
I
SPI - Serial Data Input. Data is captured at the falling edge of SCLK.
SPI - Serial Data Output. Data is updated at the rising edge of SCLK.
SDO
PP
(1) I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Power supply pin voltage
VM
VM
–0.3
40
2
Power supply transient voltage ramp
V/µs
V
Output pin voltage
OUT1, OUT2
OUT1, OUT2
-0.9
VVM + 0.9
Output pin current
Internally limited
A
Driver disable pin voltage
Logic I/O voltage
DRVOFF
–0.3
–0.3
–0.3
–0.3
40
V
EN/IN1, PH/EN2, nFAULT
MODE, ITRIP, SR, DIAG
IPROPI
5.75
5.75
5.75
V
HW variant - Configuration pins voltage
Analog feedback pin voltage
V
V
Sleep pin voltage (Not applicable for SPI "P"
variant)
nSLEEP
–0.3
40
V
SPI I/O voltage - SPI variant
SPI "P" variant - Logic supply
SDI, SDO, nSCS, SCLK
VDD
–0.3
-0.3
5.75
5.75
V
V
SPI "P" variant - Logic supply transient voltage
ramp
VDD
5
V/µs
Ambient temperature, TA
Junction temperature, TJ
Storage temperature, Tstg
–40
–40
–65
125
150
150
°C
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
±4000
±2000
±750
UNIT
Human body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
VM, OUT1, OUT2, GND
All other pins
Electrostatic
discharge
V(ESD)
V
Corner pins
Charged device model (CDM), per AEC Q100-011
CDM ESD Classification Level C4B
Other pins
±500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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7.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
MAX
UNIT
Power supply voltage
VM
VM
4.5
35
V
VVM
Max voltage for reliable over current
protection
28
5.5
5.5
V
V
V
VVDD
SPI "P" variant - Logic supply voltage
Logic pin voltage
VDD
3
0
EN/IN1, PH/EN2, nSLEEP, DRVOFF,
nFAULT
VLOGIC
fPWM
PWM frequency
EN/IN1, PH/EN2
MODE, ITRIP, SR, DIAG
IPROPI
0
0
0
25
5.5
5.5
KHz
V
VCONFIG
VIPROPI
HW variant - Configuration pin voltage
Analog feedback voltage
V
VnSLEEP
0.5
+
SPI "S" variant - SPI pin voltage
SDI, SDO, nSCS, SCLK
SDI, SDO, nSCS, SCLK
0
V
VSPI_IOS
SPI "P" variant - SPI pin voltage
Operating ambient temperature
Operating junction temperature
0
VVDD + 0.5
125
V
TA
TJ
–40
–40
°C
°C
150
7.4 Thermal Information
Refer Transient thermal impedance table for application related use case.
THERMAL METRIC(1)
HVSSOP package VQFN-HR package
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
RθJC(top)
RθJB
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
31.0
29.1
9.3
48.4
22.3
8.1
ΨJT
1.4
0.5
ΨJB
9.3
7.9
RθJC(bot)
1.3
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
4.5 V (falling) ≤ VVM ≤ 35 V, -40°C ≤ TJ ≤ 150°C (unless otherwise noted)
For SPI "P" variant only: 3 V ≤ VVDD ≤ 5.5 V (unless otherwise noted)
For HW and SPI "S" variant: VDD is internally derived from VM
7.5.1 Power Supply & Initialization
Refer wake up transient waveforms
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply pin voltage during reverse
current
VVM_REV
IVM = - 5 A, device in unpowered state
0.8
V
VVM = 13.5 V or VVDD < PORVDD (P
variant), TA = 25°C or
1
µA
µA
IVMQ
VM current in SLEEP state
VVM = 13.5 V or VVDD < PORVDD (P
variant), TA = 125°C
5.8
IVMS
IVDD
VM current in STANDBY state
VDD current in ACTIVE state
VVM = 13.5 V
3
5
mA
mA
SPI "P" variant only
10
HW variant only - RESET pulse filter
time
tRESET
Signal on nSLEEP pin
5
20
µs
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PARAMETER
TEST CONDITIONS
Signal on nSLEEP pin
MIN
TYP
MAX
UNIT
HW variant only - SLEEP command filter
time
tSLEEP
tSLEEP_SPI
tWAKEUP
40
120
µs
SPI "S" variant only - SLEEP command
filter time
Signal on nSLEEP pin
Signal on nSLEEP pin
5
20
µs
µs
HW & SPI "S" variant only - wake up
command filter time
10
Time for communication to be available
after wake up through nSLEEP pin or
internal POR
Signal on nSLEEP pin or power cycle
through VM / VDD for SPI "P" variant
tCOM
400
1
µs
Time for driver ready to be driven after
wake up through nSLEEP pin or internal
POR
Signal on nSLEEP pin or power cycle
through VM / VDD for SPI "P" variant
tREADY
ms
7.5.2 Logic I/Os
PARAMETER
TEST CONDITIONS
nSLEEP pin
MIN
TYP
200
100
MAX
UNIT
V
VIL_nSLEEP Input logic low voltage
VIH_nSLEEP Input logic high voltage o
0.65
nSLEEP pin
1.55
V
VIHYS_nSLEE
Input hysteresis
nSLEEP pin
mV
P
VIL
VIH
Input logic low voltage
Input logic high voltage
Input hysteresis
DRVOFF, EN/IN1, PH/IN2 pins
DRVOFF, EN/IN1, PH/IN2 pins
DRVOFF, EN/IN1, PH/IN2 pins
0.7
V
V
1.5
VIHYS
mV
Internal pull-down resistance on nSLEEP
to GND
RPD_nSLEEP
Measured at min VIL level
Measured at min VIH level
Measured at max VIL level
VnFAULT = 0.3 V
100
200
200
5
KΩ
KΩ
KΩ
mA
Internal pull-up resistance to VDD
(reverse current blocked) on DRVOFF
RPU
Internal pull-down resistance to GND on
EN/IN1 and PH/IN2
RPD
Sink current to GND on nFAULT pin
when asserted low
InFAULT_PD
7.5.3 SPI I/Os
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Internal pull-up resistance to VDD
(reverse current blocked) on nSCS
RPU_nSCS
RPD_SPI
Measured at min VIH level
200
KΩ
Internal pull-down resistance to GND on
SDI, SCLK
Measured at max VIL level
150
1.5
KΩ
VIL
VIH
Input logic low voltage
Input logic high voltage
Input hysteresis
SDI, SCLK, nSCS pins
SDI, SCLK, nSCS pins
SDI, SCLK, nSCS pins
0.5 mA sink into SDO
0.7
0.4
V
V
VIHYS
100
mV
V
VOL_SDO Output logic low voltage
0.5 mA source from SDO, VnSLEEP, VVM
> 7 V
4.1
2.7
V
V
Output logic high voltage for "S" variant
0.5 mA source from SDO, VnSLEEP
3.3 V, VVM > 5 V
=
VOH_SDO
0.5 mA source from SDO, VVDD = 5 V
0.5 mA source from SDO, VVDD = 3.3 V
4.5
3
V
V
Output logic high voltage for "P" variant
No current from SDO, VnSLEEP = 5 V,
VVM > 7 V
5.5
3.8
V
V
Output logic high voltage at no load on
SDO, valid only for "S" variant
VOH_SDO_NL
No current from SDO, VnSLEEP = 3.3 V,
VVM > 5 V
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UNIT
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7.5.4 Configuration Pins - HW Variant Only
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
6 level setting for ITRIP, SR and DIAG
Connect to GND
RLVL1OF6
RLVL2OF6
RLVL3OF6
RLVL4OF6
RLVL5OF6
RLVL6OF6
Level 1 of 6
Level 2 of 6
Level 3 of 6
Level 4 of 6
Level 5 of 6
Level 6 of 6
10
9
Ω
+/- 10% resistor to GND
+/- 10% resistor to GND
+/- 10% resistor to GND
+/- 10% resistor to GND
Hi-Z (no connect)
7.4
19.8
42.3
90
8.2
22
KΩ
KΩ
KΩ
KΩ
KΩ
24.2
51.7
110
47
100
250
3 level setting for MODE
Connect to GND
RLVL1OF3
RLVL2OF3
RLVL3OF3
Level 1 of 3
Level 2 of 3
Level 3 of 3
10
9
Ω
+/- 10% resistor to GND
Hi-Z (no connect)
7.4
8.2
KΩ
KΩ
100
7.5.5 Power FET Parameters
Measured at VVM = 13.5 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
93.1
79.8
93.1
79.8
UNIT
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
V
IOUT = 3 A, TJ = 25°C
IOUT = 3 A, TJ = 150°C
IOUT = 3 A, TJ = 25°C
IOUT = 3 A, TJ = 150°C
IOUT = 3 A, TJ = 25°C
IOUT = 3 A, TJ = 150°C
IOUT = 3 A, TJ = 25°C
IOUT = 3 A, TJ = 150°C
IOUT = +/- 3 A (Both directions)
49
High-side FET on resistance, HVSSOP
package
RHS_ON
42
49
42
High-side FET on resistance, VQFN-HR
package
Low-side FET on resistance, HVSSOP
package
RLS_ON
Low-side FET on resistance, VQFN-HR
package
VSD
Body diode forward voltage drop
+/- 0.8
1.2
OUT resistance to GND in SLEEP or
STANDBY state
RHi-Z
VOUTx = VVM = 13.5 V
KΩ
7.5.6 Switching Parameters with High-Side Recirculation
Load = 1.5mH / 4.7 Ohm, VVM = 13.5 V, refer high-side recirculation waveform
PARAMETER
TEST CONDITIONS
MIN
0.7
TYP
1.6
4
MAX
2.5
UNIT
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
SR = 3'b000 or LVL2
SR = 3'b001 (SPI only)
SR = 3'b010 (SPI only)
SR = 3'b011 or LVL3
SR = 3'b100 or LVL4
SR = 3'b101 or LVL1
SR = 3'b110 or LVL6
SR = 3'b111 or LVL5
2.4
5.6
4.8
8
11.2
16.8
25.2
32.2
46.2
60.2
7.2
12
18
23
33
43
SRLSOFF Output voltage rise time, 10% - 90%
10.8
13.8
19.8
25.8
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PARAMETER
TEST CONDITIONS
SR = 3'b000 or LVL2
MIN
TYP
1.1
0.9
0.8
0.7
0.5
0.75
1.6
4
MAX
UNIT
µs
SR = 3'b001 (SPI only)
SR = 3'b010 (SPI only)
SR = 3'b011 or LVL3
All other SRs
µs
Propagation time during output voltage
rise
tPD_LSOFF
µs
µs
µs
tDEAD_LSOFF Dead time during output voltage rise
All SRs
µs
SR = 3'b000 or LVL2
SR = 3'b001 (SPI only)
SR = 3'b010 (SPI only)
SR = 3'b011 or LVL3
SR = 3'b100 or LVL4
SR = 3'b101 or LVL1
SR = 3'b110 or LVL6
SR = 3'b111 or LVL5
SR = 3'b000 or LVL2
SR = 3'b001 (SPI only)
All other SRs
0.7
2.4
2.5
5.6
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
µs
4.8
8
11.2
16.8
25.2
32.2
46.2
60.2
7.2
12
SRLSON
Output voltage fall time, 90% - 10%
10.8
13.8
19.8
25.8
18
23
33
43
0.22
0.21
0.2
1.2
0.35
Propagation time during output voltage
fall
tPD_LSON
µs
µs
SR = 3'b000 or LVL2
All other SRs
µs
tDEAD_LSON Dead time during output voltage fall
µs
Output voltage rise and fall slew rate
MatchSRLS
matching
All SRs
+/- 20
%
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7.5.7 Switching Parameters with Low-Side Recirculation
Load = 1.5 mH / 4.7 Ohm, VVM = 13.5 V, refer low-side recirculation waveform
PARAMETER
TEST CONDITIONS
MIN
0.7
2.4
4.8
4.8
4.8
4.8
4.8
4.8
TYP
1.6
4
MAX
2.5
UNIT
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
µs
SR = 3'b000 or LVL2
SR = 3'b001 (SPI only)
SR = 3'b010 (SPI only)
SR = 3'b011 or LVL3
SR = 3'b100 or LVL4
SR = 3'b101 or LVL1
SR = 3'b110 or LVL6
SR = 3'b111 or LVL5
SR = 3'b000 or LVL2
SR = 3'b001 (SPI only)
SR = 3'b010 (SPI only)
SR = 3'b011 or LVL3
All other SRs
5.6
8
11.2
11.2
11.2
11.2
11.2
11.2
8
SRHSON
Output voltage rise time, 10% - 90%
8
8
8
8
3.9
2.2
1
µs
Propagation time during output voltage
rise
tPD_HSON
µs
0.8
0.5
0.35
1.6
4
µs
µs
tDEAD_HSON Dead time during output voltage rise
All SRs
µs
SR = 3'b000 or LVL2
SR = 3'b001 (SPI only)
SR = 3'b010 (SPI only)
SR = 3'b011 or LVL3
SR = 3'b100 or LVL4
SR = 3'b101 or LVL1
SR = 3'b110 or LVL6
SR = 3'b111 or LVL5
0.7
2.4
2.5
5.6
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
4.8
8
11.2
16.8
25.2
32.2
46.2
60.2
7.2
12
18
23
33
43
SRHSOFF Output voltage fall time, 90% - 10%
10.8
13.8
19.8
25.8
Propagation time during output voltage
fall
tPD_HSOFF
All SRs
0.25
µs
SR = 3'b000 or LVL2
SR = 3'b001 (SPI only)
All other SRs
1.7
0.7
µs
µs
µs
tDEAD_HSOFF Dead time during output voltage fall
0.25
Current regulation blanking time after
tBLANK
OUT slewing for current sense output to Valid for only for LS recirculation
settle
500
ns
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7.5.8 IPROPI & ITRIP Regulation
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Current scaling factor, HVSSOP
package
3020
A/A
AIPROPI
Current scaling factor, VQFN-HR
3070
A/A
package
IOUT > 0.8 A, measured up to 4.3 A
IOUT = 0.2 A to 0.8 A
-5
+5
%
%
%
AI_ERR
Current scaling factor error
-20
-50
+20
+50
IOUT = 0.1 A to 0.2 A
Current matching between the two half-
bridges
AI_ERR_M
OffsetIPROPI
BWIPROPI
IOUT > 0.8 A
-2
+2
12
%
µA
Offset current on IPROPI at no load
current
IOUT = 0 A
Bandwidth of the IPROPI internal sense
circuit
No external capacitor on IPROPI.
1
MHz
VIPROPI_LIM Internal clamping voltage on IPROPI
5
5.5
1.3
V
V
ITRIP = 3'b001 or LVL2
ITRIP = 3'b010 (SPI only)
ITRIP = 3'b011 (SPI only)
ITRIP = 3'b100 or LVL3
ITRIP = 3'b101 or LVL4
ITRIP = 3'b110 or LVL5
ITRIP = 3'b111 or LVL6
TOFF = 2'b00 (SPI only)
1.06
1.27
1.49
1.78
2.08
2.38
2.67
1.18
1.41
1.65
1.98
2.31
2.64
2.97
20
1.55
1.82
2.18
2.54
2.9
V
V
Voltage limit on VIPROPI to trigger TOFF
VITRIP_LVL
V
cycle for ITRIP regulation
V
V
3.27
V
µs
TOFF = 2'b01 (SPI). Only choice for
HW
30
µs
tOFF
ITRIP regulation - off time
TOFF = 2'b10 (SPI only)
TOFF = 2'b11 (SPI only)
40
50
µs
µs
7.5.9 Over Current Protection (OCP)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OCP_SEL = 2'b00 (SPI), Only choice
for HW
12
24
A
Over current protection threshold on the
IOCP_HS
high side
OCP_SEL = 2'b10 (SPI only)
OCP_SEL = 2'b01 (SPI only)
9
6
18
14
A
A
OCP_SEL = 2'b00 (SPI), Only choice
for HW
12
24
A
Over current protection threshold on the
IOCP_LS
low side
OCP_SEL = 2'b10 (SPI only)
OCP_SEL = 2'b01 (SPI only)
9
6
18
14
A
A
TOCP_SEL = 2'b00 (SPI), Only choice
for HW
Over current protection deglitch time
6
µs
Over current protection deglitch time
Over current protection deglitch time
Over current protection deglitch time
TOCP_SEL = 2'b01 (SPI only)
TOCP_SEL = 2'b10 (SPI only)
TOCP_SEL = 2'b11 (SPI only)
3
µs
µs
µs
tOCP
1.5
0.2
7.5.10 Over Temperature Protection (OTD)
PARAMETER
TEST CONDITIONS
MIN
TYP
170
30
MAX
UNIT
°C
TTSD
THYS
tTSD
Thermal shutdown temperature
Thermal shutdown hysteresis
Thermal shutdown deglitch time
155
185
°C
12
µs
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7.5.11 Voltage Monitoring
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VMOV_SEL = 2'b00 (SPI), Only choice
in HW variant
33.6
37
V
VVMOV
VM over voltage threshold while rising
VMOV_SEL = 2'b01 (SPI only)
VMOV_SEL = 2'b10 (SPI only)
28
18
31
21
V
V
VVMOV_HYS VM over voltage hysteresis
0.5
12
V
tVMOV
VM over voltage deglitch time
µs
V
VVMUV
VM under voltage threshold while falling
4.2
4.5
VVMUV_HYS VM under voltage hysteresis
200
12
mV
µs
tVMUV
VM under voltage deglitch time
VM voltage at which device goes into
POR
VMPOR_FALL
Applicable for HW & SPI "S" variant
Applicable for HW & SPI "S" variant
Applicable for SPI "P" variant
3.6
3.9
3.5
3.8
V
V
V
V
VM voltage at which device comes out of
POR
VMPOR_RISE
VDDPOR_FAL VDD voltage at which device goes into
POR
L
VDDPOR_RIS VDD voltage at which device comes out
Applicable for SPI "P" variant
of POR
E
7.5.12 Load Monitoring
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Off-state diagnostics (OLP)
Resistance on OUT to GND that will be
RS_GND
1
1
KΩ
KΩ
KΩ
KΩ
KΩ
detected as short, All modes
Resistance on OUT to VM that will be
RS_VM
detected as short , All modes
Resistance between OUTx that will be
ROPEN_FB
1.5
2
detected as open, PH/EN or PWM mode
Resistance on OUT to GND that will be
ROPEN_LS
Valid for low-side load
detected as open , Independent mode
Resistance on OUT to VM that will be
ROPEN_HS
Valid for high-side load, VVM = 13.5 V
10
detected as open, Independent mode
VOLP_REFH OLP Comparator Reference High
VOLP_REFL OLP Comparator Reference Low
2.65
2
V
V
Internal pull-up resistance on OUT to
VDD during OLP
ROLP_PU
VOUTx = VOLP_REFH + 0.1V
VOUTx = VOLP_REFL - 0.1V
1
1
KΩ
KΩ
Internal pull-down resistance on OUT to
GND during OLP
ROLP_PD
SPI variant only - On-state diagnostics (OLA)
Internal sink current on OUT to
IPD_OLA
GND during dead-time in high-side
recirculation
0.5
5
mA
V
Comparator Reference with respect to
VM used for OLA
VOLA_REF
0.25
7.5.13 Fault Retry Setting
Refer to retry setting waveform
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tRETRY
Automatic driver retry time
Fault reaction set to RETRY
6
ms
Fault free operation time to auto-clear
from over current event
tCLEAR
Fault reaction set to RETRY
90
200
µs
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PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Fault free operation time to auto-clear
from over temperature event
tCLEAR_TSD
Fault reaction set to RETRY
4.6
6.7
ms
7.5.14 Transient Thermal Impedance & Current Capability
Information based on thermal simulations
Table 7-1. Transient Thermal Impedance (RθJA) and Current Capability - full-bridge
Current [A](2)
RθJA [°C/W](1)
PACKA
GE
PART NUMBER
without PWM(3)
with PWM(4)
0.1 sec
7.3
1 sec
13
10 sec
17.5
DC
34.2
32.4
0.1 sec
7.5
1 sec
5.6
10 sec
4.8
DC
3.5
3.3
10 sec
4.4
DC
3.0
2.9
VQFN-
HR
DRV8243-Q1
DRV8243-Q1
HVSSOP
5.8
10.5
15.3
7.8
5.8
4.8
4.4
(1) Based on thermal simulations using 40 mm x 40 mm x 1.6 mm 4 layer PCB – 2 oz Cu on top and bottom layers, 1 oz Cu on internal
planes with 0.3 mm thermal via drill diameter, 0.025 mm Cu plating, 1 minimum mm via pitch.
(2) Estimated transient current capability at 85 °C ambient temperature for junction temperature rise up to 150°C
(3) Only conduction losses (I2R) considered
(4) Switching loss roughly estimated by the following equation:
PSW = VVM x ILoad x fPWM x VVM/SR, where VVM = 13.5 V, fPWM = 20 KHz, SR = 23 V/µs
(1)
7.6 SPI Timing Requirements
MIN
NOM
MAX
UNIT
ns
tSCLK
SCLK minimum period(1)
SCLK minimum high time
SCLK minimum low time
SDO minimum high time
nSCS input setup time
nSCS input hold time
100
50
tSCLKH
tSCLKL
ns
50
ns
tHI_nSCS
tSU_nSCS
tH_nSCS
tSU_SDI
tH_SDI
300
25
ns
ns
25
ns
SDI input data setup time
SDI input data hold time
SDO enable delay time(1)
SDO disable delay time(1)
25
ns
25
ns
tEN_SDO
tDIS_SDO
35
ns
100
ns
(1) Only for SPI "S" variant: SCLK and SDO delay times are valid only with SDO external load of 5 pF. At 20 pF load on SDO, there is a
25% increase in SCLK minimum time and SDO delays (8 MHz operation). There is NO such limitation for the SPI "P" variant.
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tHI_nSCS
tH_nSCS
tSU_nSCS
nSCS
tSCLK
SCLK
tSCLKH
tSCLKL
DON’T CARE
DON’T CARE
LSB
MSB
SDI
tSU_SDI
tH_SDI
tDIS_SDO
HI-Z
LSB
HI-Z
SDO
MSB
tEN_SDO
Write Command
executed by device
SDI capture point
SDO propogate point
Figure 7-1. SPI Peripheral-Mode Timing Definition
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7.7 Switching Waveforms
This section illustrates the switching transients for an inductive load due to external PWM or internal ITRIP
regulation.
7.7.1.1 High-Side Recirculation
LOAD
1, 2
LOAD
LOAD
4, 5, 6
LOAD
LOAD
3
7
8, 1
1
2
3
4
5
6
7
8
1
Isense OK
tDEAD_LSOFF
tDEAD_LSON
VM + VD(FET BODY DIODE)
VM
OUT1
OUT2
90%
~SRHSOFF
tPD_LSON
90%
~SRHSON
Accuracy not
Accuracy not
applicable
applicable
High side recircula on
Slew rate controlled by Low Side Driver (SRLSON & SRLSOFF
SRLSON
SRLSOFF
)
10%
10%
GND
tPD_LSOFF
“fPWM” @ duty cycle “D”
EN/IN1
PH/IN2
E.g. Full bridge in PH/EN mode, OUT1 is held high, while OUT2 is switching
Figure 7-2. Output Switching Transients for a H-Bridge with High-Side Recirculation
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LOAD
LOAD
LOAD
4, 5, 6
LOAD
LOAD
1, 2
3
7
8, 1
1
2
3
4
5
6
7
8
1
Isense NOT OK
tDEAD_LSOFF
tDEAD_LSON
VM + VD(FET BODY DIODE)
VM
90%
~SRHSOFF
tPD_LSON
90%
~SRHSON
Accuracy not
Accuracy not
applicable
applicable
High side recircula on
Slew rate controlled by Low Side Driver (SRLSON & SRLSOFF
)
SRLSON
SRLSOFF
10%
10%
OUT1
GND
tPD_LSOFF
“fPWM” @ duty cycle “1-D”
IN1
E.g. High side load in Independent mode, OUT1 is switching
Figure 7-3. Output Switching Transients for a Half-Bridge with High-Side Recirculation
7.7.1.2 Low-Side Recirculation
LOAD
LOAD
LOAD
4, 5, 6
LOAD
LOAD
8, 1
1, 2
3
7
1
2
3
4
5
6
7
8
1
Isense OK
Isense NOT OK
VM
Isense OK
OUT1
90%
90%
tBLANK
tPD_HSOFF
Low side recircula on
SRHSOFF
SRHSON
Slew rate controlled by High Side Driver (SRHSON & SRHSOFF
)
10%
10%
~SRLSOFF
~SRLSON
Accuracy not applicable
Accuracy not applicable
GND
GND - VD(FET BODY DIODE)
tDEAD_HSOFF
tDEAD_HSON
tPD_HSON
“fPWM” @ duty cycle “D”
IN1
E.g. Low side load in Independent mode, OUT1 is switching
Figure 7-4. Output Switching Transients for a half-bridge with Low-Side Recirculation
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7.7.2 Wake-up Transients
7.7.2.1 HW Variant
tRESET
tWAKEUP
tREADY
nSLEEP
nFAULT
tCOM
nSLEEP RESET
pulse ACK
Hand shake between controller and device
t0: Controller - nSLEEP = 1'b1 to ini ate device wakeup
t1: Device internal state - Wakeup command registered by device (end of Sleep state)
t2: Device – nFAULT asserted to “0” to acknowledge wakeup and indicate device ready for communica on
t3: Device internal state - Ini aliza on complete
t4 (any me a er t2): Controller – Issue nSLEEP reset pulse to acknowledge device wakeup
t5: Device - nFAULT de-asserted as an acknowledgement of nSLEEP reset pulse. Device in STANDBY state
Figure 7-5. SLEEP State to STANDBY State Transition for HW Variant
tREADY
VM
VVMUV_HYST
VVMUV
VMPOR_RISE
VMPOR_FALL
Internal
nPOR
tRESET
nSLEEP=
1'b1
tCOM
nFAULT
nSLEEP RESET
pulse ACK
Hand shake between controller and device
t0: Device internal state - POR asserted based on under voltage of internal LDO (VM dependent)
t1: Device internal state – POR de-asserted based on recovery of internal LDO voltage
t2: Device – nFAULT asserted to “0” to acknowledge wakeup and indicate device ready for communica on
t3: Device internal state - Ini aliza on complete
t4 (any me a er t2): Controller – Issue nSLEEP reset pulse to acknowledge device wakeup
t5: Device - nFAULT de-asserted as an acknowledgement of nSLEEP reset pulse. Device in STANDBY state
Figure 7-6. Power up to STANDBY State Transition for HW Variant
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7.7.2.2 SPI Variant
CLR_FLT
cmd
tWAKEUP
tREADY
nSLEEP
nFAULT
tCOM
CLR_FLT
cmd ACK
Hand shake between controller and device
t0: Controller - nSLEEP = 1'b1 to ini ate device wakeup
t1: Device internal state - Wakeup command registered by device (end of Sleep state)
t2: Device – nFAULT asserted to “0” to acknowledge wakeup and indicate device ready for communica on
t3: Device internal state - Ini aliza on complete
t4 (Any me a er t2): Controller – Issue CLR_FLT command through SPI to acknowledge device wakeup
t5: Device - nFAULT de-asserted as an acknowledgement of nSLEEP reset pulse. Device in STANDBY state
Figure 7-7. SLEEP State to STANDBY State Transition for SPI - "S" Variant
tREADY
VM
CLR_FLT
cmd
VVMUV_HYST
VVMUV
VMPOR_RISE
VMPOR_FALL
Internal
nPOR
nSLEEP=
1'b1
tCOM
nFAULT
CLR_FLT
cmd ACK
Hand shake between controller and device
t0: Device internal state - POR asserted based on under voltage of internal LDO (VM dependent)
t1: Device internal state – POR de-asserted based on recovery of internal LDO voltage
t2: Device – nFAULT asserted to “0” to acknowledge wakeup and indicate device ready for communica on
t3: Device internal state - Ini aliza on complete
t4 (any me a er t2): Controller – Issue CLR_FLT command through SPI to acknowledge device wakeup
t5: Device - nFAULT de-asserted as an acknowledgement of nSLEEP reset pulse. Device in STANDBY state
Figure 7-8. Power up to STANDBY State Transition for SPI - "S" Variant
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tREADY
VDD
CLR_FLT
cmd
VDDPOR_RISE
VDDPOR_FALL
Internal
nPOR
tCOM
nFAULT
CLR_FLT
cmd ACK
Hand shake between controller and device
t0: Device internal state - POR asserted based on under voltage of VDD supply
t1: Device internal state – POR de-asserted based on recovery of VDD supply
t2: Device – nFAULT asserted to “0” to acknowledge wakeup and indicate device ready for communica on
t3: Device internal state - Ini aliza on complete
t4 (any me a er t2): Controller – Issue CLR_FLT command through SPI to acknowledge device wakeup
t5: Device - nFAULT de-asserted as an acknowledgement of nSLEEP reset pulse. Device in STANDBY state
Figure 7-9. Power up to STANDBY State Transition for SPI - "P" Variant
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7.7.3 Fault Reaction Transients
7.7.3.1 Retry setting
Valid for both SPI and HW variants
tCLEAR
nFAULT
tOCP
tOCP
tOCP
IOCP
tRETRY
tRETRY
I(VM)
IVMQ
ILOAD
External short to ground fault
t1: Occurrence of short
t2: Short con rmed, output disabled, nFAULT asserted low
t3: Auto retry a empt a er a xed me (In case of TSD, cool o based on thermal hysteresis), each me output brie y
turned on to con rm short and then disabled, nFAULT remains asserted low through out. Cycle repeats ll driver disabled or
short removed.
t4: Removal of short
t5: Auto retry a empt, but this me with no fault
t6: Fault free opera on con rmed, nFAULT de-asserted
SPI Variant – Fault status remains latched ll CLR_FLT command
Figure 7-10. Fault reaction with RETRY setting (shown for OCP occurrence on high-side when OUT is
shorted to ground)
In the event high-side OCP occurs due to a short to GND, IPROPI pin will continue to be pulled up to VIPROPI_LIM
voltage to indicate this type of short, while the output is forced Hi-Z.
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7.7.3.2 Latch setting
Valid for both SPI and HW variants
CLR_FLT CMD (SPI) /
nSLEEP RESET PULSE (HW)
nFAULT
tOCP
tOCP
IOCP
I(VM)
IVMQ
ILOAD
External short to ground fault
t1: Occurrence of short
t2: Short con rmed, output disabled, nFAULT asserted low
t3: CLR_FLT CMD (SPI variant) or nSLEEP RESET Pulse (HW variant) issued by controller. nFAULT de-asserted and output
brie y turned to con rm short. Output disabled and nFAULT asserted low.
t4: Removal of short
t5: CLR_FLT CMD (SPI variant) or nSLEEP RESET Pulse (HW variant) issued by controller. nFAULT de-asserted and output
turned on for normal opera on
Figure 7-11. Fault reaction with Latch setting (shown for OCP occurrence on high-side when OUT is
shorted to ground)
In the event high-side OCP occurs due to a short to GND, IPROPI pin will continue to be pulled up to VIPROPI_LIM
voltage to indicate this type of short, while the output is forced Hi-Z.
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8 Detailed Description
8.1 Overview
The DRV824x-Q1 family of devices are brushed DC motor drivers that operate from 4.5 to 35-V supporting a
wide range of output load currents for various types of motors and loads. The devices integrate an H-bridge
output power stage that can be operated in different control modes set by the MODE function. This allows for
driving a single bidirectional brushed DC motor or two unidirectional brushed DC motors. The devices integrate
a charge pump regulator to support efficient high-side N-channel MOSFETs with 100% duty cycle operation.
The devices operate from a single power supply input (VM) which can be directly connected to a battery or DC
voltage supply. The devices also provide a low power mode to minimize current draw during system inactivity.
The devices are available in two interface variants -
1. HW variant - Hardwired interface variant is available for easy device configuration. Due to the limited number
of available pins in the device this variant offers fewer configuration and fault reporting capability compared
to the SPI variant.
2. SPI variant - A standard 4-wire serial peripheral interface (SPI) with daisy chain capability allows flexible
device configuration and detailed fault reporting to an external controller. The feature differences of the SPI
and HW variants can be found in the device comparison section. The SPI interface is available in two device
variant choices, as stated below:
a. "S" variant - The power supply for the digital block is provided by an internal LDO regulator sourced from
VM supply. The nSLEEP pin is a high impedance input pin.
b. "P" variant - This allows for an external supply input to the digital block of the device through a VDD pin.
The nSLEEP pin is replaced by this VDD supply pin. This prevents device reset (brown out) during a VM
under voltage condition.
The DRV824x family of devices provide a load current sense output using current mirrors on the high-side
power MOSFETs. The IPROPI pin sources a small current that is proportional to the current in the high-side
MOSFETs (current sourced out of the OUTx pin). This current can be converted to a proportional voltage using
an external resistor (RIPROPI). Additionally, the devices also support a fixed off-time PWM chopping scheme for
limiting current to the load. The current regulation level can be configured through the ITRIP function.
A variety of protection features and diagnostic functions are integrated into the device. These include supply
voltage monitors (VMOV, VMUV), , off-state (Passive) diagnostics (OLP), on-state (Active) diagnostics (OLA) -
SPI variant only, overcurrent protection (OCP) for each power FET and over-temperature shutdown (TSD). Fault
conditions are indicated on the nFAULT pin. The SPI variant has additional communication protection features
such as frame errors and lock features for configuration register bits and driver control bits.
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8.2 Functional Block Diagram
8.2.1 HW Variant
High Side load to VM
(Independent mode)
Low Side load to GND
(Independent mode)
Full Bridge load
(PH/EN or PWM mode)
VM
VM
PSM
Gate Driver
VVCP
VCP
ISNS1
0.1 μF
Charge
Pump
HS
VDD
OUT1
GND
Internal
LDO & Bias
GND
VDD
Supply
Monitors
LS
VDD
Oscillator
DRVOFF
nSLEEP
Thermal Protection (OTD)
Over Current Protection (OCP)
Off-state Diagnostics (OLP)
VM
Digital IOs
EN/IN1
PH/IN2
Gate Driver
ISNS2
VVCP
HS
OUT2
VDD
MODE
LS
ITRIP
SR
GND
Impedance
Estimator
RnFAULT
nFAULT
IPROPI
DIAG
ISNS1
ISNS2
RIPROPI
Figure 8-1. Functional Block Diagram - HW Variant
8.2.2 SPI Variant
There are two variants for the SPI interface - "S" variant and "P" variant as shown below.
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High Side load to VM
(Independent mode)
Low Side load to GND
(Independent mode)
Full Bridge load
(PH/EN or PWM mode)
VM
VM
PSM
Gate Driver
VCP
ISNS1
VVCP
0.1 μF
Charge
Pump
HS
VDD
OUT1
GND
Internal
LDO & Bias
GND
VDD
Supply
Monitors
LS
VDD
Oscillator
DRVOFF
nSLEEP
Thermal Protection (OTD)
Over Current Protection (OCP)
Load Diagnostics (OLP & OLA)
VM
EN/IN1
PH/IN2
Gate Driver
ISNS2
VVCP
HS
VDD
OUT2
VDD
Digital IOs
nSCS
SDI
LS
GND
RnFAULT
nFAULT
IPROPI
SCLK
SDO
ISNS1
ISNS2
∑
RIPROPI
Figure 8-2. Functional Block Diagram - SPI "S" Variant
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High Side load to VM
(Independent mode)
Low Side load to GND
(Independent mode)
Full Bridge load
(PH/EN or PWM mode)
VM
VM
PSM
Gate Driver
VCP
ISNS1
VVCP
0.1 μF
Charge
Pump
VDD
GND
HS
OUT1
GND
Bias
VDD
Supply
Monitors
LS
Oscillator
VDD
Thermal Protection (OTD)
Over Current Protection (OCP)
Load Diagnostics (OLP & OLA)
DRVOFF
EN/IN1
PH/IN2
VM
Gate Driver
ISNS2
VVCP
HS
OUT2
VDD
VDD
Digital IOs
nSCS
SDI
LS
GND
RnFAULT
nFAULT
IPROPI
SCLK
SDO
ISNS1
ISNS2
∑
RIPROPI
Figure 8-3. Functional Block Diagram - SPI "P" Variant
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8.3 Feature Description
8.3.1 External Components
Section 8.3.1.1 and Section 8.3.1.2 contain the recommended external components for the device.
8.3.1.1 HW Variant
Table 8-1. External Components Table for HW Variant
Component
PIN
Recommendation
CVM1
VM
0.1 µF, low ESR ceramic capacitor to GND rated for VM
Local bulk capacitor to GND, 10 µF or higher, rated for VM to handle load transients. Refer the
section on bulk capacitor sizing.
CVM2
VM
Typically 500 - 5000 Ω 0.063 W resistor to GND, depending on the controller ADC dynamic range.
Pin can be shorted to GND if ITRIP and IPROPI function is not needed.
RIPROPI
IPROPI
RnFAULT
RMODE
RSR
nFAULT
MODE
SR
1000 - 2000 Ω, 0.063 W pull-up resistor to controller supply.
Open or short to GND or 0.063 W 10% resistor to GND depending on setting. Refer MODE table.
Open or short to GND or 0.063 W 10% resistor to GND depending on setting. Refer SR section.
Open or short to GND or 0.063 W 10% resistor to GND depending on setting. Refer ITRIP table.
Open or short to GND or 0.063 W 10% resistor to GND depending on setting. Refer DIAG section.
RITRIP
RDIAG
ITRIP
DIAG
8.3.1.2 SPI Variant
Table 8-2. External Components Table for SPI Variant
Component
PIN
Recommendation
CVM1
VM
0.1 µF, low ESR ceramic capacitor to GND rated for VM
Local bulk capacitor to GND, 10 µF or higher, rated for VM to handle load transients. Refer the
section on bulk capacitor sizing.
CVM2
VM
Typically 500 - 5000 Ω 0.063 W resistor to GND, depending on the controller ADC dynamic range.
Pin can be shorted to GND if ITRIP and IPROPI function is not needed.
RIPROPI
IPROPI
1000 - 2000 Ω, 0.063 W pull-up resistor to controller supply. If nFAULT signaling is not used, this
pin can be short to GND.
RnFAULT
CVDD
nFAULT
VDD
0.1 µF, 6.3 V, low ESR ceramic capacitor to GND. This is applicable the SPI "P" variant only.
8.3.2 Bridge Control
The DRV824x-Q1 family of devices provides three separate modes to support different control schemes with the
EN/IN1 and PH/IN2 pins. The control mode is selected through the MODE setting. MODE is a 3-level setting
based on the MODE pin for the HW variant or S_MODE bits in the CONFIG3 register for the SPI variant as
summarized in Table 8-3:
Table 8-3. Mode table
MODE pin
RLVL1OF3
RLVL2OF3
RLVL3OF3
S_MODE bits
2'b00
Device Mode
Description
full-bridge mode where EN/IN1 is the PWM input,
PH/EN2 is the direction input
PH/EN mode
2'b01
Independent mode
PWM mode
Independent control for 2 half-bridges
full-bridge mode where EN/IN1 and PH/EN2 control
the PWM respectively depending on the direction
2'b10, 2b'11
In the HW variant, MODE pin is latched during device initialization following power-up or wake-up from sleep.
Update during operation is blocked.
In the SPI variant of the device, the mode setting can be changed anytime the SPI communication is available by
writing to the S_MODE bits. This change is immediately reflected.
The inputs can accept static or pulse-width modulated (PWM) voltage signals for either 100% or PWM drive
modes. The device input pins can be powered before VM is applied. By default, the nSLEEP and DRVOFF
pins have an internal pull-down and pull-up resistor respectively, to ensure the outputs are Hi-Z if no inputs are
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present. Both the EN/IN1 and PH/IN2 pins also have internal pull down resistors. The sections below show the
truth table for each control mode.
The device automatically generates the optimal dead-time needed during transitioning between the high-side
and low-side FET on the switching half-bridge. This timing is based on internal FET gate-source voltage
feedback. No external timing is required. This scheme ensures minimum dead time, while guaranteeing no
shoot-through current.
Note
1. The SPI variant also provides additional control through the SPI_IN register bits. Refer to -
Register - Pin control.
2. For the SPI "P" variant, ignore the nSLEEP column in the control table as there is no nSLEEP pin.
Internally, nSLEEP = 1, always. The control table is valid when VDD > VDDPOR level.
8.3.2.1 PH/EN mode
In this mode, the two half-bridges are configured to operate as a full-bridge. EN/IN1 is the PWM input and
PH/IN2 is the direction input. For load illustration, refer the Load Summary section.
Table 8-4. Control table - PH/EN mode
nSLEEP
DRVOFF
EN/IN1
PH/IN2
OUT1
OUT2
IPROPI
Device State
SLEEP
0
1
1
1
1
1
1
1
X
1
1
1
1
0
0
0
X
0
1
0
1
0
1
1
X
0
0
1
1
X
0
1
Hi-Z
Hi-Z
No current
No current
Hi-Z
Hi-Z
STANDBY
Refer Off-state diagnostics table
No current
STANDBY
H
L(2)
H
H
H
ISNS1 or ISNS2(1)
ISNS2
ACTIVE
ACTIVE
ACTIVE
L(2)
ISNS1
(1) Current sourcing out of the device (VM → OUTx → Load)
(2) If internal ITRIP regulation is enabled and ITRIP level is reached, then OUTx is forced "H" for a fixed time
8.3.2.2 PWM mode
In this mode, the two half-bridges are configured to operate as a full-bridge. EN/IN1 provides the PWM input
in one direction, while PH/IN2 provides the PWM in the other direction. For load illustration, refer the Load
Summary section.
Table 8-5. Control table - PWM mode
nSLEEP
DRVOFF
EN/IN1
PH/IN2
OUT1
OUT2
IPROPI
No current
No current
No current
No current
No current
ISNS1 or ISNS2(1)
ISNS2
Device State
SLEEP
0
1
1
1
1
1
1
1
1
X
1
1
1
1
0
0
0
0
X
0
1
0
1
0
0
1
1
X
0
0
1
1
0
1
0
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
STANDBY
STANDBY
STANDBY
STANDBY
ACTIVE
Refer Off-state diagnostics table
H
L(2)
H
H
H
ACTIVE
L(2)
ISNS1
ACTIVE
Hi-Z
Hi-Z
No current
STANDBY
(1) Current sourcing out of device (VM → OUTx → Load)
(2) If internal ITRIP regulation is enabled and ITRIP level is reached, then OUTx is forced "H" for a fixed time
For the SPI variant, by setting the PWM_EXTEND bit in the CONFIG2 register, there are additional Hi-Z states
that are possible, when a forward ([EN/IN1 PH/IN2] = [1 0]) or reverse ([EN/IN1 PH/IN2] = [0 1]) command is
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followed by a Hi-Z command ([EN/IN1 PH/IN2] = [1 1]). In this condition of Hi-Z (coasting), only the half-bridge
involved with the PWM is Hi-Z, while the HS FET on the other half-bridge is kept ON. The determination on
which half-bridge to Hi-Z is made based on the previous cycle. This is summarized in Table 8-6.
Table 8-6. PWM EXTEND table (PWM_EXTEND bit = 1'b1)
PREVIOUS STATE
CURRENT STATE
Device State Transition
OUT1
OUT2
Hi-Z
H
OUT1
Hi-Z
Hi-Z
Hi-Z
H
OUT2
Hi-Z
Hi-Z
H
IPROPI
No current
No current
ISNS2
Hi-Z
H
remains in STANDBY, no change
ACTIVE to STANDBY
L
H
ACTIVE to STANDBY
H
L
Hi-Z
ISNS1
ACTIVE to STANDBY
Note
For the pre-production samples, the truth table is modified as shown in Table 8-7:
Table 8-7. Control Table Differences - PWM Mode in Pre-Production Samples
nSLEEP
DRVOFF
EN/IN1
PH/IN2
OUT1
OUT2
IPROPI
ISNS1 or ISNS2
No current
Device State
ACTIVE
1
1
0
0
1
0
1
0
H
H
Hi-Z
Hi-Z
STANDBY
With this change, as an example, the PWM cycle for a forward → brake (HS recirculation) → forward, inputs will
be as follows:
•
•
Pre-production samples: [EN/IN1 PH/IN2] = [1 0] → [1 1] → [1 0]
Final product: [EN/IN1 PH/IN2] = [1 0] → [0 0] → [1 0]
8.3.2.3 Independent mode
In this mode, the two half-bridges are configured to be used as two independent half-bridges. TheTable 8-8
shows the logic table for bridge control. For load illustration, refer the Load Summary section.
Table 8-8. Control table - Independent mode
nSLEEP
DRVOFF
EN/IN1
PH/IN2
OUT1
OUT2
IPROPI
No current
No current
No current
No current
No current
No current
ISNS2(1)
Device State
SLEEP
0
1
1
1
1
1
1
1
1
X
1
1
1
1
0
0
0
0
X
0
1
0
1
0
0
1
1
X
0
0
1
1
0
1
0
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
STANDBY
STANDBY
STANDBY
STANDBY
ACTIVE
Refer Off-state diagnostics table
L
L
L
H(2)
ACTIVE
H(2)
H(2)
L
ISNS1(1)
ACTIVE
H(2)
ISNS1 + ISNS2(1)
ACTIVE
For the SPI variant, it is possible to have independent Hi-Z control of both half-bridges through equivalent bits,
S_DRVOFF & S_DRVOFF2 in the SPI_IN register, when the SPI_IN register has been unlocked. Table 8-9
shows the logic table for bridge control using the pin & register combined inputs. Refer to - Register - Pin control
for details on the combined inputs shown in Table 8-9.
Table 8-9. Control table - Independent mode for SPI variant, when SPI_IN is unlocked
DRVOFF1 DRVOFF2 EN_IN1
combined combined combined combined
PH_IN2
nSLEEP
OUT1
OUT2
IPROPI
Device State
0
1
X
1
X
1
X
0
X
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
No current
No current
SLEEP
STANDBY
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Table 8-9. Control table - Independent mode for SPI variant, when SPI_IN is unlocked (continued)
DRVOFF1 DRVOFF2 EN_IN1
combined combined combined combined
PH_IN2
OUT1
OUT2
IPROPI
Device State
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
1
1
0
0
0
1
0
1
X
X
0
1
0
0
1
0
1
1
0
1
X
X
0
1
0
No current
No current
No current
No current
ISNS2(1)
STANDBY
STANDBY
STANDBY
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Refer Off-state diagnostics table
Hi-Z
Hi-Z
L
L
H(2)
Hi-Z
Hi-Z
L
No current
ISNS1(1)
H(2)
L
No current
ISNS2(1)
L
H(2)
H(2)
L
ISNS1(1)
ISNS1 +
ISNS2(1)
1
0
0
1
1
H(2)
H(2)
ACTIVE
(1) Current sourcing out of device (VM → OUTx → Load)
(2) If internal ITRIP regulation is enabled and ITRIP level is reached, then OUTx is forced "L" for a fixed time
In this mode, the device behavior is as listed below:
•
Load current can be sensed only for current from VM → OUTx → Load. So current sense is not possible for
high-side loads
•
The current on IPROPI pin is the sum of the high-side sense current from both the half-bridges. This limits the
ITRIP current regulation feature as a combined current regulation, rather than as truly independent.
Slew rate configurability is limited for low-side recirculation (low-side loads)
Active state open load diagnostics (OLA) is possible only for high-side loads
For the HW variant, it is NOT possible to have independent Hi-Z control of each half-bridge. Asserting
DRVOFF pin high will Hi-Z both the half-bridges.
•
•
•
8.3.2.4 Register - Pin Control - SPI Variant Only
The SPI variant allows control of the bridge through the specific register bits, S_DRVOFF, S_DRVOFF2,
S_EN_IN1, S_PH_IN2 in the SPI_IN register, provided the SPI_IN register has been unlocked. The user
can unlock this register by writing the right combination to the SPI_IN_LOCK bits in the COMMAND register.
Additionally, the user can configure between an AND / OR logic combination of each of external input pin with
their equivalent register bit in the SPI_IN register. This logical configuration is done through the equivalent
selects bits in the CONFIG4 register:
•
DRVOFF_SEL, EN_IN1_SEL and PH_IN2_SEL
The control of the output is similar to the truth tables described in the section before, but with these logically
combined inputs. These combined inputs are listed as follows:
•
•
•
Combined input = Pin input OR equivalent SPI_IN register bit, if equivalent CONFIG4 select bit = 1'b0
Combined input = Pin input AND equivalent SPI_IN register bit, if equivalent CONFIG4 select bit = 1'b1
In Independent mode:
– DRVOFF2 combined = DRVOFF pin OR S_DRVOFF2 bit, if DRVOFF_SEL bit = 1'b0
– DRVOFF2 combined = DRVOFF pin AND S_DRVOFF2 bit, if DRVOFF_SELbit = 1'b1
Note that external nSLEEP pin is still needed for sleep function.
This logical combination offers more configurability to the user as shown in the table below.
Table 8-10. Register - Pin Control Examples
CONFIG4: xxx_SEL
Example
PIN status
SPI_IN Bit Status
Comment
Bit
DRVOFF as
Either DRVOFF pin = 1 or S_DRVOFF bit = 1
will shutoff the output
DRVOFF_SEL = 1’b0
DRVOFF active
S_DRVOFF active
redundant shutoff
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Table 8-10. Register - Pin Control Examples (continued)
CONFIG4: xxx_SEL
Bit
Example
PIN status
SPI_IN Bit Status
S_DRVOFF = 1'b1
S_PH_IN2 active
Comment
Pin only control
DRVOFF_SEL = 1’b1
DRVOFF active
Only DRVOFF pin function is available
PH_IN2_SEL bit =
1’b0
PH/IN2 - short to
GND or float
PH (direction) will be controlled by the
register bit alone
Register only control
Note
This logical combination is NOT supported in the pre-production samples. In this case, when the
SPI_IN register is unlocked, the output is controlled from the equivalent register bits and the input
pins are ignored. In other words, if SPI_IN unlocked, xxx_combined = S_xxx register bits, else
xxx_combined = Input pin.
8.3.3 Device Configuration
This section describes the various device configurations to enable the user to configure the device to suit their
use case.
8.3.3.1 Slew Rate (SR)
The SR pin (HW variant) or S_SR bits in the CONFIG3 register (SPI variant) determines the slew rate of
the driver. This enables the user to optimize the PWM switching losses while meeting the EM conformance
requirements. For the HW variant, SR is a 6-level setting as summarized in the table below. SPI variant has
additional 2 levels.
Table 8-11. SR Table
SRLSOFF, SRLSON [V/µsec](1)
SR Pin
RLVL2OF6
S_SR Register Bits
3'b000
SRHSOFF [V/µsec](2)
SRHSON [V/µsec](2)
1.6
4
1.6
4
1.6
4
Not available
Not available
RLVL3OF6
3'b001
3'b010
8
8
8
3'b011
12
18
23
33
43
12
18
23
33
43
8
RLVL4OF6
3'b100
8
RLVL1OF6
3'b101
8
RLVL6OF6
3'b110
8
RLVL5OF6
3'b111
8
(1) Applicable for high-side recirculation (1)
(2) Applicable for low-side recirculation (2)
Note
The SPI variant also offers an optional spread spectrum clocking (SSC) feature that spreads the
internal oscillator frequency +/- 12% around its mean with a period triangular function of ~1.3 MHz to
reduce emissions at higher frequencies.
In the HW variant, the SR pin is latched during device initialization following power-up or wake-up from sleep.
Update during operation is blocked. Also there is no spread spectrum clocking (SSC) feature.
In the SPI variant, the slew rate setting can be changed at any time when SPI communication is available by
writing to the S_SR bits. This change is immediately reflected.
Note
For the pre-production samples, the SR settings are as shown in Table 8-12 the table below. Also, in
the HW variant, SSC feature is always enabled.
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Table 8-12. Pre-Production Samples - SR Table
SR Pin
RLVL1OF6
RLVL2OF6
S_SR Register Bits
SRLSOFF, SRLSON [V/µsec](1)
SRHSOFF [V/µsec](2)
SRHSON [V/µsec](2)
3'b000
3'b001
3'b010
3'b011
3'b100
3'101
23
1.6
33
38
43
28
18
12
23
1.6
33
38
43
28
18
12
8
1.6
8
RLVL3OF6
RLVL4OF6
8
RLVL5OF6
8
RLVL6OF6
8
Not available
Not available
3'b110
3'b111
8
8
8.3.3.2 IPROPI
The device integrates a current sensing feature with a proportional analog current output on the IPROPI pin that
can be used for load current regulation. This eliminates the need of an external sense resistor or sense circuitry
reducing system size, cost, and complexity.
The device senses the load current by using a shunt-less high-side current mirror topology. This way the device
can only sense an uni-directional high-side current from VM → OUTx → Load through the high-side FET when
it is fully turned ON (linear mode). The IPROPI pin outputs an analog current proportional to this sensed current
scaled by AIPROPI as follows:
IIPROPI = (IHS1 + IHS2) / AIPROPI
The IPROPI pin must be connected to an external resistor (RIPROPI) to ground in order to generate a proportional
voltage VIPROPI. This allows for the load current to be measured as a voltage-drop across the RIPROPI resistor
with an analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current
in the application so that the full range of the controller ADC is utilized.
The current expressed on IPROPI is the sum of the currents flowing out of the OUTx pins from VM. This implies
that:
•
In full-bridge operation using PWM or PH/EN mode, the current expressed on IPROPI pin is always from one
of the half-bridges that is sourcing the current from VM to the load.
•
In independent mode, the current expressed on IPROPI pin could be from either half-bridges or both of them.
It is not possible to observe only one half-bridge current independently.
8.3.3.3 ITRIP Regulation
The device offers an optional internal load current regulation feature using fixed TOFF time method. This is done
by comparing the voltage on the IPROPI pin against a reference voltage determined by ITRIP setting. TOFF time
is fixed at 30 µsec for HW variant, while it is configurable between or 20 to 50 µsec for the SPI variant using
TOFF_SEL bits in the CONFIG3 register.
The ITRIP regulation, when enabled, comes into action only when the HS FET is enabled and current sensing is
possible. In this scenario, when the voltage on the IPROPI pin exceeds the reference voltage set by the ITRIP
setting, the internal current regulation loop forces the following action:
•
In PH/EN or PWM mode, OUT1 = H, OUT2 = H (high-side recirculation) for the fixed TOFF time
– Cycle skipping: To prevent current walk away up due to current sensing bandwidth, a cycle skipping
scheme is implemented, where, if IOUT sensed is still greater than ITRIP at the end of TOFF time, then
TOFF time is doubled. This "double TOFF" time will continue till IOUT sensed is less than ITRIP at the end
of TOFF time.
•
In Independent mode, If OUTx = H, then toggle OUTx = L for the fixed TOFF time, else no action on OUTx
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Note
The user inputs always takes precedence over the internal control. That means that if the inputs
change during the TOFF time, the remainder of the TOFF time is ignored and the outputs will follow
the inputs as commanded.
ISNS
VM
IPROPI
RIPROPI
High Side Current
Sense
V(IPROPI)
V(ITRIP)
OUTx
GND
ITRIP
RITRIP
Impedance Estimator
(HW variant)
DAC
SPI (SPI variant)
Digital Core
Figure 8-4. ITRIP Implementation
Current limit is set by the following equation:
ITRIP regulation level = VITRIP / RIPROPI X AIPROPI
(2)
ITRIP regula on ac ve
ITRIP
IOUT
VOUT1
VOUT2
EN/IN1
tOFF
tOFF
tOFF
PH/IN2
E.g. PH/EN mode
Figure 8-5. Fixed TOFF ITRIP Current Regulation
In Independent mode, since ITRIP regulation is based on summation of the two half-bridge currents on IPROPI
pin, it is not possible to have completely independent current regulation for the two half-bridges simultaneously.
The ITRIP comparator output (ITRIP_CMP) is ignored during output slewing to avoid false triggering of the
comparator output due to current spikes from the load capacitance. Additionally, in the event of transition from
low-side recirculation, an additional blanking time tBLANK is needed for the sense loop to stabilize before the
ITRIP comparator output is valid.
ITRIP is a 6-level setting for the HW variant. The SPI variant offers two more settings. This is summarized in the
table below:
Table 8-13. ITRIP Table
ITRIP Pin
RLVL1OF6
RLVL2OF6
S_ITRIP Register Bits
VITRIP [V]
Regulation Disabled
1.18
3'b000
3'b001
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Table 8-13. ITRIP Table (continued)
ITRIP Pin
Not available
Not available
RLVL3OF6
S_ITRIP Register Bits
VITRIP [V]
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
1.41
1.65
1.98
2.31
2.64
2.97
RLVL4OF6
RLVL5OF6
RLVL6OF6
In the HW variant of the device, the ITRIP pin changes are transparent and changes are reflected immediately.
In the SPI variant of the device, the ITRIP setting can be changed at any time when SPI communication is
available by writing to the S_ITRIP bits. This change is immediately reflected in the device behavior.
SPI variant only - If the ITRIP regulation levels are reached, the ITRIP_CMP bit in the STATUS1 register is set.
There is no nFAULT pin indication. This bit can be cleared with a CLR_FLT command.
Note
For pre-production samples, the ITRIP settings are as shown in the table below.
Table 8-14. Pre-Production Samples - ITRIP Table
ITRIP Pin
RLVL1OF6
RLVL2OF6
RLVL3OF6
RLVL4OF6
RLVL5OF6
RLVL6OF6
S_ITRIP Register Bits
VITRIP [V]
3'b000
Regulation Disabled
3'b001
1.65
1.98
2.31
2.64
2.97
3'b010
3'b011
3'b100
3'b101, 3'b110, 3'b111
8.3.3.4 DIAG
The DIAG is a pin (HW variant) or register (SPI variant) setting that is used in both ACTIVE and STANDBY
operation of the device, as follows:
•
STANDBY state
– In PH/EN or PWM modes: Enable or disable Off-state diagnostics (OLP).
– Enable or disable Off-state diagnostics (OLP), as well as select the OLP combinations when enabled.
Refer to the tables in the Off-state diagnostics (OLP) section for details on this.
ACTIVE state
•
– Mask ITRIP regulation function if the load type is indicated as high-side load.
– SPI variant only - Mask active open load detection (OLA) if the load type is indicated as low-side. load
– HW variant only - Configure fault reaction between retry and latch settings
8.3.3.4.1 HW variant
For the HW variant, the DIAG pin is a 6-level setting. Depending on the mode, its configurations are
summarized in the table below.
Table 8-15. DIAG table for the HW variant, PH/EN or PWM mode
STANDBY state
Off-state diagnostics
Disabled
ACTIVE state
Fault reaction
Retry
DIAG pin
RLVL1OF6
All other levels
Enabled(1)
Latch
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Table 8-16. DIAG table for the HW variant, Independent mode
STANDBY state
Off-state diagnostics
Disabled
ACTIVE state
Fault reaction
Retry
DIAG pin
Load Configuration
Low-side load
Low-side load
High-side load
High-side load
Low-side load
Low-side load
IPROPI / ITRIP
RLVL1OF6
RLVL2OF6
RLVL3OF6
RLVL4OF6
RLVL5OF6
RLVL6OF6
Available
Available
Disabled
Disabled
Available
Available
Enabled(1)
Latch
Enabled(1)
Latch
Enabled(1)
Retry
Disabled
Latch
Enabled(1)
Retry
(1) Refer to the tables in the Off-state diagnostics (OLP) section for combination details
Note
HW variant only - Option to disable off-state diagnostics for a high-side load use case is not
supported. In this case, setting DRVOFF pin high and IN pin low is only way to disable off-state
diagnostics.
In the HW variant, the DIAG pin is latched during device initialization following power-up or wake-up from sleep.
Update during operation is blocked.
8.3.3.4.2 SPI variant
For the SPI variant, S_DIAG is a 2-bit setting in the CONFIG2 register. Depending on the mode, its
configurations are summarized in the table below.
Table 8-17. DIAG table for the SPI variant, PH/EN or PWM mode
STANDBY state
Off-state diagnostics
Disabled
ACTIVE state
On-state diagnostics
Available
S_DIAG bits
2'b00
2'b01, 2'b10, 2'b11
Enabled1
Available
Table 8-18. DIAG table for the SPI variant, Independent mode
STANDBY state
Off-state diagnostics
Disabled
ACTIVE state
On-state diagnostics
Disabled
S_DIAG bits
Load Configuration
Low-side load
IPROPI / ITRIP
Available
2'b00
2'b01
2'b10
2'b11
Enabled1
Low-side load
Disabled
Available
Disabled
High-side load
High-side load
Available
Disabled
Enabled1
Available
Disabled
1. Refer to the tables in the Off-state diagnostics (OLP) section for combination details
In the SPI variant of the device, the settings can be changed anytime when SPI communication is available by
writing to the S_DIAG bits. This change is immediately reflected.
8.3.4 Protection and Diagnostics
The driver is protected against over-current and over-temperature events to ensure device robustness.
Additionally, the device also offers load monitoring (on-state and off-state), over/ under voltage monitoring on
VM pin to signal any unexpected voltage conditions. Fault signaling is done through a low-side open drain
nFAULT pin which gets pulled to GND by InFAULT_PD current on detection of a fault condition. Transition to SLEEP
state automatically de-asserts nFAULT.
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Note
In the SPI variant, nFAULT pin logic level is the inverted copy of the FAULT bit in the FAULT
SUMMARY register. Only exception is when off-state diagnostics is enabled and SPI_IN register is
locked (Refer OLP section) .
For the SPI variant, whenever nFAULT is asserted low, the device logs the fault into the FAULT SUMMARY and
STATUS registers. These registers can be cleared only by
•
•
CLR FLT command or
SLEEP command through the nSLEEP pin
It is possible to get all the useful diagnostic information for periodic software monitoring in a single 16 bit SPI
frame by:
•
•
Reading the STATUS1 register during ACTIVE state
Reading the STATUS2 register during STANDBY state
All the diagnosable fault events can be uniquely identified by reading the STATUS registers.
8.3.4.1 Over Current Protection (OCP)
•
•
Device state: ACTIVE
Mechanism & thresholds: An analog current limit circuit on each MOSFET limits the peak current out of the
device even in hard short circuit events. If the output current exceeds the overcurrent threshold, IOCP, for
longer than tOCP, then an over current fault is detected.
•
Action:
– nFAULT pin is asserted low
– Depending on the mode selection, either the effected half-bridge is disabled (Independent mode) or the
entire H-bridge is disabled (PH/EN or PWM mode)
– For a short to GND fault (over current detected on the high-side FET), the IPROPI pin continues to be
pulled up to VIPROPI_LIM even if the FET has been disabled. For the HW variant, this helps differentiate a
short to GND fault during ACTIVE state from other fault types, as the IPROPI pin is pulled high while the
nFAULT pin is asserted low.
•
Reaction configurable between latch setting and retry setting based on tRETRY and tCLEAR
The SPI variant offers configurable IOCP levels and tOCP filter times. Refer CONFIG4 register for these settings.
8.3.4.2 Over Temperature Protection (TSD)
•
•
Device state: STANDBY, ACTIVE
Mechanism & thresholds: The device has several temperature sensors spread around the die. If any of the
sensors detect an over temperature event, set by TTSD for a time greater than tTSD, then an over temperature
fault is detected.
•
Action:
– nFAULT pin is asserted low
– full-bridge is disabled
– IPROPI pin is Hi-Z
•
Reaction configurable between latch setting and retry setting based on THYS and tCLEAR_TSD
8.3.4.3 Off-State Diagnostics (OLP)
The user can determine the terminal impedance on the OUTx node using off-state diagnostics in the STANDBY
state when the power FETs are off. It is possible to detect the following terminal fault conditions passively:
•
•
•
Output short to VM or GND < 100 Ω
Open load > 1K Ω for full-bridge load or low-side load
Open load > 10K Ω for high-side load, VM = 13.5 V
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Note
It is NOT possible to detect a load short with this diagnostic. The user can deduce this logically if an
over current fault (OCP) occurs, but OLP does not report any fault. Occurrence of both OCP and OLP
would imply a terminal short (short on OUT node).
•
The user can configure the following combinations
– Internal pull up resistor (ROLP_PU) on OUTx
– Internal pull down resistor (ROLP_PD) on OUTx
– Comparator reference level
– Comparator input selection (OUT1 or OUT2)
•
•
•
•
•
This combination is determined by the controller inputs (pins only for the HW variant) or equivalent bits in the
SPI_IN register for the SPI variant if the SPI_IN register has been unlocked.
HW variant - When off-state diagnostics are enabled, comparator output (OLP_CMP) is available on nFAULT
pin
SPI variant - When off-state diagnostics are enabled, comparator output (OLP_CMP) is available on
OLP_CMP bit in STATUS2 register if the SPI_IN register has been unlocked, else on the nFAULT pin
The user is expected to toggle through all the combinations and record the comparator output after its output
is settled.
Based on the input combinations and comparator output, the user can determine if there is a terminal fault on
the output.
Internal 5V
5V Shunt
VM
ROLP_PU
ROLP_PU
D1
D1
OUT1
OUT2
Filter
Filter
ROLP_PD
ROLP_PD
RHIZ
RHIZ
D2
D2
GND
OLP_CMP
PIN / REG
input
REF Voltage
Propor onal to
VOLP_REFH
nFAULT PIN /
REG output
VOLP_REFL
Internal 5V
Figure 8-6. Off-State Diagnostics for full-bridge Load (PH/EN or PWM Mode)
The OLP combinations and truth table for a no fault scenario vs. fault scenario for a full-bridge load in PH/EN or
PWM modes is shown in Table 8-19.
Table 8-19. Off-State Diagnostics Table - PH/EN or PWM Mode (full-bridge)
User Inputs
OLP Set-Up
OLP CMP Output
Output
GND
Open
VM
nSLEEP DRVOFF EN/IN1 PH/IN2
OUT1
OUT2
CMP REF
Normal
selected
Short
Short
1
1
1
1
1
0
0
1
ROLP_PU
ROLP_PU
ROLP_PD
ROLP_PD
VOLP_REFH
VOLP_REFL
OUT1
OUT2
L
H
L
L
L
H
H
H
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Table 8-19. Off-State Diagnostics Table - PH/EN or PWM Mode (full-bridge) (continued)
User Inputs
OLP Set-Up
OLP CMP Output
Output
GND
VM
nSLEEP DRVOFF EN/IN1 PH/IN2
OUT1
OUT2
ROLP_PU
CMP REF
Normal
H
Open
H
selected
Short
Short
1
1
1
1
ROLP_PD
VOLP_REFL
OUT2
L
H
The OLP combinations and truth table for a no fault scenario vs. fault scenario for a low-side load in Independent
mode is shown in Table 8-20.
Table 8-20. Off-State Diagnostics Table for Low-Side Load - Independent Mode
User Inputs
OLP Set-Up
OUT2
OLP_CMP Output
Normal Open Short
DIAG S_DIAG nSLEE DRVOF
Output
EN/IN1 PH/IN2
OUT1
ROLP_PU
ROLP_PU
Hi-Z
CMP REF
VOLP_REFH
VOLP_REFL
VOLP_REFH
VOLP_REFL
pin
bits
P
F
selected
LVL2,
LVL6
don't
2'b01
1
1
1
Hi-Z
Hi-Z
OUT1
OUT1
OUT2
OUT2
L
L
L
L
H
L
H
L
H
H
H
H
care
LVL3,
LVL4
don't
2'b11
2'b01
2'b11
1
1
1
1
1
1
1
care
LVL2,
LVL6
0
0
1
1
ROLP_PD
LVL3,
LVL4
Hi-Z
ROLP_PD
The OLP combinations and truth table for a no fault scenario vs. fault scenario for a high-side load in
Independent mode is shown in Table 8-21.
Table 8-21. Off-State Diagnostics Table for High-Side Load - Independent Mode
User Inputs
OLP Set-Up
OUT2
OLP_CMP Output
Normal Open Short
DIAG S_DIAG nSLEE DRVOF
Output
EN/IN1 PH/IN2
OUT1
ROLP_PU
ROLP_PU
Hi-Z
CMP REF
VOLP_REFH
VOLP_REFL
VOLP_REFH
VOLP_REFL
pin
bits
P
F
selected
LVL2,
LVL6
don't
2'b01
1
1
1
Hi-Z
Hi-Z
OUT1
OUT1
OUT2
OUT2
H
H
H
H
H
L
H
L
L
L
L
L
care
LVL3,
LVL4
don't
2'b11
2'b01
2'b11
1
1
1
1
1
1
1
care
LVL2,
LVL6
0
0
1
1
ROLP_PD
LVL3,
LVL4
Hi-Z
ROLP_PD
Note
For the pre-production samples, it is NOT possible to differentiate between an open fault and a load
short in the Independent mode.
8.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only
•
•
Device state: ACTIVE - high-side recirculation
Mechanism and threshold: On-state diagnostics (OLA) can detect an open load detection in the ACTIVE state
during high-side recirculation. This includes high-side load connected directly to VM or through a high-side
FET on the other half-bridge. During a PWM switching transition, the inductive load current re-circulates into
VM through the HS body diode when the LS FET is turned OFF. The device looks for a voltage spike on
OUTx above VM during the brief dead time, before the HS FET is turned ON. To observe the voltage spike,
this load current needs to be higher than the pull down current (IPD_OLA) on the output asserted by the FET
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driver. Absence of this voltage spike for "3" consecutive re-circulation switching cycles indicates a loss of load
inductance or increase in load resistance and is detected as an OLA fault.
Action:
– nFAULT pin is asserted low
– Output - normal function maintained
– IPROPI pin - normal function maintained
Reaction configurable between latch setting and retry setting. In retry setting, OLA fault is automatically
cleared with the detection of "3" consecutive voltage spikes during re-circulation switching cycles.
•
•
This monitoring is optional and can be disabled.
Note
OLA is not supported for low-side loads (low-side recirculation).
VM
OLA_VREF
OUTx_OLA_CMP
D1
OUTx
IPD_OLA
D2
Figure 8-7. On-State Diagnostics
8.3.4.5 VM Over Voltage Monitor
•
•
Device state: STANDBY, ACTIVE
Mechanism & thresholds: If the supply voltage on the VM pin exceeds the threshold, set by VVMOV for a time
greater than tVMOV, then an VM over voltage fault is detected.
Action:
•
– nFAULT pin is asserted low
– Output - normal function maintained
– IPROPI pin - normal function maintained
•
Reaction configurable between retry and latch setting
In the SPI variant, this monitoring is optional and can be disabled. Also the thresholds are configurable. Refer
CONFIG1 register.
8.3.4.6 VM Under Voltage Monitor
•
•
Device state: STANDBY, ACTIVE
Mechanism & thresholds: If the supply voltage on the VM pin drops below the threshold, set by VVMUV for a
time greater than tVMUV, then an VM under voltage fault is detected.
Action:
•
– nFAULT pin is asserted low
– full-bridge is disabled
– IPROPI pin is Hi-Z
•
•
HW and SPI "S" variant: Reaction fixed to retry setting
Only for SPI "P" variant: Reaction configurable between retry and latch setting
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8.3.4.7 Power On Reset (POR)
•
•
Device state: ALL
Mechanism & thresholds: If logic supply drops below VDDPOR_FALL for a time greater than tPOR, then a power
on reset will occur that will hard reset the device.
•
Action:
– nFAULT pin is de-asserted
– full-bridge is disabled
– IPROPI pin is Hi-Z.
– When this supply recovers above the VDDPOR_RISE level, the device will go through a wake up
initialization and nFAULT pin will be asserted low to notify the user on this reset (Refer Wake-up
transients).
•
HW and SPI "S" variant: These thresholds translate to VMPOR_FALL and VMPOR_RISE as the logic supply is
internally derived from the VM supply
•
•
Only for SPI "P" variant: These thresholds directly map to the VDD pin voltage
Fault reaction: always retry
8.3.4.8 Event Priority
In the ACTIVE state, in a scenario where two or more events occur simultaneously, the device assigns control of
the driver based on the following priority table.
Table 8-22. Event Priority Table
Event
Priority
User SLEEP command
1
2
3
4
5
6
7
8
9
User input: DRVOFF
Over temperature detection (TSD)
Over current detection (OCP)(1)
VM under voltage detection (VMUV)
User input: EN/IN1 and/or PH/IN2
Internal PWM control from ITRIP regulation
VM over voltage detection (VMOV)(2)
On-state fault detection (OLA - SPI variant only)(2)
(1) If the device is waiting for an OCP event to be confirmed (waiting for tOCP) when any of events with lower priority than OCP occur, then
the device may delay servicing the other events up to a maximum time of tOCP to enable detection of the OCP event.
(2) Priority is "don't care" in this case as this fault event does not cause a change in OUTx
8.4 Device Functional States
The device has three functional states:
•
•
•
SLEEP
STANDBY
ACTIVE
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SLEEP
nFAULT = H, No communica on
1
2
2
2
ACTIVE
Protec on Enabled
nFAULT = fault
signaling
Communica on
available
STANDBY
nFAULT = H
Communica on
available
INIT2
nFAULT = L
Communica on
enabled
6
7
INIT1
nFAULT = H
5
3
4
1. nSLEEP = 1 for t > tWAKE
3. Power on reset
2. nSLEEP = 0 for t > tSLEEP
4. End of tCOM
5. CLR_FLT or HW RESET pulse from from controller & End of tREADY
6. DRVOFF = 0 & [IN1/EN IN2/PH] != [1 1], if PWM mode
7. DRVOFF = 1 or [IN1/EN IN2/PH] = [1 1], if PWM mode
Note
For pre-production samples, [IN1/EN IN2/PH] = [0 0], if PWM mode
Figure 8-8. Illustrative State Diagram
These states are described in the following section.
8.4.1 SLEEP State
This is NOT applicable for the SPI "P" variant.
This is the deep sleep low power (ISLEEP) state of the device where all functions except a wake-up command are
not serviced. The drivers are in Hi-Z. The internal power supply rails (5 V and others) are powered off. nFAULT
pin is de-asserted in this state. The device can enter this state from either the STANDBY or the ACTIVE state,
when the nSLEEP pin is asserted low for time longer than tSLEEP (HW variant) or for tSLEEP_SPI (SPI "S" variant).
8.4.2 STANDBY State
The device is in this state when nSLEEP = 1'b1 and DRVOFF = 1'b0 for all modes and additionally, in PWM
mode when both IN1/EN & IN2/PH are 1'b1 [Note: 1'b0 for pre-production samples]. In this state, the device
is powered up (ISTANDBY), with the driver Hi-Z and nFAULT de-asserted. The device is ready to transition to
ACTIVE state or SLEEP state when commanded so. Off-state diagnostics (OLP), if enabled, are done in this
state.
8.4.3 Wake-up to STANDBY State
The device starts transition from SLEEP state to STANDBY state
•
•
if the nSLEEP pin goes high for a duration longer than tWAKE, or
if VM supply pin is ramped up such that internal POR is released to indicate a power cycle wake up.
The device goes through an initialization sequence to load its internal registers and wake up all the blocks in the
following sequence:
•
At a certain time, tCOM from wake-up, the device is capable of communication. This is indicated by asserting
the nFAULT pin low.
•
•
This is followed by the time tREADY, when the device wake up is complete.
At this point, once the device receives a nSLEEP reset pulse (HW variant) or a CLR FAULT command
through SPI (SPI variant) as an acknowledgment of the wake-up from the controller, the device enters the
STANDBY state. This is indicated by the de-assertion of the nFAULT pin. The driver is held in Hi-Z till this
point.
•
From here on, the device is ready to drive the bridge based on the truth tables for the specific mode
configured.
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Refer to the wake-up transients waveforms for the illustration.
8.4.4 ACTIVE State
The device is fully functional in this state with the drivers controlled by other inputs as described in prior sections.
All protection features are fully functional with fault signaling on nFAULT pin. SPI communication is available.The
device can transition into this state only from the STANDBY state.
8.4.5 nSLEEP Reset Pulse (HW Variant Only)
This is a special communication signal from the controller to the device through the nSLEEP pin available only
for the HW variant. This is used to:
•
•
Acknowledge the nFAULT asserted during the SLEEP/ Power up transition to active state
Clear a latched fault when the fault reaction is configured to the LATCHED setting, without forcing the device
into SLEEP or effecting any of the other functions (Equivalent to the CLR_FAULT command in the SPI
variant)
This pulse on nSLEEP must be greater than the nSLEEP deglitch time of tRESET time, but shorter than tSLEEP
time. The device behavior is summarized in Table 8-23:
Table 8-23. nSLEEP Timing (HW Variant Only)
Case #
Window Start
0
Window End
tRESET min
tRESET max
tSLEEP min
tSLEEP max
No limit
Clear Faults
Sleep Command
1
2
3
4
5
No
No
No
tRESET min
tRESET max
tSLEEP min
tSLEEP max
May be
Yes
No
Yes
May be
Yes
Yes
t
SLEEP max
t
SLEEP min
tRESET max
RESET min
t
Case 1
Case 2
Case 3
Case 4
Case 5
Window 5
Window 1
Window 2
Window 3
Window 4
me
Figure 8-9. nSLEEP Pulse Scenarios
8.5 Programming - SPI Variant Only
8.5.1 SPI Interface
The SPI variant has full-duplex, 4-wire synchronous communication that is used to set device configurations,
operating parameters, and read out diagnostic information from the device. The SPI operates in peripheral mode
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and connects to a controller. The serial data input (SDI) word consists of a 16-bit word, with an 8-bit command
(A1), followed by 8-bit data (D1). The serial data output (SDO) word consists of the FAULT_SUMMARY byte
(S1), followed by a report byte (R1). The report byte is either the register data being accessed by read command
or null for a write command. The data sequence between the MCU and the SPI peripheral driver is shown in
Figure 8-10.
nSCS
A1
S1
D1
R1
SDI
SDO
Figure 8-10. SPI Data - Standard "16-bit" Frame
A valid frame must meet the following conditions:
•
•
•
SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
nSCS pin should be pulled high between words.
When nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is placed
in the Hi-Z state.
•
Data on SDO from the device is propagated on the rising edge of SCLK, while data on SDI is captured by the
device on the subsequent falling edge of SCLK.
•
•
The most significant bit (MSB) is shifted in and out first.
A full 16 SCLK cycles must occur for a valid transaction for a standard frame, or alternately, for a daisy chain
frame with "n" number of peripheral devices, 16 + (n x 16) SCLK cycles must occur for a valid transaction.
Else, a frame error (SPI_ERR) is reported and the data is ignored if it is a WRITE operation.
8.5.2 Standard Frame
The SDI input data word is 2 bytes long and consists of the following format:
•
Command byte (first byte)
– MSB bit indicates frame type (bit B15 = 0 for standard frame).
– Next to MSB bit, W0, indicates read or write operation (bit B14, write = 0, read = 1)
– Followed by 6 address bits, A[5:0] (bits B13 through B8)
•
Data byte (second byte)
– Second byte indicates data, D[7:0] (bits B7 through B0). For a read operation, these bits are typically set
to null values, while for a write operation, these bits have the data value for the addressed register.
Table 8-24. SDI - Standard Frame Format
Command Byte
Data Byte
Bit
B15
0
B14
W0
B13
A5
B12
A4
B11
A3
B10
A2
B9
A1
B8
A0
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
Data
The SDO output data word is 2 bytes long and consists of the following format:
•
Status byte (first byte)
– 2 MSB bits are forced high (B15, B14 = 1)
– Following 6 bits are from the FAULT SUMMARY register (B13:B8)
Report byte (second byte)
•
– The second byte (B7:B0) is either the data currently in the register being read for a read operation (W0 =
1), or, existing data in the register being written to for a write command (W0 = 0)
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Table 8-25. SDO - Standard Frame Format
Status Byte
Report Byte
Bit
B15
B14
1
B13
B12 B11
B10
B9
B8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
SPI_E
RR
Data
1
FAULT VMOV VMUV OCP
TSD
Note
For the pre-production samples, B8 in the above SDO format is OLA bit (not SPI_ERR as shown).
8.5.3 SPI Interface for Multiple Peripherals
Multiple devices can be connected to the controller with and without the daisy chain. For connecting a 'n' number
of devices to a controller without using a daisy chain, 'n' number of I/O resources from controller has to utilized
for nSCS pins as shown in Figure 8-11. Whereas, if the daisy chain configuration is used, then a single nSCS
line can be used for connecting multiple devices. Figure 8-12
DRV8x
DRV8x
SCLK
SDI
SCLK
SDI
Master Controller
Master Controller
SPI
Communication
SPI
Communication
SDO
nSCS
SDO
nSCS
CS1
MCLK
MO
CS
MCLK
MO
SPI
Communication
SPI
Communication
DRV8x
DRV8x
MI
MI
SCLK
SDI
SCLK
SDI
CS2
SPI
SPI
SDO
nSCS
SDO
nSCS
Communication
Communication
Figure 8-11. SPI Operation Without Daisy Chain
Figure 8-12. SPI Operation With Daisy Chain
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8.5.3.1 Daisy Chain Frame for Multiple Peripherals
The device can be connected in a daisy chain configuration to save GPIO ports when multiple devices
are communicating to the same MCU. Figure 8-13 shows the topology with waveforms, where, number of
peripherals connected in a daisy chain "n" is set to 3. A maximum of up to 63 devices can be connected in this
manner.
SDO2
SDI3
SDO3
M-SDI
M-SDO
SDI1
SDO1
SDI2
M-SDO
SDI1
SDI2
SDI2
SDO3
SDO2
SDO1
M-nSCS
M-SCLK
M-SDI
nSCS
SDI1
HDR1
HDR2
HDR1
S1
A3
A2
A1
A2
A3
D3
R1
R2
R3
D2
D3
R1
R2
D1
D2
D3
R1
SDO1
SDI2
S1
S2
S3
HDR2
HDR1
S1
A3
SDO2
SDI3
HDR2
HDR1
SDO3
S2
HDR2
All Address
Bytes Reach
Destination
All Address
Bytes Reach
Destination
Status
Response Here
Reads
Execute Here
Writes
Execute Here
Figure 8-13. Daisy Chain SPI Operation
The SDI sent by the controller in this case would be in the following format (see SDI1 in Figure 8-13 ):
•
•
•
•
2 bytes of header (HDR1, HDR2)
"n" bytes of command byte starting with furthest peripheral in the chain (for this example, this is A3, A2, A1)
"n" bytes of data byte starting with furthest peripheral in the chain (for this example, this is D3, D2, D1)
Total of 2 x "n" + 2 bytes
While the data is being transmitted through the chain, the controller receives it in the following format (see SDO3
in Figure 8-13):
•
•
•
3 bytes of status byte starting with furthest peripheral in the chain (for this example, this is S3, S2, S1)
2 bytes of header that were transmitted before (HDR1, HDR2)
3 bytes of report byte starting with furthest peripheral in the chain (for this example, this is R3, R2, R1)
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The Header bytes are special bytes asserted at the beginning of a daisy chain SPI communication. Header
bytes must start with 1 and 0 for the two leading bits.
The first header byte (HDR1) contains information of the total number of peripheral devices in the daisy chain.
N5 through N0 are 6 bits dedicated to show the number of device in the chain as shown in Figure 8-14. Up to
63 devices can be connected in series per daisy chain connection. Number of peripheral = 0 is not permitted and
will result in a SPI_ERR flag.
The second header byte (HDR2) contains a global CLR FAULT command that will clear the fault registers of
all the devices on the rising edge of the chip select (nSCS) signal. The 5 trailing bits of the HDR2 register are
marked as SPARE (don’t care bits). These can be used by the MCU to determine integrity of the daisy chain
connection.
#unique_9/unique_9_Connect_42_REG_USER_REG_USER_FAULT_SUMMARY_TABLEreferenceTitle
#unique_9/unique_9_Connect_42_REG_USER_REG_USER_COMMAND_TABLEreferenceTitle
1
0
N5
N4
N3
N2
N1
N0
HDR1
Number of Devices in the Chain (Up to 63 max)
1
0
CLR_FLT SPARE SPARE SPARE SPARE SPARE
Don’t Care
HDR2
1 = Global CLR_FAULT
0 = Don’t Care
Figure 8-14. Header bytes
In addition, the device recognizes bytes that start with 1 and 1 for the two leading bits as a "pass" byte. These
"pass" bytes are NOT processed by the device, but they are simply transmitted out on SDO in the following byte.
When data passes through a device, it determines the position of itself in the chain by counting the number of
Status bytes it receives following by the first Header byte. For example, in this 3 device configuration, device 2 in
the chain will receive two status bytes before receiving the two header bytes.
From the two status bytes it knows that its position is second in the chain, and from HDR2 byte it knows how
many devices are connected in the chain. That way it only loads the relevant address and data byte in its buffer
and bypasses the other bits. This protocol allows for faster communication without adding latency to the system
for up to 63 devices in the chain.
The command, data, status and report bytes remain the same as described in the standard frame format.
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8.6 Register Map - SPI Variant Only
This section describes the user configurable registers in the device.
Note
While the device allows register writes at any time SPI communication is available, it is recommended
to exercise caution while updating registers in the ACTIVE state while the load is being driven. This
is especially important for settings such as S_MODE and S_DIAG which control the critical device
configuration. In order to prevent accidental register writes, the device offers a locking mechanism
through the REG_LOCK bits in the COMMAND register to lock the contents of all configurable
registers. Best practice would be to write all the configurable registers during initialization and then
lock these settings. Run-time register writes for output control are handled by the SPI_IN register,
which offers its own separate locking mechanism through the SPI_IN_LOCK bits.
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8.6.1 User Registers
The following table lists all the registers that can be accessed by the user. All register addresses NOT listed in this table should be considered as
"reserved" locations and access is blocked to this space. Accessing them will cause a SPI_ERR.
Table 8-26. User Registers
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DEVICE_ID
FAULT_SUMMARY
STATUS1
DEV_ID[5]
SPI_ERR(3)
OLA1
DEV_ID[4]
POR
DEV_ID[3]
FAULT
DEV_ID[2]
VMOV
DEV_ID[1]
VMUV
DEV_ID[0]
OCP
REV_ID[1]
TSD
REV_ID[0]
OLA (3)
R
R
R
R
00h
01h
02h
03h
OLA2
ITRIP_CMP
N/A(4)
ACTIVE
ACTIVE
OCP_H1
N/A(4)
OCP_L1
N/A(4)
OCP_H2
N/A(4)
OCP_L2
OLP_CMP
STATUS2
DRVOFF_STAT
N/A(4)
SPI_IN_LOCK[0]
COMMAND
CLR_FLT
N/A(4)
N/A(4)
SPI_IN_LOCK[1]
N/A(4)
REG_LOCK[1] REG_LOCK[0] (1) R/W 08h
(1)
SPI_IN
N/A(4)
EN_OLA
N/A(4)
N/A(4)
VMOV_SEL[0]
S_DIAG[0]
N/A(4)
N/A(4)
SSC_DIS(1)
N/A(4)
S_DRVOFF (1)
OCP_RETRY
N/A(4)
S_DRVOFF2 (1)
OTD_RETRY
S_ITRIP[2]
S_EN_IN1
VMOV_RETRY
S_ITRIP[1]
S_PH_IN2
OLA_RETRY
S_ITRIP[0]
R/W 09h
R/W 0Ah
R/W 0Bh
R/W 0Ch
R/W 0Dh
CONFIG1
CONFIG2
CONFIG3
CONFIG4
VMOV_SEL[1]
S_DIAG[1]
PWM_EXTEND
TOFF[1]
TOFF[0] (1)
S_SR[2]
S_SR[1]
S_SR[0]
S_MODE[1]
EN_IN1_SEL
S_MODE[0]
PH_IN2_SEL
TOCP_SEL[1]
TOCP_SEL[0]
N/A(4)
OCP_SEL[1]
OCP_SEL[0]
DRVOFF_SEL(1)
(1) Defaulted to 1b on reset, others are defaulted to 0b on reset
(2) R = Read Only, R/W = Read/Write
(3) OLA replaced by SPI_ERR in the first SDO byte response, common to all SPI frames. Refer SDO - Standard frame format.
(4) N/A = Not available (read back of this bit will be 0b)
Note
For the pre-production samples, the register map has the following differences:
Table 8-27. Pre-Production Samples - Register Map Differences
Address
02h
Name
Bit
Pre-production samples
OLP_CMP
STATUS1
STATUS2
CONFIG4
4
03h
All
All
Not defined
0Dh
Not defined
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8.6.1.1 DEVICE_ID register (Address = 00h)
Return to the User Register table.
Device
Pre-production samples
Final Product
DRV8243S-Q1
DRV8244S-Q1
DRV8245S-Q1
DRV8243P-Q1
DRV8244P-Q1
DRV8245P-Q1
30h
40h
32h
42h
52h
36h
46h
56h
50h
Not available
Not available
Not available
8.6.1.2 FAULT_SUMMARY Register (Address = 01h) [reset = 40h]
Return to the User Register table.
Bit
7
Field
SPI_ERR
POR
Type
R
Reset
0b
Description
1b indicates that a SPI communication fault has occurred in the previous SPI frame.
1b indicates that a power-on-reset has been detected.
6
R
1b
5
FAULT
R
0b
Logic OR of SPI_ERR, POR, VMOV, VMUV, OCP, TSD & OLA
1b indicates that a VM over voltage has been detected. Refer VMOV_SEL to change
thresholds or disable diagnostic, VMOV_RETRY to configure fault reaction.
4
3
VMOV
VMUV
R
R
0b
0b
1b indicates that a VM under voltage has been detected.
1b indicates that an over current has been detected in either one or more power FETs. Refer
OCP_SEL, TOCP_SEL to change thresholds & filter times. Refer OCP_RETRY to configure
fault reaction.
2
OCP
R
0b
1b indicates that an over temperature has been detected. Refer OTD_RETRY to configure
fault reaction.
1
0
TSD
OLA
R
R
0b
0b
1b indicates that an open load condition has been detected in the ACTIVE state. Refer to
EN_OLA to disable diagnostic, OLA_RETRY to configure fault reaction.
8.6.1.3 STATUS1 Register (Address = 02h) [reset = 00h]
Return to the User Register table.
Bit
7
Field
OLA1
Type
R
Reset
0b
Description
1b indicates that an open load condition has been detected in the ACTIVE state on OUT1
1b indicates that an open load condition has been detected in the ACTIVE state on OUT2
1b indicates that load current has reached the ITRIP regulation level.
6
OLA2
R
0b
5
ITRIP_CMP
R
0b
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Bit
Field
Type
Reset
Description
1b indicates that the device is in the ACTIVE state
4
ACTIVE
R
0b
1b indicates that an over current has been detected on the high-side FET (short to GND) on
OUT1
3
2
1
0
OCP_H1
OCP_L1
OCP_H2
OCP_L2
R
R
R
R
0b
0b
0b
0b
1b indicates that an over current has been detected on the low-side FET (short to VM) on
OUT1
1b indicates that an over current has been detected on the high-side FET (short to GND) on
OUT2
1b indicates that an over current has been detected on the low-side FET (short to VM) on
OUT2
8.6.1.4 STATUS2 Register (Address = 03h) [reset = 80h]
Return to the User Register table.
Bit
Field
Type
Reset
Description
7
DRVOFF_STAT
R
1b
This bit shows the status of the DRVOFF pin. 1b implies the pin status is high.
6, 5
4
N/A
ACTIVE
N/A
R
R
R
0b
0b
0b
Not available
1b indicates that the device is in the ACTIVE state (Copy of bit4 in STATUS1)
Not available
3, 2, 1
When SPI_IN is unlocked & OLP is enabled, this bit is the output of the off-state diagnostics
(OLP) comparator.
0
OLP_CMP
R
0b
8.6.1.5 COMMAND Register (Address = 08h) [reset = 09h]
Return to the User Register table.
Bit
7
Field
CLR_FLT
N/A
Type
R/W
R
Reset
0b
Description
Clear Fault command - Write 1b to clear all faults reported in the fault registers and de-assert
the nFAULT pin
6-5
0b
Not available
Write 01b to lock the SPI_IN register (default)
Write 10b to unlock the SPI_IN register
4-3
2
SPI_IN_LOCK
N/A
R/W
R
01b
0b
00b and 11b are invalid writes and will be ignored
Not available
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Bit
Field
Type
Reset
Description
Write 01b to unlock the CONFIG registers (default)
Write 10b to lock the CONFIG registers
1-0
REG_LOCK
R/W
01b
00b and 11b are invalid writes and will be ignored
8.6.1.6 SPI_IN Register (Address = 09h) [reset = 0Ch]
Return to the User Register table.
Bit
Field
Type
Reset
Description
7-4
N/A
R
0b
Not available
Register bit equivalent of DRVOFF pin when SPI_IN is unlocked. Refer Register Pin control
section. In Independent mode, this bit shuts off half-bridge 1.
3
2
1
0
S_DRVOFF
S_DRVOFF2
S_EN_IN1
R/W
R/W
R/W
R/W
1b
1b
0b
0b
Register bit to shut off half-bridge 2 in Independent mode when SPI_IN is unlocked. Refer
Register Pin control section
Register bit equivalent of EN/IN1 pin when SPI_IN is unlocked. Refer Register Pin control
section
Register bit equivalent of PH/IN2 pin when SPI_IN is unlocked. Refer Register Pin control
section
S_PH_IN2
8.6.1.7 CONFIG1 Register (Address = 0Ah) [reset = 10h]
Return to the User Register table.
Bit
Field
Type
Reset
Description
Write 1b to enable open load detection in the active state. In Independent mode, OLA is
always disabled for low-side load. Refer DIAG section.
7
EN_OLA
R/W
0b
Determines the thresholds for the VM over voltage diagnostics
00b = VM > 35 V
01b = VM > 28 V
10b = VM > 18 V
11b = VMOV disabled
6-5
VMOV_SEL
R/W
0b
4
3
SSC_DIS
R/W
R/W
1b
0b
0b: Enables the spread spectrum clocking feature
Write 1b to configure fault reaction to retry setting on the detection of over current, else the
fault reaction is latched
OCP_RETRY
Write 1b to configure fault reaction to retry setting on the detection of over temperature, else
the fault reaction is latched
2
OTD_RETRY
R/W
0b
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Bit
Field
Type
Reset
Description
Write 1b to configure fault reaction to retry setting on the detection of VMOV, else the fault
reaction is latched.
Note
For the SPI "P" variant, this bit also controls the fault reaction for a VM under
voltage detection.
1
0
VMOV_RETRY
R/W
0b
Write 1b to configure fault reaction to retry setting on the detection of open load during active,
else the fault reaction is latched.
OLA_RETRY
R/W
0b
8.6.1.8 CONFIG2 Register (Address = 0Bh) [reset = 00h]
Return to the User Register table.
Bit
Field
Type
Reset
Description
Write 1b to access additional Hi-Z (coast) states in the PWM mode - refer PWM EXTEND
table
7
PWM_EXTEND
R/W
0b
6-5
4-3
2-0
S_DIAG
N/A
R/W
R
0b
0b
0b
Load type indication - refer to DIAG table
Not available
S_ITRIP
R/W
ITRIP level configuration - refer ITRIP table
8.6.1.9 CONFIG3 Register (Address = 0Ch) [reset = 40h]
Return to the User Register table.
Bit
Field
Type
Reset
Description
TOFF time used for ITRIP current regulation
00b = 20 µsec
01b = 30 µsec
10b = 40 µsec
11b = 50 µsec
7-6
TOFF
R/W
1b
5
N/A
R
0b
0b
0b
Not available
4-2
1-0
S_SR
R/W
R/W
Slew Rate configuration - refer to Section 8.3.3.1
Device mode configuration - refer MODE table
S_MODE
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8.6.1.10 CONFIG4 Register (Address = 0Dh) [reset = 04h]
Return to the User Register table.
Bit
Field
Type
Reset
Description
Filter time for over current detection configuration
00b = 6 µsec
01b = 3 µsec
7-6
TOCP_SEL
R/W
0b
10b = 1.5 µsec
11b = Minimum (~0.2 µsec)
5
N/A
R
0b
0b
Not available
Threshold for over current detection configuration
00b = 100% setting
01b = 50% setting
4-3
OCP_SEL
R/W
10b, 11b = 75% setting
DRVOFF pin - register logic combination, when SPI_IN is unlocked
0b = OR
2
1
0
DRVOFF_SEL
EN_IN1_SEL
PH_IN2_SEL
R/W
R/W
R/W
1b
0b
0b
1b = AND
EN/IN1 pin - register logic combination, when SPI_IN is unlocked
0b = OR
1b = AND
PH/IN2 pin - register logic combination, when SPI_IN is unlocked
0b = OR
1b = AND
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The DRV824x-Q1 family of devices can be used in a variety of applications that require either a half-bridge
or H-bridge power stage configuration. Common application examples include brushed DC motors, solenoids,
and actuators. The device can also be utilized to drive many common passive loads such as LEDs, resistive
elements, relays, etc. The application examples below will highlight how to use the device in bidirectional current
control applications requiring an H-bridge driver and dual unidirectional current control applications requiring two
half-bridge drivers.
9.1.1 Load Summary
Table 9-1 summarizes the utility of the device features for different type of inductive loads.
Table 9-1. Load Summary Table
Configuration
Device Feature
LOAD TYPE
Recirculation
Path
Device
Slew Rate
Current sense ITRIP regulation
Bi-directional motor or
solenoid(1)
DRV824x in PH/EN or PWM
mode
High-side
Low-side
High-side
Full range
Continuous
Useful
2 Uni-directional motors or
low-side solenoids (one side
connected to GND)
Individual load
regulation not
possible
DRV824x in Independent
mode (2)
Limited(4)
Full range
Discontinuous(3)
,
2 High-side solenoids (one
side connected to VM)
DRV824x in Independent
mode (2)
Not available, need external solution
(1) Solenoid - clamping or quick demagnetization possible, but clamping level will be VM dependent
(2) Independent Hi-Z only supported in the SPI variant
(3) Not sensed during recirculation and during OUTx voltage slew times including tblank
(4) Rising edge slew rate capped at 8 V/µsec for higher settings
VM
nFAULT
IPROPI
to Controller ADC
SPI (Opt)
DRVOFF
Controller I/Os
(can be shared)
DRV824X
Applicable for
PWM or
PH/EN
mode
BDC
solenoid
nSLEEP
OUT1
EN/IN1
PH/IN2
LOAD
to Controller I/O
OUT2
GND
Figure 9-1. Illustration Showing a Full-Bridge Topology With DRV824X-Q1 in PWM or PH/EN Mode
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VM
nFAULT
to Controller ADC
IPROPI
SPI (Opt)
DRVOFF
Controller I/Os
(can be shared)
Summing current
Applicable for
DRV824X
BDC
solenoid
Independent
mode
nSLEEP
OUT1
LOAD
EN/IN1
PH/IN2
to Controller I/O
OUT2
LOAD
GND
Figure 9-2. Illustration Showing Half-Bridge Topology to Drive Two Low-side Loads Independently With
DRV824X-Q1 Device in INDEPENDENT Mode
VM
VM
nFAULT
HS Switch for
clamping
(OPT)
IPROPI
Not useful
to Controller I/O
SPI (Opt)
DRVOFF
Controller I/Os
(can be shared)
DRV824X
Independent
mode
nSLEEP
OUT1
OUT2
solenoid
solenoid
EN/IN1
PH/IN2
to Controller I/O
GND
Figure 9-3. Illustration Showing a Half-Bridge Topology to Drive Two High-side Loads Independently With
DRV824X-Q1 Device in INDEPENDENT Mode
9.2 Typical Application
The figures below show the typical application schematic for driving a brushed DC motor or any inductive load in
various modes. There are several optional connections shown in these schematics, which are listed as follows:
•
SPI "S" variant - the nSLEEP pin can be tied off high in the application if SLEEP function is not needed (not
relevant for the "P" variant). For the HW variant, the nSLEEP pin control is needed to issue a reset pulse
during wake-up as well as to modify and latch any changes with MODE, DIAG, SR, and ITRIP.
SPI variant - the DRVOFF pin can be tied off low in the application if DRVOFF pin function is not needed.
SPI variant - EN/IN1 pin can be tied off low or left floating if register only control is needed.
SPI variant - the PH/IN2 pin can be tied off low or left floating if register only control is needed.
IPROPI pin monitoring is optional. Also IPROPI pin can be tied low if ITRIP feature & IPROPI function is not
needed.
•
•
•
•
•
SPI variant - the nFAULT pin monitoring is optional. All diagnostic information can be read from the STATUS
registers.
•
HW variant - Resistor on CONFIG pins is not needed for two selections - tie off to GND and Hi-Z.
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9.2.1 HW Variant
VCC
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VCC
Reverse Supply
Protected Input
Reverse Supply
Protected Input
SSOP HW
SSOP HW
24
5
6,7,8,21,22,23
24
5
6,7,8,21,22,23
I/O
nSLEEP
VM
I/O
I/O
I/O
I/O
nSLEEP
VM
CVM2
CVM2
I/O
I/O
DRVOFF
CVM1
DRVOFF
EN/IN1
PH/IN2
IPROPI
CVM1
4
3
4
EN/IN1
PH/IN2
IPROPI
nFAULT
MODE
DIAG
3
18,19,20
18,19,20
OUT2
LOAD
I/O
OUT2
25
26
27
2
Op onal (5)
25
Op onal (5)
RIPROPI
ADC
I/O
ADC
I/O
RIPROPI
VCC
RnFAULT
VM / GND
VCC
RnFAULT
26
27
nFAULT
MODE
9,10,11
9,10,11
LOAD
OUT1
GND
OUT1
GND
RMODE
RDIAG
RITRIP
RSR
RMODE
2
28
1
DIAG
ITRIP
SR
RDIAG
RITRIP
RSR
12,13,14,
15,16,17
12,13,14,
15,16,17
28
1
ITRIP
SR
HS/ LS load in Independent mode
FB with PH/EN or PWM mode
Figure 9-4. Typical Application Schematic - HW Variant in HVSSOP Package
VCC
VCC
VQFN-HR HW
VQFN-HR HW
Reverse Supply
Protected Input
Reverse Supply
Protected Input
3
8
4
3
8
4
I/O
I/O
nSLEEP
DRVOFF
EN/IN1
PH/IN2
IPROPI
nFAULT
MODE
DIAG
VM
I/O
I/O
nSLEEP
DRVOFF
EN/IN1
VM
CVM2
CVM2
CVM1
CVM1
9
9
I/O
I/O
5
10
2
5
10
2
OUT2
I/O
LOAD
OUT2
I/O
PH/IN2
Op onal (5)
RIPROPI
Op onal (5)
ADC
I/O
ADC
I/O
IPROPI
VCC
RnFAULT
RIPROPI
VM / GND
VCC
RnFAULT
1
1
nFAULT
MODE
DIAG
ITRIP
SR
14
11
13
12
7
6
14
11
13
12
7
6
OUT1
GND
LOAD
OUT1
GND
RMODE
RMODE
RDIAG
RITRIP
RSR
RDIAG
RITRIP
RSR
ITRIP
SR
HS/ LS load in Independent mode
FB with PH/EN or PWM mode
Figure 9-5. Typical Application Schematic - HW Variant in VQFN-HR Package
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9.2.2 SPI Variant
VCC
VCC
Reverse Supply
Protected Input
Reverse Supply
Protected Input
SSOP SPI
SSOP SPI
24
5
6,7,8,21,22,23
Op onal (1)
Op onal (2)
Op onal (3)
Op onal (4)
Op onal (5)
24
5
6,7,8,21,22,23
Op onal (1)
I/O
nSLEEP
VM
I/O
I/O
nSLEEP
VM
CVM2
Op onal (2)
Op onal (3)
Op onal (4)
Op onal (5)
CVM2
I/O
I/O
DRVOFF
EN/IN1
PH/IN2
IPROPI
nFAULT
SDO
CVM1
DRVOFF
EN/IN1
PH/IN2
IPROPI
nFAULT
SDO
CVM1
4
4
I/O
3
3
18,19,20
18,19,20
OUT2
I/O
LOAD
OUT2
I/O
25
26
27
2
25
26
27
2
ADC
I/O
ADC
I/O
RIPROPI
VCC
RnFAULT
RIPROPI
VM / GND
VCC
RnFAULT
Op onal (6)
Op onal (6)
9,10,11
9,10,11
OUT1
GND
LOAD
OUT1
GND
S
P
I
nSCS
S
P
I
nSCS
12,13,14,
15,16,17
12,13,14,
15,16,17
28
1
28
1
SDI
SDI
SCLK
SCLK
HS/ LS load in Independent mode
FB with PH/EN or PWM mode
Figure 9-6. Typical Application Schematic - SPI "S" Variant in HVSSOP Package
VCC
VCC
Reverse Supply
Protected Input
Reverse Supply
Protected Input
SSOP SPI
SSOP SPI
24
6,7,8,21,22,23
24
5
6,7,8,21,22,23
Logic Supply
VDD
Logic Supply
Op onal (2)
VM
VDD
VM
5
4
CVM2
Op onal (2)
CVM2
I/O
I/O
DRVOFF
EN/IN1
PH/IN2
IPROPI
nFAULT
SDO
CVM1
I/O
I/O
DRVOFF
EN/IN1
PH/IN2
IPROPI
nFAULT
SDO
CVM1
Op onal (3)
Op onal (4)
Op onal (5)
4
Op onal (3)
Op onal (4)
Op onal (5)
3
3
18,19,20
18,19,20
OUT2
I/O
LOAD
OUT2
I/O
25
26
27
2
25
26
27
2
ADC
I/O
ADC
I/O
RIPROPI
VCC
RnFAULT
RIPROPI
VM / GND
VCC
RnFAULT
Op onal (6)
Op onal (6)
9,10,11
9,10,11
OUT1
GND
LOAD
OUT1
GND
S
P
I
nSCS
SDI
S
P
I
nSCS
SDI
12,13,14,
15,16,17
12,13,14,
15,16,17
28
1
28
1
SCLK
SCLK
HS/ LS load in Independent mode
FB with PH/EN or PWM mode
Figure 9-7. Typical Application Schematic - SPI "P" Variant in HVSSOP Package
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VCC
VCC
VQFN-HR SPI
VQFN-HR SPI
Reverse Supply
Protected Input
Reverse Supply
Protected Input
3
8
4
Op onal (1)
Op onal (2)
Op onal (3)
Op onal (4)
Op onal (5)
3
8
4
Op onal (1)
Op onal (2)
Op onal (3)
Op onal (4)
Op onal (5)
I/O
nSLEEP
DRVOFF
EN/IN1
PH/IN2
IPROPI
nFAULT
SDO
VM
I/O
nSLEEP
DRVOFF
EN/IN1
PH/IN2
IPROPI
nFAULT
SDO
VM
CVM2
CVM2
I/O
I/O
CVM1
I/O
I/O
CVM1
9
9
5
10
2
5
10
2
OUT2
I/O
LOAD
OUT2
I/O
ADC
I/O
ADC
I/O
RIPROPI
VCC
RnFAULT
RIPROPI
VM / GND
VCC
RnFAULT
1
1
Op onal (6)
Op onal (6)
14
11
13
12
7
6
14
11
13
12
7
6
OUT1
GND
LOAD
OUT1
GND
S
P
I
nSCS
S
P
I
nSCS
SDI
SDI
SCLK
SCLK
HS/ LS load in Independent mode
FB with PH/EN or PWM mode
Figure 9-8. Typical Application Schematic - SPI "S" Variant in VQFN-HR Package
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10 Power Supply Recommendations
The device is designed to operate with an input voltage supply (VM) range from 4.5 V to 40 V. A 0.1-µF ceramic
capacitor rated for VM must be placed as close to the device as possible. Also, an appropriately sized bulk
capacitor must be placed on the VM pin.
10.1 Bulk Capacitance Sizing
Bulk capacitance sizing is an important factor in motor drive system design. It is beneficial to have more bulk
capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors including:
•
•
•
•
•
•
The highest current required by the motor system.
The capacitance of the power supply and the ability of the power supply to source current.
The amount of parasitic inductance between the power supply and motor system.
The acceptable voltage ripple.
The type of motor used (brushed DC, brushless DC, and stepper).
The motor braking method.
The inductance between the power supply and motor drive system limits the rate that current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When sufficient bulk capacitance is used, the motor voltage
remains stable, and high current can be quickly supplied.
The data sheet provides a recommended value, but system-level testing is required to determine the appropriate
sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
œ
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 10-1. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage to provide a margin for cases
when the motor transfers energy to the supply.
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11 Layout
11.1 Layout Guidelines
Each VM pin must be bypassed to ground using low-ESR ceramic bypass capacitors with recommended values
of 0.1 μF rated for VM. These capacitors should be placed as close to the VM pins as possible with a thick trace
or ground plane connection to the device GND pin.
Additional bulk capacitance is required to bypass the high current path. This bulk capacitance should be placed
such that it minimizes the length of any high current paths. The connecting metal traces should be as wide as
possible, with numerous vias connecting PCB layers. These practices minimize inductance and allow the bulk
capacitor to deliver high current.
For the SPI "P" device variant, VDD pin may be bypassed to ground using low-ESR ceramic 6.3 V bypass
capacitor with recommended values of 0.1 μF.
11.2 Layout Example
The following figure shows a layout example for a 4 cm X 4 cm x 1.6 mm, 4 layer PCB for a leaded package
device. The 4 layers uses 2 oz copper on top/ bottom signal layers and 1 oz copper on internal supply layers,
with 0.3 mm thermal via drill diameter, 0.025 mm Cu plating, 1 mm minimum via pitch. The same layout can be
adopted for the non-leaded VQFN-HR package as well. The Section 7.5.14 for the 4 cm X 4 cm X 1.6 mm is
based on a similar layout.
Note: The layout example shown is for a full bridge topology using DRV824xQ1 device in SSOP package.
Figure 11-1. Layout example: 4cm x 4 cm x 1.6mm, 4 layer PCB
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
•
•
Texas Instruments, Full Bridge Driver Junction Temperature Estimator (Excel-based worksheet)
Texas Instruments, Calculating Motor Driver Power Dissipation application report
Texas Instruments, Current Recirculation and Decay Modes application report
Texas Instruments, PowerPAD™ Made Easy application report
Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
Texas Instruments, Understanding Motor Driver Current Ratings application report
Texas Instruments, Best Practices for Board Layout of Motor Drivers application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
12.4 Trademarks
All trademarks are the property of their respective owners.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and order-able information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Figure 13-1. DGQ28A: HVSSOP(28) Package Drawing
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PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RXY0014A
A
3.1
2.9
B
0.100 MIN
PIN 1 INDEX AREA
4.6
4.4
(0.130)
SECTION A-A
TYPICAL
C
1 MAX
.05
.00
0.08
C
3.1
2.9
2X
1.475
1.275
2X
(0.2) TYP
1.2
1.0
(0.15) TYP
6X (0.4) TYP
6
1.35
0.65
(0.16)
A
0.3
10X
0.2
7
0.1
C
B
0.05
C
PKG
0
0.05
0.625
1.125
1.625
0.3
10X
0.2
0.1
0.05
C
A B
10
1
C
PIN1 ID
(OPTIONAL)
14
11
0.5
0.3
10X
4226096/A 08/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
RXY0014A
PLASTIC QUAD FLATPACK- NO LEAD
14
11
10X (0.6)
(2.15)
1
(1.625)
(R0.05) TYP
10
10X (0.25)
(1.125)
(0.625)
(0.05)
6X (0.4) TYP
6X (0.25)
PKG
(0)
(0.65)
7
(0.35) TYP
6
(1.35)
(1.8)
(1.3)
SOLDER MASK
OPENING
4X
(0.25)
METAL UNDER
SOLDER MASK
2X (1.575)
2X (3.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 18X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4226096/A 08/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271)
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
.
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EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RXY0014A
4X (1.6)
14
11
10X (0.6)
(2.15)
1
(1.625)
(R0.05) TYP
10
10X (0.25)
(1.125)
(0.2)
TYP
(0.625)
(0.05)
6X (0.4) TYP
6X (0.25)
PKG
(0)
(0.65)
7
(0.35) TYP
6
(1.35)
(0.2)
4X (0.7)
(2.1)
4X
(0.25)
METAL UNDER
SOLDER MASK
2X (1.575)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 18X
4226096/A 08/2020
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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Figure 13-2. RXY0014A: VQFN-HR(14) Package Drawing
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13.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Device
Package Package Pins
Type Drawing
SPQ
Reel
Width
W1 (mm)
A0
B0
K0
P1
W
Reel
Pin 1
Diameter
(mm)
Quadrant
PDRV82 HVSSOP DGQ
43SDGQ
Q1
28
28
14
14
14
14
28
28
3000
3000
5000
5000
5000
5000
3000
3000
PDRV82 HVSSOP DGQ
43HDGQ
Q1
PDRV82 VQFN-
43SRXY HR
Q1
RXY
RXY
RXY
RXY
180
180
180
180
12.4
12.4
12.4
12.4
2.45
2.45
2.45
2.45
2.75
2.75
2.75
2.75
1.2
1.2
1.2
1.2
4
4
4
4
12
12
12
12
Q1
Q1
Q1
Q1
PDRV82 VQFN-
43HRXY HR
Q1
DRV824 VQFN-
3SQRXY HR
RQ1
DRV824 VQFN-
3HQRXY HR
RQ1
DRV824 HVSSOP DGQ
3SQDG
QRQ1
DRV824 HVSSOP DGQ
3HQDG
QRQ1
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Type
Pins
SPQ
PDRV8243SDGQQ1
HVSSOP
DGQ
28
3000
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Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
PDRV8243HDGQQ1
PDRV8243SRXYQ1
PDRV8243HRXYQ1
HVSSOP
VQFN-HR
VQFN-HR
DGQ
RYJ
RYJ
RYJ
RYJ
DGQ
DGQ
28
14
14
14
14
28
28
3000
5000
5000
5000
5000
3000
3000
180
180
180
180
12.4
12.4
12.4
12.4
2.45
2.45
2.45
2.45
2.75
2.75
2.75
2.75
1.2
1.2
1.2
1.2
4
4
4
4
12
12
12
12
Q1
Q1
Q1
Q1
DRV8243SQRXYRQ1 VQFN-HR
DRV8243HQRXYRQ1 VQFN-HR
DRV8243SQDGQRQ1
HVSSOP
DRV8243HQDGQRQ1 HVSSOP
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
HVSSOP
Package Drawing Pins
SPQ
Length (mm) Width (mm)
Height (mm)
PDRV8243SDGQQ1
PDRV8243HDGQQ1
PDRV8243SRXYQ1
PDRV8243HRXYQ1
DRV8243SQRXYRQ1
DRV8243HQRXYRQ1
DRV8243SQDGQRQ1
DRV8243HQDGQRQ1
DGQ
DGQ
RYJ
28
28
14
14
14
14
28
28
3000
3000
5000
5000
5000
5000
3000
3000
552
552
210
210
210
210
552
552
154
154
185
185
185
185
154
154
36
36
35
35
35
35
36
36
HVSSOP
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
HVSSOP
RYJ
RYJ
RYJ
DGQ
DGQ
HVSSOP
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PDRV8243HRXYQ1
PDRV8243SDGQQ1
ACTIVE
ACTIVE
VQFN-HR
HVSSOP
RXY
14
28
5000
1
TBD
TBD
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
DGQ
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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7-Oct-2021
Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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