DRV104PWPG4 [TI]
PWM High-Side Driver (1.5A) for Solenoids, Coils, Valves, Heaters, and Lamps 14-HTSSOP -40 to 85;
| 型号： | DRV104PWPG4 |
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TEXAS INSTRUMENTS |
| 描述： | PWM High-Side Driver (1.5A) for Solenoids, Coils, Valves, Heaters, and Lamps 14-HTSSOP -40 to 85 驱动 光电二极管 接口集成电路 驱动器 |
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DRV104
®
D
R
V
1
0
4
SBVS036B – SEPTEMBER 2003 – REVISED MARCH 2006
1.2A PWM High-Side Driver
for Solenoids, Coils, Valves, Heaters, and Lamps
DESCRIPTION
FEATURES
● HIGH OUTPUT DRIVE: 1.2A
The DRV104 is a DMOS, high-side power switch employing
a pulse-width modulated (PWM) output. Its rugged design is
optimized for driving electromechanical devices such as
valves, solenoids, relays, actuators, and positioners. It is also
ideal for driving thermal devices such as heaters, coolers,
and lamps. PWM operation conserves power and reduces
heat rise, resulting in higher reliability. In addition, adjustable
PWM allows fine control of the power delivered to the load.
Time from dc-to-PWM output and oscillator frequency are
externally adjustable.
● WIDE SUPPLY RANGE: +8V to +32V
● COMPLETE FUNCTION:
PWM Output
Adjustable Internal Oscillator: 500Hz to 100kHz
Digitally Controlled Input
Adjustable Delay and Duty Cycle
Over-Current Indicator Flag
● FULLY PROTECTED:
Thermal Shutdown with Indicator Flag
Internal Current Limit
Separate supply pins for the circuit and driver transistor allow
the output to operate on a different supply than the rest of the
circuit.
● PACKAGE: HTSSOP-14 Surface-Mount PowerPAD™
The DRV104 can be set to provide a strong initial solenoid
closure, automatically switching to a soft hold mode for
power savings. The duty cycle can be controlled by a
resistor, analog voltage, or a digital-to-analog (D/A) converter
for versatility. The Status OK Flag pin indicates when thermal
shutdown or over-current occurs.
APPLICATIONS
● ELECTROMECHANICAL DRIVERS:
Solenoids, Valves, Positioners, Actuators, Relays,
Power Contactor Coils, Heaters, and Lamps
● FLUID AND GAS FLOW SYSTEMS
● FACTORY AUTOMATION
The DRV104 is specified for –40°C to +85°C at its case. The
exposed lead frame must be soldered to the circuit board.
● PART HANDLERS AND SORTERS
● PHOTOGRAPHIC PROCESSING
● ENVIRONMENTAL MONITORING AND HVAC
● THERMOELECTRIC COOLERS
● MOTOR SPEED CONTROLS
Status OK
Flag
+VS
DRV104
Thermal Shutdown
Over/Under Current
● SOLENOID PROTECTORS
● MEDICAL ANALYZERS
+VPS1
+VPS2
VREF
Oscillator
PWM
Input
Off
OUT1
OUT2
On
Delay
Delay
Adj
Osc Freq
Adj
Duty Cycle
Adj
GND
Coil
BOOT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2003-2006, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Supply Voltage VS, VPS1, VPS2(2) ....................................................... +40V
Input Voltage, Master, SYNC ......................................... –0.2V to +5.5V(3)
PWM Adjust Input .......................................................... –0.2V to +5.5V(3)
Delay Adjust Input .......................................................... –0.2V to +5.5V(3)
Frequency Adjust Input .................................................. –0.2V to +5.5V(3)
(4)
Status OK Flag and OUT .................................................... –0.2V to VS
Boot Voltage ............................................................................... VS + 10V
Operating Temperature Range ...................................... –55°C to +125°C
Storage Temperature .....................................................–65°C to +150°C
Junction Temperature .................................................................... +150°C
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTES: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may de-
grade device reliability. (2) See the Bypass section for discussion about
operating near the maximum supply. (3) Higher voltage may be applied if
current is limited to 2mA. (4) Status OK flag will internally current limit at
about 10mA.
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
DRV104
PowerPAD HTSSOP-14
PWP
–40°C to +85°C
DRV104
DRV104PWP
Rails, 90
"
"
"
"
"
DRV104PWPR
Tape and Reel, 2000
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this document, or see the TI web site
at www.ti.com.
LOGIC BLOCK DIAGRAM
Status OK
+VS
10
Flag
13
DRV104
Thermal Shutdown
Over Current
DMOS
4
Master
SYNC
8
9
12
+VPS1
+VPS2
1.25V VREF
Oscillator
PWM
DMOS
14
Input
Off
OUT1
6
7
On
Delay
2.75 • IREF
IREF
OUT2
2
3
Osc Freq
Adj
RFREQ
1
11
GND
5
Delay
Adj
CD
Duty Cycle
Adj
Coil
CBOOT
RPWM
DRV104
2
SBVS036B
www.ti.com
ELECTRICAL CHARACTERISTICS
At TC = +25°C, VS = VPS = +24V, Load = 100Ω, 4.99kΩ Status OK flag pull-up to +5V, Boot capacitor = 470pF, Delay Adj Capacitor (CD) = 100pF to GND, Osc
Freq Adj Resistor = 191kΩ to GND, Duty Cycle Adj Resistor = 147kΩ to GND, and Master and SYNC open, unless otherwise noted.
DRV104
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUT
Output Saturation Voltage, Source
IO = 1A
IO = 0.1A
+0.45
+0.05
2.0
+0.65
+0.07
2.6
V
V
A
Current Limit(1)(7)
Leakage Current
1.2
DMOS Output Off, VPS = VS = 32V
DC to PWM Mode
1
10
µA
DELAY TO PWM(3)
Delay Equation(4)
Delay Time
Delay to PWM ≈ CD • 106(CD in F • 1.24)
s
ms
µs
CD = 0.1µF
CD = 0
60
80
18
100
Minimum Delay Time(5)
DUTY CYCLE ADJUST
Duty Cycle Range
Duty Cycle Accuracy
vs Supply Voltage
Nonlinearity(6)
10 to 90
%
%
%
50% Duty Cycle, 25kHz
50% Duty Cycle, VS = VPS = 8V to 32V
10% to 90% Duty Cycle
±2
±2
1
±5
% FSR
DYNAMIC RESPONSE
Output Voltage Rise Time
Output Voltage Fall Time
SYNC Output Rise Time
SYNC Output Fall Time
Oscillator Frequency Range
Oscillator Frequency Accuracy
VO = 10% to 90% of VPS
VO = 90% to 10% of VPS
VSYNC = 10% to 90%
VSYNC = 10% to 90%
External Adjust
1
0.2
0.5
2
2
2
2
µs
µs
µs
µs
kHz
kHz
0.5
0.5 to 100
25
RFREQ = 191kΩ
20
30
STATUS OK FLAG
Normal Operation
Fault(7)
20kΩ Pull-Up to +5V
4.99kΩ Pull-Up to +5V
+4.5
+5
+0.45
5
V
V
µs
+0.6
Over-Current Flag: Set—Delay
INPUT(2)
VINPUT Low
VINPUT High
IINPUT Low (output disabled)
IINPUT High (output enabled)
Propagation Delay
(master mode)
0
+2.2
+1.2
+5.5
1
V
V
µA
µA
µs
µs
VINPUT = 0V
VINPUT = +4.5V
On to Off and Off to On, INPUT to OUT
On to Off and Off to On, INPUT to SYNC
0.01
0.01
2.2
1
0.4
MASTER INPUT
VMSTR Low
VMSTR High
IMSTR Low (slave mode)
IMSTR High (master mode)
0
+2.2
+1.2
+5.5
25
V
V
µA
µA
VINPUT = 0V
VINPUT = +4.5V
15
15
25
SYNC INPUT
VSYNC Low
VSYNC High
IMSTR Low (OUT disabled in slave mode)
IMSTR High (OUT disabled in slave mode)
Propagation Delay
0
+2.2
+1.2
+5.5
1
V
V
µA
µA
µs
VINPUT = 0V
VINPUT = +4.5V
On to Off and Off to On, SYNC to OUT (slave)
0.01
0.01
2.2
1
SYNC OUTPUT(9)
VOL Sync
VOH Sync
ISYNC = 100µA (sinking)
ISYNC = 100µA (sourcing)
0.1
+4.2
0.3
V
V
+4.0
THERMAL SHUTDOWN
Junction Temperature
Shutdown
+160
+140
°C
°C
Reset from Shutdown
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Quiescent Current (VS)
+24
0.6
V
V
mA
+8
+32
1
IO = 0
TEMPERATURE RANGE
Specified Range
–40
–55
–65
+85
+125
+150
°C
°C
°C
Operating Range
Storage Range
(8)
Thermal Resistance, θJA
HTSSOP-14 with PowerPAD
37.5
°C/W
NOTES: (1) Output current resets to zero when current limit is reached. (2) Logic high enables output (normal operation). (3) Constant dc output to PWM (Pulse-
Width Modulated) time. (4) Maximum delay is determined by an external capacitor. Pulling the Delay Adjust Pin low corresponds to an infinite (continuous) delay.
(5) Connecting the Delay Adjust pin to +5V reduces delay time to 3µs. (6) VIN at pin 1 to percent of duty cycle at pins 6 and 7. (7) Flag indicates fault from over-
temperature or over-current conditions. (8) θJA = 37.5°C/W measured on JEDEC standard test board. θJC = 2.07°C/W. (9) SYNC output follows power output in
master mode. Power output follows SYNC input in slave mode.
DRV104
SBVS036B
3
www.ti.com
PIN CONFIGURATION
Top View
HTSSOP
Top View
SO
Duty Cycle Adj
Delay Adj
1
3
5
7
14 Input
Duty Cycle Adj
Delay Adj
Osc Freq Adj
Master
1
2
3
4
5
6
7
14 Input
13 Status OK Flag
12 SYNC
12 Status OK Flag
10 +VS
DRV103
PowerPAD
DRV104
PowerPAD
11 GND
Osc Freq Adj
GND
Boot
10 +VS
OUT1
9
8
VPS
1
8
OUT
OUT2
V
PS2
DRV103 for Reference
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
1
Duty Cycle Adjust Internally, this pin connects to the input of a comparator and a (2.75 x IREF) current source from VS. The voltage at this node linearly
sets the duty cycle. The duty cycle can be programmed with a resistor, analog voltage, or the voltage output of a D/A converter. The
active voltage range is from 1.3V to 3.9V to facilitate the use of single-supply control electronics. At 3.56V, the output duty cycle is
near 90%. At 1.5V, the output duty cycle is near 10%. Internally, this pin is forced to 1.24V. No connection is required when the device
is in slave mode.
2
3
Delay Adjust
This pin sets the duration of the initial 100% duty cycle before the output goes into PWM mode. Leaving this pin floating results in
a delay of approximately 18µs, which is internally limited by parasitic capacitance. Minimum delay may be reduced to less than 3µs
by tying the pin to 5V. This pin connects internally to a 15µA current source from VS and to a 2.6V threshold comparator. When the
pin voltage is below 2.6V, the output device is 100% On. The PWM oscillator is not synchronized to the Input (pin 1), so the duration
of the first pulse may be any portion of the programmed duty cycle. No connection is required when the device is in slave mode.
Oscillator
PWM frequency is adjustable. A resistor to ground sets the current IREF and the internal PWM oscillator frequency. A range of 500Hz
Frequency Adjust to 100kHz can be achieved with practical resistor values. Although oscillator frequency operation below 500Hz is possible, resistors
higher than 10MΩ will be required. The pin then becomes a very high-impedance node and is, therefore, sensitive to noise pickup
and PCB leakage currents. Resistor connection to this pin in slave mode sets the frequency at which current limit reset occurs.
4
5
Master
With no connection, this pin is driven to 5V by an internal 15µA current source. In this mode the device is the master and the SYNC
pin becomes a 0V to 4.2V output, which is High when the power device is on. When the Master/Input is 0V, the SYNC pin is an
input. In slave mode, the output follows the SYNC pin; the output is High when SYNC is High.
BOOT
The bootstrap capacitor between this pin and the output, supplies the charge to provide the VGS necessary to turn on the power
device. CBOOT should be larger than 100pF. Use of a smaller CBOOT may slow the output rise time, device is specified and tested
with 470pF.
6, 7
OUT1, OUT2
The output is the source of a power DMOS transistor with its drain connected to VPS. Its low on-resistance (0.45Ω typ) assures
low power dissipation in the DRV104. Gate drive to the power device is controlled to provide a slew-rate limited rise-and-fall time.
This reduces the radiated RFI/EMI noise. A flyback diode is needed with inductive loads to conduct the load current during the off
cycle. The external diode should be selected for low forward voltage and low storage time. The internal diode should not be used
as a flyback diode. If devices are connected in parallel, the outputs must be connected through individual diodes. Devices are
current-limit protected for shorts to ground, but not to supply.
8, 9
VPS1, VPS
2
These are the load power-supply pins to the drain of the power device. The load supply voltage may exceed the voltage at pin 10
by 5V, but must not exceed 37V.
10
11
+VS
This is the power-supply connection for all but the drain of the power device. The operating range is 8V to 32V.
GND
This pin must be connected to the system ground for the DRV104 to function. It does not carry the load current when the power
DMOS device is switched on.
12
SYNC
The SYNC pin is a 0V to 4.2V copy of the output when the Master/Slave pin is High. As an output, it can supply 100µA with 1kΩ
output resistance. At 2mA, it current limits to either 4.2V or 0V. When the Master pin is Low, it is an input and the threshold is 2V.
SYNC output follows power output in master mode, and is not affected by thermal or current-limit shutdown. Power output follows
SYNC input in slave mode.
13
14
Status OK Flag
Input
Normally High (active Low), a Flag Low signals either an over-temperature or over-current fault. A thermal fault (thermal shutdown)
occurs when the die surface reaches approximately 160°C and latches until the die cools to 140°C. This output requires a pull-
up resistor and it can typically sink 2mA, sufficient to drive a low-current LED. Sink current is internally limited at 10mA, typical.
The input is compatible with standard TTL levels. The device becomes enabled when the input voltage is driven above the typical
switching threshold, 1.8V; below this level, the device is disabled. Input current is typically 1µA when driven High and 1µA when driven
Low. The input should not be directly connected to the power supply (VS) or damage will occur.
DRV104
4
SBVS036B
www.ti.com
TYPICAL CHARACTERISTICS
At TC = +25°C and VS = +24V, unless otherwise noted.
VOUT AND ISOLENOID WAVEFORMS WITH SOLENOID LOAD
VOUT AND IOUT WAVEFORMS WITH RESISTIVE LOAD
Input
+VS
0
+VS
PWM Mode
VOUT
0
I
+VS
RL
2
1
0
2
1
0
drop-out
pull-in
0
0
ON
0
50
100
0
50
100
140
140
Time (ms)
Time (ms)
CURRENT LIMIT SHUTDOWN WAVEFORMS
QUIESCENT CURRENT vs TEMPERATURE
0.70
0.65
0.60
0.55
0.50
0.45
0.40
VIN
12V
32V
24V
5
Status
OK
Flag
0
24
0
24
8V
VOUT
0
0
50
Time (µs)
100
–60
–10
40
90
Temperature (°C)
CURRENT LIMIT SHUTDOWN vs TEMPERATURE
DELAY TO PWM vs TEMPERATURE
CD = 0.1µF
2.5
2.3
2.1
1.9
1.7
1.5
1.3
88
86
84
82
80
78
24V
12V, 8V
32V
–60
–10
40
90
140
–60
–10
40
Temperature (°C)
90
Temperature (°C)
DRV104
SBVS036B
5
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TC = +25°C and VS = +24V, unless otherwise noted.
OSCILLATOR FREQUENCY
vs JUNCTION TEMPERATURE
MINIMUM DELAY vs JUNCTION TEMPERATURE
14
26.0
25.5
25.0
24.5
24.0
8V
CD = 0pF
RFREQ = 191kΩ
13
12
11
10
9
32V
12V
12V
24V
12V
32V
8
24V
7
6
–60
–10
40
Temperature (°C)
90
140
–60
–60
–60
40
Temperature (°C)
140
DUTY CYCLE vs JUNCTION TEMPERATURE
32V
VSAT vs JUNCTION TEMPERATURE
53
52
51
50
49
48
47
0.8
0.6
0.4
0.2
0
RPWM = 147kΩ
24V
8V
12V
40
140
–60
–10
40
90
140
Temperature (°C)
Temperature (°C)
VREF vs TEMPERATURE
32V
INPUT CURRENT vs INPUT VOLTAGE
1.250
1.249
1.248
1.247
1.246
1.245
1.244
250
200
150
100
50
24V
12V
8V
0
–10
40
90
140
4
5
6
Temperature (°C)
Input Voltage (V)
DRV104
6
SBVS036B
www.ti.com
to set a longer delay time. A resistor, analog voltage, or a
voltage from a D/A converter can be used to control the duty
cycle of the PWM output. The D/A converter must be able
to sink a current of 2.75 • IREF (IREF = VREF/RFREQ).
BASIC OPERATION
The DRV104 is a high-side, DMOS power switch employing
a PWM output for driving electromechanical and thermal
devices. Its design is optimized for two types of applications:
as a 2-state driver (open/close) for loads such as solenoids
and actuators; and a linear driver for valves, positioners,
heaters, and lamps. Its low 0.45Ω On resistance, small size,
adjustable delay to PWM mode, and adjustable duty cycle
make it suitable for a wide range of applications.
Figure 2 illustrates a typical timing diagram with the Delay
Adjust pin connected to a 4.7nF capacitor, the duty cycle set
to 75%, and oscillator frequency set to 1kHz. See the
Adjustable and Adjustable Delay Time section for equations
and further explanation. Ground (pin 11) must be connected
to the system ground for the DRV104 to function. The load
(relay, solenoid, valve, etc.) should be connected between
the ground and the output (pins 6, 7). For an inductive load,
an external flyback diode is required, as shown in Figure 1.
The diode maintains continuous current flow in the inductive
load during Off periods of PWM operation. For remotely
located loads, the external diode is ideally located next to the
DRV104. The internal ESD clamp diode between the output
and ground is not intended to be used as a “flyback diode.”
The Status OK Flag (pin 13) provides fault status for over-
current and thermal shutdown conditions. This pin is active
Low with an output voltage of typically +0.48V during a fault
condition.
Figure 1 shows the basic circuit connections to operate the
DRV104. A 1µF (10µF when driving high current loads) or
larger ceramic bypass capacitor is recommended on the
power-supply pin.
Control input (pin 14) is level-triggered and compatible with
standard TTL levels. An input voltage between +2.2V and
+5.5V turns the device’s output On, while a voltage of 0V to
+1.2V shuts the DRV104’s output Off. Input bias current is
typically 1µA. Delay Adjust (pin 2) and Duty Cycle Adjust
(pin 1) allow external adjustment of the PWM output signal.
The Delay Adjust pin can be left floating for minimum delay
to PWM mode (typically 18µs) or a capacitor can be used
+VS
1µF
+
RLED
2mA
NOTES: (1) Motorola MSRS1100T3 (1A, 100V),
Motorola MBRS360T3 (3A, 60V), or Microsemi SK34MS (3A, 40V).
(2) Performance specified with CBOOT = 470pF. (3) When switching a
high-load current, a 100pF capacitor in parallel with RFREQ is
recommended to maintain a clean output switching waveform
and duty cycle, see Figure 5.
+8V to +32V
LED
OK = LED On
13
8, 9 10
VPS +VS
Status
OK Flag
6, 7
OUT
14
DRV104
TTL IN
3A
Flyback
Diode(1)
Delay
Adj
(2)
Osc Freq
Adj
Duty Cycle
Adj
CBOOT
Relay
= TON + TOFF
5
GND
11
2
3
1
5
(3)
RFREQ
RPWM
CD
FIGURE 1. DRV104 Basic Circuit Connections.
On
TTL High
Input (V)
Off
Off
1
TTL Low
Period =
FREQ
+VS
VO (V)
0
Delay Time
+VS/RL
TOFF
TON
TON + TOFF
IO (A)
0
Duty Cycle =
TON
0
1
2
3
4
6
7
8
9
Time (ms)
FIGURE 2. Typical Timing Diagram.
DRV104
SBVS036B
7
www.ti.com
pickup and PCB leakage currents if very high resistor values
are used. Refer to Figure 3 for a simplified circuit of the
frequency adjust input.
APPLICATIONS INFORMATION
POWER SUPPLY
The DRV104 operates from a single +8V to +32V supply with
excellent performance. Most behavior remains unchanged
throughout the full operating voltage range. Parameters that
vary significantly with operating voltage are shown in the
Typical Characteristics.
The DRV104’s adjustable PWM output frequency allows it to
be optimized for driving virtually any type of load.
+VS
3µA
ADJUSTABLE DELAY TIME
(INITIAL 100% DUTY CYCLE)
A unique feature of the DRV104 is its ability to provide an initial
constant DC output (100% duty cycle) and then switch to
PWM mode output to save power. This function is particularly
useful when driving solenoids that have a much higher pull-in
current requirement than continuous-hold requirement.
The duration of this constant DC output (before PWM output
begins) can be externally controlled by a capacitor con-
nected from Delay Adjust (pin 2) to ground according to
Equation 1:
CD
Reset
+2.6V
Input
VREF
VREF
IREF
+1.25V
RFREQ
Delay Time ≈ (CD • 106)/1.24
(1)
FIGURE 3. Simplified Delay Adjust and Frequency Adjust Inputs.
(time in seconds, CD in Farads)
Leaving the Delay Adjust pin open results in a constant output
time of approximately 18µs. The duration of this initial output
can be reduced to less than 3µs by connecting the pin to 5V.
Table I provides examples of delay times (constant output
before PWM mode) achieved with selected capacitor values.
OSCILLATOR FREQUENCY
(Hz)
RFREQ (nearest 1% values)
(Ω)
100k
50k
25k
10k
5k
47.5k
100k
191k
499k
976M
10M
The internal Delay Adjust circuitry is composed of a 3µA
current source and a 2.6V comparator, as shown in Figure 3.
Thus, when the pin voltage is less than 2.6V, the output
device is 100% On (DC output mode).
500
TABLE II. Oscillator Frequency Resistance.
PWM FREQUENCY vs RFREQ
1000M
OSCILLATOR FREQUENCY ADJUST
The DRV104 PWM output frequency can be easily pro-
100M
10M
1M
grammed over a wide range by connecting a resistor (RFREQ
)
between Osc Freq Adj (pin 3) and ground. A range of 500Hz
to 100kHz can be achieved with practical resistor values, as
shown in Table II. Refer to the PWM Frequency vs RFREQ plot
shown in Figure 4 for additional information. Although oscilla-
tor frequency operation below 500Hz is possible, resistors
higher than 10MΩ will be required. The pin becomes a very
high impedance node and is therefore sensitive to noise
100k
10k
1k
1
RFREQ(kΩ) =
1.4518 × 10−6 + 2.0593 ×10−7 × F Hz
(
)
INITIAL CONSTANT
OUTPUT DURATION
10
100
1k
10k
100k
1M
CD
Frequency (Hz)
3µs
18µs
81µs
0.81ms
8.1ms
81ms
0.81s
8.1s
Pin 2 Tied to +5V
Pin 2 Open
100pF
FIGURE 4. Using a Resistor to Program Oscillator Frequency.
1nF
10nF
100nF
1µF
When switching a high-load current, 100pF capacitors in
parallel with RFREQ are recommended to maintain a clean
output switching waveform and duty cycle, see Figure 5.
10µF
TABLE I. Delay Adjust Times.
DRV104
8
SBVS036B
www.ti.com
DUTY CYCLE vs RPWM
10M
1M
RFREQ
only
RPWM (kΩ) = 334.35 + 7.75(%DC)
5kHz
RPWM (kΩ) = 68.73 + 1.52(%DC)
25kHz
With
100k
10k
100pF in
Parallel
with RFREQ
100kHz
RPWM (kΩ) = 20.62 + 0.39(%DC)
Time (10µs)
0
20
40
60
80
100
Duty Cycle (%)
FIGURE 5. Output Waveform at High Load Current.
FIGURE 6. Using a Resistor to Program Duty Cycle.
ADJUSTABLE DUTY CYCLE (PWM MODE)
Voltage Controlled Duty Cycle
The DRV104’s externally adjustable duty cycle provides an
accurate means of controlling power delivered to a load.
Duty cycle can be set over a range of 10% to 90% with an
external resistor, analog voltage, or the voltage output of a
D/A converter. A low duty cycle results in reduced power
dissipation in the load. This keeps the DRV104 and the load
cooler, resulting in increased reliability for both devices.
The duty cycle can also be programmed by analog voltage
PWM. With VPWM ≈ 3.59V, the duty cycle is about 90%.
Decreasing this voltage results in decreased duty cycles. Table
IV provides VPWM values for typical duty cycles. Figure 7 shows
the relationship of duty cycle versus VPWM and its linearity.
V
DUTY CYCLE AND DUTY CYCLE ERROR
vs VOLTAGE
Resistor Controlled Duty Cycle
100
90
80
70
60
50
40
30
20
10
0
2.0
Duty cycle is easily programmed by connecting a resistor
(RPWM) between Duty Cycle Adjust (pin 1) and ground. High
resistor values correspond to high duty cycles. At 100kHz,
the range of adjustable duty cycle is limited to 10% to 70%.
Table III provides resistor values for typical duty cycles.
Resistor values for additional duty cycles can be obtained
from Figure 6.
At VS = 24V and F = 25kHz: VPWM = 1.25 + 0.026 × %DC
1.5
1.0
Duty Cycle
0.5
0
–0.5
–1.0
–1.5
–2.0
Duty Cycle Error
DUTY CYCLE
(%)
RPWM (Ω) (Nearest 1% Values)
1
2
3
4
5kHz
25kHz
100kHz
V
PWM (V)
10
20
30
40
50
60
70
80
90
412k
487k
562k
649k
715k
787k
887k
953k
1050k
84.5k
97.6k
113k
130k
147k
162k
174k
191k
205k
25.5k
28.7k
31.6k
35.7k
39.2k
43.2k
44.9k
—
FIGURE 7. Using a Voltage to Program Duty Cycle.
DUTY CYCLE
(%)
VPWM
(V)
—
10
20
40
60
80
90
1.501
1.773
2.296
2.813
3.337
3.589
TABLE III. Duty Cycle Adjust Resistance.
TABLE IV. Duty Cycle Adjust Voltage.
DRV104
SBVS036B
9
www.ti.com
The Duty Cycle Adjust pin is internally driven by an oscillator
frequency dependent current source and connects to the
input of a comparator, as shown in Figure 8. The DRV104’s
PWM adjustment is inherently monotonic; that is, a de-
creased voltage (or resistor value) always produces an
decreased duty cycle.
+5V
5kΩ
Pull-Up
TTL or HCT
8, 9
VPS
Status OK Flag
13
Thermal Shutdown
Over-Current
3.9V
OSC
PWM
1.3V
6, 7
+VS
DRV104
OUT
2.75 • IREF
FIGURE 9. Non-Latching Fault Monitoring Circuit.
RPWM
+5V
74XX76A
VS
Q
20kΩ
OK
OK
J
Q
FIGURE 8. Simplified Duty Cycle Adjust Input.
OK Reset
CLR
CLK
K
(1)
GND
STATUS OK FLAG
The Status OK Flag (pin 13) provides a fault indication for
over-current and thermal shutdown conditions. During a fault
condition, the Status OK Flag output is driven Low (pin
voltage typically drops to 0.45V). A pull-up resistor, as shown
in Figure 9, is required to interface with standard logic. Figure
9 also gives an example of a non-latching fault monitoring
circuit, while Figure 10 provides a latching version. The
Status OK Flag pin can sink up to 10mA, sufficient to drive
external logic circuitry, a reed relay, or an LED (as shown in
Figure 11) to indicate when a fault has occurred. In addition,
the Status OK Flag pin can be used to turn off other
DRV104s in a system for chain fault protection.
8, 9
13
Status OK Flag
VPS
Thermal Shutdown
Over-Current
PWM
6, 7
DRV104
OUT
NOTE: (1) A small capacitor (10pF) may be required in noisy environments.
FIGURE 10. Latching Fault Monitoring Circuit.
Over-Current Fault
An over-current fault occurs when the PWM peak output
current is greater than typically 2.0A. The Status OK flag is
not latched. Since current during PWM mode is switched on
and off, the Status OK flag output will be modulated with
PWM timing (see the Status OK flag waveforms in the
Typical Characteristics).
+5V
5kΩ
(LED)
HLMP-Q156
8, 9
Status OK Flag
13
VPS
Avoid adding capacitance to pins 6, 7 (OUT) because this
can cause momentary current limiting.
Thermal Shutdown
Over-Current
Over-Temperature Fault
A thermal fault occurs when the die reaches approximately
160°C, producing an effect similar to pulling the input low.
Internal shutdown circuitry disables the output. The Status
OK Flag is latched in the Low state (fault condition) until the
die has cooled to approximately 140°C.
PWM
6, 7
DRV104
OUT
FIGURE 11. Using an LED to Indicate a Fault Condition.
DRV104
10
SBVS036B
www.ti.com
PACKAGE MOUNTING
THERMAL RESISTANCE vs
PCB COPPER AREA
Figure 12 provides recommended printed circuit board (PCB)
layouts for the PowerPAD HTSSOP-14 package. The metal
pad of the PowerPAD HTSSOP-14 package is electrically
isolated from other pins and ideally should be connected to
a ground. For reliable operation, the PowerPAD must be
directly soldered to a circuit board, as shown in Figure 13.
Increasing the heat-sink copper area improves heat dissipa-
tion. Figure 14 shows typical junction-to-ambient thermal
resistance as a function of the PCB copper area.
80
70
60
50
40
30
DRV104
PowerPAD
Surface-Mount Package
1oz. Copper
0
1
2
3
4
5
DRV104 Die
Copper Area (inches2)
FIGURE 14. Heat-Sink Thermal Resistance vs PCB Copper
Area.
Pad-to-Board
Signal Trace
Solder
POWER DISSIPATION
The DRV104 power dissipation depends on power supply,
signal, and load conditions. Power dissipation (PD) is equal to
the product of output current times the voltage across the
conducting DMOS transistor times the duty cycle. Using the
lowest possible duty cycle necessary to assure the required
hold force can minimize power dissipation in both the load and
in the DRV104. At 1A, the output DMOS transistor on-resis-
tance is 0.45Ω, increasing to 0.65Ω at current limit.
Copper Pad
Copper Traces
Thermal Vias
FIGURE 13. PowerPAD Heat Transfer.
3.5
2.0
1.0
0.33
2.4
2.0
0.0
Solder Attachment
to PCB
0.65
(all dimensions in mm)
FIGURE 12. Recommended PCB Layout.
DRV104
SBVS036B
11
www.ti.com
At very high oscillator frequencies, the energy in the DRV104’s
linear rise and fall times can become significant and cause
an increase in PD.
The answer to the question of selecting a heat-sink lies in
determining the power dissipated by the DRV104. For DC
output into a purely resistive load, power dissipation is simply
the load current times the voltage developed across the
conducting output transistor times the duty cycle. Other loads
are not as simple. (For further information on calculating
power dissipation, refer to Application Bulletin SBFA002,
available at www.ti.com.) Once power dissipation for an
application is known, the proper heat-sink can be selected.
THERMAL PROTECTION
Power dissipated in the DRV104 causes its internal junction
temperature to rise. The DRV104 has an on-chip thermal
shutdown circuitry that protects the IC from damage. The
thermal protection circuitry disables the output when the
junction temperature reaches approximately +160°C, allow-
ing the device to cool. When the junction temperature cools
to approximately +140°C, the output circuitry is again en-
abled. Depending on load and signal conditions, the thermal
protection circuit may cycle on and off. This limits the dissi-
pation of the driver but may have an undesirable effect on the
load.
Heat-Sink Selection Example
A PowerPAD HTSSOP-14 package dissipates 2W. The maxi-
mum expected ambient temperature is 35°C. Find the proper
heat-sink to keep the junction temperature below 125°C.
Combining Equations 1 and 2 gives:
TJ = TA + PD(θJC + θCH + θHA
)
(5)
TJ, TA, and PD are given. θJC is provided in the specification
table: 2.07°C/W. θCH depends on heat sink size, area, and
material used. Semiconductor package type and mounting can
also affect θCH. A typical θCH for a soldered-in-place PowerPAD
Any tendency to activate the thermal protection circuit indi-
cates excessive power dissipation or an inadequate heat
sink. For reliable operation, junction temperature should be
limited to a maximum of +125°C. To estimate the margin of
safety in a complete design (including heat-sink), increase
the ambient temperature until the thermal protection is trig-
gered. Use worst-case load and signal conditions. For good
reliability, thermal protection should trigger more than 35°C
above the maximum expected ambient condition of your
application. This produces a junction temperature of 125°C
at the maximum expected ambient condition.
HTSSOP-14 package is 2°C/W. Now, solving for θHA
:
TJ – TA
θHA
=
– θJC +θCH
(
)
PD
125°C – 35°C
θ HA
=
– 2.07°C/ W + 2°C/ W
(
)
(6)
2W
The internal protection circuitry of the DRV104 is designed to
protect against overload conditions. It is not intended to
replace proper heat sinking. Continuously running the DRV104
into thermal shutdown will degrade device reliability.
θ HA= 40.9°C/ W
To maintain junction temperature below 125°C, the heat-sink
selected must have a θHA less than 40.9°C/W. In other
words, the heat-sink temperature rise above ambient tem-
perature must be less than 81.8°C (40.9°C/W • 2W).
HEAT SINKING
Most applications do not require a heat-sink to assure that
the maximum operating junction temperature (125°C) is not
exceeded. However, junction temperature should be kept as
low as possible for increased reliability. Junction temperature
can be determined according to the following equations:
Another variable to consider is natural convection versus
forced convection air flow. Forced-air cooling by a small fan
can lower θCA (θCH + θHA) dramatically.
As mentioned above, once a heat-sink has been selected,
the complete design should be tested under worst-case load
and signal conditions to ensure proper thermal protection.
TJ = TA + PDθJA
(3)
(4)
θJA = θJC + θCH + θHA
where:
RFI/EMI
TJ = Junction Temperature (°C)
Any switching system can generate noise and interference
by radiation or conduction. The DRV104 is designed with
controlled slew rate current switching to reduce these effects.
By slowing the rise time of the output to 1µs, much lower
switching noise is generated.
TA = Ambient Temperature (°C)
PD = Power Dissipated (W)
θJC = Junction-to-Case Thermal Resistance (°C/W)
θCH = Case-to-Heat Sink Thermal Resistance (°C/W)
Radiation from the DRV104-to-load wiring (the antenna ef-
fect) can be minimized by using twisted pair cable or by
shielding. Good PCB ground planes are recommended for
low noise and good heat dissipation. Refer to the Bypassing
section for notes on placement of the flyback diode.
θHA = Heat Sink-to-Ambient Thermal Resistance (°C/W)
θJA = Junction-to-Air Thermal Resistance (°C/W)
Using a heat sink significantly increases the maximum allow-
able power dissipation at a given ambient temperature.
DRV104
12
SBVS036B
www.ti.com
BYPASSING
DRV104s, a beat frequency of 22.5kHz can be established
by setting one internal oscillator to a center of 62.5kHz and
the other to 40kHz. Considering the specification of ±20%
frequency accuracy, the beat could range from 2kHz (48kHz
and 50kHz) to 43kHz (75kHz and 32kHz). By limiting the
analog measurement bandwidth to 100Hz, for example,
interference can be avoided.
A 1µF ceramic bypass capacitor is adequate for uniform duty
cycle control when switching loads of less than 0.5A. Larger
bypass capacitors are required when switching high-current
loads. A 10µF ceramic capacitor is recommended for heavy-
duty (1.2A) applications. It may also be desirable to run the
DRV104 and load driver on separate power supplies at high-
load currents. Bypassing is especially critical near the abso-
lute maximum supply voltage of 32V. In the event of a current
overload, the DRV104 current limit responds in microsec-
onds, dropping the load current to zero. With inadequate
bypassing, energy stored in the supply line inductance can
lift the supply sufficiently to exceed voltage breakdown with
catastrophic results.
BEAT FREQUENCY ELIMINATION—OPTIONAL
SYNCHRONIZATION
The benefit of synchronization in multichannel systems is
that measurement interference can be avoided in low-level
analog circuits, particularly when physically close to the
DRVs. Specifically, synchronization will accomplish the fol-
lowing:
Place the flyback diode at the DRV104 end when driving long
(inductive) cables to a remotely located load. This minimizes
RFI/EMI and helps protect the output DMOS transistor from
breakdown caused by dI/dt transients. Fast rectifier diodes
such as epitaxial silicon or Schottky types are recommended
for use as flyback diodes.
1. Eliminate beat frequencies between DRVs or DRVs and
the system clock.
2. Predict quiet or non-switching times.
Synchronization of DRV104s is possible by using one oscil-
lator frequency for all DRVs. See Figure 15 for an example
of one DRV internal oscillator as the master and the others
as slaves. Also, one external clock can be used as the
master and all the others as slaves.
APPLICATIONS CIRCUITS
SINGLE AND MULTICHANNEL
The DRV104 can be used in a variety of ways with resistive
and inductive loads. As a single-channel driver, it can be
placed on one PC board or inside a solenoid, relay, actuator,
valve, motor, heater, thermoelectric cooler, or lamp housing.
In high-density systems, multichannel power drivers may be
packed close together on a PC board. For these switching
applications, it is important to provide power supply bypass-
ing as close to the driver IC as possible to avoid cross-
coupling of spikes from one circuit to another. Also, in some
applications, it may be necessary to keep beat frequencies
(sum and difference between DRV oscillators or between
DRV oscillators and system clock frequencies) from interfer-
ing with low-level analog circuits that are located relatively
near to the power drivers. Paralleling device outputs is not
recommended as unequal load sharing and device damage
will result.
PEAK SUPPLY CURRENT ELIMINATION—OPTIONAL
SWITCHING SKEW
In many systems, particularly where only a few channels are
used or low magnitude load currents are present, it is
unnecessary to skew the switching times.
In some multichannel systems, where just PWM is used,
without initial dc time delay, simultaneous switching of edges
can cause large peak currents to be drawn from the main
power supply. This is similar to that which occurs when
multiple switching power supplies draw current from one
power source.
Peak currents can be reduced by synchronizing oscillators
and skewing switching edges. Synchronization has the added
benefit of eliminating beat frequencies, as discussed above.
Skewing can be accomplished by using a polyphase clock
approach, which intentionally delays the time that each DRV
switches on PWM edges.
BEAT FREQUENCIES IN NON-SYNCHRONIZED
MULTICHANNEL SYSTEMS
The DRV104 is useful for a variety of relay driver applications
(see Figures 16 and 17), as well as valve drivers (see Figures
18 and 19).
In many multichannel systems, beat frequencies are of no
consequence where each DRV uses its own internal oscilla-
tor.
Beat frequencies can be intentionally set up to be outside the
measurement base-band to avoid interference in sensitive
analog circuits located nearby. For example, with two
DRV104
SBVS036B
13
www.ti.com
+VS
10
Sync
12
4
9
8
+VPS
Master/Slave
+5V
Master
pwm
dc
6
7
DRV104
14
Input
Boot 5
On
Off
2
3
1
11
LOAD 1
470pF
Osc
Freq
Duty
Cycle
Delay
GND
+VS
10
Sync
12
4
9
8
+VPS
Master/Slave
Slave
DRV104
#2
dc
pwm
6
7
14
Input
Boot 5
On
Off
2
3
1
11
LOAD 2
470pF
Osc
Freq
Duty
Cycle
Delay
GND
+VS
10
Sync
12
4
9
8
+VPS
Master/Slave
Slave
DRV104
#n
dc
pwm
6
7
14
Input
Boot 5
On
Off
2
3
1
11
LOAD n
470pF
Osc
Freq
Duty
Cycle
Delay
GND
FIGURE 15. Multichannel DRV104s, Synchronized with One as the Master and the Others as Slaves.
DRV104
14
SBVS036B
www.ti.com
+12V
5.6kΩ
10µF
Fault
HLMP-0156
Microsemi
SK34MS
Relay
+
1MΩ
3A 40V Schottky
13
10
+VS
8, 9
VPS
Status OK
Flag
6, 7
5
OUT
1.7V
14
Input
470pF
+
47µF
Tantalum
CT
DRV104
316kΩ
CT (µF)
T
ON (s)
47
22
10
4.7
2.2
10
5
2
1
0.5
11
GND
Delay
Adj
Duty Cycle
Adj
Osc Freq
Adj
2
1
3
147kΩ
191kΩ
0.22µF
FIGURE 16. Time-Delay Relay Driver.
+28V
10µF
+
Relay
24kΩ
10
8, 9
VPS
+VS
DRV104
6, 7
OUT
14
470pF
Input
5
Osc
Freq
Adj
11
GND
Delay
Adj
Duty Cycle
Adj
3.9kΩ
2
1
3
137kΩ
205kΩ
0.1µF
Housing
FIGURE 17. Remotely-Operated Solenoid Valve or Relay.
DRV104
SBVS036B
15
www.ti.com
+12V
10µF
(1)
12V
70A
LOAD
10
+VS
8, 9
VPS
IRF7476
14
Input
6, 7
OUT
GND
TTLIN
High = Load On
Low = Load Off
CBOOT
DRV104
5
3kΩ
11
Delay
Adj
Duty Cycle
Adj
Osc Freq
Adj
2
1
3
10MΩ
CD
F ~ 500Hz
NOTE: (1) Flyback diode required for inductive loads:
IXYS DSE160-06A.
FIGURE 18. High-Power, Low-Side Driver.
+8V to +32V
2mA
10µF
+
HLMP-Q156
Fault
13
10
+VS
8, 9
VPS
Status
6, 7
CBOOT
OUT
GND
OK Flag
Linear
Valve
Actuator
14
Microsemi
SK34MS
3A 40V
5
DRV104
TTL IN
High = On
Low = Off
Osc
Freq
Adj
11
Delay
Adj
Duty Cycle
Adj
Schottky
NC
2
1
3
NC = No Connection
191kΩ
1.3V 5% Duty Cycle
3.7V 95% Duty Cycle
DATA
D/A
Converter
FIGURE 19. Linear Valve Driver.
DRV104
16
SBVS036B
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
DRV104PWP
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
HTSSOP
HTSSOP
HTSSOP
HTSSOP
PWP
14
14
14
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
DRV104
DRV104PWPG4
DRV104PWPR
DRV104PWPRG4
ACTIVE
ACTIVE
ACTIVE
PWP
PWP
PWP
90
Green (RoHS
& no Sb/Br)
-40 to 85
DRV104
DRV104
DRV104
2000
2000
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV104PWPR
HTSSOP PWP
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 14
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
DRV104PWPR
2000
Pack Materials-Page 2
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相关型号：
DRV10963DSNR
5-V nominal, 1.8-A peak sensorless sinusoidal control 3-phase BLDC motor driver 10-SON -40 to 125
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