DP8421AVX-20 [TI]
DRAM CONTROLLER, PQCC68, PLASTIC, LCC-68;型号: | DP8421AVX-20 |
厂家: | TEXAS INSTRUMENTS |
描述: | DRAM CONTROLLER, PQCC68, PLASTIC, LCC-68 动态存储器 外围集成电路 |
文件: | 总60页 (文件大小:1073K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DP8420A,DP8421A,DP8422A
DP8420A DP8421A DP8422A microCMOS Programmable 256k/1M/4M Dynamic RAM
Controller/Drivers
Literature Number: SNOSBX7A
July 1992
DP8420A/21A/22A microCMOS Programmable
256k/1M/4M Dynamic RAM Controller/Drivers
General Description
Features
Y
On chip high precision delay line to guarantee critical
DRAM access timing parameters
The DP8420A/21A/22A dynamic RAM controllers provide a
low cost, single chip interface between dynamic RAM and
all 8-, 16- and 32-bit systems. The DP8420A/21A/22A gen-
erate all the required access control signal timing for
DRAMs. An on-chip refresh request clock is used to auto-
matically refresh the DRAM array. Refreshes and accesses
are arbitrated on chip. If necessary, a WAIT or DTACK out-
put inserts wait states into system access cycles, including
burst mode accesses. RAS low time during refreshes and
RAS precharge time after refreshes and back to back ac-
cesses are guaranteed through the insertion of wait states.
Separate on-chip precharge counters for each RAS output
can be used for memory interleaving to avoid delayed back
to back accesses because of precharge. An additional fea-
ture of the DP8422A is two access ports to simplify dual
accessing. Arbitration among these ports and refresh is
done on chip.
Y
Y
microCMOS process for low power
High capacitance drivers for RAS, CAS, WE and DRAM
address on chip
Y
Y
On chip support for nibble, page and static column
DRAMs
Byte enable signals on chip allow byte writing in a word
size up to 32 bits with no external logic
Selection of controller speeds: 20 MHz
On board Port A/Port B (DP8422A oarbia-
tion logic
Y
Y
Y
Y
Direct interface to all majicroproors (appa-
tion notes available)
4 RAS and 4 CAS drivers (the Rand CAS configura-
tion is programmable)
Largest
DRAM
Direct Dr
Memory
Access
Ports
Ý
Ý
of Pins
of Address
Outputs
Control
(PLCC)
Possible
pacity
Available
DP8420A
DP8421A
DP8422A
68
68
84
9
256 kbit
1 Mbit
4 Mb
4 Mes
6 Mbyte
ytes
gle Access Port
10
11
Single Access Port
Dual Access Ports (A and B)
Block Diagram
DP842021A/22A DRAM Controller
TL/F/8588–5
FIGURE 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
Staggered RefreshTM is a trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/8588
RRD-B30M105/Printed in U. S. A.
Table of Contents
1.0 INTRODUCTION
6.0 PORT A WAIT STATE SUPPORT
6.1 WAIT Type Output
2.0 SIGNAL DESCRIPTIONS
2.1 Address, R/W and Programming Signals
2.2 DRAM Control Signals
6.2 DTACK Type Output
6.3 Dynamically Increasing the Number of Wait States
6.4 Guaranteeing RAS Low Time and RAS Precharge
Time
2.3 Refresh Signals
2.4 Port A Access Signals
7.0 RAS AND CAS CONFIGURATION MODES
7.1 Byte Writing
2.5 Port B Access Signals (DP8422A)
2.6 Common Dual Port Signals (DP8422A)
2.7 Power Signals and Capacitor Input
2.8 Clock Inputs
7.2 Memory Interleaving
7.3 Address Pipelining
7.4 Error Scrubbing
3.0 PROGRAMMING AND RESETTING
3.1 External Reset
7.5 Page/Burst Mode
8.0 TEST MODE
3.2 Programming Methods
9.0 DRAM CRITICAL TIMING PARAMETE
3.2.1 Mode Load Only Programming
3.2.2 Chip Selected Access Programming
3.3 Internal Programming Modes
9.1 Programmable Values of t
d t
AS
R
9.2 Calculation of t
and t
AS
RAH
10.0 DUAL ACCESSING (DP8422A)
10.1 Port B Access M
4.0 PORT A ACCESS MODES
4.1 Access Mode 0
10.2 PorB Wait Sta
4.2 Access Mode 1
10.3 CommPort A Port B DuPort Functions
4.3 Extending CAS with Either Access Mode
4.4 Read-Modify-Write Cycles with Either Access Mode
4.5 Additional Access Support Features
10.3.1 GRTB Out
10.3.2 LOCK ut
4.5.1 Address Latches and Column Increment
4.5.2 Address Pipelining
11.0 MAXIMRATINGS
12.AL CHARACTERISTICS
13.0 ARAMETERS
4.5.3 Delay CAS During Write Accesses
5.0 REFRESH OPTIONS
14.0 FUNCTIONAL DIFFERENCES BETWEEN THE
8420A/21A/22A AND THE DP8420/21/22
5.1 Refresh Control Modes
5.1.1 Automatic Internal Refresh
15.0 P8420A/21A/22A USER HINTS
5.1.2 Externally Controlled/Burst Refresh
5.1.3 Refresh Request/Acknowge
5.2 Refresh Cycle Types
5.2.1 Conventional Refres
5.2.2 Staggered R
5.2.3 Error Scru
5.3 Extending Refr
5.4 Clearing the Re
5.5 Clearing the Refre
2
1.0 Introduction
The DP8420A/21A/22A are CMOS Dynamic RAM control-
lers that incorporate many advanced features which include
address latches, refresh counter, refresh clock, row, column
and refresh address multiplexer, delay line, refresh/access
arbitration logic and high capacitive drivers. The program-
mable system interface allows any manufacturer’s micro-
processor or bus to directly interface via the
DP8420A/21A/22A to DRAM arrays up to 64 Mbytes in
size.
Sequential Accesses (Static Column/Page Mode):
The DP8420A/21A/22A have address latches, used to
latch the bank, row and column address inputs. Once the
address is latched, a COLumn INCrement (COLINC) feature
can be used to increment the column address. The address
latches can also be programmed to be fall through. COLINC
can be used for Sequential Accesses of Static Column
DRAMs. Also, COLINC in conjunction with ECAS inputs can
be used for Sequential Accesses to Page Mode DRAMs.
After power up, the user must first reset and program the
DP8420A/21A/22A before accessing the DRAM. The chip
is programmed through the address bus.
RAS and CAS Configuration (Byte Writing):
The RAS and CAS drivers can be configured to drive a one,
two or four bank memory array up to 32 bits in width. The
ECAS signals can then be used to select one of four CAS
drivers for Byte Writing with no extra logic.
Reset:
Due to the differences in power supplies, the internal reset
circuit may not always reset correctly; therefore, an External
(hardware) Reset must be performed before programming
the chip.
Memory Interleaving:
When configuring the DP820A/21A/22A for more than one
bank, Memory Interleaving can be uying the low
order address bits to the bank seland B1, se-
quential back to back accesses wdelayd since
these controllers havseparate ge cours per
bank.
Programming:
After resetting the chip, the user can program the controller
by either one of two methods: Mode Load Only Program-
ming or Chip Select Access Programming.
Initialization Period:
Address Pipelining:
Once the DP8420A/21A/22A has been programmed for the
first time, a 60 ms initialization period is entered. During this
time the DRC performs refreshes to the DRAM array so
further warm up cycles are unnecessary. The initialization
period is entered only after the first programming after a
reset.
The DP8420A/21A/22A are cable of performing Address
Pipelining. In addelining, tDRwill guarantee the
column addresnd switche internal multiple-
xor to place dress on the address bus. At this
timanother access another bank can be initiat-
ed.
Accessing Modes:
Dual Acssing:
After resetting and programming the chip, the
DP8420A/21A/22A is ready to access the DRAM. There
are two modes of accessing with these controllers. Mode 0,
which indicates RAS synchronously and Mode 1, which indi-
cates RAS asynchronously.
Finally, the 8422A has all the features previously men-
and unthe DP8420A/21A, the DP8422A has a
rt to aw a second CPU to access the same
ay. The DP8422A has four signals to support
ing, these signals are AREQB, ATACKB, LOCK
TB. All arbitration for the two ports and refresh is
chip by the controller through the insertion of wait
states. Since the DP8422A has only one input address bus,
the address lines must be multiplexed externally. The signal
GRANTB can be used for this purpose.
Refresh Modes:
The DP8420A/21A/22A have expanded refresh cpabilities
compared to previous DRAM controllers. Therare thre
modes of refreshing available: Internal AutomatReh-
ing, Externally Controlled/Burst Refreshing and Refresh Re-
quest/Acknowledge Refreshng. Any modes can
be used together or separatto asired
sults.
Terminology:
The following explains the terminology used in this data
sheet. The terms negated and asserted are used. Asserted
refers to a ‘‘true’’ signal. Thus, ‘‘ECAS0 asserted’’ means
the ECAS0 input is at a logic 0. The term ‘‘COLINC assert-
ed’’ means the COLINC input is at a logic 1. The term negat-
Refresh Types:
These controllerpes of vailable:
Conventional, r Scrub. Any refresh
control mode type of fresh.
ed refers to
a ‘‘false’’ signal. Thus, ‘‘ECAS0 negated’’
means the ECAS0 input is at a logic 1. The term ‘‘COLINC
negated’’ means the input COLINC is at a logic 0. The table
shown below clarifies this terminology.
Wait Suppo
The DP8420support available as
DTACK or Wmmable. DTACK, Data
Transfer ACKnowor processors whose wait
signal is active highuseful for those processors
whose wait signal is active low. The user can choose either
at programming. These signals are used by the on chip arbi-
ter to insert wait states to guarantee the arbitration between
accesses, refreshes and precharge. Both signals are inde-
pendent of the access mode chosen and both signals can
be dynamically delayed further through the WAITIN signal to
the DP8420A/21A/22A.
Signal
Action
Asserted
Negated
Asserted
Negated
Logic Level
High
Active High
Active High
Active Low
Active Low
Low
Low
High
3
Connection Diagrams
TL/F/8588–4
–3
Top View
FIGURE 2
Top View
Order Number DP8420AV-20 or DP8420AV-25
See NS Package Number V68A
OrdeNumber D20 or DP8421AV-25
ee NS PNumbeV68A
TL/F/8588–2
Top View
FIGURE 4
Order Number DP8422AV-20 or DP8422AV-25
See NS Package Number V84A
4
2.0 Signal Descriptions
Pin
Device (If not
Input/
Description
Name
Applicable to All) Output
2.1 ADDRESS, R/W AND PROGRAMMING SIGNALS
R0–10
R0–9
DP8422A
I
I
ROW ADDRESS: These inputs are used to specify the row address during an access
to the DRAM. They are also used to program the chip when ML is asserted (except
R10).
DP8420A/21A
C0–10
C0–9
DP8422A
I
I
COLUMN ADDRESS: These inputs are used to specify the column address during an
access to the DRAM. They are also used to program the chip when ML is asserted
(except C10).
DP8420A/21A
B0, B1
I
I
BANK SELECT: Depending on programming, these inputs are used to select a group
of RAS and CAS outputs to assert during an access. They are also used to program
the chip when ML is asserted.
ECAS0–3
ENABLE CAS: These inputs are used to enable a single or group of CAS outputs
when asserted. In combination with the B0, B1 and the programming bits, these
inputs select which CAS output or CAS outputs will assert duress. The
ECAS signals can also be used to toggle a group of CAS oue/nibble
mode accesses. They also can be used for byte write operCAS0
negated during programming, continuing to asrt the ECAe negatiAREQ
or AREQB during an access, will cause the CAS uts to btended wle the
RAS outputs are negated (the ECASn inputs havnffect duricring
refreshes).
WIN
I
WRITE ENABLE IN: This input is used to write optioto the DRAM. If
ECAS0 is asserted during programmintput will follow this input. This
input asserted will also case CAS to e nexpositive clock edge if address
bit C9 is asserted during pramming
COLINC
I
I
COLUMN INCREMENT: When e addrlatches e used, and RFIP is negated,
this input functions as COLINC. Arting thial causes the column address to
be incremented by one. hen RFIP sserted, this signal is used to extend the
refresh cycle by any eriods CLK until it is negated.
(EXTNDRF)
ML
I
MODE LOAD: Then low, enables the internal programming register
that stores the proation.
2.2 DRAM CONTROL SIGNALS
Q0–10
Q0–9
Q0–8
DP8422A
DP8421A
DP8421A
O
O
O
DRAADDRESS: These outputs are the multiplexed output of the R0–9, 10 and
C0–10 anm e DRAM address bus. These outputs contain the refresh
addreenever RP is asserted. They contain high capacitive drivers with 20X
series damping resiors.
RAS0–3
ADDRSTROBES: These outputs are asserted to latch the row address
d on the outputs Q0–8, 9, 10 into the DRAM. When RFIP is asserted, the
puts are used to latch the refresh row address contained on the Q0–8, 9, 10
n the DRAM. These outputs contain high capacitive drivers with 20X series
ng resistors.
CAS0–3
O
OLUMN ADDRESS STROBES: These outputs are asserted to latch the column
address contained on the outputs Q0–8, 9, 10 into the DRAM. These outputs have
high capacitive drivers with 20X series damping resistors.
WE
O
O
WRITE ENABLE or REFRESH REQUEST: This output asserted specifies a write
operation to the DRAM. When negated, this output specifies a read operation to the
DRAM. When the DP8420A/21A/22A is programmed in address pipelining mode or
when ECAS0 is negated during programming, this output will function as RFRQ.
When asserted, this pin specifies that 13 ms or 15 ms have passed. If DISRFSH is
negated, the DP8420A/21A/22A will perform an internal refresh as soon as possible.
If DISRFRSH is asserted, RFRQ can be used to externally request a refresh through
the input RFSH. This output has a high capacitive driver and a 20X series damping
resistor.
(RFRQ)
5
2.0 Signal Descriptions (Continued)
Pin
Device (If not
Input/
Description
Name
Applicable to All) Output
2.3 REFRESH SIGNALS
RFIP
O
I
REFRESH IN PROGRESS: This output is asserted prior to a refresh cycle and is
negated when all the RAS outputs are negated for that refresh.
RFSH
REFRESH: This input asserted with DISRFRSH already asserted will request a
refresh. If this input is continually asserted, the DP8420A/21A/22A will perform
refresh cycles in a burst refresh fashion until the input is negated. If RFSH is asserted
with DISRFSH negated, the internal refresh address counter is cleared (useful for
burst refreshes).
DISRFSH
I
DISABLE REFRESH: This input is used to disable internal refreshes and must be
asserted when using RFSH for externally requested refreshes.
2.4 PORT A ACCESS SIGNALS
ADS
I
I
ADDRESS STROBE or ADDRESS LATCH ENABLE: Depending on proing,
this input can function as ADS or ALE. In mode 0, the input functions
when asserted along with CS causes an internal latch to be set. Oncs set
an access will start from the positive clock edge of CLK s soon as pIn Mod
1, the input functions as ADS and when asserted along wCcause access
RAS to assert if no other event is taking place. If an event king placAS will e
asserted from the positive edge of CLK as soon as possible. In oth cases, tow
going edge of this signal latches the bank, row and column addreif programmed to
do so.
(ALE)
CS
I
I
CHIP SELECT: This input signal must be assere a Port A access.
AREQ
ACCESS REQUEST: This input signn Mode be assed some time after
the first positive clock edge after ALE been arted. Whethis signal is
negated, RAS is negated for the access. ode 1, sigl must be asserted
before ADS can be negated. When this signnegated, RAS is negated for the
access.
WAIT
O
O
WAIT or DTACK: This outpmmed o insert wait states into a CPU
access cycle. With R7 negmming, the output will function as a
WAIT type output. In this cabe active low to signal a wait condition.
With R7 asserted dg progutput will function as DTACK. In this
case, the outpuwill be negated ty a wait condition and will be asserted to
signify the acss has talace. Each of these signals can be delayed by a
number of pove cedgor negative clock levels of CLK to increase the
microprocessor’s access cyclthrough the insertion of wait states.
(DTACK)
WAITIN
I
WASE: Tint can be used to dynamically increase the number of
pges of CLK until DTACK will be asserted or WAIT will be negated
cess.
6
2.0 Signal Descriptions (Continued)
Pin
Device (If not
Input/
Description
Name
Applicable to All)
Output
2.5 PORT B ACCESS SIGNALS
AREQB
DP8422A
only
I
PORT B ACCESS REQUEST: This input asserted will latch the row, column and bank
address if programmed, and requests an access to take place for Port B. If the
access can take place, RAS will assert immediately. If the access has to be delayed,
RAS will assert as soon as possible from a positive edge of CLK.
ATACKB
DP8422A
only
O
ADVANCED TRANSFER ACKNOWLEDGE PORT B: This output is asserted when
the access RAS is asserted for a Port B access. This signal can be used to generate
the appropriate DTACK or WAIT type signal for Port B’s CPU or bus.
2.6 COMMON DUAL PORT SIGNALS
GRANTB
LOCK
DP8422A
only
O
GRANT B: This output indicates which port is currently granted access to the DRAM
array. When GRANTB is asserted, Port B has access to the array. When GRANTB is
negated, Port A has access to the DRAM array. This signal is used to multiplex the
signals R0–8, 9, 10; C0–8, 9, 10; B0–1; WIN; LOCK and ECAe DP8422A
when using dual accessing.
DP8422A
only
I
LOCK: This input can be used by the currently ranted port out’’ thother
port from the DRAM array by inserting wait statenthe loout port’s ccess
cycle until LOCK is negated.
2.7 POWER SIGNALS AND CAPACITOR INPUT
V
I
I
I
POWER: Supply Voltage.
CC
GND
CAP
GROUND: Supply Voltage Reference.
CAPACITOR: This input is ed by the l PLL fotabilization. The value of the
ceramic capacitor should be 0mF and uld be conected between this input and
ground.
2.8 CLOCK INPUTS
There are two clock inputs to the DP8420A/21A/22A, CLK anse two ocks may both be tied to the same clock
input, or they may be two separate clocks, running at differeynchronous to each other.
CLK
I
SYSTEM CLOCK: Tin the range of 0 Hz up to 25 MHz. This input is
generally stant frit may be controlled externally to change
frequeies or perhaps be ped for some arbitrary period of time.
This iut provclock to the internal state machine that arbitrates between
accesrefresh. This clock’s positive edges and negative levels are used to
extend the WAIT (DTCK) signals. Ths clock is also used as the reference for the
precharge timand RAS low time during refresh.
and Port B accesses are assumed to be synchronous to the system clock
DELCLK
I
NE CLOCK: The clock input DELCLK, may be in the range of 6 MHz to
and should be a multiple of 2 (i.e., 6, 8, 10, 12, 14, 16, 18, 20 MHz) to have
DP8420A/21A/22A switching characteristics hold. If DELCLK is not one of the
above frequencies the accuracy of the internal delay line will suffer. This is because
the phase locked loop that generates the delay line assumes an input clock
frequency of a multiple of 2 MHz.
For example, if the DELCLK input is at 7 MHz and we choose a divide by 3 (program
bits C0–2) this will produce 2.333 MHz which is 16.667% off of 2 MHz. Therefore, the
DP8420A/21A/22A delay line would produce delays that are shorter (faster delays)
than what is intended. If divide by 4 was chosen the delay line would be longer
(slower delays) than intended (1.75 MHz instead of 2 MHz). (See Section 10 for more
information.)
This clock is also divided to create the internal refresh clock.
7
3.0 Programming and Resetting
Due to the variety in power supplies power-up times, the
internal power up reset circuit may not work in every design;
therefore, an EXTERNAL RESET must be performed before
the DRAM controller can be programmed and used.
3.1 EXTERNAL RESET
At power up, if the internal power up reset worked, all inter-
nal latches and flip-flops are cleared and the part is ready to
be programmed. The power up state can also be achieved
by performing an External Reset, which is required to insure
proper operation. External Reset is achieved by asserting
ML and DISRFSH for at least 16 positive clock edges. In
order to perform simply a Reset, the ML signal must be
negated before DISRFSH is negated as shown in Figure 5a.
This procedure will only reset the controller which now is
ready for programming.
After going through the reset procedure, the
DP8420A/21A/22A can be programmed by either of two
methods; Mode Load Only Programming or Chip Select Ac-
cess Programming. After programming the DRC for the first
time after reset, the chip enters a 60 ms initialization period,
during this period the controller performs refreshes every
13 ms or 15 ms, this makes further DRAM warm up cycles
unnecessary. After this stage the chip can be repro-
grammed as many times as the user wishes and the 60 ms
period will not be entered into unless the chip is reset and
programmed again.
While performing an External Reset, if the user negates
DISRFSH at least one clock period before negating ML, as
shown in Figure 5b, ML negated will program the
DP8420A/21A/22A with the values in R0–9, C0–9, B0–1
and ECAS0. The 60 ms initialization period will be entered
since it is the first programming after reset. Thigood
way of resetting and programming the part at e.
Make sure the right programming bits are ress
lines before ML is negated.
During the 60 ms initialization period, RFIP is asserted low
and RAS toggles every 13 ms or 15 ms depending on the
programming bit for refresh (C3). CAS will be inactive (logic
1) and the ‘‘Q’’ outputs will count from 0 to 2047 refreshing
the entire DRAM array. The actual initialization time period
e
is given by the following formula. T
4096* (Clock Divisor
The DRC may be Reset and proamed ame on th
fly, but the user must make sure to AccesRefre
is in progress.
Select)* (Refresh Clock Fine Tune)/(DELCLK Frq.)
TL/F/8588–E1
FIGURE 5a. Chip Reset but N
TL/F/8588–E2
IGReset and Programmed
8
3.0 Programming and Resetting (Continued)
3.2 PROGRAMMING METHODS
3.2.1 Mode Load Only Programming
3.2.2 Chip Selected Access Programming
To use this method the user asserts ML enabling the inter-
nal programming register. After ML is asserted, a valid pro-
gramming selection is placed on the address bus, B0, B1
and ECAS0 inputs, then ML is negated. When ML is negat-
ed the programming bits are latched into the internal pro-
gramming register and the DP8420A/21A/22A is pro-
grammed, see Figure 6. When programming the chip, the
controller must not be refreshing, RFIP must be high (1) to
have a successful programming.
The chip can also be programmed by performing a chip
selected access. To program the chip using this method,
ML is asserted, then CS is asserted and a valid program-
ming selection is placed on the address bus. When AREQ is
asserted, the programming bits affecting the wait logic be-
come effective immediately, then DTACK is asserted allow-
ing the access to terminate. After the access, ML is negated
and the rest of the programming bits take effect.
F/8588–G3
FIGURE 6. ML Only Programming
TL/F/8588–G4
FIGRE 7. Accs Programming
9
3.0 Programming and Resetting (Continued)
3.3 PROGRAMMING BIT DEFINITIONS
Symbol
Description
ECAS0
Extend CAS/Refresh Request Select
0
The CASn outputs will be negated with the RASn outputs when AREQ (or AREQB, DP8422A only) is negated.
The WE output pin will function as write enable.
1
The CASn outputs will be negated, during an acccess (Port A (or Port B, DP8422A only)) when their
corresponding ECASn inputs are negated. This feature allows the CAS outputs to be extended beyond the RAS
outputs negating. Scrubbing refreshes are NOT affected. During scrubbing refreshes the CAS outputs will negate
along with the RAS outputs regardless of the state of the ECAS inputs.
The WE output will function as ReFresh ReQuest (RFRQ) when this mode is programmed.
B1
Access Mode Select
0
ACCESS MODE 0: ALE pulsing high sets an internal latch. On the next positive edge of CLK, the access (RAS)
will start. AREQ will terminate the access.
1
ACCESS MODE 1: ADS asserted starts the access (RAS) immediately. AREQ will terminate the acce
B0
0
Address Latch Mode
ADS or ALE asserted for Port A or AREQB asserted for Port B with the appropriate GANT latch t row,
column and bank address.
1
The row, column and bank latches are fall through.
Delay CAS during WRITE Accesses
C9
0
1
CAS is treated the same for both READ and WRITE accesses.
During WRITE accesses, CAS will be asserted by the event that occurs lastted by the internal delay
line or CAS asserted on the positive edge of CLK after RAS is arted.
C8
Row Address Hold Time
e
e
0
1
Row Address Hold Time
Row Address Hold Time
25 ns minimum
15 ns minimum
C7
Column Address Setup Time
e
0
1
Column Address Setup Time
Column Address Setup Time
10 ns miniumum
0 ns minimum
e
C6, C5, C4
RAS and CAS Configuration Modes/ErroScrubbing during fresh
0, 0, 0
RAS0–3 and CAS0–3 are all selected durg an ass. ASn must be asserted for CASn to be asserted.
B0 and B1 are not used during an access. Erscrubbing ring refresh.
0, 0, 1
RAS and CAS pairs are selected n access by B1ECASn must be asserted for CASn to be asserted.
e
e
B1
B1
0 during an acceelend CAS–1.
1 during an access sCAS2–3.
B0 is not used durng an Acce
Error scruresh.
0, 1, 0
RAS anlected dg an access by B0–1. ECASn must be asserted for CASn to be asserted.
e
e
e
e
B1
B1
B1
B1
1,
ess selects RAS0 and CAS0.
ss selects RAS1 and CAS1.
ess selects RAS2 and CAS2.
cess selects RAS3 and CAS3.
Error scrubsh.
0, 1, 1
1, 0, 0
RAS0–3 and CAS0–3 are all selected during an access. ECASn must be asserted for CASn to be asserted.
B1, B0 are not used during an access.
No error scrubbing. (RAS only refreshing)
RAS pairs are selected by B1. CAS0–3 are all selected. ECASn must be asserted for CASn to be asserted.
e
e
B1
B1
0 during an access selects RAS0–1 and CAS0–3.
1 during an access selects RAS2–3 and CAS0–3.
B0 is not used during an access.
No error scrubbing.
10
3.0 Programming and Resetting (Continued)
3.3 PROGRAMMING BIT DEFINITIONS (Continued)
Symbol
Description
C6, C5, C4
RAS and CAS Configuration Modes (Continued)
1, 0, 1
RAS and CAS pairs are selected by B1. ECASn must be asserted for CASn to be asserted.
e
e
B1
B1
0 during an access selects RAS0–1 and CAS0–1.
1 during an access selects RAS2–3 and CAS2–3.
B0 is not used during an access.
No error scrubbing.
1, 1, 0
RAS singles are selected by B0–1. CAS0–3 are all selected. ECASn must be asserted for CASn to be
asserted.
e
e
e
e
e
e
e
e
B1
B1
B1
B1
0, B0
0, B0
1, B0
1, B0
0 during an access selects RAS0 and CAS0–3.
1 during an access selects RAS1 and CAS0–3.
0 during an access selects RAS2 and CAS0–3.
1 during an access selects RAS3 and CAS0–3.
No error scrubbing.
1, 1, 1
RAS and CAS singles are selected by B0, 1. ECASn must be asserted for CASn to be
e
e
e
e
e
e
e
e
B1
B1
B1
B1
0, B0
0, B0
1, B0
1, B0
0 during an access selects RAS0 and CAS0.
1 during an access selects RAS1 and CAS1.
0 during an access selects RAS2 and CAS2.
1 during an access selects RAS3 and CAS3.
No error scrubbing.
C3
Refresh Clock Fine Tune Divisor
e
e
e
e
0
Divide delay line/refresh clock further by 30 (If DELCK/Refresh ck Dior
refresh period).
2 MHz
2 MHz
15 ms
13 ms
1
Divide delay line/refresh clock further by 26 (If DELCLK/Resh ClClock Dsor
refresh period).
C2, C1, C0
Delay Line/Refresh Clock Divisor Select
0, 0, 0
0, 0, 1
0, 1, 0
0, 1, 1
1, 0, 0
1, 0, 1
1, 1, 0
1, 1, 1
Divide DELCLK by 10 to get as close to 2 MH
Divide DELCLK by 9 to get as close to 2 MHz
Divide DELCLK by 8 to get as close to 2 MHz
Divide DELCLK by 7 to get as close MHz as
Divide DELCLK by 6 to get as cle to 2 MHz as possible.
Divide DELCLK by 5 to get as cse to 2 ossible.
Divide DELCLK by 4 to get as clo2 MHz as ossible.
Divide DELCLK by 3 to s close to 2 MHz apossible.
R9
Refresh MoSel
0
1
RAS0–3 will all athe same time during a refresh.
Stefresh. ring refresh are separated by one positive clock edge. Depending on the
ode chone or two RASs will be asserted.
R8
g Selec
0
selected. The DRAM controller will switch the DRAM column address back to the row
teeing the column address hold time.
1
ning is selected. The DRAM controller will hold the column address on the DRAM address
ss RASs are negated.
R7
WAIT or DTACK Select
0
1
WAIT type output is selected.
DTACK (Data Transfer ACKnowledge) type output is selected.
R6
Add Wait States to the Current Access if WAITIN is Low
0
1
WAIT or DTACK will be delayed by one additional positive edge of CLK.
WAIT or DTACK will be delayed by two additional positive edges of CLK.
11
3.0 Programming and Resetting (Continued)
3.3 PROGRAMMING BIT DEFINITIONS (Continued)
Symbol
R5, R4
0, 0
Description
WAIT/DTACK during Burst (See Section 5.1.2 or 5.2.2)
e
NO WAIT STATES; If R7
0 during programming, WAIT will remain negated during burst portion of access.
e
If R7
1T; If R7
WAIT will negate from the positive edge of CLK after the ECASs have been asserted.
1 programming, DTACK will remain asserted during burst portion of access.
e
0, 1
1, 0
1, 1
0 during programming, WAIT will assert when the ECAS inputs are negated with AREQ asserted.
e
DTACK will assert from the positive edge of CLK after the ECASs have been asserted.
If R7
1 during programming, DTACK will negate when the ECAS inputs are negated with AREQ asserted.
e
WAIT will negate on the negative level of CLK after the ECASs have been asserted.
(/2T; If R7
0 during programming, WAIT will assert when the ECAS inputs are negated with AREQ asserted.
e
DTACK will assert from the negative level of CLK after the ECASs have been asserted.
If R7
1 during programming, DTACK will negate when the ECAS inputs are negated with AREQ asserted.
e
the ECAS inputs are asserted.
0T; If R7
0 during programming, WAIT will assert when the ECAS inputs are negated. WAIT will negate when
e
the ECAS inputs are asserted.
If R7
1 during programming, DTACK will negate when the ECAS inputs are negated. DTACK will
R3, R2
WAIT/DTACK Delay Times (See Section 5.1.1 or 5.2.1)
e
NO WAIT STATES; If R7 0 during programming, WAIT will remain high during non-deaccesseAIT
will negate when RAS is negated during delayed accesses.
0, 0
e
NO WAIT STATES; If R7
1 during programming, DTACK will be asserted when RS is assert
e
(/2T; If R7
0, 1
1, 0
0 during programming, WAIT will negate on the negative level of access S.
e
1T; If R7
1 during programming, DTACK will be asserted on the positive eafter he access RAS.
e
NO WAIT STATES, (/2T; If R7
WAIT will negate on the negative level of CLK, after the access RASuring ded access.
0 during programming, WAIT wilmain hignon-deyed accesses.
e
(/2T; If R7
1 during programming, DTACK will be asserted on the negve leveLter the access RAS.
e
0 during programming, WAIT will negate on the positive edge oLK after the access RAS.
1, 1
1T; If R7
e
of CLK after the access RAS.
1(/2T; If R7
1 during programming, DTACK will be assertgative el of CLK after the positive edge
R1, R0
RAS Low and RAS Precharge Time
e
0, 0
RAS asserted during refresh
2 positive edges CLK.
1 positive edge of CL.
RAS will start from the first positive edge of LK after TB transitions (DP8422A).
e
RAS precharge time
e
0, 1
1, 0
1, 1
RAS asserted during refresh
3 positive eCLK.
2 positive edges of CLK.
RAS will start from the cond pof CLGRANTB transitions (DP8422A).
e
RAS precharge time
e
RAS asserted during refre
s of CLK.
2 pos.
RAS will starrst positafter GRANTB transitions (DP8422A).
e
RAS precharge time
e
RAS ass
4 pges of CLK.
ve edgeof CLK.
RAS wositive edge of CLK after GRANTB transitions (DP8422A).
RAS pr
12
4.0 Port A Access Modes
The DP8420A/21A/22A have two general purpose access
modes. Mode 0 RAS synchronous and Mode 1 RAS asyn-
chronous. One of these modes is selected at programming
through the B1 input. A Port A access to DRAM is initiated
by two input signals: ADS (ALE) and CS. The access is al-
ways terminated by one signal: AREQ. These input signals
should be synchronous to the input clock.
first rising edge of clock. If a refresh or a Port B access is in
progress or precharge time is required, the controller will
wait until these events have taken place and assert RAS
(RASs) on the next positive edge of clock.
Sometime after the first positive edge of clock after ALE and
CS have been asserted, the input AREQ must be asserted.
In single port applications, once AREQ is asserted, CS can
be negated. On the other hand, ALE can stay asserted sev-
eral periods of clock; however, ALE must be negated before
or during the period of CLK in which AREQ is negated.
4.1 ACCESS MODE 0
Mode 0, synchronous access, is selected by negating the
e
input B1 during programming (B1 0). To initiate a Mode 0
The controller samples AREQ on the every rising edge of
clock after DTACK is asserted. The access will end when
AREQ is sampled negated.
access, ALE is pulse high and CS is asserted. If precharge
time was met, a refresh of DRAM or a Port B access was
not in progress, the RAS (RASs) would be asserted on the
TL/F/8588–60
GURE 8a. Access ode 0
13
4.0 Port A Access Modes (Continued)
en place and assert RAS (RASs) from the next rising edge
of clock.
4.2 ACCESS MODE 1
Mode 1, asynchronous access, is selected by asserting the
e
When ADS is asserted or sometime after, AREQ must be
asserted. At this time, ADS can be negated and AREQ will
continue the access. Also, ADS can continue to be asserted
after AREQ has been asserted and negated; however, a
new access will not start until ADS is negated and asserted
again. When address pipelining is not implemented, ADS
and AREQ can be tied together.
input B1 during programming (B1 1). This mode allows ac-
cesses to start immediately from the access request input,
ADS. To initiate a Mode 1 access, CS is asserted followed
by ADS asserted. If precharge time was met, a refresh of
the DRAM or a Port B access was not in progress, the RAS
(RASs) would be asserted from ADS being asserted. If a
refresh or Port B access is in progress or precharge time is
required, the controller will wait until these events have tak-
The access will end when AREQ is negated.
TL/F/8588–62
FIGURE 8b. Access
14
4.0 Port A Access Modes (Continued)
with AREQ. If ECAS0 was negated (1) during programming,
CAS (CASs) will continue to be asserted after RAS has
been negated, given that the appropriate ECAS inputs are
asserted. This allows a DRAM to have data present on the
data out bus while gaining RAS precharge time.
4.3 EXTENDING CAS WITH EITHER ACCESS MODE
In both access modes, once AREQ is negated, RAS and
DTACK if programmed will be negated. If ECAS0 was as-
serted (0) during programming, CAS (CASs) will be negated
TL/F/8588–61
FIGURE 9a. Access Mode 0 ExtendCAS
TL/F/8588–63
FIGURE 9b. Access Mode 1 Extending CAS
15
4.0 Port A Access Modes (Continued)
4.4 READ-MODIFY-WRITE CYCLES WITH EITHER ACCESS MODE
There are 2 methods by which this chip can be used to do
read-modify-write access cycles. The first method involves
doing a late write access where the WIN input is asserted
some delay after CAS is asserted. The second method in-
volves doing a page mode read access followed by a page
mode write access with RAS held low (see Figure 9c ).
WIN from negated to asserted in a late write access be-
cause here a problem may arise with DATA IN and DATA
OUT being valid at the same time. This may result in a data
line trying to drive two different levels simultaneously. The
page mode method of a read-modify-write access allows
the user to have transceivers in the system because the
data in (read data) is guaranteed to be high impedance dur-
ing the time the data out (write data) is valid.
CASn must be toggled using the ECASn inputs and WIN has
to be changed from negated to asserted (read to write)
while CAS is negated. This method is better than changing
TL/F/8588–G2
*There may be idle states inserted here by the CPU.
FIGURE 9cRead-Modify-Write ccess Cycle
16
4.0 Port A Access Modes (Continued)
In Mode 1, the address latches are in fall through mode until
ADS is asserted. ADS asserted latches the address.
4.5 ADDITIONAL ACCESS SUPPORT FEATURES
To support the different modes of accessing, the
DP8420A/21A/22A offer other access features. These ad-
ditional features include: Address Latches and Column In-
crement (for page/burst mode support), Address Pipelining,
and Delay CAS (to allow the user with a multiplexed bus to
ensure valid data is present before CAS is asserted).
Once the address is latched, the column address can be
incremented with the input COLINC. COLINC can be used
for sequential accesses of static column DRAMs. COLINC
can also be used with the ECAS inputs to support sequen-
tial accesses to page mode DRAMs as shown in Figure 10.
COLINC should only be asserted when the signal RFIP is
negated during an access since this input functions as ex-
tended refresh when RFIP is asserted. COLINC must be
negated (0) when the address is being latched (ADS falling
edge in Mode 1). If COLINC is asserted with all of the bits of
the column address asserted (ones), the column address
will return to zero.
4.5.1 Address Latches and Column Increment
The Address Latches can be programmed, through pro-
gramming bit B0. They can be programmed to either latch
the address or remain in a fall-through mode. If the address
latches are used to latch the address, the controller will
function as follows:
In Mode 0, the rising edge of ALE places the latches in fall-
through, once ALE is negated, the address present in the
row, column and bank input is latched.
TL/F/8588–C4
FIGURE 10. C
The address latches function differently with the DP8422A.
The DP8422A will latch the address of the currently aned
port. If Port A is currently granted, the addres will be
latched as described in Section 4.5.1. If Port A inot gra
ed, and requests an access, the address will be on
the first or second positive edge of CLK after GRANTB has
been negated depending on e progts R0, 1.
, if GRANTB is asserted, the address will be
ith AREQB asserted. If GRANTB is negated, the
address will latch on the first or second positive edge of
CLK after GRANTB is asserted depending on the program-
ming bits R0, R1.
17
4.0 Port A Access Modes (Continued)
During address pipelining in Mode 0, shown in Figure 11c,
ALE cannot be pulsed high to start another access until
AREQ has been asserted for the previous access for at
least one period of CLK. DTACK, if programmed, will be
negated once AREQ is negated. WAIT, if programmed to
insert wait states, will be asserted once ALE and CS are
asserted.
4.5.2 Address Pipelining
Address pipelining is the overlapping of accesses to differ-
ent banks of DRAM. If the majority of successive accesses
are to a different bank, the accesses can be overlapped.
Because of this overlapping, the cycle time of the DRAM
accesses are greatly reduced. The DP8420A/21A/22A can
be programmed to allow a new row address to be placed on
the DRAM address bus after the column address hold time
has been met. At this time, a new access can be initiated
with ADS or ALE, depending on the access mode, while
AREQ is used to sustain the current access. The DP8422A
supports address pipelining for Port A only. This mode can-
not be used with page, static column or nibble modes of
operations because the DRAM column address is switched
back to the row address after CAS is asserted. This mode is
programmed through address bit R8 (see Figures 11a and
11b). In this mode, the output WE always functions as
RFRQ.
In Mode 1, shown in Figure 11d, ADS can be negated once
AREQ is asserted. After meeting the minimum negated
pulse width for ADS, ADS can again be asserted to start a
new access. DTACK, if programmed, will be negated once
AREQ is negated. WAIT, if programmed, will be asserted
once ADS is asserted.
In either mode with either type of wait programmed, the
DP8420A/21A/22A will still delay the access for precharge
if sequential accesses are to the same bank or if a refresh
takes place.
TL/F/8588–G0
FIGURE 11a. Non-Address Pipelined M
TL/F/8588–G1
GURE 1b. Address Pipelined Mode
18
4.0 Port A Access Modes (Continued)
19
4.0 Port A Access Modes (Continued)
4.5.3 Delay CAS during Write Accesses
Address bit C9 asserted during programming will cause CAS
to be delayed until the first positive edge of CLK after RAS
is asserted when the input WIN is asserted. Delaying CAS
during write accesses ensures that the data to be written to
DRAM will be setup to CAS asserting as shown in Figures
12a and 12b. If the possibility exists that data still may not
be present after the first positive edge of CLK, CAS can be
delayed further with the ECAS inputs. If address bit C9 is
negated during programming, read and write accesses will
be treated the same (with regard to CAS).
TL/F/8588–C7
FIGURE 12a. Mode 0 Delay CAS
TL/F/8588–C8
FIGURE 12b. Mode 1 Delay CAS
20
5.0 Refresh Options
The DP8420A/21A/22A support three refresh control mode
options:
In every combination of refresh control mode and refresh
type, the DP8420A/21A/22A is programmed to keep RAS
asserted a number of CLK periods. The time values of RAS
low during refresh are programmed through programming
bits R0 and R1.
1. Automatic Internally Controlled Refresh.
2. Externally Controlled/Burst Refresh.
3. Refresh Request/Acknowledge.
5.1 REFRESH CONTROL MODES
5.1.1. Automatic Internal Refresh
With each of the control modes above, three types of re-
fresh can be performed.
1. All RAS Refresh.
The DP8420A/21A/22A have an internal refresh clock. The
period of the refresh clock is generated from the program-
ming bits C0–3. Every period of the refresh clock, an inter-
nal refresh request is generated. As long as a DRAM ac-
cess is not currently in progress and precharge time has
been met, the internal refresh request will generate an auto-
matic internal refresh. If a DRAM access is in progress, the
DP8420A/21A/22A on-chip arbitration logic will wait until
the access is finished before performing the refresh. The
refresh/access arbitration logic can efresh cycle
between two address pipelined accever, the re-
fresh arbitration logic can not inteccesycle to
perform a refresh. To able automernally cntrolled
refreshes, the input DISRH must egated.
2. Staggered Refresh.
3. Error Scrubbing During All RAS Refresh.
There are three inputs, EXTNDRF, RFSH and DISRFSH,
and two outputs, RFIP and RFRQ, associated with refresh.
There are also ten programming bits: R0–1, R9, C0–6 and
ECAS0 used to program the various types of refreshing.
Asserting the input EXTNDRF, extends the refresh cycle for
a single or multiple integral periods of CLK.
The output RFIP is asserted one period of CLK before the
first refresh RAS is asserted. If an access is currently in
progress, RFIP will be asserted up to one period of CLK
before the first refresh RAS, after AREQ or AREQB is nega-
ted for the access (see Figure 13 ).
The DP8420A/21A/22A will increment the refresh address
counter automatically, independent of the refresh mode
used. The refresh address counter will be incremented once
all the refresh RASs have been negated.
TL/F/8588–F8
Explanation of Terms
e
e
RFRQ
RFSH
ReFresh ReQuest internal to the DP842021A/22A. RFRQ has the ability to hold off a pending access.
Externally requested ReFreSH
ReFresh in Progress
e
RFIP
ACIP
e
Port A or Port B (DP422A onin Progress. Tmeans that either RAS is low for an access or is in the process of
transitioning low for acce
FIGURE 22A Access/Refresh Arbitration State Program
21
5.0 Refresh Options (Continued)
5.1.2 Externally Controlled/Burst Refresh
take place on the next positive edge of CLK as shown in
Figure 14a. If an access to DRAM is in progress or pre-
charge time for the last access has not been met, the re-
fresh will be delayed. Since pulsing RFSH low sets a latch,
the user does not have to keep RFSH low until the refresh
starts. When the last refresh RAS negates, the internal re-
fresh request latch is cleared.
To use externally controlled/burst refresh, the user must
disable the automatic internally controlled refreshes by as-
serting the input DISRFSH. The user is responsible for gen-
erating the refresh request by asserting the input RFSH.
Pulsing RFSH low, sets an internal latch, that is used to
produce the internal refresh request. The refresh cycle will
TL/F/8588–64
FIGURE 14a. Single External Refreshes (2 Periods of RAS Low during Refrgramme
By keeping RFSH asserted past the positive edge of CLK
which ends the refresh cycle as shown in Figure 14b, the
user will perform another refresh cycle. Using this tech-
nique, the user can perform a burst refresh consisting of any
number of refresh cycles. Each refresh cycle during a burst
refresh will meet the refresh RAS low time and the RAS
precharge time (programming bits R0–1).
If the user desires to bthe entire DRAM (all row
addressese could gn end count signal (burst
refresh
fined)
b
oking
one
of
the
DP8420A/21A/A high dress outs (Q7, Q8, Q9 or
Q10) and the RFIutput. n outputs function as a
decode of ow many w addresses have been refreshed
fres
e
24 refreshes).
e
512 re-
(Q7
hes, Q
256 refreshes, Q9
TL/F/8588–65
FIGURE 14b. Eresh (2 Periods of RAS Precharge,
ds of Rw during Refresh Programmed)
22
5.0 Refresh Options (Continued)
5.1.3 Refresh Request/Acknowledge
The DP8420A/21A/22A can be programmed to output in-
ternal refresh requests. When the user programs ECAS0
negated (1) and/or address pipelining mode is selected, the
WE output functions as RFRQ. RFRQ (WE) will be asserted
by one of two events:
First, if DISRFSH is negated, an automatic internal refresh
will take place. See Figure 15b.
Second, with DISRFSH asserted, RFRQ will stay asserted
until RFSH is pulsed low . This option will cause an external-
ly requested/burst refresh to take place. See Figure 15c.
First, when the external circuitry pulses low the input RFSH
which will request an external refresh.
RFRQ will go high and then assert (toggle) if additional peri-
ods of the internal refresh clock have expired and neither an
externally controlled refresh nor an automatically controlled
internal refresh have taken place, see Figure 15d. If a time
critical event, or long accesses like page/static column
mode can not be interrupted, RFRQ pulsing high can be
used to increment a counter. This counter can be used to
perform a burst refresh of the number of refreshes missed
(through the RFSH input).
Second, when the internal refresh clock has expired, which
signals that another refresh is needed.
An example of the first case, where an external refresh is
requested while RFRQ is negated (1), is shown in Figure
15a. Notice that RFRQ will be asserted from a positive edge
of clock.
On the second case, when the RFRQ is asserted from the
expiration of the internal refresh clock, the user has two
options:
TL/F/8588–66
FIGURE 15a. Externally Controlled Singfresh th Refresh Request
(RFRQ) Output (2 Periods of RAresh Programmed)
TL/F/8588–67
FIGURal Refresh with Refresh Request (3T of RAS Low during Refresh Programmed)
23
5.0 Refresh Options (Continued)
24
5.0 Refresh Options (Continued)
5.2 REFRESH CYCLE TYPES
Three different types of refresh cycles are available for use.
The three different types are mutually exclusive and can be
used with any of the three modes of refresh control. The
three different refresh cycle types are: all RAS refresh, stag-
gered RAS refresh and error scrubbing during all RAS re-
fresh. In all refresh cycle types, the RAS precharge time is
guaranteed: between the previous access RAS ending and
the refresh RAS0 starting; between refresh RAS3 ending
and access RAS beginning; between burst refresh RASs.
5.2.1 Conventional RAS Refresh
A conventional refresh cycle causes RAS0–3 to all assert
from the first positive edge of CLK after RFIP is asserted as
shown in Figure 16. RAS0–3 will stay asserted until the
number of positive edges of CLK programmed have passed.
On the last positive edge, RAS0–3, and RFIP will be negat-
ed. This type of refresh cycle is programmed by negating
address bit R9 during programming.
TL/F/8588–69
FIGURE 16. Conventional RAS resh
5.2.2 Staggered RAS Refresh
A staggered refresh staggers each RAS or group of RASs
by a positive edge of CLK as shown in Figure 17. The num-
ber of RASs, which will be asserted on each positive edge
of CLK, is determined by the RAS, CAS configuration mode
programming bits C4–C6. If single RAS outputs aselect-
ed during programming, then each RAS will asst on suc-
cessive positive edges of CLK. If two RAS outps are
lected during programming then RAS0 and RAS1 ssert
t posite edge of CLK after RFIP is asserted.
RAS3 will assert on the second positive edge of
FIP is asserted. If all RAS outputs were selected
ramming, all RAS outputs would assert on the
tive edge of CLK after RFIP is asserted. Each RAS
or group of RASs will meet the programmed RAS low time
and then negate.
TL/F/8588–70
FIGURE 17. Staggered RAS Refresh
25
5.0 Refresh Options (Continued)
5.2.3 Error Scrubbing during Refresh
tend refresh, EXTNDRF, and a read-modify-write operation
can be performed by asserting WE. It is the responsibility of
the designer to ensure that WE is negated. The DP8422A
has a 24-bit internal refresh address counter that contains
The DP8420A/21A/22A support error scrubbing during all
RAS DRAM refreshes. Error scrubbing during refresh is se-
lected through bits C4–C6 with bit R9 negated during pro-
gramming. Error scrubbing can not be used with staggered
refresh (see Section 8.0). Error scrubbing during refresh al-
lows a CAS or group of CASs to assert during the all RAS
refresh as shown in Figure 18. This allows data to be read
from the DRAM array and passed through an Error Detec-
tion And Correction Chip, EDAC. If the EDAC determines
that the data contains a single bit error and corrects that
error, the refresh cycle can be extended with the input ex-
the 11 row, 11 column and
2 bank addresses. The
DP8420A/21A have a 22-bit internal refresh address coun-
ter that contains the 10 row, 10 column and 2 bank address-
es. These counters are configured as bank, column, row
with the row address as the least significant bits. The bank
counter bits are then used with the programming selection
to determine which CAS or group of CASs will assert during
a refresh.
TL/F/8588–46
FIGURE 18. Error Scrubbing during Refresh
26
5.0 Refresh Options (Continued)
5.3 EXTENDING REFRESH
5.4 CLEARING THE REFRESH ADDRESS COUNTER
The programmed number of periods of CLK that refresh
RASs are asserted can be extended by one or multiple peri-
ods of CLK. Only the all RAS (with or without error scrub-
bing) type of refresh can be extended. To extend a refresh
cycle, the input extend refresh, EXTNDRF, must be assert-
ed before the positive edge of CLK that would have negated
all the RAS outputs during the refresh cycle and after the
positive edge of CLK which starts all RAS outputs during the
refresh as shown inFigure 19. This will extend the refresh to
the next positive edge of CLK and EXTNDRF will be sam-
pled again. The refresh cycle will continue until EXTNDRF is
sampled low on a positive edge of CLK.
The refresh address counter can be cleared by asserting
RFSH while DISRFSH is negated as shown in Figure 20a.
This can be used prior to a burst refresh of the entire memo-
ry array. By asserting RFSH one period of CLK before
DISRFSH is asserted and then keeping both inputs assert-
ed, the DP8420A/21A/22A will clear the refresh address
counter and then perform refresh cycles separated by the
programmed value of precharge as shown in Figure 20b. An
end-of-count signal can be generated from the Q DRAM
address outputs of the DP8420A/21A/22A and used to ne-
gate RFSH.
TL/F/8588–71
FIGURE 19. Extending Refresh with the End RefreDRF) put
TL/F/8588–72
FIGURE 20a. Caring the Rress Counter
TL/F/8588–73
FIGURE 20b. Clearing the Refresh Counter during Burst
27
5.0 Refresh Options (Continued)
refresh request clock, the user is guaranteed that an inter-
nal refresh request will not be generated for approximately
15 ms, one refresh clock period, from the time RFSH is neg-
ated. This action will also clear the refresh address counter.
5.5 CLEARING THE REFRESH REQUEST CLOCK
The refresh request clock can be cleared by negating
DISRFSH and asserting RFSH for 500 ns, one period of the
internal 2 MHz clock as shown in Figure 21. By clearing the
TL/F/8588–75
FIGURE 21. Clearing the Refresh Request Clock Counter
6.0 Port A Wait State Support
Wait states allow a CPU’s access cycle to be increased by
one or multiple CPU clock periods. The wait or ready input is
named differently by CPU manufacturers. However, any
CPU’s wait or ready input is compatible with either the WAIT
or DTACK output of the DP8420A/21A/22A. The user de-
termines whether to program WAIT or DTACK (R7) and
which value to select for WAIT or DTACK (R2, R3) depend-
ing upon the CPU used and where the CPU samples its wait
input during an access cycle.
length of the CPU’s access. Once the event has been com-
pleted, the DP8420A/21A/22A will allow the access to take
place and stop inserting wait states.
There are six programming bits, R2–R7; an IN;
and an output that functions as WAIT or D
6.1 WAIT TYPE OUTPUT
With the R7 address bit negated ng progrming, e
user selects the WAIT output. As long WAIT is sampled
asserted by the CPU, wait states (extra ck periods) are
inserted into the current cle as sin Figure
22. Once WAIT is samd, the access cycle is
completed y the CPUssertat the beginning of
a chip seled accesis progrmmed to negate a
number of poe edgnd/or native levels of CLK
from the event tstarts ss. WAIT can also be
programmed to funn in page/burst mode applications.
Once negateuring an access, and the ECAS
inpuwith AQ asserted, WAIT can be pro-
graollowing the ECAS inputs. Once AREQ
is ne access, WAIT will stay negated until
the nd access. For more details about WAIT
Type OApplication Note AN-773.
The decision to terminate the CPU access cycle is directly
affected by the speed of the DRAMs used. The system de-
signer must ensure that the data from the DRAMs will be
present for the CPU to sample or that the data has been
written to the DRAM before allowing the CPU access cycle
to terminate.
The insertion of wait states also allows a CPU’s access cy-
cle to be extended until the DRAM access has taken place.
The DP8420A/21A/22A insert wait states into CPU access
cycles due to; guaranteeing precharge time, refresh current-
ly in progress, user programmed wait states, the WAITIN
signal being asserted and GRANTB not being valid
(DP8422A only). If one of these events is taking place and
the CPU starts an access, the DP8420A/21A/22A will inse
wait states into the access cycle, thereby increasing t
TL/F/8588–76
FIGURE 22. WAIT Type Output
28
6.0 Port A Wait State Support (Continued)
6.2 DTACK TYPE OUTPUT
6.3 DYNAMICALLY INCREASING THE
NUMBER OF WAIT STATES
With the R7 address bit asserted during programming, the
user selects the DTACK type output. As long as DTACK is
sampled negated by the CPU, wait states are inserted into
the current access cycle as shown in Figure 23. Once
DTACK is sampled asserted, the access cycle is completed
by the CPU. DTACK, which is normally negated, is pro-
grammed to assert a number of positive edges and/or neg-
ative levels from the event that starts RAS for the access.
DTACK can also be programmed to function during page/
burst mode accesses. Once DTACK is asserted and the
ECAS inputs are negated with AREQ asserted, DTACK can
be programmed to negate and assert from the ECAS inputs
toggling to perform a page/burst mode operation. Once
AREQ is negated, ending the access, DTACK will be negat-
ed and stays negated until the next chip selected access.
For more details about DTACK type output see Application
Note AN-773.
The user can increase the number of positive edges of CLK
before DTACK is asserted or WAIT is negated. With the
input WAITIN asserted, the user can delay DTACK asserting
or WAIT negating either one or two more positive edges of
CLK. The number of edges is programmed through address
bit R6. If the user is increasing the number of positive edges
in a delay that contains a negative level, the positive edges
will be met before the negative level. For example if the user
programmed DTACK of (/2T, asserting WAITIN, pro-
grammed as 2T, would increase the number of positive edg-
es resulting in DTACK of 2(/2T as shown inFigure 24a. Simi-
larly, WAITIN can increase the number of positive edges in
a page/burst access. WAITIN can be permanently asserted
in systems requiring an increased number of wait states.
WAITIN can also be asserted and negated, depending on
the type of access. As an example, d invert the
WRITE line from the CPU and e output to
WAITIN. This could be used to peaccees with
1 wait state and read aesss witt states shown
in Figure 24b.
TL/F/8588–97
FIGU. DTACput
TL/F/8588–C1
FIGURE 24a. WAITIN Example (DTACK is Sampled at the ‘‘T3’’ Falling Clock Edge)
29
6.0 Port A Wait State Support (Continued)
/8588–C
FIGURE 24b. WAITIN Example (WAIT is Sampled at the End of ‘‘T2’’).
6.4 GUARANTEEING RAS LOW TIME
AND RAS PRECHARGE TIME
The DP8420A/21A/22A will guarantee RAS precharge time
between accesses; between refreshes; and between ac-
cess and refreshes. The programming bits R0 and R1 are
used to program combinations of RAS precharge time and
RAS low time referenced by positive edges of CLK. RAS
low time is programmed for refreshes only. During an ac-
cess, the system designer guarantees the time RAS is as-
serted through the DP8420A/21A/22A wait logic. Since in-
serting wait states into an access increases the length of
the CPU signals which are used to create ADS or ALE and
AREQ, the time that RAS is asserted can be guaranteed.
tive edge oCLK couns negted setup to a posi-
tive edge CLK to e the aess. That positive
edge is 1T. Tnext pe edge i2T. RAS will not be
asserted until the ogramnumr of positive edges of
CLK have passed shown in Figure 25. Once the pro-
grammarge tihas been met, RAS will be assert-
ed fre edge CLK. However, since there is a
preer RAS, an access using another RAS
will Precharge time before a refresh is al-
wayom the access RAS negating before
RAS0 sh asserting. After a refresh, precharge
time is refernced from RAS3 negating, for the refresh, to
ess RAS asserting.
The precharge time is also guaranteed by t
DP8420A/21A/22A. Each RAS output has a separate po-
TL/F/8588–C3
FIGURE 25. Guaranteeing RAS Precharge (DTACK is Sampled at the ‘‘T2’’ Falling Clock Edge)
30
7.0 RAS and CAS Configuration Modes
The DP8420A/21A/22A allow the user to configure the
DRAM array to contain one, two or four banks of DRAM.
Depending on the functions used, certain considerations
must be used when determining how to set up the DRAM
array. Programming address bits C4, C5 and C6 along with
bank selects, B0–1, and CAS enables, ECAS0–3, deter-
mine which RAS or group of RASs and which CAS or group
of CASs will be asserted during an access. Different memo-
ry schemes are described. The DP8420A/21A/22A is spec-
ified driving a heavy load of 72 DRAMs, representing four
banks of DRAM with 16-bit words and 2 parity bits. The
DP8420A/21A/22A can drive more than 72 DRAMs, but the
AC timing must be increased. Since the RAS and CAS out-
puts are configurable, all RAS and CAS outputs should be
used for the maximum amount of drive.
7.1 BYTE WRITING
By selecting a configuration in which all CAS outputs are
selected during an access, the ECAS inputs enable a single
or group of CAS outputs to select a byte (or bytes) in a word
size of up to 32 bits. In this case, the RAS outputs are used
to select which of up to 4 banks is to be used as shown in
Figures 26a and 26b. In systems with a word size of 16 bits,
the byte enables can be gated with a high order address bit
to produce four byte enables which gives an equivalent to 8
banks of 16-bit words as shown inFigure 26d. If less memo-
ry is required, each CAS should be used to drive each nibble
in the 16-bit word as shown in Figure 26c.
TL/F/8588–C9
e
FIGURE 26a. DRAM Array Setup f32-Bit System , C4
1, 1, 0 during Programming)
TL/F/8588–D0
e
0, 1, 1 No Error Scrubbing during Programming)
FIGURE 26b. DRAM Array Setup for 32-Bit, 1 Bank System (C6, C5, C4
e
0, 0, 0 Allowing Error Scrubbing
or C6, C5, C4
31
7.0 RAS and CAS Configuration Modes (Continued)
TL/
e
FIGURE 26c. DRAM Array Setup for 16-Bit System (C6, C5, C4
1, 1, 0 during Pramming
TL/F/8588–D2
e
FIGURE 26d. 8 Bank DRAM ystem (C6, C5, C4
1, 1, 0 during Programming)
32
7.0 RAS and CAS Configuration Modes (Continued)
7.2 MEMORY INTERLEAVING
7.3 ADDRESS PIPELINING
Memory interleaving allows the cycle time of DRAMs to be
reduced by having sequential accesses to different memory
banks. Since the DP8420A/21A/22A have separate pre-
charge counters per bank, sequential accesses will not be
delayed if the accessed banks use different RAS outputs.
To ensure different RAS outputs will be used, a mode is
selected where either one or two RAS outputs will be as-
serted during an access. The bank select or selects, B0 and
B1, are then tied to the least significant address bits, caus-
ing a different group of RASs to assert during each sequen-
tial access as shown in Figure 27. In this figure there should
be at least one clock period of all RAS’s negated between
different RAS’s being asserted to avoid the condition of a
CAS before RAS refresh cycle.
Address pipelining allows several access RASs to be as-
serted at once. Because RASs can overlap, each bank re-
quires either a mode where one RAS and one CAS are used
per bank as shown in Figure 28a or where two RASs and
two CASs are used per bank as shown in Figure 28b. Byte
writing can be accomplished in a 16-bit word system if two
RASs and two CASs are used per bank. In other systems,
WEs (or external gating on the CAS outputs) must be used
to perform byte writing. If WEs are used separate data in
and data out buffers must be used. If the array is not layed
out this way, a CAS to a bank can be low before RAS, which
will cause a refresh of the DRAM, not an access. To take
full advantage of address pipelining, memory interleaving is
used. To memory interleave, the least significant address
bits should be tied to the bank select inputs to ensure that
all ‘‘back to back’’ sequential accesses are not delayed,
since different memory banks are ac
TL/F/8588–D3
e
FIGURE aving (C6, C5, C4
1, 1, 0 during Programming)
33
7.0 RAS and CAS Configuration Modes (Continued)
TL/F/8588–D4
e
FIGURE 28a. DRAM Array Setup for 4 Banks Using Address Pipelining (C6, C5, C4
e
1, 1, 1
or C6, C5, C4
0, 1, 0 (Also Allowing Error Scrubbing) during Programming)
TL//8588–D5
e
0, 0, 1 (Also Allowing Error Scrubbing) ing Prmming)
FIGURE 28b. DRAM Array Setup for Address Pipelining witBanks (C4
e
1, 1
or C6, C5, C4
7.4 ERROR SCRUBBING
In error scrubbing during refresh, the user selects one, two
or four RAS and CAS outputs per bank. When performing
error detection and correction, memory is always accessed
as wordce the S signals are not used to select
indive ECAnputs can be tied low as shown
in F9b.
TL/F/8588–D6
e
FIGURE 29a. DBanks Using Error Scrubbing (C6, C5, C4
0, 1, 0 during Programming)
TL/F/8588–D7
e
FIGURE 29b. DRAM Array Setup for Error Scrubbing with 2 Banks (C6, C5, C4
0, 0, 1 during Programming)
34
7.0 RAS and CAS Configuration Modes (Continued)
7.5 PAGE/BURST MODE
In a static column, page or burst mode system, the least
significant bits must be tied to the column address in order
to ensure that the page/burst accesses are to sequential
memory addresses, as shown in Figure 30. In a nibble
mode system, the least significant bits must be tied to the
highest column and row address bits in order to ensure that
sequential address bits are the ‘‘nibble’’ bits for nibble mode
accesses (Figure 30). The ECAS inputs may then be tog-
gled with the DP8420A/21A/22A’s address latches in fall-
through mode, while AREQ is asserted. The ECAS inputs
can also be used to select individual bytes. When using nib-
ble mode DRAMS, the third and fourth address bits can be
tied to the bank select inputs to perform memory interleav-
ing. In page or static column modes, the two address bits
after the page size can be tied to the bank select inputs to
select a new bank if the page size is exceeded.
TL/F/8588–D8
*See table below for row, column & bank address bit map. A0, A1 are used for byte addressing in example.
Page olumn e Page Size
Addresses
Nibble Mode*
256 Bits/Page 024 Bits/Page 2048 Bits/Page
e
e
e
0–9 A2–11
Column
Address
C9,R9
A2,A3 C0–7
A2–9
e
C0–10
A2–12
e
e
C10 X
C0–8
X
C8–10
X
Row
X
X
X
X
X
Address
B0
B1
A4
A5
A11
A11
A12
A12
A13
A13
A14
Assume that tast sbits afor byte addressing. Given a 32-bit system A0,A1 would be
used for byte addin
e
X
DON’T CARE, teases.
*alues for system using 1 Mbit DRAMs.
FIGUe, Static Column, Nibble Mode System
35
8.0 Test Mode
Staggered refresh in combination with the error scrubbing
mode places the DP8420A/21A/22A in test mode. In this
mode, the 24-bit refresh counter is divided into a 13-bit and
11-bit counter. During refreshes both counters are incre-
mented to reduce test time.
9.2 CALCULATION OF t
RAH
AND t
ASC
There are two clock inputs to the DP8420A/21A/22A.
These two clocks, DELCLK and CLK can either be tied to-
gether to the same clock or be tied to different clocks run-
ning asynchronously at different frequencies.
The clock input, DELCLK, controls the internal delay line
and refresh request clock. DELCLK should be a multiple of
9.0 DRAM Critical Timing
Parameters
The two critical timing parameters, shown in Figure 31, that
2 MHz. If DELCLK is not a multiple of 2 MHz, t
and t
ASC
and t
RAH ASC
can be calcu-
will change. The new values of t
lated by the following formulas:
RAH
must be met when controlling the access timing to a DRAM
, and the column ad-
RAH
are the row address hold time, t
dress setup time, t
e
was programmed to equal 15 ns then t
RAH
If t
RAH
30*(((DELCLK Divisor)* 2 MHz/(DELCLK Frequency)) 1)
. Since the DP8420A/21A/22A con-
ASC
b
tain a precise internal delay line, the values of these param-
eters can be selected at programming time. These values
will also increase and decrease if DELCLK varies from
2 MHz.
a
15 ns.
e
If t was programmed to equal 25 ns then t
RAH RAH
b
30*(((DELCLK Divisor)* 2 MHz/(DELCLK Frequency)) 1)
a
25 ns.
9.1 PROGRAMMABLE VALUES OF t
RAH
AND t
ASC
If t
ASC
was programmed to equal 0 ns then
5*
ns.
((DELCLK Divisor)* 2 MHz/(DELCLK Frequ
If t was programmed to eqal 10 ns th
The DP8420A/21A/22A allow the values of t
RAH
and t
ASC
e
25*
15 ns
to be selected at programming time. For each parameter,
two choices can be selected. t , the row address hold
ASC
((DELCLK Divisor)* 2 MHz/(DELK reque
b
RAH
time, is measured from RAS asserted to the row address
starting to change to the column address. The two choices
Since the values of t and t
RAH
are incred or -
creased, the time to CAS asserted wilso increase or de-
crease. These parameters can be adjustby the following
formula:
for t
are 15 ns and 25 ns, programmable through ad-
RAH
dress bit C8.
t
, the column address setup time, is measured from the
ASC
e
b
tual t
RAH
Delay to CAS
Programmt
Actual
a
column address valid to CAS asserted. The two choices for
are 0 ns and 10 ns, programmable through address bit
b
A
Prammed t
.
ASC
RAH
C
t
ASC
C7.
TL/F/8588–E3
1. t
RAH
nd t
ASC
36
10.0 Dual Accessing (DP8422A)
The DP8422A has all the functions previously described. In
addition to those features, the DP8422A also has the capa-
bilities to arbitrate among refresh, Port A and a second port,
Port B. This allows two CPUs to access a common DRAM
array. DRAM refresh has the highest priority followed by the
currently granted port. The ungranted port has the lowest
priority. The last granted port will continue to stay granted
even after the access has terminated, until an access re-
quest is received from the ungranted port (see Figure 32a ).
The dual access configuration assumes that both Port A
and Port B are synchronous to the system clock. If they are
not synchronous to the system clock they should be exter-
nally synchronized (Ex. By running the access requests
through several Flip-Flops, see Figure 34a ).
has completed. It is important to note that for GRANTB to
transition to Port B, Port A must not be requesting an ac-
cess at a rising clock edge (or locked) and Port B must be
requesting an access at that rising clock edge. Port A can
request an access through CS and ADS/ALE or CS and
AREQ. Therefore during an interleaved access where CS
and ADS/ALE become asserted before AREQ from the pre-
e
vious access is negated, Port A will retain GRANTB
whether AREQB is asserted or not.
0
Since there is no chip select for Port B, AREQB must incor-
porate this signal. This mode of accessing is similar to Mode
1 accessing for Port A.
10.1 PORT B ACCESS MODE
Port B accesses are initiated from a single input, AREQB.
When AREQB is asserted, an access request is generated.
If GRANTB is asserted and a refresh is not taking place or
precharge time is not required, RAS will be asserted when
AREQB is asserted. Once AREQB is asserted, it must stay
asserted until the access is over. AREQB negated, negates
TL8588–F9
Explanation of Terms
e
RAS as shown inFigure 32b. Note that if ECAS0
1 during
e
e
AREQA
AREQB
Chip Selected acs uest from P
Chip Selected access reqt from Port B
programming the CAS outputs may be held asserted (be-
yond RASn negating) by continuing to assert the appropri-
ate ECASn inputs (the same as Port A accesses). If Port B
is not granted, the access will begin on the first or second
positive edge of CLK after GRANTB is asserted (See R0,
R1 programming bit definitions) as shown in Figure 32c, as-
suming that Port A is not accessing the DRAM (CS, ADS/
ALE and AREQ) and RAS precharge for the particular bank
e
LOCK
Externally ed LOCKinthe ort
that is Ted.
FIGURE A Port A/Port B Arbitration
State Dihis arration may take place
duri‘‘ACCE’’ or ‘‘REFRESH’’
ate (seegure 13a ).
TL/F/8588–E4
2b. Access Request for Port B
TL/F/8588–E5
FIGURE 32c. Delayed Port B Access
37
10.0 Dual Accessing (DP8422A) (Continued)
10.2 PORT B WAIT STATE SUPPORT
Port A or Port B to lock out the other port from the DRAM.
When a Port is locked out of the DRAM, wait states will be
inserted into its access cycle until it is allowed to access
memory. GRANTB is used to multiplex the input control sig-
nals and addresses to the DP8422A.
Advanced transfer acknowledge for Port B, ATACKB, is
used for wait state support for Port B. This output will be
asserted when RAS for the Port B access is asserted, as
shown in Figures 33a and 33b. Once asserted, this output
will stay asserted until AREQB is negated. With external
logic, ATACKB can be made to interface to any CPU’s wait
input as shown in Figure 33c.
10.3.1 GRANTB Output
The output GRANTB determines which port has current ac-
cess to the DRAM array. GRANTB asserted signifies Port B
has access. GRANTB negated signifies Port A has access
to the DRAM array.
10.3 COMMON PORT A AND PORT B DUAL PORT
FUNCTIONS
An input, LOCK, and an output, GRANTB, add additional
functionality to the dual port arbitration logic. LOCK allows
/F/8588–E6
FIGURE 33a. Non-Delayed Port B Access
TL/F/8588–E7
FI. Delayed PoB Access
TL/F/8588–31
B. Extend ATACK to 1T after RAS goes low.
TL/F/8588–30
A. Extend ATACK to (/2T ((/2 Clow.
TL/F/8588–32
C. Synchronize ATACKB to CPU B Clock. This is useful if CPU B runs asynchronous to the DP8422.
FIGURE 33c. Modifying Wait Logic for Port B
38
10.0 Dual Accessing (DP8422A) (Continued)
Since the DP8422A has only one set of address inputs, the
signal is used, with the addition of buffers, to allow the cur-
rently granted port’s addresses to reach the DP8422A. The
signals which need to be bufferred are R0–10, C0–10,
B0–1, ECAS0–3, WE, and LOCK. All other inputs are not
common and do not have to be buffered as shown in Figure
34a. If a Port, which is not currently granted, tries to access
the DRAM array, the GRANTB output will transition from a
rising clock edge from AREQ or AREQB negating and will
precede the RAS for the access by one or two clock peri-
ods. GRANTB will then stay in this state until the other port
requests an access and the currently granted port is not
accessing the DRAM as shown in Figure 34b.
TL/F/8588–55
*If Port B is synchronous the Request Synchronizing logic will not be required
FIGURE 34a. Dual Accessith the ystem Block Diagram)
39
10.0 Dual Accessing (DP8422A) (Continued)
TL/F/8588–29
FIGURE 34b. Wait States during s
10.3.2 LOCK Input
When the LOCK input is asserted, the currently granted pt
can ‘‘lock out’’ the other port through the insertion of w
states to that port’s access cycle. LOCK does not disable
es, it only keeps GRANTB in the same state even if
the otr port requests an access, as shown in Figure 35a.
LOCK can be used by either port.
TL/F/8588–E8
FIGURE 35. LOCK Function
40
11.0 Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
All Input or Output Voltage
b
a
with Respect to GNDÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 0.5V to 7V
@
Power Dissipation 20 MHzÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0.5W
a
Temperature under Bias ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0 C to 70 C
§
Storage Temperature ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C
§
§
ESD Rating to be determined.
b
a
§
e
a
0 C to 70 C, V
e
e
5V 10%, GND 0V
g
12.0 DC Electrical Characteristics T
§
§
A
CC
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
V
Logical 1 Input Voltage
Tested with a Limited
Functional Pattern
IH
a
2.0
V
CC
0.5
V
Logical 0 Input Voltage
Tested with a Limited
Functional Pattern
IL
b
0.5
0.8
5
V
e b
b
b
V
OH1
V
OL1
V
OH2
V
OL2
Q and WE Outputs
Q and WE Outputs
All Outputs except Qs, WE
All Outputs except Qs, WE
Input Leakage Current
ML Input Current (Low)
Standby Current
I
I
I
I
10 mA
V
V
1.0
1.0
V
V
OH
OL
OH
OL
CC
e
10 mA
e b
3 mA
V
CC
e
e
e
3 mA
or GND
0.5
10
V
b
I
I
I
I
I
I
V
V
10
mA
mA
mA
mA
mA
IN
IN
IN
CC
GND
V
0
15
IL ML
CC1
CC1
CC1
CC2
e
CLK at 8 MHz (V
IN
V
or GND)
6
8
CC
e
Standby Current
CLK at 20 MHz (V
CLK at 25 MHz (V
V
V
or GND)
GND)
17
IN
IN
CC
CC
e
Standby Current
10
20
Supply Current
CLK at 8 MHz (Inputs Active)
e
V
20
40
50
40
75
mA
mA
e
(I
LOAD
0) (V
IN
or GND)
CC
I
I
Supply Current
Supply Current
Input Capacitance
CLK at 20 MHz (Inputs
e
CC2
CC2
e
(I
LOAD
0) (V
IN
CLK at 25 MHz (In
95
10
mA
pF
e
e
(I
f
0) (V
IN
LOAD
C
*
at 1 Mz
IN
IN
*C is not 100% tested.
IN
41
13.0 AC Timing Parameters
Two speed selections are given, the DP8420A/21A/22A-20
and the DP8420A/21A/22A-25. The differences between
the two parts are the maximum operating frequencies of the
input CLKs and the maximum delay specifications. Low fre-
b
quency applications may use the ‘‘ 25’’ part to gain im-
proved timing.
300–315 Mode 0 access parameters used in both single
and dual access applications
400–416 Mode 1 access parameters used in both single
and dual access applications
450–455 Special Mode 1 access parameters which super-
sede the 400–416 parameters when dual ac-
cessing
The AC timing parameters are grouped into sectional num-
bers as shown below. These numbers also refer to the tim-
ing diagrams.
500–506 Programming parameters
k
T
A
k
e
g
Unless otherwise stated V
CC
5.0V 10%, 0
1–36
Common parameters to all modes of operation
Difference parameters used to calculate;
RAS low time,
70 C, the output load capacitance is typical for 4 banks of
§
50–56
18 DRAMs per bank, including trace capacitance (see Note
2).
RAS precharge time,
Two different loads are specified:
CAS high time and
e
e
e
e
e
C
C
C
C
C
50 pF loads on all outputs except
L
CAS low time
150 pF loads on Q0–8, 9, 10 and WE; or
50 pF loads on all outputs except
L
100–121 Common dual access parameters used for Port
B accesses and inputs and outputs used only in
dual accessing
H
H
H
125 pF loads on RAS0–3 and CAS0
380 pF loads on Q0–8, , 10 and W
200–212 Refresh parameters
Note 1: ‘‘Absolute Maximum Ratings’’ are the values beyond which the safety of the device cannot be guaranteed. They are nomto imply thice
should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation.
e
e
2.5 ns. Input reference point on AC measurements is 1.5V. Output reference 2.4V for Hand 8V for Low.
Note 2: Input pulse 0V to 3V; tR
tF
Note 3: AC Production testing is done at 50 pF.
TL/F/8588–E9
ock, DELCLK Timing
42
13.0 AC Timing Parameters (Continued)
k
k
e
per bank, including trace capacitance (Note 2).
g
5.0V 10%, 0 C
Unless otherwise stated V
CC
T
70 C, the output load capacitance is typical for 4 banks of 18 DRAMs
§
§
A
e
e
e
Two different loads are specified:
C
H
C
H
C
H
50 pF loads on all outputs except
125 pF loads on RAS0–3 and CAS0–3 and
380 pF loads on Q0–8, 9, 10 and WE.
e
e
C
C
50 pF loads on all outputs except
150 pF loads on Q0–8, 9, 10 and WE; or
L
L
8420A/21A/22A-20
8420A/21A/22A-25
Common Parameter
Description
Number
Symbol
C
L
C
C
L
C
H
H
Min
0
Max
Min
0
Max
Min
0
Max
Min
0
Max
1
f
CLK Frequency
20
20
25
25
CLK
2
tCLKP
CLK Period
50
15
5
50
15
5
40
12
5
40
12
5
3, 4
5
tCLKPW
fDCLK
CLK Pulse Width
DELCLK Frequency
DELCLK Period
DELCLK Pulse Width
20
20
20
20
6
tDCLKP
tDCLKPW
50
15
200
50
15
200
50
1
50
12
200
7, 8
9a
tPRASCAS0 RAS Asserted to CAS Asserted
e
0 ns)
30
40
40
50
30
40
30
40
40
50
40
40
50
e
(tRAH
15 ns, tASC
9b
9c
9d
tPRASCAS1 RAS Asserted to CAS Asserted
e
10 ns)
e
(tRAH
15 ns, tASC
tPRASCAS2 (RAS Asserted to CAS Asserted
e
0 ns)
e
(tRAH
25 ns, tASC
tPRASCAS3 (RAS Asserted to CAS Asserted
e
10 ns)
e
(tRAH
25 ns, tASC
e
e
10a
10b
11a
11b
12
tRAH
Row Address Hold Time (tRAH
Row Address Hold Time (tRAH
15)
25)
15
15
25
0
15
25
0
15
25
0
tRAH
e
e
tASC
Column Address Setup Time (tASC
Column Address Setup Time (tASC
tASC
10
10
10
tPCKRAS
CLK High to RAS Asserted
following Precharge
27
32
22
26
13
14
15
16
17
18
tPARQRAS AREQ Negated to RAS Ngate
38
23
25
60
39
43
31
33
68
39
31
20
20
47
31
35
27
27
54
31
tPENCL
tPENCH
ECAS0–3 Asserted to CAS Asserted
ECAS3 NeNega
tPARQCAS AREQ Neted
tPCLKWH
tPCL
o WAIT
ACK As
d as DTACK of 1/2, 1, 1(/2
Asserted)
33
44
33
44
28
36
28
36
19
20
tPEW
tSECK
d to WAIT Asserted
st Access
sserted Setup to CLK High to
Recognize the Rising Edge of CLK
during a Burst Access
24
24
19
19
43
13.0 AC Timing Parameters (Continued)
k
k
70 C, the output load capacitance is typical for 4 banks of 18 DRAMs
e
per bank, including trace capacitance (Note 2).
g
5.0V 10%, 0 C
Unless otherwise stated V
CC
T
A
§
§
e
e
e
Two different loads are specified:
C
H
C
H
C
H
50 pF loads on all outputs except
125 pF loads on RAS0–3 and CAS0–3 and
380 pF loads on Q0–8, 9, 10 and WE.
e
e
C
C
50 pF loads on all outputs except
150 pF loads on Q0–8, 9, 10 and WE; or
L
L
8420A/21A/22A-20
8420A/21A/22A-25
Common Parameter
Description
Number
Symbol
C
L
C
C
L
C
H
H
Min
Max
Min
Max
Min
Max
Min
Max
21
tPEDL
ECAS Asserted to DTACK
Asserted during a Burst Access
(Programmed as DTACK0)
48
48
38
38
22
tPEDH
tSWCK
ECAS Negated to DTACK
49
49
38
38
Negated during a Burst Access
23
24
25
26
WAITIN Asserted Setup to CLK
5
5
5
tPWINWEH WIN Asserted to WE Asserted
tPWINWEL WIN Negated to WE Negated
34
34
44
44
27
27
37
3
tPAQ
Row, Column Address Valid to
Q0–8, 9, 10 Valid
29
34
38
26
30
35
39
27
tPCINCQ
tSCINEN
COLINC Asserted to Q0–8, 9, 10
Incremented
28
COLINC Asserted Setup to ECAS
e
18
46
1
19
9
17
15
19
37
15
Asserted to Ensure tASC
0 ns
29a
29b
tSARQCK1 AREQ, AREQB Negated Setup to CLK
High with 1 Period of Precharge
tSARQCK2 AREQ, AREQB Negated Setup to CLK High
l
with 1 Period of Precharge Programmed
30
31
tPAREQDH AREQ Negated to DTACK Negated
34
39
27
25
27
32
tPCKCAS
CLK High to CAS Asserted
when Delayed by WIN
32
tSCADEN
Column Address Setup to ECAS
e
14
15
20
14
20
16
20
Asserted to Guarantee tASC
0
33
tWCINC
COLINC Pulse idth
34a
tPCKCL0
CLK High to CAS e
e
81
91
89
99
72
82
82
92
79
89
89
99
s)
Precharge (tRAH
1
34b
34c
34d
35
tPCKCL1
tPCKCL2
tPCKCL3
tCAH
CLsserte
e
5 ns, t
10 ns)
0 ns)
ted following
91
99
e
ns, tASC
rted following
101
109
e
10 ns)
Pre
25 ns, tASC
Column Address Hold Time
(Interleave Mode Only)
32
32
32
32
36
tPCQR
CAS Asserted to Row Address
Valid (Interleave Mode Only)
90
90
90
90
44
13.0 AC Timing Parameters (Continued)
k
k
70 C, the output load capacitance is typical for 4 banks of 18 DRAMs
e
per bank, including trace capacitance (Note 2).
g
5.0V 10%, 0 C
Unless otherwise stated V
CC
T
§
§
A
e
e
e
Two different loads are specified:
C
H
C
H
C
H
50 pF loads on all outputs except
125 pF loads on RAS0–3 and CAS0–3 and
380 pF loads on Q0–8, 9, 10 and WE.
e
e
C
C
50 pF loads on all outputs except
150 pF loads on Q0–8, 9, 10 and WE; or
L
L
8420A/21A/22A-20
8420A/21A/22A-25
Difference
Number Symbol
C
L
C
C
C
H
H
L
Parameter Description
Min
Max
Min
Max
Min
Max
Min
Max
50
tD1
(AREQ or AREQB Negated to RAS
Negated) Minus (CLK High to RAS
Asserted)
16
16
14
14
51
52
tD2
(CLK High to Refresh RAS Negated)
Minus (CLK High to RAS Asserted)
13
4
13
4
11
11
4
tD3a
(ADS Asserted to RAS Asserted
(Mode 1)) Minus (AREQ Negated
to RAS Negated)
53
54
55
56
tD3b
tD4
tD5
tD6
(CLK High to RAS Asserted (Mode 0))
Minus (AREQ Negated to RAS Negated)
4
7
6
4
7
4
7
6
4
7
6
(ECAS Asserted to CAS Asserted)
b
b
b
b
7
7
7
Minus (ECAS Negated to CAS Negated)
(CLK to Refresh RAS Asserted) Minus
(CLK to Refresh RAS Negated)
(AREQ Negated to RAS Negated)
Minus (ADS Asserted to RAS
Asserted (Mode 1))
12
10
10
45
13.0 AC Timing Parameters (Continued)
k
k
70 C, the output load capacitance is typical for 4 banks of 18 DRAMs
e
per bank, including trace capacitance (Note 2).
g
5.0V 10%, 0 C
Unless otherwise stated V
CC
T
A
§
§
e
e
e
Two different loads are specified:
C
H
C
H
C
H
50 pF loads on all outputs except
125 pF loads on RAS0–3 and CAS0–3 and
380 pF loads on Q0–8, 9, 10 and WE.
e
e
C
C
50 pF loads on all outputs except
150 pF loads on Q0–8, 9, 10 and WE; or
L
L
8420A/21A/22A-20
8420A/21A/22A-25
Common Dual Access
Parameter Description
Number
Symbol
C
L
C
C
C
H
H
L
Min
3
Max
Min
3
Max
Min
3
Max
Min
3
Max
100
101
102
103
105
tHCKARQB
tSARQBCK
tPAQBRASL
AREQB Negated Held from CLK High
AREQB Asserted Setup to CLK High
AREQB Asserted to RAS Asserted
8
8
7
7
43
41
48
46
37
32
41
36
tPAQBRASH AREQB Negated to RAS Negated
tPCKRASG
CLK High to RAS Asserted for
Pending Port B Access
55
57
67
60
57
67
44
45
5
48
45
5
106
107
tPAQBATKBL AREQB Asserted to ATACKB Asserted
tPCKATKB
CLK High to ATACKB Asserted
for Pending Access
108
109
110
tPCKGH
CLK High to GRANTB Asserted
CLK High to GRANTB Negated
40
35
40
35
32
29
29
tPCKGL
tSADDCKG
Row Address Setup to CLK High That
Asserts RAS following a GRANTB
11
5
15
5
5
16
5
e
Change to Ensure tASR
0 ns for Port B
111
tSLOCKCK
LOCK Asserted Setup to CLK Low
to Lock Current Port
112
113
114
tPAQATKBH AREQ Negated to ATACKB Negated
tPAQBCASH AREQB Negated to CAS Negated
26
26
67
21
47
21
54
tSADAQB
Address Valid Setup to
AREQB Asserted
5
7
5
12
5
116
117
tHCKARQG
tWAQB
AREQ Negated Held from CLK High
AREQB High Pulse Width
e
31
35
26
31
to Guarantee tASR
0 ns
118a
118b
118c
118d
120a
tPAQBCAS0
tPAQBCAS1
tPAQBCAS2
tPAQBCAS3
tPCKCASG0
AREQB Asserted to CAS Assert
e
0 ns)
103
113
113
123
111
121
121
131
87
97
94
e
(tRAH
15 ns, tASC
AREQB Assed to Cd
104
104
114
e
(tRAH
15 nAS
AREQB Asserted
97
(tR
ns, tASC
to CAS
e
10 )
107
C
erted
cess
113
123
123
133
121
131
131
141
96
103
113
113
123
e
0 ns)
120b
120c
120d
121
tPCKCASG1
tPCKCASG2
tPCKCASG3
CAsserted
for Prt B Access
106
106
116
e
e
10 ns)
(tRAH
15 ns, tASC
CLK High to CAS Asserted
for Pending Port B Access
e
e
0 ns)
(tRAH
25 ns, tASC
CLK High to CAS Asserted
for Pending Port B Access
e
e
10 ns)
(tRAH
25 ns, tASC
tSBADDCKG Bank Address Valid Setup to CLK
High That Starts RAS
for Pending Port B Access
10
10
10
10
46
13.0 AC Timing Parameters (Continued)
TL/F/8588–F0
FIGURE 37. 100: DuPort
TL/F/8588–F1
FIGURE 38. 100: Port A and Port B Dual Access
47
13.0 AC Timing Parameters (Continued)
k
k
70 C, the output load capacitance is typical for 4 banks of 18 DRAMs
e
per bank, including trace capacitance (Note 2).
g
5.0V 10%, 0 C
Unless otherwise stated V
CC
T
A
§
§
e
e
e
Two different loads are specified:
C
H
C
H
C
H
50 pF loads on all outputs except
125 pF loads on RAS0–3 and CAS0–3 and
380 pF loads on Q0–8, 9, 10 and WE.
e
e
C
C
50 pF loads on all outputs except
150 pF loads on Q0–8, 9, 10 and WE; or
L
L
8420A/21A/22A-20
8420A/21A/22A-25
Refresh Parameter
Description
Number
Symbol
C
L
C
C
C
H
H
L
Min
27
Max
Min
27
Max
Min
22
Max
Min
22
Max
200
201
202
204
205
206
207
208
209a
tSRFCK
RFSH Asserted Setup to CLK High
DISRFSH Asserted Setup to CLK High
EXTENDRF Setup to CLK High
CLK High to RFIP Asserted
tSDRFCK
tSXRFCK
tPCKRFL
tPARQRF
tPCKRFH
28
28
22
22
15
15
12
12
39
62
65
35
28
39
62
65
40
33
31
50
51
29
23
31
50
51
33
27
AREQ Negated to RFIP Asserted
CLK High to RFIP Negated
tPCKRFRASH CLK High to Refresh RAS Negated
tPCKRFRASL CLK High to Refresh RAS Asserted
tPCKCL0
tPCKCL1
tPCKCL2
tPCKCL3
CLK High to CAS Asserted
during Error Scrubbing
82
92
90
73
83
83
93
80
90
e
e
0 ns)
(t
15 ns, t
ASC
RAH
209b
209c
209d
CLK High to CAS Asserted
during Error Scrubbing
100
110
e
e
10 ns)
(t
RAH
15 ns, t
ASC
CLK High to CAS Asserted
during Error Scrubbing
92
90
e
e
0 ns)
(t
25 ns, t
ASC
RAH
CLK High to CAS Asserted
during Error Scrubbing
100
e
e
10 ns)
(t
25 ns, t
ASC
RAH
210
211
212
tWRFSH
tPCKRQL
tPCKRQH
RFSH Pulse Width
15
15
15
CLK High to RFRQ Asserted
CLK High to RFRQ Negated
46
50
46
50
40
40
40
40
TL/F/8588–F2
FIGURE 39. 200: Refresh Timing
48
13.0 AC Timing Parameters (Continued)
k
k
70 C, the output load capacitance is typical for 4 banks of 18 DRAMs
e
per bank, including trace capacitance (Note 2).
g
5.0V 10%, 0 C
Unless otherwise stated V
CC
T
§
§
A
e
e
e
Two different loads are specified:
C
H
C
H
C
H
50 pF loads on all outputs except
125 pF loads on RAS0–3 and CAS0–3 and
380 pF loads on Q0–8, 9, 10 and WE.
e
e
C
C
50 pF loads on all outputs except
150 pF loads on Q0–8, 9, 10 and WE; or
L
L
8420A/21A/22A-20
8420A/21A/22A-25
Mode 0 Access
Parameter Description
Number
Symbol
C
L
C
H
C
L
C
H
Min
Max
Min
Max
Min
Max
Min
Max
300
tSCSCK
CS Asserted to CLK High
14
14
13
13
301a
tSALECKNL ALE Asserted Setup to CLK High
Not Using On-Chip Latches or
if Using On-Chip Latches and
16
29
16
29
15
29
15
29
B0, B1, Are Constant, Only 1 Bank
301b
tSALECKL
ALE Asserted Setup to CLK High,
if Using On-Chip Latches if B0, B1
Can Change, More Than One Bank
302
303
304
tWALE
ALE Pulse Width
18
20
18
20
13
18
1
1
tSBADDCK
tSADDCK
Bank Address Valid Setup to CLK High
Row, Column Valid Setup to
CLK High to Guarantee
11
10
3
15
11
8
16
8
e
tASR
0 ns
305
306
tHASRCB
tSRCBAS
Row, Column, Bank Address
Held from ALE Negated
(Using On-Chip Latches)
Row, Column, Bank Address
Setup to ALE Negated
(Using On-Chip Latches)
2
2
307
tPCKRL
CLK High to RAS Asserted
27
32
89
22
72
26
79
308a
tPCKCL0
CLK High to CAS Asserted
e
e
(t
RAH
15 ns, t
0 ns)
ASC
308b
308c
308d
tPCKCL1
tPCKCL2
tPCKCL3
CLK High to CAS Asserted
e
91
99
99
82
82
92
89
89
99
e
(t
RAH
15 ns, t
10
ASC
CLK High to CAS Assert
e
e
(t
RAH
25 ns, t
0 s)
ASC
CLK High to CAS Asserted
e
101
109
0 ns)
(t
RA
25 n
309
310
tHCKALE
tSWINCK
ALE NeteK High
0
0
0
0
WIN AssertHigh
rantee d
b
b
b
b
16
21
21
16
311
312
313
tPCS
tPC
tPC
d to WAsserted
to WAIT Negated
26
30
26
30
22
25
22
25
DTACK Asserted
d as DTACK0)
40
35
40
35
32
29
32
29
314
315
tPALE
ted to WAIT Asserted
lready Asserted)
AREQ Negated to CLK High That Starts
e
Access RAS to Guarantee tASR
(Non-Interleaved Mode Only)
0 ns
41
45
34
39
316
tPCKCV0
CLK High to Column
Address Valid
78
87
66
75
e
e
0 ns)
(t
15 ns, t
ASC
RAH
49
13.0 AC Timing Parameters (Continued)
TL/F/8588–F3
FIGURE 40. 300: Mode 0 Timing
50
13.0 AC Timing Parameters (Continued)
TL/F/8588–F4
e
e
1)
(Programmed as C4
RE 41. 300: Mode 0 Interleaving
51
13.0 AC Timing Parameters (Continued)
k
k
70 C, the output load capacitance is typical for 4 banks of 18 DRAMs
e
per bank, including trace capacitance (Note 2).
g
5.0V 10%, 0 C
Unless otherwise stated V
CC
T
A
§
§
e
e
e
Two different loads are specified:
C
H
C
H
C
H
50 pF loads on all outputs except
125 pF loads on RAS0–3 and CAS0–3 and
380 pF loads on Q0–8, 9, 10 and WE.
e
e
C
C
50 pF loads on all outputs except
150 pF loads on Q0–8, 9, 10 and WE; or
L
L
8420A/21A/22A-20
8420A/21A/22A-25
Mode 1 Access
Parameter Description
Number
Symbol
C
L
C
C
C
H
H
L
Min
Max
Min
Max
Min
Max
Min
Max
400a
400b
tSADSCK1 ADS Asserted Setup to CLK High
15
31
6
15
13
13
tSADSCKW ADS Asserted Setup to CLK
(to Guarantee Correct WAIT
31
6
25
5
25
5
or DTACK Output; Doesn’t Apply for DTACK0)
401
tSCSADS
tPADSRL
tPADSCL0
CS Setup to ADS Asserted
402
ADS Asserted to RAS Asserted
ADS Asserted to CAS Asserted
30
86
35
94
25
7
29
82
403a
e
e
0 ns)
(tRAH
15 ns, tASC
403b
403c
403d
404
tPADSCL1
tPADSCL2
tPADSCL3
ADS Asserted to CAS Asserted
e
10 ns)
96
96
104
104
85
85
95
9
92
e
(tRAH
15 ns, tASC
ADS Asserted to CAS Asserted
e
0 ns)
e
(tRAH
25 ns, tASC
ADS Asserted to CAS Asserted
e
10 ns)
106
102
e
(tRAH
25 ns, tASC
tSADDADS Row Address Valid Setup to ADS
e
9
0
13
9
0
14
0
Asserted to Guarantee tASR
0 ns
405
406
tHCKADS
tSWADS
ADS Negated Held from CLK High
WAITIN Asserted Setup to ADS
Asserted to Guarantee DTACK0
Is Delayed
0
0
0
407
408
tSBADAS
tHASRCB
Bank Address Setup to ADS Asserted
10
11
10
11
10
11
10
Row, Column, Bank Address Held fr
ADS Asserted (Using On-Chip Lates)
409
tSRCBAS
Row, Column, Bank Address Setup
ADS Asserted (Using On-Chip Latches)
3
2
2
410
411
tWADSH
tPADSD
ADS Negated se W
12
16
12
17
ADS Asserted to D
(Programmed as DTA
43
43
35
35
412
tSWINADS Wp to Ad
elayed ng
b
b
b
b
10
10
10
10
413
414
415
tPADSWL0 Asserted
0, Delayed Access)
35
35
35
35
29
29
29
29
tPADSWL1 ADAIT Asserted
(ProgrAIT 1/2 or 1)
tPCLKDL1
CLK High to DTACK Asserted
(Programmed as DTACK0,
Delayed Access)
40
40
32
32
416
417
AREQ Negated to ADS Asserted
e
(Non Interleaved Mode Only)
to Guarantee tASR
0 ns
38
42
31
36
tPADSCV0 ADS Asserted to Column
Address Valid
83
92
69
78
e
e
0 ns)
(t
15 ns, t
ASC
RAH
52
13.0 AC Timing Parameters (Continued)
TL/F/8588–F5
FIGURE 42. 400: ode 1 Timing
53
13.0 AC Timing Parameters (Continued)
TL/F/8588–F6
FIGU43. 40Page/Column Access Timing
54
13.0 AC Timing Parameters (Continued)
k
k
70 C, the output load capacitance is typical for 4 banks of 18 DRAMs
e
per bank, including trace capacitance (Note 2).
g
5.0V 10%, 0 C
Unless otherwise stated V
CC
T
§
§
A
e
e
e
Two different loads are specified:
C
H
C
H
C
H
50 pF loads on all outputs except
125 pF loads on RAS0–3 and CAS0–3 and
380 pF loads on Q0–8, 9, 10 and WE.
e
e
C
C
50 pF loads on all outputs except
150 pF loads on Q0–8, 9, 10 and WE; or
L
L
8420A/21A/22A-20
8420A/21A/22A-25
Mode 1 Dual Access
Number
Symbol
C
L
C
C
C
H
H
L
Parameter Description
Min
Max
Min
Max
Min
Max
Min
Max
450
tSADDCKG
Row Address Setup to CLK High That
Asserts RAS following a GRANTB
11
15
11
16
e
Port Change to Ensure tASR
0 ns
451
tPCKRASG
tPCLKDL2
tPCKCASG0
CLK High to RAS Asserted
for Pending Access
48
53
53
53
38
42
43
452
CLK to DTACK Asserted for Delayed
Accesses (Programmed as DTACK0)
453a
CLK High to CAS Asserted
for Pending Access
101
111
111
121
09
119
119
129
86
96
93
e
e
0 ns)
(t
15 ns, t
ASC
RAH
453b
453c
453d
tPCKCASG1
tPCKCASG2
tPCKCASG3
CLK High to CAS Asserted
for Pending Access
103
103
113
e
e
10 ns)
(t
15 ns, t
ASC
RAH
CLK High to CAS Asserted
for Pending Access
96
e
e
0 ns)
(t
RAH
25 ns, t
ASC
CLK High to CAS Asserted
for Pending Access
106
e
e
10 ns)
(t
25 ns, t
ASC
RAH
454
455
tSBADDCKG Bank Address Valid Setup to CLK H
that Asserts RAS for Pending Acces
5
4
4
tSADSCK0
ADS Asserted Setup to CK High
12
11
11
55
13.0 AC Timing Parameters (Continued)
k
DRAMs per bank, including trace capacitance (Note 2).
k
70 C, the output load capacitance is typical for 4 banks of 18
e
g
5.0V 10%, 0 C
Unless otherwise stated V
T
A
§
§
CC
e
e
e
Two different loads are specified:
C
H
C
H
C
H
50 pF loads on all outputs except
125 pF loads on RAS0–3 and CAS0–3 and
380 pF loads on Q0–8, 9, 10 and WE.
e
e
C
C
50 pF loads on all outputs except
150 pF loads on Q0–8, 9, 10 and WE; or
L
L
8420A/21A/22A-20
8420A/21A/22A-25
Programming
Number
Symbol
C
L
C
H
C
L
C
H
Parameter Description
Min Max Min Max Min Max Min Max
500
501
502
503
504
505
tHMLADD
tSADDML
tWML
Mode Address Held from ML Negated
Mode Address Setup to ML Negated
ML Pulse Width
8
6
8
6
7
6
7
6
15
0
15
0
15
0
15
0
tSADAQML Mode Address Setup to AREQ Asserted
tHADAQML Mode Address Held from AREQ Asserted
51
51
38
tSCSARQ
CS Asserted Setup to
AREQ Asserted
6
6
6
506
tSMLARQ
ML Asserted Setup to AREQ Asserted
10
10
0
10
TL/F/8588–F7
GURE 44. 500: Programming
56
wrap board) because they may be needed. The value of
these damping resistors (if needed) will vary depending
upon the output, the capacitance of the load, and the
characteristics of the trace as well as the routing of the
trace. The value of the damping resistor also may vary
between the wire-wrap board and the printed circuit
board. To determine the value of the series damping re-
sistor it is recommended to use an oscilloscope and look
at the furthest DRAM from the DP8420A/21A/22A. The
undershoot of RAS, CAS, WE and the addresses should
be kept to less than 0.5V below ground by varying the
value of the damping resistor. The damping resistors
should be placed as close as possible with short leads to
the driver outputs of the DP8420A/21A/22A.
14.0 Functional Differences
between the DP8420A/21A/22A
and the DP8420/21/22
1. Extending the Column Address Strobe (CAS) after
AREQ Transitions High
The DP8420A/21A/22A allows CAS to be asserted for
an indefinite period of time beyond AREQ (or AREQB,
DP8422A only. Scrubbing refreshes are not affected.) be-
ing negated by continuing to assert the appropriate ECAS
inputs. This feature is allowed as long as the ECAS0 input
was negated during programming. The DP8420/21/22
does not allow this feature.
2. Dual Accessing
5. The circuit board must have a good V
and ground
CC
plane connection. If the board is wire-wrapped, the V
The DP8420A/21A/22A asserts RAS either one or two
clock periods after GRANTB has been asserted or negat-
ed depending upon how the R0 bit was programmed dur-
ing the mode load operation. The DP8420/21/22 will al-
ways start RAS one clock period after GRANTB is assert-
ed or negated. The above statements assume that RAS
precharge has been completed by the time GRANTB is
asserted or negated.
CC
and ground pins of the DP8420A/21A/22A, the DRAM
associated logic and buffer circuitry must be soldered to
the V
and ground planes.
CC
6. The traces from the DP8420A/21A/2RAM
should be as short as possible.
7. ECAS0 should be held low during progif the ur
wishes that the DP8420A/22A be patible wia
DP8420/21/22 design.
3. Refresh Request Output (RFRQ)
The DP8420A/21A/22A allows RFRQ (refresh request)
to be output on the WE output pin given that ECAS0 was
negated during programming or the controller was pro-
grammed to function in the address pipelining (memory
interleaving) mode. The DP8420/21/22 only allows
RFRQ to be output during the address pipelining mode.
8. Parameter Changes due to Load
All A.C. parameters arcified withe equivalent load
capacitances, inclof 64 Ms organized
as 4 banks of 18 h. Maximums are based on
worsase condin outpoad changes then the
A.C. tig paraassociad with that particular
output mue chad. For emple, if we changed our
output load t
4. Clearing the Refresh Request Clock Counter
The DP8420A/21A/22A allows the internal refresh re-
quest clock counter to be cleared by negating DISRFSH
and asserting RFSH for at least 500 ns. The
DP8420/21/22 clears the internal refresh request clock
counter if DISRFSH remains low for at least 500 ns. Once
the internal refresh request clock counter is cleared the
user is guaranteed that an internally generated RFR
not be generated for at least 13 ms–15 ms (deending
e
C
0 pF loaon RAS0–3 and CAS0–3
loads Q0–9 and WE
to modify some parameters (not all calcu-
CAS asserted
e
0 ns)
(t
ns, t
R
ASC
A ratio can be used to figure out the timing change per
ange in capacitance for a particular parameter by using
e specifications and capacitances from heavy and light
oad timing.
upon how programming bits C0, 1, 2,
grammed).
3 wre pro-
15.0 DP8420A/21A/22A Hints
1. All inputs to the DP8420A/2122d high,
low or the output of some other
b
$308a w/Heavy Load $308a w/Light Load
e
Ratio
b
(CAS) C (CAS)
L
C
H
b
79 ns
72 ns
50 pF
7 ns
Note: One signal is activOLINC (EXed low
to disable.
e
e
b
125 pF
75 pF
2. Each ground A/22A t be decou-
pled to the V ) wi0.1 mF ce-
e
c
(capacitance difference
$308a (actual)
CC
ramic capaary because these
a
ratio)
$308a (specified)
7 ns
e
b
a
79 ns
grounds
te
inside
the
(250 pF
125 pF)
79 ns
75 pF
DP8420A/21g capacitors should
be placed as cith short leads to the
ground and supply P8420A/21A/22A.
e
e
a
11.7 ns
@
90.7 ns 250 pF load
9. It is required that the user perform a hardware reset of
the DP8420A/21A/22A before programming and using
the chip. A hardware reset consists of asserting both ML
and DISRFSH for a minimum of 16 positive edges of CLK,
see Section 3.1.
3. The output called ‘‘CAP’’ should have a 0.1 mF capacitor
to ground.
4. The DP8420A/21A/22A has 20X series damping resis-
tors built into the output drivers of RAS, CAS, address
and WE/RFRQ. Space should be provided for external
damping resistors on the printed circuit board (or wire-
57
Ý
Lit. 103064
Physical Dimensions inches (millimeters)
Plastic Chip Carrier (V)
Order Number DP8420AV-20, DP8420AV-25, DP8421AV-20 or DP842AV-25
NS Package Number V68A
Plastic Chip Carr (V)
Orr DP84A0 or DP8422AV-25
kage Number V84A
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