DP8406VX [TI]
84 SERIES, 32-BIT ERROR DETECT AND CORRECT CKT, PQCC68, PLASTIC, LCC-68;
| 型号： | DP8406VX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 84 SERIES, 32-BIT ERROR DETECT AND CORRECT CKT, PQCC68, PLASTIC, LCC-68 逻辑集成电路 |
| 文件： | 总14页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1991
DP8406 (54F/74F632)
32-Bit Parallel Error Detection and Correction Circuit
General Description
The DP8406 device is a 32-bit parallel error detection and
correction circuit (EDAC) in a 52-pin or 68-pin package. The
EDAC uses a modified Hamming code to generate a 7-bit
check word from a 32-bit data word. This check word is
stored along with the data word during the memory write
cycle. During the memory read cycle, the 39-bit words from
memory are processed by the EDAC to determine if errors
have occurred in memory.
detected. Otherwise, errors in three or more bits of the
39-bit word are beyond the capabilities of these devices to
detect.
Read-modify-write (byte-control) operations can be per-
formed by using output latch enable, LEDBO, and the indi-
vidual OEB through OEB byte control pins.
0
3
Diagnostics are performed on the EDACs by controls and
internal paths that allow the user to read the contents of the
Data Bit and Check Bit input latches. These will determine if
the failure occurred in memory or in the EDAC.
Single-bit errors in the 32-bit data word are flagged and cor-
rected.
Single-bit errors in the 7-bit check word are flagged, and the
CPU sends the EDAC through the correction cycle even
though the 32-bit data word is not in error. The correction
cycle will simply pass along the original 32-bit data word in
this case and produce error syndrome bits to pinpoint the
error-generating location.
Features
Y
Detects and corrects single-bit errors
Y
Detects and flags dual-bit errors
Y
Built-in diagnostic capability
Y
Fast write and read cycle processing times
Dual-bit errors are flagged but not corrected. These errors
may occur in any two bits of the 39-bit word from memory
(two errors in the 32-bit data word, two errors in the 7-bit
check word, or one error in each word). The gross-error
condition of all LOWs or all HIGHs from memory will be
Y
Byte-write capability
Y
Guaranteed 4000V minimum ESD protection
Y
Fully pin and function compatible with TI’s
SN74ALS632A thru SN74ALS635 series
Simplified Functional Block
TL/F/9579–9
Device
DP8406
DP8406
Package
52-Pin
Byte-Write
Output
TRI-STATE
TRI-STATE
yes
yes
É
É
68-Pin
FASTÉ and TRI-STATEÉ are registered trademarks of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9579
RRD-B30M105/Printed in U. S. A.
Logic Symbol
TL/F/9579–1
Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I /I
IH IL
Output I /I
HIGH/LOW
OH OL
b
70 mA/ 650 mA
3 mA/24 mA (20 mA)
CB –CB
0
Check Word Bit, Input
3.5/1.083
150/40 (33.3)
3.5/1.083
150/40 (33.3)
1.0/1.0
6
b
b
or TRI-STATE Output
É
b
DB –DB
0
Data Word Bit, Input
or TRI-STATE Output
Output Enable Data Bits
Output Latch Enable Data Bit
Output Enable Check Bit
Select Pins
70 mA/ 650 mA
3 mA/24 mA (20 mA)
31
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
OEB –OEB
0
3
LEDBO
OECB
1.0/1.0
1.0/1.0
S , S
0
1.0/1.0
1
b
b
ERR
Single Error Flag
50/33.3
1 mA/20 mA
1 mA/20 mA
MERR
Multiple Error Flag
50/33.3
Connection Diagrams
Pin Assignment
for LCC and PCC
52-Pin
Pin Assignment
for LCC and PCC
68-Pin
TL/F/9579–3
Order Number DP8406QV (74F632QC)
See NS Package Number V52A
TL/F/9579–8
NCÐNo internal connection
Order Number DP8406V (74F632VC)
See NS Package Number V68A
2
Connection Diagram (Continued)
Functional Description
MEMORY WRITE CYCLE DETAILS
Pin Assignment for
Side Brazed DIP
During a memory write cycle, the check bits (CB through
0
CB ) are generated internally in the EDAC by seven 16-in-
6
put parity generators using the 32-bit data word as defined
in Table II. These seven check bits are stored in memory
along with the original 32-bit data word. This 32-bit word will
later be used in the memory read cycle for error detection
and correction.
ERROR DETECTION AND CORRECTION DETAILS
During a memory read cycle, the 7-bit check word is re-
trieved along with the actual data. In order to be able to
determine whether the data from memory is acceptable to
use as presented to the bus, the error flags must be tested
to determine if they are at the HIGH level.
The first case in Table III represents the normal, no-error
conditions. The EDAC presents HIGHs on both flags. The
next two cases of single-bit errors give a HIGH on MERR
and a LOW on ERR, which is the signal for a correctable
error, and the EDAC should be sent through the correction
cycle. The last three cases of double-bit errors will cause
the EDAC to signal LOWs on both ERR and MERR, which is
the interrupt indication for the CPU.
Error detection is accomplished as the 7-bit check word and
the 32-bit data word from memory are applied to internal
parity generators/checkers. If the parity of all seven group-
ings of data and check bits is correct, it is assumed that no
error has occurred and both error flags will be HIGH.
TL/F/9579–2
Order Number DP8406D (74F632DC)
See NS Package Number D52A
TABLE I. Write Control Function
DB Output
DB Control
Latch
CB
Memory
Cycle
EDAC
Control
Error Flags
ERR MERR
Data I/O
Check I/O
Control
OECB
Function
S
1
S
OEB
0
n
LEDBO
Generate
Output
Write
L
L
Input
H
X
L
H
H
Check Word
Check Bit*
*See Table II for details of check bit generation.
3
Functional Description (Continued)
TABLE II. Parity Algorithm
32-Bit Data Word
Check Word
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
X
X
7
6
X
X
5
4
X
X
X
3
2
1
X
X
0
X
X
X
X
CB
0
CB
1
CB
2
CB
3
CB
4
CB
5
CB
6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
The seven check bits are parity bits derived from the matrix of data bits as indicated by X for each bit.
TABLE III. Error Function
Total Number of Errors
Error Flags
Data Correction
32-Bit Data Word
7-Bit Check Word
ERR
MERR
0
1
0
1
2
0
0
0
1
1
0
2
H
L
L
L
L
L
H
H
H
L
Not Applicable
Correction
Correction
Interrupt
L
Interrupt
L
Interrupt
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
If the parity of one or more of the check groups is incorrect,
an error has occurred and the proper error flag or flags will
be set LOW. Any single error in the 32-bit data word will
change the state of either three or five bits of the 7-bit
check word. Any single error in the 7-bit check word chang-
es the state of only that one bit. In either case, the single
error flag (ERR) will be set LOW while the dual error flag
(MERR) will remain HIGH.
Byte control can now be employed on the data word
through the OEB through OEB controls. OEB controls
0
3
DB –DB (byte 0), OEB controls DB –DB
0
(byte 1),
(byte 2), and OEB controls
0
7
1
8
15
OEB controls DB –DB
16
2
23
3
DB –DB (byte 3). Placing a HIGH on the byte control will
24 31
disable the output and the user can modify the byte. If a
LOW is placed on the byte control, then the original byte is
allowed to pass onto the data bus unchanged. If the original
data word is altered through byte control, a new check word
must be generated before it is written back into memory.
Any 2-bit error will change the state of an even number of
check bits. The 2-bit error is not correctable since the parity
tree can only identify single-bit errors. Both error flags are
set LOW when any 2-bit error is detected.
This is easily accomplished by taking controls S and S
1
0
LOW. Table VI lists the read-modify-write functions.
Three or more simultaneous bit errors can cause the EDAC
to believe that no error, a correctable error, or an uncorrect-
able error has occurred and will produce erroneous results
in all three cases. It should be noted that the gross-error
conditions of all LOWs and all HIGHs will be detected.
DIAGNOSTIC OPERATIONS
The ’F632 is capable of diagnostics that allow the user to
determine whether the EDAC or the memory is failing. The
diagnostic function tables will help the user to see the possi-
bilities for diagnostic control. In the diagnostic mode
e
e
H), the check word is latched into the input
As the corrected word is made available on the data I/O
port (DB through DB ), the check word I/O port (CB
(S
L, S
1
0
latch while the data input latch remains transparent. This
lets the user apply various data words against a fixed known
check word. If the user applies a diagnostic data word with
an error in any bit location, the ERR flag should be LOW. If a
diagnostic data word with two errors in any bit location is
applied, the MERR flag should be LOW. After the check
word is latched into the input latch, it can be verified by
taking OECB LOW. This outputs the latched check word.
The diagnostic data word can be latched into the output
data latch and verified. By changing from the diagnostic
0
31
0
through CB ) presents a 7-bit syndrome error code. This
6
syndrome error code can be used to locate the bad memory
chip. See Table V for syndrome decoding.
READ-MODIFY-WRITE (BYTE CONTROL) OPERATIONS
The ’F632 device is capable of byte-write operations. The
39-bit word from memory must first be latched into the Data
Bit and Check Bit input latches. This is easily accomplished
e
e
by switching from the read and flag mode (S
H, S
L)
e
H). The EDAC will
1
0
e
to the latch input mode (S
H, S
0
1
e
e
e
H) to the correction mode (S H, S
1
mode (S
e
L, S
1
0
0
then make any corrections, if necessary, to the data word
and place it at the input of the output data latch. This data
word must then be latched into the output data latch by
taking LEDBO from a LOW to a HIGH.
H), the user can verify that the EDAC will correct the
diagnostic data word. Also, the syndrome bits can be pro-
duced to verify that the EDAC pinpoints the error location.
Table VII lists the diagnostic functions.
4
Functional Description (Continued)
TABLE IV. Read, Flag and Correct Function
DB Output
Latch
CB
Memory
Cycle
EDAC
Control
DB Control
Error Flags
ERR MERR
Data I/O
Check I/O
Control
OECB
Function
S
1
S
OEB
n
0
LEDBO
Read
Read
Read & Flag
H
L
Input
H
X
Input
H
Enabled (Note 1)
Enabled (Note 1)
Latch Input
Data & Check
Bits
Latched
Input
Latched
Input
H
H
H
H
H
L
L
H
Data
Check Word
Read
Output
Output
Output
Corrected Data
& Syndrome Bits
Corrected
Data Word
X
Syndrome
Bits (Note 2)
L
Enabled (Note 1)
Note 1: See Table III for error description.
Note 2: See Table V for error location.
TABLE V. Syndrome Decoding
Error
Syndrome Bits
Syndrome Bits
Error
0
6
5
4
3
2
1
0
6
5
4
3
2
1
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
unc
2-Bit
2-Bit
unc
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
2-Bit
unc
DB
7
H
H
2-Bit
DB
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
2-Bit
unc
unc
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
6
2-Bit
2-Bit
DB
H
2-Bit (Note 2)
H
5
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
2-Bit
unc
DB
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
DB
2-Bit
2-Bit
4
31
H
2-Bit
H
DB
3
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
unc
2-Bit
2-Bit
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
2-Bit
DB
unc
2
H
DB
30
H
2-Bit
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
2-Bit
unc
DB
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
DB
0
2-Bit
2-Bit
unc
29
H
2-Bit
DB
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
2-Bit
DB
28
2-Bit
2-Bit
DB
1
unc
2-Bit
H
H
27
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
DB
26
2-Bit
2-Bit
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
2-Bit
unc
unc
H
DB
25
H
2-Bit
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
2-Bit
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
unc
2-bit
2-bit
DB
24
unc
2-Bit
H
H
CB
6
e
e
e
CB
DB
Error in check bit X
Error in data bit Y
Double-bit error
X
Y
2-Bit
e
unc
Uncorrectable multi-bit error
Note: 2-bit and unc condition will cause both ERR and MERR to be LOW
Note 1: Syndrome bits for all LOWs. MERR and ERR LOW for all LOWs,
only ERR LOW for DB error.
30
Note 2: Syndrome bits for all HIGHs.
5
Functional Description (Continued)
TABLE V. Syndrome Decoding (Continued)
Syndrome Bits
Syndrome Bits
Error
Error
6
5
4
3
2
1
0
6
5
4
3
2
1
0
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
2-Bit
unc
unc
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
unc
2-Bit
2-Bit
H
2-Bit
H
DB
23
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
unc
2-Bit
2-Bit
unc
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
2-Bit
DB
DB
22
21
H
H
2-Bit
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
unc
2-Bit
2-Bit
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
2-Bit
DB
DB
20
19
H
DB
H
2-Bit
15
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
2-Bit
unc
DB
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
DB
18
2-Bit
2-Bit
14
H
2-Bit
H
CB
4
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
unc
2-Bit
2-Bit
DB
13
2-Bit
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
2-Bit
DB
16
unc
2-Bit
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
DB
17
2-Bit
2-Bit
DB
DB
12
11
H
2-Bit
H
CB
3
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
2-Bit
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
unc (Note 1)
2-Bit
2-Bit
DB
10
DB
9
H
2-Bit
H
CB
2
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
DB
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
2-Bit
8
2-Bit
2-Bit
CB
CB
CB
1
0
H
H
None
5
e
e
e
CB
Error in check bit X
Error in data bit Y
Double-bit error
X
Y
DB
2-Bit
e
unc
Uncorrectable multi-bit error
Note: 2-bit and unc condition will cause both ERR and MERR to be LOW
Note 1: Syndrome bits for all LOWs. MERR and ERR LOW for all LOWs,
only ERR LOW for DB error.
30
Note 2: Syndrome bits for all HIGHs.
6
Functional Description (Continued)
TABLE VI. Read-Modify-Write Function
DB Output
Latch
CB
Memory
Cycle
EDAC
Control
Error Flags
BYTEn*
Input
OEBn*
Check I/O
Control
OECB
Function
S
S
ERR
MERR
1
0
LEDBO
Read
Read
Read & Flag
H
L
H
H
X
Input
H
Enabled
Enabled
Latch Input
Data &
Latched
Input
Latched
Input
H
H
H
H
L
H
Check Bits
Data
Check Word
Read
Latch Corrected
Data Word into
Output Latch
High Z
H
L
Latched
Output
Data
Output
Syndrome
Bits
Enabled
H
H
H
Word
Modify/
Write
Modify
Input
Appropriate
Byte or Bytes
& Generate New
Check Word
Modified
H
L
BYTE
Output
0
L
L
L
H
H
Check Word
Output
Unchanged
BYTE
0
*OEB controls DB –DB (BYTE ); OEB controls DB –DB (BYTE ); OEB controls DB –DB (BYTE ); OEB controls DB –DB (BYTE ).
0
0
7
0
1
8
15
1
2
16
23
2
3
24
31
3
TABLE VII. Diagnostic Function
DB Byte
Control
DB Output
Latch
CB
EDAC
Control
Error Flags
ERR MERR
Data I/O
Check I/O
Control
OECB
Function
S
S
1
0
OEB
LEDBO
n
Read & Flag
Input Correct
Data Word
Input Correct
Check Bits
H
L
H
X
L
H
H
Latch Input Check
Word while Data
Input Latch
Input
Latched
Input
L
H
Diagnostic
Data Word*
H
H
Enabled
Remains
Check Bits
Transparent
Latch Diagnostic
Data Word into
Output Latch
Output
Input
Latched
Check Bits
L
H
L
L
H
H
H
H
H
H
H
Diagnostic
Data Word*
H
H
L
H
H
H
L
Enabled
Enabled
High Z
Latch Diagnostic
Data Word into
Input Latch
Output
Syndrome
Bits
Latched
Input
Diagnostic
Data Word
High Z
H
L
Output Diagnostic
Data Word &
Output
Syndrome
Bits
Output
Diagnostic
Data Word
Enabled
Enabled
Syndrome Bits
High Z
H
L
Output Corrected
Diagnostic Data
Word & Output
Syndrome Bits
Output
Syndrome
Bits
Output
Corrected
Diagnostic
Data Word
L
High Z
H
*Diagnostic data is a data word with an error in one bit location except when testing the MERR error flag. In this case,the diagnostic data word will contain errors in
two bit locations.
7
Block Diagram
TL/F/9579–4
Timing Waveforms
Read, Flag and Correct Mode
TL/F/9579–5
8
Timing Waveforms (Continued)
Read, Correct and Modify Mode
TL/F/9579–6
Diagnostic Mode
TL/F/9579–7
9
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Current Applied to Output
in LOW State (Max)
twice the rated I (mA)
OL
ESD Last Passing Voltage (Min)
4000V
b
b
b
a
65 C to 150 C
Storage Temperature
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
§
§
a
55 C to 125 C
Ambient Temperature under Bias
Junction Temperature under Bias
§
§
§
§
a
55 C to 175 C
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
V
Pin Potential to
CC
Ground Pin
b
a
0.5V to 7.0V
Recommended Operating
Conditions
b
a
0.5V to 7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
b
a
30 mA to 5.0 mA
Free Air Ambient Temperature
Military
Commercial
b
a
55 C to 125 C
§
0 C to 70 C
§
e
in HIGH State (with V
CC
Standard Output
0V)
a
§
§
b
0.5V to 5.5V
0.5V to V
CC
Supply Voltage
Military
Commercial
b
a
TRI-STATE Output
a
a
a
4.5V to 5.5V
a
4.5V to 5.5V
DC Electrical Characteristics
54F/74F
Symbol
Parameter
Units
V
CC
Conditions
Min Typ Max
V
Input HIGH Voltage
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
V
V
V
Input LOW Voltage
0.8
IL
b
e b
18 mA
Input Clamp Diode Voltage
1.2
Min
Min
I
IN
CD
OH
e b
e b
e b
e b
e b
e b
Output HIGH
Voltage
54F 10% V
2.5
2.4
2.5
2.4
2.7
2.7
I
I
I
I
I
I
1 mA (ERR, MERR, DB , CB )
n n
CC
CC
CC
CC
OH
OH
OH
OH
OH
OH
54F 10% V
74F 10% V
74F 10% V
3 mA (DB , CB )
n n
1 mA (ERR, MERR, DB , CB )
n
n
V
V
3 mA (DB , CB )
n
n
74F 5% V
74F 5% V
1 mA (ERR, MERR, DB , CB )
n n
3 mA (DB , CB )
CC
CC
n
n
e
e
e
V
OL
Output LOW
Voltage
54F 10% V
74F 10% V
74F 10% V
0.5
I
I
I
20 mA (ERR, MERR, DB , CB )
n n
CC
CC
CC
OL
OL
OL
0.5
0.5
Min
20 mA (ERR, MERR)
24 mA (DB , CB )
n
n
e
e
e
I
I
I
I
Input HIGH
Current
54F
74F
20.0
5.0
V
V
V
V
2.7V (S , S , OEB , OECB, LEDBO)
0 1 n
IH
IN
IN
IN
mA
mA
mA
mA
V
Max
Max
Max
Max
0.0
Input HIGH Current 54F
Breakdown Test 74F
100
7.0
7.0V (S , S , OEB , OECB, LEDBO)
0 1 n
BVI
Input HIGH Current 54F
1.0
0.5
5.5V (CB , DB )
n n
BVIT
CEX
Breakdown (I/O)
74F
e
V
CC
Output HIGH
54F
74F
250
50
OUT
Leakage Current
e
All Other Pins Grounded
V
Input Leakage
Test
I
ID
1.9 mA
ID
OD
IL
74F
74F
4.75
e
All Other Pins Grounded
I
Output Leakage
Circuit Current
V
150 mV
IOD
3.75
mA
0.0
b
e
0.5V (S , S , OEB , OECB, LEDBO)
I
I
I
I
I
I
I
I
I
Input LOW Current
0.6
mA
mA
mA
mA
mA
mA
mA
mA
mA
Max
Max
Max
Max
Max
Max
0.0V
Max
Max
V
V
V
V
V
V
V
T
IN
0
1
n
a
e
e
e
e
I
Output Leakage Current
Output Leakage Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
70
2.7V (CB , DB )
n n
IH
IL
OZH
I/O
I/O
I/O
I/O
a
b
650
I
0.5V (CB , DB )
n n
OZL
70
2.7V (CB , DB )
n n
OZH
OZL
OS
b
650
150
0.5V (CB , DB )
n n
b
b
e
60
0V
OUT
e
500
5.25V (CB , DB )
n n
ZZ
OUT
e
Power Supply Current
Power Supply Current
340
325
0 C–25 C
§
§
25 C–70 C
CC
A
A
e
T
§
§
CC
10
AC Electrical Characteristics
74F
54F
74F
e a
T
V
C
25 C
§
A
e
e
T
C
, V
CC
e
Mil
50 pF
T
, V
C
L
Com
e
50 pF
A
A CC
e a
Symbol
Parameter
5.0V
Units
CC
L
e
50 pF
L
Min
Typ
Max
Min
Max
Min
Max
t
t
Propagation Delay
DB or CB to ERR
4.0
4.0
14.0
10.5
27.0
18.0
4.0
4.0
31.0
20.0
PLH
PHL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
Propagation Delay
DB to ERR
4.0
4.0
21.0
14.0
27.0
18.0
4.0
4.0
31.0
20.0
PLH
PHL
t
t
Propagation Delay
DB or CB to MERR
5.0
5.0
17.0
16.0
27.0
27.0
5.0
5.0
31.0
31.0
PLH
PHL
t
t
Propagation Delay
DB to MERR
5.0
5.0
23.0
19.0
27.0
27.0
5.0
5.0
31.0
31.0
PLH
PHL
t
t
Propagation Delay
and S , LOW, to DB
1
4.0
4.0
12.0
12.0
16.0
16.0
4.0
4.0
20.0
20.0
PLH
PHL
S
0
t
t
Propagation Delay
to CB
4.0
4.0
10.5
9.0
14.0
14.0
4.0
4.0
15.0
15.0
PLH
PHL
S
1
t
Propagation Delay
or S to ERR or MERR
PLH
2.0
11.5
13.0
2.0
14.0
S
0
1
t
t
Propagation Delay
DB to CB
4.0
4.0
16.0
18.0
23.0
23.0
4.0
4.0
25.0
25.0
PLH
PHL
t
t
Propagation Delay
LEDBO to DB
2.0
2.0
11.0
11.0
13.0
13.0
2.0
2.0
14.0
14.0
PLH
PHL
t
t
Output Enable Time
OEB to DB
n
1.0
1.0
6.0
6.0
10.0
10.0
1.0
1.0
10.0
10.0
PZH
PZL
t
t
Output Disable Time
OEB to DB
n
10
1.0
5.0
4.0
10.0
10.0
1.0
1.0
10.0
10.0
PHZ
PLZ
t
t
Output Enable Time
OECB to CB
1.0
1.0
6.0
6.0
10.0
10.0
1.0
1.0
10.0
10.0
PZH
PZL
t
t
Output Disable Time
OECB to CB
1.0
1.0
5.0
4.0
10.0
10.0
1.0
1.0
10.0
10.0
PHZ
PLZ
11
AC Operating Requirements
74F
54F
74F
e a
T
V
25 C
§
A
e
e
Symbol
Parameter
T
, V
CC
Mil
T
, V
A CC
Com
Max
Units
A
e a
5.0V
CC
Min
Max
Min
Max
Min
t
Setup Time, HIGH or LOW
DB/CB before S HIGH (S HIGH)
s
3.0
3.0
ns
ns
ns
ns
ns
0
1
t (H)
s
Setup Time, HIGH
HIGH before LEDBO HIGH
12.0
14.0
S
0
t (H)
s
Setup Time, HIGH
LEDBO HIGH before S or S LOW
0
0
0
0
0
0
0
1
t (H)
s
Setup Time, HIGH
LEDBO HIGH before S HIGH
1
t
s
t
s
Setup Time, HIGH or LOW
Diagnostic DB before S HIGH
1
Setup Time, HIGH or LOW
Diagnostic CB before
3.0
8.0
3.0
8.0
ns
ns
S
1
LOW or S HIGH
0
t
s
Setup Time, HIGH or LOW
Diagnostic DB before
LEDBO HIGH (S LOW, S HIGH)
1
0
t (L)
h
Hold Time, LOW
LOW after S HIGH
8.0
8.0
8.0
5.0
8.0
8.0
8.0
5.0
ns
ns
ns
ns
S
0
1
t
h
t
h
t
h
t
h
Hold Time, HIGH or LOW
DB and CB Hold after S HIGH
0
Hold Time, HIGH or LOW
DB Hold after S HIGH
1
Hold Time, HIGH or LOW
CB Hold after S LOW or S HIGH
1
0
Hold Time, HIGH or LOW
Diagnostic DB after
LEDBO HIGH (S LOW, S HIGH)
0
0
ns
1
0
t
t
(L)*
LEDBO Pulse Width
8.0
8.0
ns
ns
w
*
corr
Correction Time
25.0
28.0
*Note: These parameters are guaranteed by characterization or other tests performed.
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 632
D
C
QR
Temperature Range Family
Special Variations
e
e
e
74F
54F
Commercial FAST
Military FAST
QR
Commercial grade device
with burn-in
e
QB
Military grade device with
environmental and burn-in
processing
Device Type
Package Code
e
e
e
D
Q
V
Ceramic DIP
52-Lead Plastic Chip Carrier (PCC)
68-Lead Plastic Chip Carrier (PCC)
Temperature Range
e
a
C
Commercial (0 C to 70 C)
§
§
e
b a
Military ( 55 C to 125 C)
M
§
§
*Order DP8406QV, DP8406V or DP8406D
12
Physical Dimensions inches (millimeters)
52-Lead Side-Brazed Ceramic Dual-In-Line Package (D)
NS Package Number D52A
52-Lead Plastic Chip Carrier (Q)
NS Package Number V52A
13
Physical Dimensions inches (millimeters) (Continued)
68-Lead Plastic Chip Carrier (V)
NS Package Number V68A
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