DP83847ALQA56AX/NOPB

February 2002

DP83847 DsPHYTER II — Single 10/100 Ethernet Transceiver

General Description

Features

The DP83847 is a full feature single Physical Layer device ■ Low-power 3.3V, 0.18µm CMOS technology

with integrated PMD sublayers to support both 10BASE-T

and 100BASE-TX Ethernet protocols over Category 3 (10

Mb/s) or Category 5 unshielded twisted pair cables.

■ Power consumption < 351mW (typical)

■ 5V tolerant I/Os

■ 5V/3.3V MAC interface

The DP83847 is designed for easy implementation of

■ IEEE 802.3 ENDEC, 10BASE-T transceivers and filters

■ IEEE 802.3u PCS, 100BASE-TX transceivers and filters

■ IEEE 802.3 compliant Auto-Negotiation

10/100 Mb/s Ethernet home or office solutions. It interfaces

to Twisted Pair media via an external transformer. This

device interfaces directly to MAC devices through the IEEE

802.3u standard Media Independent Interface (MII) ensur-

ing interoperability between products from different ven-

dors.

■ Output edge rate control eliminates external filtering for

Transmit outputs

■ BaseLine Wander compensation

The DP83847 utilizes on chip Digital Signal Processing

(DSP) technology and digital Phase Lock Loops (PLLs) for

robust performance under all operating conditions,

enhanced noise immunity, and lower external component

count when compared to analog solutions.

■ IEEE 802.3u MII (16 pins/port)

■ LED support (Link, Rx, Tx, Duplex, Speed, Collision)

■ Single register access for complete PHY status

■ 10/100 Mb/s packet loopback BIST (Built in Self Test)

■ 56-pin LLP package (9w) x (9l) x (.75h) mm

Applications

■ LAN on Motherboard

■ Embedded Applications

System Diagram

DP83847

10/100 Mb/s

10BASE-T

RJ-45

or

Ethernet MAC

DsPHYTER II

MII

100BASE-TX

Status

LEDs

25 MHz

Clock

Typical DsPHYTER II application

www.national.com

MII

SERIAL

MANAGEMENT

HARDWARE

CONFIGURATION

PINS

(AN_EN, AN0, AN1)

(PAUSE_EN)

(LED_CFG, PHYAD)

MII INTERFACE/CONTROL

RX_DATA

RX_CLK

RX_DATA

TX_DATA

TX_CLK

TRANSMIT CHANNELS &

STATE MACHINES

RECEIVE CHANNELS &

STATE MACHINES

REGISTERS

MII

100 Mb/s

4B/5B

10 Mb/s

100 Mb/s

4B/5B

10 Mb/s

PHY ADDRESS

ENCODER

DECODER

MANCHESTER

TO NRZ

NRZ TO

AUTO

NEGOTIATION

MANCHESTER

ENCODER

PARALLEL TO

SERIAL

CODE GROUP

ALIGNMENT

DECODER

BASIC MODE

CONTROL

CLOCK

RECOVERY

SERIAL TO

PARALLEL

PCS CONTROL

10BASE-T

SCRAMBLER

LINK PULSE

GENERATOR

DESCRAMBLER

NRZ TO NRZI

ENCODER

100BASE-TX

NRZI TO NRZ

DECODER

LINK PULSE

DETECTOR

TRANSMIT

FILTER

BINARY TO

MLT-3

ENCODER

CLOCK

RECOVERY

AUTO-NEGOTIATION

STATE MACHINE

RECEIVE

FILTER

MLT-3 TO

BINARY

10/100 COMMON

OUTPUT DRIVER

DECODER

ADAPTIVE

BLW

SMART

SQUELCH

CLOCK

GENERATION

AND EQ

COMP

10/100 COMMON

INPUT BUFFER

LED

DRIVERS

RD±

LEDS

TD±

SYSTEM CLOCK

REFERENCE

Figure 1. Block Diagram of the 10/100 DSP based core.

2

www.national.com

Table of Content

1.0

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

10 Mb/s and 100 Mb/s PMD Interface . . . . . . . . . . 6

Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Special Connections . . . . . . . . . . . . . . . . . . . . . . . 7

LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Strapping Options/Dual Purpose Pins . . . . . . . . . . 8

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power and Ground Pin . . . . . . . . . . . . . . . . . . . . . 9

Package Pin Assignments . . . . . . . . . . . . . . . . . . 10

2.0

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1

2.2

2.3

2.4

2.5

2.6

2.7

Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . 11

PHY Address and LEDs . . . . . . . . . . . . . . . . . . . 12

LED INTERFACES . . . . . . . . . . . . . . . . . . . . . . . 13

Half Duplex vs. Full Duplex . . . . . . . . . . . . . . . . . 13

MII Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . . 14

Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.0

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

802.3u MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

100BASE-TX TRANSMITTER . . . . . . . . . . . . . . . 16

100BASE-TX RECEIVER . . . . . . . . . . . . . . . . . . 20

10BASE-T TRANSCEIVER MODULE . . . . . . . . . 23

TPI Network Circuit . . . . . . . . . . . . . . . . . . . . . . . 24

ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . 26

Reference Bypass Couple . . . . . . . . . . . . . . . . . . 26

4.0

5.0

6.0

Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1

4.2

Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1

5.2

Register Definition . . . . . . . . . . . . . . . . . . . . . . . . 29

Extended Registers . . . . . . . . . . . . . . . . . . . . . . . 37

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . 44

6.1

6.2

6.3

6.4

6.5

6.6

6.7

Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

PGM Clock Timing . . . . . . . . . . . . . . . . . . . . . . . 47

MII Serial Management Timing . . . . . . . . . . . . . . 47

100 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . . 48

10 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . 57

Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 60

7.0

3

www.national.com

Pin Layout

COL 43

RESERVED 44

CRS/LED_CFG 45

RESET 46

28 VDD

27 RXD_2

26 RXD_3

25 MDC

59

60

RESERVED 47

X2 48

24 MDIO

23 LED_DPLX/PHYAD0

22 LED_COL/PHYAD1

21 LED_GDLNK/PHYAD2

20 LED_TX/PHYAD3

19 LED_RX/PHYAD4

18 LED_SPEED

17 AN_EN

X1 49

65 Gnd

RESERVED 50

RESERVED 51

RESERVED 52

RESERVED 53

RESERVED 54

RESERVED 55

VDD 56

64

63

16 AN_1

15 AN_0

Top View

Leadless Leadframe Package (LLP)

Order Number DP83847ALQA56A

NS Package Number LQA-56A

Note 1: Pins 57 to 65 required soldering care. Check Package Instruction, AN-1187, for details.

4

www.national.com

1.0 Pin Descriptions

The DP83847 pins are classified into the following interface All DP83847 signal pins are I/O cells regardless of the par-

categories (each interface is described in the sections that ticular use. Below definitions define the functionality of the

follow):

I/O cells for each pin.

— MII Interface

Type: I

Inputs

— 10/100 Mb/s PMD Interface

— Clock Interface

Type: O

Type: I/O

Type OD

Outputs

Input/Output

Open Drain

— Special Connect Pins

— LED Interface

Type: PD,PU Internal Pulldown/Pullup

Type: S Strapping Pin (All strap pins except PHY-

— Strapping Options/Dual Function pins

— Reset

AD[0:4] have internal pull-ups or pull-

downs. If the default strap value is needed

to be changed then an external 5 kΩ resistor

should be used. Please see Table 1.6 on

page 8 for details.)

— Power and Ground pins

Note: Strapping pin option (BOLD) Please see Section 1.6

for strap definitions.

1.1 MII Interface

Signal Name

Type

LLP Pin #

Description

MDC

I

25

MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO

management data input/output serial interface which may be

asynchronous to transmit and receive clocks. The maximum clock

rate is 25 MHz with no minimum clock rate.

MDIO

I/O, OD

O, S

24

45

MANAGEMENT DATA I/O: Bi-directional management instruc-

tion/data signal that may be sourced by the station management

entity or the PHY. This pin requires a 1.5 kΩ pullup resistor.

CRS/LED_CFG

CARRIER SENSE: Asserted high to indicate the presence of car-

rier due to receive or transmit activity in 10BASE-T or 100BASE-

TX Half Duplex Modes, while in full duplex mode carrier sense is

asserted to indicate the presence of carrier due only to receive ac-

tivity.

COL

O

43

COLLISION DETECT: Asserted high to indicate detection of a

collision condition (simultaneous transmit and receive activity) in

10 Mb/s and 100 Mb/s Half Duplex Modes.

While in 10BASE-T Half Duplex mode with Heartbeat enabled this

pin are also asserted for a duration of approximately 1µs at the

end of transmission to indicate heartbeat (SQE test).

In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this sig-

nal is always logic 0. There is no heartbeat function during 10

Mb/s full duplex operation.

TX_CLK

O

I

36

TRANSMIT CLOCK: 25 MHz Transmit clock outputs in

100BASE-TX mode or 2.5 MHz in 10BASE-T mode derived from

the 25 MHz reference clock.

TXD[3]

TXD[2]

TXD[1]

TXD[0]]

41, 40, 39, TRANSMIT DATA: Transmit data MII input pins that accept nib-

38

37

35

ble data synchronous to the TX_CLK (2.5 MHz in 10BASE-T

Mode or 25 MHz in 100BASE-TX mode).

TX_EN

I

TRANSMIT ENABLE: Active high input indicates the presence of

valid nibble data on data inputs, TXD[3:0] for both 100 Mb/s or 10

Mb/s nibble mode.

TX_ER

TRANSMIT ERROR: In 100MB/s mode, when this signal is high

and the corresponding TX_EN is active the HALT symbol is sub-

stituted for data.

In 10 Mb/s this input is ignored.

RX_CLK

O, PU

32

RECEIVE CLOCK: Provides the 25 MHz recovered receive

clocks for 100BASE-TX mode and 2.5 MHz for 10BASE-T nibble

mode.

5

www.national.com

Signal Name

Type

LLP Pin #

Description

RXD[3]

O, PU/PD 26, 27, 29, RECEIVE DATA: Nibble wide receive data (synchronous to cor-

30

responding RX_CLK, 25 MHz for 100BASE-TX mode, 2.5 MHz

for 10BASE-T nibble mode). Data is driven on the falling edge of

RX_CLK. RXD[2] has an internal pull-down resistor. The remain-

ing RXD pins have pull-ups.

RXD[2]

RXD[1]

RXD[0]

RX_ER/PAUSE_EN

S, O, PU

O

33

31

RECEIVE ERROR: Asserted high to indicate that an invalid sym-

bol has been detected within a received packet in 100BASE-TX

mode.

RX_DV

RECEIVE DATA VALID: Asserted high to indicate that valid data

is present on the corresponding RXD[3:0] for nibble mode. Data

is driven on the falling edge of the corresponding RX_CLK.

1.2 10 Mb/s and 100 Mb/s PMD Interface

Signal Name

TD+, TD-

Type

LLP Pin #

Description

O

10, 11

Differential common driver transmit output. These differential out-

puts are configurable to either 10BASE-T or 100BASE-TX signal-

ing.

The DP83847 will automatically configure the common driver out-

puts for the proper signal type as a result of either forced config-

uration or Auto-Negotiation.

RD-, RD+

I

6, 7

Differential receive input. These differential inputs can be config-

ured to accept either 100BASE-TX or 10BASE-T signaling.

The DP83847 will automatically configure the receive inputs to

accept the proper signal type as a result of either forced configu-

ration or Auto-Negotiation.

6

www.national.com

1.3 Clock Interface

Signal Name

Type

LLP Pin #

Description

X1

I

49

REFERENCE CLOCK INPUT 25 MHz: This pin is the primary

clock reference input for the DP83847 and must be connected to

a 25 MHz 0.005% (±50 ppm) clock source. The DP83847 sup-

ports CMOS-level oscillator sources.

X2

O

48

REFERENCE CLOCK OUTPUT 25 MHz: This pin is the primary

clock reference output.

1.4 Special Connections

Signal Name

Type

LLP Pin #

Description

RBIAS

I

3

Bias Resistor Connection. A 10.0 kΩ 1% resistor should be con-

nected from RBIAS to GND.

C1

O

42

Reference Bypass Regulator. Parallel caps, 10µ F (Tantalum pre-

ferred) and .1µF, should be placed close to C1 and connected to

GND. See Section 3.8 for proper placement.

RESERVED

I/O

1, 2, 4, 5, 8, RESERVED: These pins must be left unconnected

9, 12, 13,

34, 44, 47,

50, 51, 52,

53, 54, 55,

61

1.5 LED Interface

Signal Name

LED_DPLX/PHYAD0

LED_COL/PHYAD1

Type

S, O

LLP Pin #

Description

23

22

FULL DUPLEX LED STATUS: Indicates Full-Duplex status.

COLLISION LED STATUS: Indicates Collision activity in Half Du-

plex mode.

LED_GDLNK/PHYAD2

LED_TX/PHYAD3

LED_RX/PHYAD4

LED_SPEED

S, O

O

21

20

19

18

GOOD LINK LED STATUS: Indicates Good Link Status for

10BASE-T and 100BASE-TX.

TRANSMIT LED STATUS: Indicates transmit activity. LED is on

for activity, off for no activity.

RECEIVE LED STATUS: Indicates receive activity. LED is on for

activity, off for no activity.

SPEED LED STATUS: Indicates link speed; high for 100 Mb/s,

low for 10 Mb/s.

7

www.national.com

tors will set the default value. Please note that the

PHYAD[0:4] pins have no internal pull-ups or pull-downs

and they must be strapped. Since these pins may have

alternate functions after reset is deasserted, they should

not be connected directly to Vcc or GND.

1.6 Strapping Options/Dual Purpose Pins

A 5 kΩ resistor should be used for pull-down or pull-up to

change the default strap option. If the default option is

required, then there is no need for external pull-up or pull

down resistors, since the internal pull-up or pull down resis-

Signal Name

LED_DPLX/PHYAD0

LED_COL/PHYAD1

LED_GDLNK/PHYAD2

LED_TX/PHYAD3

Type

LLP Pin #

Description

S, O

23

22

21

20

19

PHY ADDRESS [4:0]: The DP83847 provides five PHY address

pins, the state of which are latched into the PHYCTRL register at

system Hardware-Reset.

The DP83847 supports PHY Address strapping values 0

(<00000>) through 31 (<11111>). PHY Address 0 puts the part

into the MII Isolate Mode. The MII isolate mode must be selected

by strapping Phy Address 0; changing to Address 0 by register

write will not put the Phy in the MII isolate mode.

LED_RX/PHYAD4

The status of these pins are latched into the PHY Control Register

during Hardware-Reset. (Please note these pins have no internal

pull-up or pull-down resistors and they must be strapped high or

low using 5 kΩ resistors.)

AN_EN

AN_1

S, O, PU

17

16

15

Auto-Negotiation Enable: When high enables Auto-Negotiation

with the capability set by ANO and AN1 pins. When low, puts the

part into Forced Mode with the capability set by AN0 and AN1

pins.

AN_0

AN0 / AN1: These input pins control the forced or advertised op-

erating mode of the DP83847 according to the following table.

The value on these pins is set by connecting the input pins to

GND (0) or V_CC(1) through 5 kΩ resistors. These pins should

NEVER be connected directly to GND or V_CC.

The value set at this input is latched into the DP83847 at Hard-

ware-Reset.

The float/pull-down status of these pins are latched into the Basic

Mode Control Register and the Auto_Negotiation Advertisement

Register during Hardware-Reset. After reset is deasserted, these

pins may switch to outputs so if pull-ups or pull-downs are imple-

mented, they should be pulled through a 5 kΩ resistor.

The default is 111 since these pins have pull-ups.

AN_EN AN1 AN0

Forced Mode

0

1

0

1

0

1

10BASE-T, Half-Duplex

10BASE-T, Full-Duplex

100BASE-TX, Half-Duplex

100BASE-TX, Full-Duplex

Advertised Mode

AN_EN AN1 AN0

1

0

1

0

1

0

10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

10BASE-T Half-Duplex

100BASE-TX, Half-Duplex

10BASE-T, Half/Full-Duplex

100BASE-TX,Half/Full-Duplex

1

8

www.national.com

Signal Name

Type

LLP Pin #

Description

RX_ER/PAUSE_EN

S, O, PU

33

PAUSE ENABLE: This strapping option allows advertisement of

whether or not the DTE(MAC) has implemented both the optional

MAC control sublayer and the pause function as specified in

clause 31 and annex 31B of the IEEE 802.3x specification (Full

Duplex Flow Control).

When left floating the Auto-Negotiation Advertisement Register

will be set to 0, indicating that Full Duplex Flow Control is not sup-

ported.

When tied low through a 5 kΩ, the Auto-Negotiation Advertise-

ment Register will be set to 1, indicating that Full Duplex Flow

Control is supported.

The float/pull-down status of this pin is latched into the Auto-Ne-

gotiation Advertisement Register during Hardware-Reset.

CRS/LED_CFG

S, O_,

PU

45

LED CONFIGURATION: This strapping option defines the polar-

ity and function of the FDPLX LED pin.

See Section 2.3 for further descriptions of this strapping option.

1.7 Reset

Signal Name

Type

LLP Pin #

Description

RESET

I

46

RESET: Active Low input that initializes or re-initializes the

DP83847. Asserting this pin low for at least 160 µs will force a re-

set process to occur which will result in all internal registers re-ini-

tializing to their default states as specified for each bit in the

Register Block section and all strapping options are re-initialized.

1.8 Power and Ground Pin

Signal Name

LLP Pin #

Description

TTL/CMOS INPUT/OUTPUT SUPPLY

IO_VDD

28, 56

GND

I/O Supply

I/O Ground

IO_GND

INTERNAL SUPPLY PAIRS

CORE_VDD

Internal

GND

Digital Core Supply

Digital Core Ground

CORE_GND

ANALOG SUPPLY PINS

ANA_VDD

14

Analog Supply

Analog Ground

ANA_GND

GND

SUBSTRATE GROUND

SUB_GND

GND

Bandgap Substrate connection

9

www.national.com

1.9 Package Pin Assignments

LLP Pin #

43

Pin Name

COL

LLP Pin #

1

Pin Name

RESERVED

RBIAS

44

RESERVED

CRS/LED_CFG

RESET

45

2

46

3

47

RESERVED

X2

4

RESERVED

RD-

48

5

49

X1

6

50

RESERVED

VDD (IO_VDD)

VDD

7

RD+

51

8

RESERVED

TD+

52

9

53

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

54

TD-

55

RESERVED

VDD (ANA_VDD)

AN_0

56

57

58

GND

59

VDD

AN_1

60

GND

AN_EN

61

RESERVED

GND

LED_SPEED

LED_RX /PHYAD4

LED_TX /PHYAD3

LED_GDLNK/PHYAD2

LED_COL /PHYAD1

LED_FDPLX /PHYAD0

MDIO

62

63

VDD

64

GND

65

GND

MDC

RXD_3

RXD_2

VDD (IO_VDD)

RXD_1

RXD_0

RX_DV

RX_CLK

RX_ER/PAUSE_EN

RESERVED

TX_ER

TX_CLK

TX_EN

TXD_0

TXD_1

TXD_2

TXD_3

C1

10

www.national.com

2.0 Configuration

This section includes information on the various configura-

tion options available with the DP83847. The configuration

options described below include:

Table 1. Auto-Negotiation Modes

AN_EN AN1

AN0

Forced Mode

0

1

0

1

10BASE-T, Half-Duplex

10BASE-T, Full-Duplex

100BASE-TX, Half-Duplex

100BASE-TX, Full-Duplex

Advertised Mode

— Auto-Negotiation

— PHY Address and LEDs

— Half Duplex vs. Full Duplex

— Isolate mode

0

1

— Loopback mode

— BIST

AN_EN AN1

AN0

0

1

0

1

10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

10BASE-T Half-Duplex

2.1 Auto-Negotiation

1

The Auto-Negotiation function provides a mechanism for

exchanging configuration information between two ends of

a link segment and automatically selecting the highest per-

formance mode of operation supported by both devices.

Fast Link Pulse (FLP) Bursts provide the signalling used to

communicate Auto-Negotiation abilities between two

devices at each end of a link segment. For further detail

regarding Auto-Negotiation, refer to Clause 28 of the IEEE

802.3u specification. The DP83847 supports four different

Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full

Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex),

so the inclusion of Auto-Negotiation ensures that the high-

est performance protocol will be selected based on the

advertised ability of the Link Partner. The Auto-Negotiation

function within the DP83847 can be controlled either by

internal register access or by the use of the AN_EN, AN1

and AN0 pins.

0

100BASE-TX, Half-Duplex

10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

1

2.1.2 Auto-Negotiation Register Control

When Auto-Negotiation is enabled, the DP83847 transmits

the abilities programmed into the Auto-Negotiation Adver-

tisement register (ANAR) at address 04h via FLP Bursts.

Any combination of 10 Mb/s, 100 Mb/s, Half-Duplex, and

Full Duplex modes may be selected.

The BMCR provides software with a mechanism to control

the operation of the DP83847. The AN0 and AN1 pins do

not affect the contents of the BMCR and cannot be used by

software to obtain status of the mode selected. Bits 1 & 2 of

the PHYSTS register are only valid if Auto-Negotiation is

disabled or after Auto-Negotiation is complete. The Auto-

Negotiation protocol compares the contents of the

ANLPAR and ANAR registers and uses the results to auto-

matically configure to the highest performance protocol

between the local and far-end port. The results of Auto-

Negotiation (Auto-Neg Complete, Duplex Status and

Speed) may be accessed in the PHYSTS register.

2.1.1 Auto-Negotiation Pin Control

The state of AN_EN, AN0 and AN1 determines whether the

DP83847 is forced into a specific mode or Auto-Negotiation

will advertise a specific ability (or set of abilities) as given in

Table 1. These pins allow configuration options to be

selected without requiring internal register access.

The state of AN_EN, AN0 and AN1, upon power-up/reset,

determines the state of bits [8:5] of the ANAR register.

Auto-Negotiation Priority Resolution:

— (1) 100BASE-TX Full Duplex (Highest Priority)

— (2) 100BASE-TX Half Duplex

The Auto-Negotiation function selected at power-up or

reset can be changed at any time by writing to the Basic

Mode Control Register (BMCR) at address 00h.

— (3) 10BASE-T Full Duplex

— (4) 10BASE-T Half Duplex (Lowest Priority)

The Basic Mode Control Register (BMCR) at address 00h

provides control for enabling, disabling, and restarting the

Auto-Negotiation process. When Auto-Negotiation is dis-

abled the Speed Selection bit in the BMCR controls switch-

ing between 10 Mb/s or 100 Mb/s operation, and the

Duplex Mode bit controls switching between full duplex

operation and half duplex operation. The Speed Selection

and Duplex Mode bits have no effect on the mode of oper-

ation when the Auto-Negotiation Enable bit is set.

The Basic Mode Status Register (BMSR) indicates the set

of available abilities for technology types, Auto-Negotiation

ability, and Extended Register Capability. These bits are

permanently set to indicate the full functionality of the

DP83847 (only the 100BASE-T4 bit is not set since the

DP83847 does not support that function).

11

www.national.com

The BMSR also provides status on:

A renegotiation request from any entity, such as a manage-

ment agent, will cause the DP83847 to halt any transmit

data and link pulse activity until the break_link_timer

expires (~1500 ms). Consequently, the Link Partner will go

into link fail and normal Auto-Negotiation resumes. The

DP83847 will resume Auto-Negotiation after the

break_link_timer has expired by issuing FLP (Fast Link

Pulse) bursts.

— Whether Auto-Negotiation is complete

— Whether the Link Partner is advertising that a remote

fault has occurred

— Whether valid link has been established

— Support for Management Frame Preamble suppression

The Auto-Negotiation Advertisement Register (ANAR) indi-

cates the Auto-Negotiation abilities to be advertised by the

DP83847. All available abilities are transmitted by default,

but any ability can be suppressed by writing to the ANAR.

Updating the ANAR to suppress an ability is one way for a

management agent to change (force) the technology that is

used.

2.1.5 Enabling Auto-Negotiation via Software

It is important to note that if the DP83847 has been initial-

ized upon power-up as a non-auto-negotiating device

(forced technology), and it is then required that Auto-Nego-

tiation or re-Auto-Negotiation be initiated via software,

bit 12 (Auto-Negotiation Enable) of the Basic Mode Control

Register must first be cleared and then set for any Auto-

Negotiation function to take effect.

The Auto-Negotiation Link Partner Ability Register

(ANLPAR) at address 05h is used to receive the base link

code word as well as all next page code words during the

negotiation. Furthermore, the ANLPAR will be updated to

either 0081h or 0021h for parallel detection to either 100

Mb/s or 10 Mb/s respectively.

2.1.6 Auto-Negotiation Complete Time

Parallel detection and Auto-Negotiation take approximately

2-3 seconds to complete. In addition, Auto-Negotiation with

next page should take approximately 2-3 seconds to com-

plete, depending on the number of next pages sent.

The Auto-Negotiation Expansion Register (ANER) indi-

cates additional Auto-Negotiation status. The ANER pro-

vides status on:

Refer to Clause 28 of the IEEE 802.3u standard for a full

description of the individual timers related to Auto-Negotia-

tion.

— Whether a Parallel Detect Fault has occurred

— Whether the Link Partner supports the Next Page func-

tion

— Whether the DP83847 supports the Next Page function

2.2 PHY Address and LEDs

— Whether the current page being exchanged by Auto-Ne-

gotiation has been received

The 5 PHY address inputs pins are shared with the LED

pins as shown below.

— Whether the Link Partner supports Auto-Negotiation

Table 2. PHY Address Mapping

2.1.3 Auto-Negotiation Parallel Detection

Pin #

23

PHYAD Function

PHYAD0

PHYAD1

PHYAD2

PHYAD3

PHYAD4

n/a

LED Function

Duplex

The DP83847 supports the Parallel Detection function as

defined in the IEEE 802.3u specification. Parallel Detection

requires both the 10 Mb/s and 100 Mb/s receivers to moni-

tor the receive signal and report link status to the Auto-

Negotiation function. Auto-Negotiation uses this informa-

tion to configure the correct technology in the event that the

Link Partner does not support Auto-Negotiation but is

transmitting link signals that the 100BASE-TX or 10BASE-

T PMAs recognize as valid link signals.

22

COL

21

Good Link

TX Activity

RX Activity

Speed

20

19

18

If the DP83847 completes Auto-Negotiation as a result of

Parallel Detection, bits 5 and 7 within the ANLPAR register

will be set to reflect the mode of operation present in the

Link Partner. Note that bits 4:0 of the ANLPAR will also be

set to 00001 based on a successful parallel detection to

indicate a valid 802.3 selector field. Software may deter-

mine that negotiation completed via Parallel Detection by

reading a zero in the Link Partner Auto-Negotiation Able

bit, once the Auto-Negotiation Complete bit is set. If config-

ured for parallel detect mode and any condition other than

a single good link occurs then the parallel detect fault bit

will set.

The DP83847 can be set to respond to any of 32 possible

PHY addresses. Each DP83847 or port sharing an MDIO

bus in a system must have a unique physical address.

Refer to Section 3.1.4, PHY Address Sensing section for

more details.

The state of each of the PHYAD inputs latched into the

PHYCTRL register bits [4:0]at system power-up/reset

depends on whether a pull-up or pull-down resistor has

been installed for each pin. For further detail relating to the

latch-in timing requirements of the PHY Address pins, as

well as the other hardware configuration pins, refer to the

Reset summary in Section 4.0.

2.1.4 Auto-Negotiation Restart

Since the PHYAD strap options share the LED output pins,

the external components required for strapping and LED

usage must be considered in order to avoid contention.

Once Auto-Negotiation has completed, it may be restarted

at any time by setting bit 9 (Restart Auto-Negotiation) of the

BMCR to one. If the mode configured by a successful Auto-

Negotiation loses a valid link, then the Auto-Negotiation Specifically, when the LED outputs are used to drive LEDs

process will resume and attempt to determine the configu- directly, the active state of each output driver is dependent

ration for the link. This function ensures that a valid config- on the logic level sampled by the corresponding PHYAD

uration is maintained if the cable becomes disconnected.

input upon power-up/reset. For example, if a given PHYAD

input is resistively pulled low then the corresponding output

will be configured as an active high driver. Conversely, if a

12

www.national.com

given PHYAD input is resistively pulled high, then the cor- nection to external components. In this example, the

responding output will be configured as an active low PHYAD strapping results in address 00011 (03h).

driver. Refer to Figure 1 for an example of a PHYAD con-

The adaptive nature of the LED outputs helps to simplify

potential implementation issues of these dual purpose pins.

PHYAD3 = 0 PHYAD2 = 0 PHYAD1 = 1 PHYAD0 = 1

PHYAD4= 0

VCC

Figure 1. PHYAD Strapping and LED Loading Example

In 100BASE-T mode, link is established as a result of input

2.3 LED INTERFACES

receive amplitude compliant with TP-PMD specifications

which will result in internal generation of signal detect.

The DP83847 has 6 Light Emitting Diode (LED) outputs,

each capable to drive a maximum of 10 mA, to indicate the

status of Link, Transmit, Receive, Collision, Speed, and

Full/Half Duplex operation. The LED_CFG strap option is

used to configure the LED_FDPLX output for use as an

LED driver or more general purpose control pin. See the

table below:

10 Mb/s Link is established as a result of the reception of at

least seven consecutive normal Link Pulses or the recep-

tion of a valid 10BASE-T packet. This will cause the asser-

tion of GD_LINK. GD_LINK will deassert in accordance

with the Link Loss Timer as specified in IEEE 802.3.

The Collision LED indicates the presence of collision activ-

ity for 10 Mb/s or 100 Mb/s Half Duplex operation. This bit

has no meaning in Full Duplex operation and will be deas-

serted when the port is operating in Full Duplex. Since this

pin is also used as the PHY address strap option, the

polarity of this indicator is adjusted to be the inverse of the

strap value. In 10 Mb/s half duplex mode, the collision LED

is based on the COL signal. When in this mode, the user

Table 3. LED Mode Select

LED_CFG

Mode Description

LED polarity adjusted

Duplex active-high

1

0

The LED_FDPLX pin indicates the Half or Full Duplex con- should disable the Heartbeat (SQE) to avoid asserting the

figuration of the port in both 10 Mb/s and 100 Mb/s opera- COL LED during transmission. See Section 3.4.2 for more

tion. Since this pin is also used as the PHY address strap information about the Heartbeat signal.

option, the polarity of this indicator may be adjusted so that

The LED_RX and LED_TX pins indicate the presence of

in the “active” (FULL DUPLEX selected) state it drives

transmit and/or receive activity. Since these pins are also

against the pullup/pulldown strap. In this configuration it is

used in PHY address strap options, the polarity is adjusted

suitable for use as an LED. When LED_CFG is high this

to be the inverse of the respective strap values.

mode is selected and DsPHYTER automatically adjusts the

polarity of the output. If LED_CFG is low, the output drives

high to indicate the “active” state. In this configuration the

2.4 Half Duplex vs. Full Duplex

output is suitable for use as

a control pin. The The DP83847 supports both half and full duplex operation

LED_SPEED pin indicates 10 or 100 Mb/s data rate of the at both 10 Mb/s and 100 Mb/s speeds.

port. The standard CMOS driver goes high when operating

in 100 Mb/s operation. Since this pin is not utilized as a

strap option, it is not affected by polarity adjustment.

Half-duplex is the standard, traditional mode of operation

which relies on the CSMA/CD protocol to handle collisions

and network access. In Half-Duplex mode, CRS responds

The LED_GDLNK pin indicates the link status of the port. to both transmit and receive activity in order to maintain

Since this pin is also used as the PHY address strap compliance with IEEE 802.3 specification.

option, the polarity of this indicator is adjusted to be the

inverse of the strap value.

Since the DP83847 is designed to support simultaneous

transmit and receive activity it is capable of supporting full-

13

www.national.com

duplex switched applications with a throughput of up to 200

Mb/s per port when operating in 100BASE-TX mode.

Because the CSMA/CD protocol does not apply to full-

duplex operation, the DP83847 disables its own internal

collision sensing and reporting functions and modifies the

behavior of Carrier Sense (CRS) such that it indicates only

receive activity. This allows a full-duplex capable MAC to

operate properly.

2.6 Loopback

The DP83847 includes a Loopback Test mode for facilitat-

ing system diagnostics. The Loopback mode is selected

through bit 14 (Loopback) of the Basic Mode Control Reg-

ister (BMCR). Writing 1 to this bit enables MII transmit data

to be routed to the MII receive outputs. Loopback status

may be checked in bit 3 of the PHY Status Register

(PHYSTS). While in Loopback mode the data will not be

transmitted onto the media in 100 Mb/s mode. To ensure

that the desired operating mode is maintained, Auto-Nego-

tiation should be disabled before selecting the Loopback

mode.

All modes of operation (100BASE-TX and 10BASE-T) can

run either half-duplex or full-duplex. Additionally, other than

CRS and Collision reporting, all remaining MII signaling

remains the same regardless of the selected duplex mode.

It is important to understand that while Auto-Negotiation

with the use of Fast Link Pulse code words can interpret

and configure to full-duplex operation, parallel detection

can not recognize the difference between full and half-

duplex from a fixed 10 Mb/s or 100 Mb/s link partner over

twisted pair. As specified in 802.3u, if a far-end link partner

is transmitting forced full duplex 100BASE-TX for example,

the parallel detection state machine in the receiving station

would be unable to detect the full duplex capability of the

far-end link partner and would negotiate to a half duplex

100BASE-TX configuration (same scenario for 10 Mb/s).

During 10BASE-T operation, in order to be standard com-

pliant, the loopback mode loops MII transmit data to the MII

receive data, however, Link Pulses are not looped back. In

100BASE-TX Loopback mode the data is routed through

the PCS and PMA layers into the PMD sublayer before it is

looped back. In addition to serving as a board diagnostic,

this mode serves as a functional verification of the device.

2.7 BIST

The DsPHYTER incorporates an internal Built-in Self Test

(BIST) circuit to accommodate in-circuit testing or diagnos-

tics. The BIST circuit can be utilized to test the integrity of

the transmit and receive data paths. BIST testing can be

performed with the part in the internal loopback mode or

externally looped back using a loopback cable fixture.

2.5 MII Isolate Mode

The DP83847 can be put into MII Isolate mode by writing to

bit 10 of the BMCR register. In addition, the MII isolate

mode can be selected by strapping in Physical Address 0.

It should be noted that selecting Physical Address 0 via an

MDIO write to PHYCTRL will not put the device in the MII

isolate mode.

The BIST is implemented with independent transmit and

receive paths, with the transmit block generating a continu-

ous stream of a pseudo random sequence. The user can

select a 9 bit or 15 bit pseudo random sequence from the

PSR_15 bit in the PHY Control Register (PHYCTRL). The

looped back data is compared to the data generated by the

BIST Linear Feedback Shift Register (LFSR, which gener-

ates a pseudo random sequence) to determine the BIST

pass/fail status.

When in the MII isolate mode, the DP83847 does not

respond to packet data present at TXD[3:0], TX_EN, and

TX_ER inputs and presents a high impedance on the

TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and

CRS outputs. The DP83847 will continue to respond to all

management transactions.

The pass/fail status of the BIST is stored in the BIST status

bit in the PHYCTRL register. The status bit defaults to 0

(BIST fail) and will transition on a successful comparison. If

an error (mis-compare) occurs, the status bit is latched and

is cleared upon a subsequent write to the Start/Stop bit.

While in Isolate mode, the TD± outputs will not transmit

packet data but will continue to source 100BASE-TX

scrambled idles or 10BASE-T normal link pulses.

14

www.national.com

3.0 Functional Description

mat is shown below in Table 4: Typical MDIO Frame For-

mat.

3.1 802.3u MII

The DP83847 incorporates the Media Independent Inter-

face (MII) as specified in Clause 22 of the IEEE 802.3u

standard. This interface may be used to connect PHY

devices to a MAC in 10/100 Mb/s systems. This section

describes both the serial MII management interface as well

as the nibble wide MII data interface.

The MDIO pin requires a pull-up resistor (1.5 kΩ) which,

during IDLE and turnaround, will pull MDIO high. In order to

initialize the MDIO interface, the station management entity

sends a sequence of 32 contiguous logic ones on MDIO to

provide the DP83847 with a sequence that can be used to

establish synchronization. This preamble may be gener-

ated either by driving MDIO high for 32 consecutive MDC

clock cycles, or by simply allowing the MDIO pull-up resis-

tor to pull the MDIO pin high during which time 32 MDC

clock cycles are provided. In addition 32 MDC clock cycles

The serial management interface of the MII allows for the

configuration and control of multiple PHY devices, gather-

ing of status, error information, and the determination of the

type and capabilities of the attached PHY(s).

The nibble wide MII data interface consists of a receive bus should be used to re-sync the device if an invalid start,

and a transmit bus each with control signals to facilitate opcode, or turnaround bit is detected.

data transfer between the PHY and the upper layer (MAC).

The DP83847 waits until it has received this preamble

sequence before responding to any other transaction.

Once the DP83847 serial management port has been ini-

3.1.1 Serial Management Register Access

tialized no further preamble sequencing is required until

after a power-on/reset, invalid Start, invalid Opcode, or

invalid turnaround bit has occurred.

The serial management MII specification defines a set of

thirty-two 16-bit status and control registers that are acces-

sible through the management interface pins MDC and

MDIO. The DP83847 implements all the required MII regis-

ters as well as several optional registers. These registers

are fully described in Section 4.0. A description of the serial

management access protocol follows.

The Start code is indicated by a <01> pattern. This assures

the MDIO line transitions from the default idle line state.

Turnaround is defined as an idle bit time inserted between

the Register Address field and the Data field. To avoid con-

tention during a read transaction, no device shall actively

drive the MDIO signal during the first bit of Turnaround.

The addressed DP83847 drives the MDIO with a zero for

the second bit of turnaround and follows this with the

required data. Figure 2 shows the timing relationship

between MDC and the MDIO as driven/received by the Sta-

tion (STA) and the DP83847 (PHY) for a typical register

read access.

3.1.2 Serial Management Access Protocol

The serial control interface consists of two pins, Manage-

ment Data Clock (MDC) and Management Data Input/Out-

put (MDIO). MDC has a maximum clock rate of 25 MHz

and no minimum rate. The MDIO line is bi-directional and

may be shared by up to 32 devices. The MDIO frame for-

Table 4. Typical MDIO Frame Format

MII Management

Serial Protocol

Read Operation

Write Operation

MDC

Z

MDIO

(STA)

Z

MDIO

(PHY)

Z

0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0

Opcode

(Read)

Register Address

(00h = BMCR)

PHY Address

Register Data

Idle

TA

Idle

Start

(PHYAD = 0Ch)

Figure 2. Typical MDC/MDIO Read Operation

For write transactions, the station management entity 3.1.3 Serial Management Preamble Suppression

writes data to the addressed DP83847 thus eliminating the

The DP83847 supports a Preamble Suppression mode as

requirement for MDIO Turnaround. The Turnaround time is

indicated by a one in bit 6 of the Basic Mode Status Regis-

filled by the management entity by inserting <10>. Figure 3

ter (BMSR, address 01h.) If the station management entity

shows the timing relationship for a typical MII register write

(i.e. MAC or other management controller) determines that

access.

all PHYs in the system support Preamble Suppression by

15

www.national.com

MDC

Z

MDIO

(STA)

Z

0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PHY Address

Register Address

(00h = BMCR)

Opcode

(Write)

Register Data

Idle

Start

TA

(PHYAD = 0Ch)

Figure 3. Typical MDC/MDIO Write Operation

returning a one in this bit, then the station management 3.1.6 Collision Detect

entity need not generate preamble for each management

transaction.

For Half Duplex, a 10BASE-T or 100BASE-TX collision is

detected when the receive and transmit channels are

active simultaneously. Collisions are reported by the COL

signal on the MII.

The DP83847 requires a single initialization sequence of

32 bits of preamble following hardware/software reset. This

requirement is generally met by the mandatory pull-up

resistor on MDIO in conjunction with a continuous MDC, or

the management access made to determine whether Pre-

amble Suppression is supported.

If the DP83847 is transmitting in 10 Mb/s mode when a col-

lision is detected, the collision is not reported until seven

bits have been received while in the collision state. This

prevents a collision being reported incorrectly due to noise

on the network. The COL signal remains set for the dura-

tion of the collision.

While the DP83847 requires an initial preamble sequence

of 32 bits for management initialization, it does not require

a full 32-bit sequence between each subsequent transac-

tion. A minimum of one idle bit between management

transactions is required as specified in IEEE 802.3u.

If a collision occurs during a receive operation, it is immedi-

ately reported by the COL signal.

When heartbeat is enabled (only applicable to 10 Mb/s

operation), approximately 1µs after the transmission of

each packet, a Signal Quality Error (SQE) signal of approx-

imately 10 bit times is generated (internally) to indicate

successful transmission. SQE is reported as a pulse on the

COL signal of the MII.

3.1.4 PHY Address Sensing

The DP83847 provides five PHY address pins, the informa-

tion is latched into the PHYCTRL register (address 19h,

bits [4:0]) at device power-up/Hardware reset.

The DP83847 supports PHY Address strapping values 0

(<00000>) through 31 (<11111>). Strapping PHY Address 3.1.7 Carrier Sense

0 puts the part into Isolate Mode. It should also be noted

Carrier Sense (CRS) may be asserted due to receive activ-

that selecting PHY Address 0 via an MDIO write to PHYC-

TRL will not put the device in Isolate Mode; Address 0 must

be strapped in.

ity, once valid data is detected via the squelch function dur-

ing 10 Mb/s operation. During 100 Mb/s operation CRS is

asserted when a valid link (SD) and two non-contiguous

zeros are detected on the line.

3.1.5 Nibble-wide MII Data Interface

For 10 or 100 Mb/s Half Duplex operation, CRS is asserted

during either packet transmission or reception.

Clause 22 of the IEEE 802.3u specification defines the

Media Independent Interface. This interface includes a

dedicated receive bus and a dedicated transmit bus. These

two data buses, along with various control and indicate sig-

nals, allow for the simultaneous exchange of data between

the DP83847 and the upper layer agent (MAC).

For 10 or 100 Mb/s Full Duplex operation, CRS is asserted

only due to receive activity.

CRS is deasserted following an end of packet.

3.2 100BASE-TX TRANSMITTER

The receive interface consists of a nibble wide data bus

RXD[3:0], a receive error signal RX_ER, a receive data

valid flag RX_DV, and a receive clock RX_CLK for syn-

chronous transfer of the data. The receive clock can oper-

ate at either 2.5 MHz to support 10 Mb/s operation modes

or at 25 MHz to support 100 Mb/s operational modes.

The 100BASE-TX transmitter consists of several functional

blocks which convert synchronous 4-bit nibble data, as pro-

vided by the MII, to a scrambled MLT-3 125 Mb/s serial

data stream. Because the 100BASE-TX TP-PMD is inte-

grated, the differential output pins, TD±, can be directly

The transmit interface consists of a nibble wide data bus routed to the magnetics.

TXD[3:0], a transmit enable control signal TX_EN, and a

The block diagram in Figure 5 provides an overview of

each functional block within the 100BASE-TX transmit sec-

tion.

transmit clock TX_CLK which runs at either 2.5 MHz or 25

MHz.

Additionally, the MII includes the carrier sense signal CRS,

as well as a collision detect signal COL. The CRS signal

asserts to indicate the reception of data from the network

or as a function of transmit data in Half Duplex mode. The

COL signal asserts as an indication of a collision which can

occur during half-duplex operation when both a transmit

and receive operation occur simultaneously.

The Transmitter section consists of the following functional

blocks:

— Code-group Encoder and Injection block (bypass option)

— Scrambler block (bypass option)

— NRZ to NRZI encoder block

— Binary to MLT-3 converter / Common Driver

16

www.national.com

The bypass option for the functional blocks within the DP83847 implements the 100BASE-TX transmit state

100BASE-TX transmitter provides flexibility for applications machine diagram as specified in the IEEE 802.3u Stan-

where data conversion is not always required. The dard, Clause 24.

TX_CLK

TXD[3:0]/

TX_ER

DIV BY 5

4B5B CODE-

GROUP ENCODER

& INJECTOR

FROM PGM

MUX

BP_4B5B

5B PARALLEL

TO SERIAL

SCRAMBLER

MUX

BP_SCR

NRZ TO NRZI

ENCODER

100BASE-TX

LOOPBACK

BINARY TO

MLT-3 /

COMMON

DRIVER

TD±

Figure 4. 100BASE-TX Transmit Block Diagram

3.2.1 Code-group Encoding and Injection

After the T/R code-group pair, the code-group encoder

continuously injects IDLEs into the transmit data stream

until the next transmit packet is detected (reassertion of

Transmit Enable).

The code-group encoder converts 4-bit (4B) nibble data

generated by the MAC into 5-bit (5B) code-groups for

transmission. This conversion is required to allow control

data to be combined with packet data code-groups. Refer

to Table 5: 4B5B Code-Group Encoding/Decoding for 4B to

5B code-group mapping details.

3.2.2 Scrambler

The scrambler is required to control the radiated emissions

at the media connector and on the twisted pair cable (for

100BASE-TX applications). By scrambling the data, the

total energy launched onto the cable is randomly distrib-

uted over a wide frequency range. Without the scrambler,

energy levels at the PMD and on the cable could peak

beyond FCC limitations at frequencies related to repeating

5B sequences (i.e., continuous transmission of IDLEs).

The code-group encoder substitutes the first 8-bits of the

MAC preamble with a J/K code-group pair (11000 10001)

upon transmission. The code-group encoder continues to

replace subsequent 4B preamble and data nibbles with

corresponding 5B code-groups. At the end of the transmit

packet, upon the deassertion of Transmit Enable signal

from the MAC, the code-group encoder injects the T/R

code-group pair (01101 00111) indicating the end of frame. The scrambler is configured as a closed loop linear feed-

back shift register (LFSR) with an 11-bit polynomial. The

output of the closed loop LFSR is X-ORd with the serial

17

www.national.com

NRZ data from the code-group encoder. The result is a 3.2.4 Binary to MLT-3 Convertor / Common Driver

scrambled data stream with sufficient randomization to

The Binary to MLT-3 conversion is accomplished by con-

decrease radiated emissions at certain frequencies by as

verting the serial binary data stream output from the NRZI

much as 20 dB. The DP83847 uses the PHY_ID (pins

encoder into two binary data streams with alternately

PHYAD [4:0]) to set a unique seed value.

phased logic one events. These two binary streams are

then fed to the twisted pair output driver which converts the

voltage to current and alternately drives either side of the

3.2.3 NRZ to NRZI Encoder

After the transmit data stream has been serialized and transmit transformer primary winding, resulting in a minimal

scrambled, the data must be NRZI encoded in order to current (20 mA max) MLT-3 signal. Refer to Figure 5 .

comply with the TP-PMD standard for 100BASE-TX trans-

mission over Category-5 Unsheilded twisted pair cable.

binary_in

binary_plus

Q

D

binary_minus

differential MLT-3

binary_plus

binary_in

COMMON

DRIVER

MLT-3

binary_minus

Figure 5. Binary to MLT-3 conversion

18

www.national.com

Table 5. 4B5B Code-Group Encoding/Decoding

Name

PCS 5B Code-group

MII 4B Nibble Code

DATA CODES

0

11110

01001

10100

10101

01010

01011

01110

01111

10010

10011

10110

10111

11010

11011

11100

11101

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

IDLE AND CONTROL CODES

H

00100

11111

11000

10001

01101

00111

HALT code-group - Error code

I

Inter-Packet IDLE - 0000 (Note 1)

First Start of Packet - 0101 (Note 1)

Second Start of Packet - 0101 (Note 1)

First End of Packet - 0000 (Note 1)

Second End of Packet - 0000 (Note 1)

J

K

T

R

INVALID CODES

V

00000

00001

00010

00011

00101

00110

01000

01100

10000

11001

Note 1: Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER asserted.

19

www.national.com

The 100BASE-TX MLT-3 signal sourced by the TD± com- — ADC

mon driver output pins is slew rate controlled. This should

— Input and BLW Compensation

be considered when selecting AC coupling magnetics to

ensure TP-PMD Standard compliant transition times (3 ns

< Tr < 5 ns).

— Signal Detect

— Digital Adaptive Equalization

— MLT-3 to Binary Decoder

— Clock Recovery Module

— NRZI to NRZ Decoder

— Serial to Parallel

The 100BASE-TX transmit TP-PMD function within the

DP83847 is capable of sourcing only MLT-3 encoded data.

Binary output from the TD± outputs is not possible in 100

Mb/s mode.

— DESCRAMBLER (bypass option)

— Code Group Alignment

3.3 100BASE-TX RECEIVER

The 100BASE-TX receiver consists of several functional

blocks which convert the scrambled MLT-3 125 Mb/s serial — 4B/5B Decoder (bypass option)

data stream to synchronous 4-bit nibble data that is pro-

vided to the MII. Because the 100BASE-TX TP-PMD is

integrated, the differential input pins, RD±, can be directly

— Link Integrity Monitor

— Bad SSD Detection

The bypass option for the functional blocks within the

100BASE-TX receiver provides flexibility for applications

where data conversion is not always required.

routed from the AC coupling magnetics.

See Figure 7 for a block diagram of the 100BASE-TX

receive function. This provides an overview of each func-

tional block within the 100BASE-TX receive section.

3.3.1 Input and Base Line Wander Compensation

The Receive section consists of the following functional

blocks:

Unlike the DP83223V Twister, the DP83847 requires no

external attenuation circuitry at its receive inputs, RD±. It

accepts TP-PMD compliant waveforms directly, requiring

only a 100Ω termination plus a simple 1:1 transformer.

Figure 6. 100BASE-TX BLW Event

The DP83847 is completely ANSI TP-PMD compliant and quency response of the AC coupling component(s) within

includes Base Line Wander (BLW) compensation. The the transmission system. If the low frequency content of

BLW compensation block can successfully recover the TP- the digital bit stream goes below the low frequency pole of

PMD defined “killer” pattern and pass it to the digital adap- the AC coupling transformers then the droop characteris-

tive equalization block.

tics of the transformers will dominate resulting in potentially

serious BLW.

BLW can generally be defined as the change in the aver-

age DC content, over time, of an AC coupled digital trans- The digital oscilloscope plot provided in Figure 6 illustrates

mission over a given transmission medium. (i.e., copper the severity of the BLW event that can theoretically be gen-

wire).

erated during 100BASE-TX packet transmission. This

event consists of approximately 800 mV of DC offset for a

BLW results from the interaction between the low fre-

quency components of a transmitted bit stream and the fre-

20

www.national.com

RX_CLK

÷5

RXD[3:0] / RX_ER

MUX

BP_4B5B

4B/5BDECODER

SERIAL TO

PARALLEL

CODE GROUP

ALIGNMENT

BP_SCR

MUX

DESCRAMBLER

CLOCK

NRZI TO NRZ

DECODER

CLOCK

RECOVERY

MODULE

LINK STATUS

MLT-3 TO

BINARY

DECODER

DIGITAL

ADAPTIVE

LINK

MONITOR

EQUALIZATION

AGC

SIGNAL

DETECT

INPUT BLW

COMPENSATION

ADC

RD±

Figure 7. Receive Block Diagram

21

www.national.com

period of 120 µs. Left uncompensated, events such as this 125 Mb/s data stream and extracts a 125 MHz recovered

can cause packet loss.

clock. The extracted and synchronized clock and data are

used as required by the synchronous receive operations as

generally depicted in Figure 7.

3.3.2 Signal Detect

The CRM is implemented using an advanced all digital

Phase Locked Loop (PLL) architecture that replaces sensi-

tive analog circuitry. Using digital PLL circuitry allows the

DP83847 to be manufactured and specified to tighter toler-

ances.

The signal detect function of the DP83847 is incorporated

to meet the specifications mandated by the ANSI FDDI TP-

PMD Standard as well as the IEEE 802.3 100BASE-TX

Standard for both voltage thresholds and timing parame-

ters.

Note that the reception of normal 10BASE-T link pulses

and fast link pulses per IEEE 802.3u Auto-Negotiation by

3.3.5 NRZI to NRZ

the 100BASE-TX receiver do not cause the DP83847 to In a typical application, the NRZI to NRZ decoder is

assert signal detect.

required in order to present NRZ formatted data to the

descrambler (or to the code-group alignment block, if the

descrambler is bypassed, or directly to the PCS, if the

receiver is bypassed).

3.3.3 Digital Adaptive Equalization

When transmitting data at high speeds over copper twisted

pair cable, frequency dependent attenuation becomes a

concern. In high-speed twisted pair signalling, the fre-

3.3.6 Serial to Parallel

quency content of the transmitted signal can vary greatly The 100BASE-TX receiver includes a Serial to Parallel

during normal operation based primarily on the random- converter which supplies 5-bit wide data symbols to the

ness of the scrambled data stream. This variation in signal PCS Rx state machine.

attenuation caused by frequency variations must be com-

pensated for to ensure the integrity of the transmission.

3.3.7 Descrambler

In order to ensure quality transmission when employing

MLT-3 encoding, the compensation must be able to adapt

to various cable lengths and cable types depending on the

installed environment. The selection of long cable lengths

for a given implementation, requires significant compensa-

tion which will over-compensate for shorter, less attenuat-

ing lengths. Conversely, the selection of short or

intermediate cable lengths requiring less compensation will

cause serious under-compensation for longer length

cables. The compensation or equalization must be adap-

tive to ensure proper conditioning of the received signal

independent of the cable length.

A serial descrambler is used to de-scramble the received

NRZ data. The descrambler has to generate an identical

data scrambling sequence (N) in order to recover the origi-

nal unscrambled data (UD) from the scrambled data (SD)

as represented in the equations:

SD= (UD N)

UD= (SD N)

Synchronization of the descrambler to the original scram-

bling sequence (N) is achieved based on the knowledge

that the incoming scrambled data stream consists of

scrambled IDLE data. After the descrambler has recog-

nized 12 consecutive IDLE code-groups, where an

unscrambled IDLE code-group in 5B NRZ is equal to five

consecutive ones (11111), it will synchronize to the receive

data stream and generate unscrambled data in the form of

unaligned 5B code-groups.

The DP83847 utilizes a extremely robust equalization

scheme referred as ‘Digital Adaptive Equalization’. Tradi-

tional designs use a pseudo adaptive equalization scheme

that determines the approximate cable length by monitor-

ing signal attenuation at certain frequencies. This attenua-

tion value was compared to the internal receive input

reference voltage. This comparison would indicate the

amount of equalization to use. Although this scheme is

used successfully on the DP83223V twister, it is sensitive

to transformer mismatch, resistor variation and process

induced offset. The DP83223V also required an external

attenuation network to help match the incoming signal

amplitude to the internal reference.

In order to maintain synchronization, the descrambler must

continuously monitor the validity of the unscrambled data

that it generates. To ensure this, a line state monitor and a

hold timer are used to constantly monitor the synchroniza-

tion status. Upon synchronization of the descrambler the

hold timer starts a 722 µs countdown. Upon detection of

sufficient IDLE code-groups (58 bit times) within the 722 µs

period, the hold timer will reset and begin a new count-

down. This monitoring operation will continue indefinitely

given a properly operating network connection with good

signal integrity. If the line state monitor does not recognize

sufficient unscrambled IDLE code-groups within the 722 µs

period, the entire descrambler will be forced out of the cur-

rent state of synchronization and reset in order to re-

acquire synchronization.

The Digital Equalizer removes ISI (inter symbol interfer-

ence) from the receive data stream by continuously adapt-

ing to provide a filter with the inverse frequency response

of the channel. When used in conjunction with a gain

stage, this enables the receive 'eye pattern' to be opened

sufficiently to allow very reliable data recovery.

Traditionally 'adaptive' equalizers selected 1 of N filters in

an attempt to match the cables characteristics. This

approach will typically leave holes at certain cable lengths,

where the performance of the equalizer is not optimized.

3.3.8 Code-group Alignment

The code-group alignment module operates on unaligned

5-bit data from the descrambler (or, if the descrambler is

bypassed, directly from the NRZI/NRZ decoder) and con-

verts it into 5B code-group data (5 bits). Code-group align-

ment occurs after the J/K code-group pair is detected.

Once the J/K code-group pair (11000 10001) is detected,

subsequent data is aligned on a fixed boundary.

The DP83847 equalizer is truly adaptive to any length of

cable up to 150m.

3.3.4 Clock Recovery Module

The Clock Recovery Module (CRM) accepts 125 Mb/s

MLT3 data from the equalizer. The DPLL locks onto the

22

www.national.com

3.3.9 4B/5B Decoder

3.4.2 Collision Detection and SQE

The code-group decoder functions as a look up table that When in Half Duplex, a 10BASE-T collision is detected

translates incoming 5B code-groups into 4B nibbles. The when the receive and transmit channels are active simulta-

code-group decoder first detects the J/K code-group pair neously. Collisions are reported by the COL signal on the

preceded by IDLE code-groups and replaces the J/K with MII. Collisions are also reported when a jabber condition is

MAC preamble. Specifically, the J/K 10-bit code-group pair detected.

is replaced by the nibble pair (0101 0101). All subsequent

The COL signal remains set for the duration of the collision.

5B code-groups are converted to the corresponding 4B

If the ENDEC is receiving when a collision is detected it is

nibbles for the duration of the entire packet. This conver-

reported immediately (through the COL pin).

sion ceases upon the detection of the T/R code-group pair

When heartbeat is enabled, approximately 1 µs after the

transmission of each packet, a Signal Quality Error (SQE)

signal of approximately 10-bit times is generated to indi-

cate successful transmission. SQE is reported as a pulse

on the COL signal of the MII.

denoting the End of Stream Delimiter (ESD) or with the

reception of a minimum of two IDLE code-groups.

3.3.10 100BASE-TX Link Integrity Monitor

The 100 Base TX Link monitor ensures that a valid and sta-

ble link is established before enabling both the Transmit

and Receive PCS layer.

The SQE test is inhibited when the PHY is set in full duplex

mode. SQE can also be inhibited by setting the

HEARTBEAT_DIS bit in the 10BTSCR register.

Signal detect must be valid for 395us to allow the link mon-

itor to enter the 'Link Up' state, and enable the transmit and

receive functions.

3.4.3 Carrier Sense

Carrier Sense (CRS) may be asserted due to receive activ-

ity once valid data is detected via the squelch function.

3.3.11 Bad SSD Detection

For 10 Mb/s Half Duplex operation, CRS is asserted during

either packet transmission or reception.

A Bad Start of Stream Delimiter (Bad SSD) is any transition

from consecutive idle code-groups to non-idle code-groups

which is not prefixed by the code-group pair /J/K.

For 10 Mb/s Full Duplex operation, CRS is asserted only

during receive activity.

If this condition is detected, the DP83847 will assert

RX_ER and present RXD[3:0] = 1110 to the MII for the

cycles that correspond to received 5B code-groups until at

least two IDLE code groups are detected. In addition, the

False Carrier Sense Counter register (FCSCR) will be

incremented by one.

CRS is deasserted following an end of packet.

3.4.4 Normal Link Pulse Detection/Generation

The link pulse generator produces pulses as defined in the

IEEE 802.3 10BASE-T standard. Each link pulse is nomi-

nally 100 ns in duration and transmitted every 16 ms in the

absence of transmit data.

Once at least two IDLE code groups are detected, RX_ER

and CRS become de-asserted.

Link pulses are used to check the integrity of the connec-

tion with the remote end. If valid link pulses are not

3.4 10BASE-T TRANSCEIVER MODULE

The 10BASE-T Transceiver Module is IEEE 802.3 compli- received, the link detector disables the 10BASE-T twisted

ant. It includes the receiver, transmitter, collision, heart- pair transmitter, receiver and collision detection functions.

beat, loopback, jabber, and link integrity functions, as

When

the

link

integrity

function

is

disabled

defined in the standard. An external filter is not required on

the 10BASE-T interface since this is integrated inside the

DP83847. This section focuses on the general 10BASE-T

system level operation.

(FORCE_LINK_10 of the 10BTSCR register), good link is

forced and the 10BASE-T transceiver will operate regard-

less of the presence of link pulses.

3.4.5 Jabber Function

3.4.1 Operational Modes

The jabber function monitors the DP83847's output and

disables the transmitter if it attempts to transmit a packet of

longer than legal size. A jabber timer monitors the transmit-

ter and disables the transmission if the transmitter is active

beyond the Jab time (20-150 ms).

The DP83847 has two basic 10BASE-T operational

modes:

— Half Duplex mode

— Full Duplex mode

Once disabled by the Jabber function, the transmitter stays

disabled for the entire time that the ENDEC module's inter-

nal transmit enable is asserted. This signal has to be de-

asserted for approximately 250-750 ms (the “unjab” time)

before the Jabber function re-enables the transmit outputs.

Half Duplex Mode

In Half Duplex mode the DP83847 functions as a standard

IEEE 802.3 10BASE-T transceiver supporting the

CSMA/CD protocol.

The Jabber function is only relevant in 10BASE-T mode.

Full Duplex Mode

3.4.6 Automatic Link Polarity Detection and Correction

In Full Duplex mode the DP83847 is capable of simulta-

neously transmitting and receiving without asserting the

collision signal. The DP83847's 10 Mb/s ENDEC is

designed to encode and decode simultaneously.

The DP83847's 10BASE-T transceiver module incorpo-

rates an automatic link polarity detection circuit. When

seven consecutive inverted link pulses are received,

inverted polarity is reported.

23

www.national.com

A polarity reversal can be caused by a wiring error at either Transmission ends when TX_EN deasserts. The last tran-

end of the cable, usually at the Main Distribution Frame sition is always positive; it occurs at the center of the bit cell

(MDF) or patch panel in the wiring closet.

if the last bit is a one, or at the end of the bit cell if the last

bit is a zero.

The inverse polarity condition is latched in the 10BTSCR

register. The DP83847's 10BASE-T transceiver module

corrects for this error internally and will continue to decode

received data correctly. This eliminates the need to correct

the wiring error immediately.

3.4.9 Receiver

The decoder consists of a differential receiver and a PLL to

separate a Manchester encoded data stream into internal

clock signals and data. The differential input must be exter-

nally terminated with a differential 100Ω termination net-

work to accommodate UTP cable. The impedance of RD±

(typically 1.1KΩ) is in parallel with the two 54.9Ω resistors

as is shown in Figure 8 below to approximate the 100Ω

termination.

The user is cautioned that if Auto Polarity Detection and

Correction is disabled and inverted Polarity is detected but

not corrected, the DsPHYTER may falsely report Good

Link status and allow Transmission and Reception of

inverted data. It is recommended that Auto Polarity Detec-

tion and Correction not be disabled during normal opera-

tion.

The decoder detects the end of a frame when no additional

mid-bit transitions are detected. Within one and a half bit

times after the last bit, carrier sense is de-asserted.

3.4.7 Transmit and Receive Filtering

External 10BASE-T filters are not required when using the

DP83847, as the required signal conditioning is integrated

into the device.

3.5 TPI Network Circuit

Figure 8 shows the recommended circuit for a 10/100 Mb/s

twisted pair interface. Below is a partial list of recom-

mended transformers. Is is important that the user realize

that variations with PCB and component characteristics

requires that the application be tested to ensure that the

circuit meets the requirements of the intended application.

Only isolation/step-up transformers and impedance match-

ing resistors are required for the 10BASE-T transmit and

receive interface. The internal transmit filtering ensures

that all the harmonics in the transmit signal are attenuated

by at least 30 dB.

Pulse PE-68515

Pulse PE-68515L

Pulse H1012B

3.4.8 Transmitter

The encoder begins operation when the Transmit Enable

input (TX_EN) goes high and converts NRZ data to pre-

emphasized Manchester data for the transceiver. For the

duration of TX_EN, the serialized Transmit Data (TXD) is

encoded for the transmit-driver pair (TD±). TXD must be

valid on the rising edge of Transmit Clock (TX_CLK).

Halo TG22-S052ND

Valor PT4171

BELFUSE S558-5999-K2

BELFUSE S558-5999-46

COMMON MODE CHOKES

MAY BE REQUIRED.

1:1

RD-

0.1µF*

RD+

TD-

RD+

Vdd

TD-

TD+

0.1µF*

TD+

RJ45

T1

1:1

49.9Ω

49.9 Ω

* PLACE CAPACITORS

CLOSE TO THE

54.9Ω 54.9

Ω

TRANSFORMER CENTER

TAPS

0.1µF

Figure 8. 10/100 Mb/s Twisted Pair Interface

24

www.national.com

For applications where high reliability is required, it is rec-

ommended that additional ESD protection diodes be added

as shown below. There are numerous dual series con-

nected diode pairs that are available specifically for ESD

protection. The level of protection will vary dependent upon

the diode ratings. The primary parameter that affects the

level of ESD protection is peak forward surge current. Typi-

cal specifications for diodes intended for ESD protection

range from 500mA (Motorola BAV99LT1 single pair diodes)

3.6 ESD Protection

Typically, ESD precautions are predominantly in effect

when handling the devices or board before being installed

in a system. In those cases, strict handling procedures can

be implemented during the manufacturing process to

greatly reduce the occurrences of catastrophic ESD

events. After the system is assembled, internal compo-

nents are usually relatively immune from ESD events.

In the case of an installed Ethernet system however, the to 12A (STM DA108S1 Quad pair array). The user should

network interface pins are still susceptible to external ESD also select diodes with low input capacitance to minimize

events. For example, a category 5 cable being dragged the effect on system performance.

across a carpet has the potential of developing a charge

Since performance is dependent upon components used,

well above the typical ESD rating of a semiconductor

board impedance characteristics, and layout, the circuit

device.

should be completely tested to ensure performance to the

required levels.

DP83847 10/100

3.3V Vcc

Vcc

RJ-45

PIN 1

TX±

PIN 2

DIODES PLACED

ON THE DEVICE

SIDE OF THE

ISOLATION

Vcc

TRANSFORMER

PIN 3

PIN 6

RX±

Figure 9. Typical DP83847 Network Interface with additional ESD protection

25

www.national.com

3.7 Crystal Oscillator Circuit

3.8 Reference Bypass Couple

The DsPHYTER II supports an external CMOS level oscil- To ensure correct operation for the DP83847, parallel caps

lator source or a crystal resonator device. If an external with values of 10 µF (Tantalum preferred) and .1 µF should

clock source is used, X1 should be tied to the clock source be placed close to pin 42 (C1) of the device. See Figure 11

and X2 should be left floating. In either case, the clock below for proper use of caps.

source must be a 25 MHz 0.005% (50 PPM) CMOS oscilla-

tor or a 25 MHz (50 PPM), parallel, 20 pF load crystal reso-

nator. Figure 10 below shows a typical connection for a

crystal resonator circuit. The load capacitor values will vary

with the crystal vendors; check with the vendor for the rec-

Pin 42 (C1)

ommended loads.

The oscillator circuit was designed to drive a parallel reso-

nance AT cut crystal with a minimum drive level of 500µW

and a maximum of 1mW. If a crystal is specified for a lower

drive level, a current limiting resistor should be placed in

series between X2 and the crystal.

10 µF

.1 µF

As a starting point for evaluating an oscillator circuit, if the

requirements for the crystal are not known, C_L1and C_L2

should be set at 22 pF, and R₁should be set at 0Ω.

Figure 11. Reference Bypass Couple

X2

X1

R₁

C_L1

C_L2

Figure 10. Crystal Oscillator Circuit

RESET pin during normal operation. This will reset the

device such that all registers will be reset to default values

and the hardware configuration values will be re-latched

into the device (similar to the power-up/reset operation).

4.0 Reset Operation

The DP83847 can be reset either by hardware or software.

A hardware reset may be accomplished by asserting the

RESET pin after powering up the device (this is required)

or during normal operation when a reset is needed. A soft-

ware reset is accomplished by setting the reset bit in the

Basic Mode Control register.

4.2 Software Reset

A software reset is accomplished by setting the reset bit

(bit 15) of the Basic Mode Control Register (BMCR). The

period from the point in time when the reset bit is set to the

point in time when software reset has concluded is approx-

imately 160 µs.

While either the hardware or software reset can be imple-

mented at any time after device initialization, a hardware

reset, as described in Section 4.1 must be provided upon

device power-up/initialization. Omitting the hardware reset

operation during the device power-up/initialization

sequence can result in improper device operation.

The software reset will reset the device such that all regis-

ters will be reset to default values and the hardware config-

uration values will be re-latched into the device (similar to

the power-up/reset operation). Software driver code should

wait 500 µs following a software reset before allowing fur-

ther serial MII operations with the DP83847.

4.1 Hardware Reset

A hardware reset is accomplished by applying a low pulse

(TTL level), with a duration of at least 160 µs, to the

26

www.national.com

5.0 Register Block

Table 6. Register Map

Tag

BMCR

Offset

Access

Description

Basic Mode Control Register

Hex

00h

Decimal

0

1

RW

RO

RW

01h

BMSR

Basic Mode Status Register

02h

2

PHYIDR1

PHYIDR2

ANAR

PHY Identifier Register #1

03h

3

PHY Identifier Register #2

04h

4

Auto-Negotiation Advertisement Register

Auto-Negotiation Link Partner Ability Register (Base Page)

Auto-Negotiation Link Partner Ability Register (Next Page)

Auto-Negotiation Expansion Register

Auto-Negotiation Next Page TX

05h

5

ANLPAR

ANLPARNP

ANER

05h

5

06h

6

07h

7

ANNPTR

RESERVED

08h-Fh

8-15

RESERVED

Extended Registers

10h

11h-13h

14h

16

17-19

20

RO

PHYSTS

RESERVED

FCSCR

PHY Status Register

RESERVED

RW

False Carrier Sense Counter Register

Receive Error Counter Register

PCS Sub-Layer Configuration and Status Register

RESERVED

15h

21

RECR

16h

22

PCSR

17h

23

RESERVED

PHYCTRL

10BTSCR

CDCTRL

RESERVED

18h

24

RESERVED

19h

25

PHY Control Register

1Ah

26

10Base-T Status/Control Register

CD Test Control Register

RESERVED

1Bh

27

1Ch-1Fh

28

27

www.national.com

5.1 Register Definition

In the register definitions under the ‘Default’ heading, the following definitions hold true:

— RW=Read Write access

— SC=Register sets on event occurrence and Self-Clears when event ends

— RW/SC =Read Write access/Self Clearing bit

— RO=Read Only access

— COR = Clear on Read

— RO/COR=Read Only, Clear on Read

— RO/P=Read Only, Permanently set to a default value

— LL=Latched Low and held until read, based upon the occurrence of the corresponding event

— LH=Latched High and held until read, based upon the occurrence of the corresponding event

29

www.national.com

Table 7. Basic Mode Control Register (BMCR), Address 0x00

Bit

Bit Name

Default

Description

15

Reset

0, RW/SC Reset:

1 = Initiate software Reset / Reset in Process.

0 = Normal operation.

This bit, which is self-clearing, returns a value of one until the reset process is

complete. The configuration is re-strapped.

14

Loopback

0, RW Loopback:

1 = Loopback enabled.

0 = Normal operation.

The loopback function enables MII transmit data to be routed to the MII receive

data path.

Setting this bit may cause the descrambler to lose synchronization and produce a

500 µs “dead time” before any valid data will appear at the MII receive outputs.

13

12

Speed Selection Strap, RW Speed Select:

When auto-negotiation is disabled writing to this bit allows the port speed to be se-

lected.

1 = 100 Mb/s.

0 = 10 Mb/s.

Auto-Negotiation Strap, RW Auto-Negotiation Enable:

Enable

Strap controls initial value at reset.

1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this

bit is set.

0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex

mode.

11

Power Down

0, RW Power Down:

1 = Power down.

0 = Normal operation.

Setting this bit powers down the PHY. Only the register block is enabled during a

power down condition.

10

9

Isolate

0, RW Isolate:

1 = Isolates the Port from the MII with the exception of the serial management.

0 = Normal operation.

Restart Auto- 0, RW/SC Restart Auto-Negotiation:

Negotiation

1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If Auto-

Negotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and

will return a value of 1 until Auto-Negotiation is initiated, whereupon it will self-

clear. Operation of the Auto-Negotiation process is not affected by the manage-

ment entity clearing this bit.

0 = Normal operation.

8

7

Duplex Mode Strap, RW Duplex Mode:

When auto-negotiation is disabled writing to this bit allows the port Duplex capa-

bility to be selected.

1 = Full Duplex operation.

0 = Half Duplex operation.

Collision Test

RESERVED

0, RW Collision Test:

1 = Collision test enabled.

0 = Normal operation.

When set, this bit will cause the COL signal to be asserted in response to the as-

sertion of TX_EN within 512-bit times. The COL signal will be de-asserted within

4-bit times in response to the de-assertion of TX_EN.

6:0

0, RO RESERVED: Write ignored, read as 0.

30

www.national.com

Table 8. Basic Mode Status Register (BMSR), address 0x01

Bit

Bit Name

Default

Description

15

100BASE-T4

0, RO/P

100BASE-T4 Capable:

0 = Device not able to perform 100BASE-T4 mode.

100BASE-TX Full Duplex Capable:

14

13

12

11

100BASE-TX

Full Duplex

100BASE-TX

Half Duplex

10BASE-T

1, RO/P

1 = Device able to perform 100BASE-TX in full duplex mode.

100BASE-TX Half Duplex Capable:

1 = Device able to perform 100BASE-TX in half duplex mode.

10BASE-T Full Duplex Capable:

Full Duplex

10BASE-T

1 = Device able to perform 10BASE-T in full duplex mode.

10BASE-T Half Duplex Capable:

Half Duplex

RESERVED

MF Preamble

Suppression

1 = Device able to perform 10BASE-T in half duplex mode.

RESERVED: Write as 0, read as 0.

10:7

6

0, RO

1, RO/P

Preamble suppression Capable:

1 = Device able to perform management transaction with preamble

suppressed, 32-bits of preamble needed only once after reset, invalid

opcode or invalid turnaround.

0 = Normal management operation.

Auto-Negotiation Complete:

1 = Auto-Negotiation process complete.

0 = Auto-Negotiation process not complete.

Remote Fault:

5

4

Auto-Negotiation

Complete

0, RO

Remote Fault

0, RO/LH

1 = Remote Fault condition detected (cleared on read or by reset).

Fault criteria: Far End Fault Indication or notification from Link Part-

ner of Remote Fault.

0 = No remote fault condition detected.

Auto Negotiation Ability:

3

2

Auto-Negotiation

Ability

1, RO/P

1 = Device is able to perform Auto-Negotiation.

0 = Device is not able to perform Auto-Negotiation.

Link Status:

Link Status

0, RO/LL

1 = Valid link established (for either 10 or 100 Mb/s operation).

0 = Link not established.

The criteria for link validity is implementation specific. The occurrence

of a link failure condition will causes the Link Status bit to clear. Once

cleared, this bit may only be set by establishing a good link condition

and a read via the management interface.

1

0

Jabber Detect

0, RO/LH

Jabber Detect: This bit only has meaning in 10 Mb/s mode.

1 = Jabber condition detected.

0 = No Jabber.

This bit is implemented with a latching function, such that the occur-

rence of a jabber condition causes it to set until it is cleared by a read

to this register by the management interface or by a reset.

Extended Capabili-

ty

1, RO/P

Extended Capability:

1 = Extended register capabilities.

0 = Basic register set capabilities only.

31

www.national.com

The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83847. The Identifier consists of a

concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision num-

ber. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended

to support network management. National's IEEE assigned OUI is 080017h.

Table 9. PHY Identifier Register #1 (PHYIDR1), address 0x02

Bit

Bit Name

Default

Description

15:0

OUI_MSB

<0010 0000 0000 OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are

0000>, RO/P

stored in bits 15 to 0 of this register. The most significant two bits

of the OUI are ignored (the IEEE standard refers to these as bits 1

and 2).

Table 10. PHY Identifier Register #2 (PHYIDR2), address 0x03

Bit

Bit Name

Default

<01 0111>, RO/P OUI Least Significant Bits:

Bits 19 to 24 of the OUI (080017h) are mapped to bits 15 to 10 of

Description

15:10

OUI_LSB

this register respectively.

9:4

3:0

VNDR_MDL

MDL_REV

<00 0011>, RO/P Vendor Model Number:

The six bits of vendor model number are mapped to bits 9 to 4

(most significant bit to bit 9).

<0000>, RO/P

Model Revision Number:

Four bits of the vendor model revision number are mapped to bits

3 to 0 (most significant bit to bit 3). This field will be incremented for

all major device changes.

32

www.national.com

This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Nego-

tiation.

Table 11. Auto-Negotiation Advertisement Register (ANAR), address 0x04

Bit

Bit Name

Default

Description

15

NP

0, RW

Next Page Indication:

0 = Next Page Transfer not desired.

1 = Next Page Transfer desired.

14

13

RESERVED

RF

0, RO/P

0, RW

RESERVED by IEEE: Writes ignored, Read as 0.

Remote Fault:

1 = Advertises that this device has detected a Remote Fault.

0 = No Remote Fault detected.

12:11

10

RESERVED

PAUSE

0, RW

RESERVED for Future IEEE use: Write as 0, Read as 0

PAUSE: The default is set by the strap option for PAUSE_EN pin.

Strap, RW

1 = Advertise that the DTE (MAC) has implemented both the op-

tional MAC control sublayer and the pause function as specified in

clause 31 and annex 31B of 802.3u.

0= No MAC based full duplex flow control.

100BASE-T4 Support:

9

8

T4

TX_FD

TX

0, RO/P

1= 100BASE-T4 is supported by the local device.

0 = 100BASE-T4 not supported.

Strap, RW

100BASE-TX Full Duplex Support:

1 = 100BASE-TX Full Duplex is supported by the local device.

0 = 100BASE-TX Full Duplex not supported.

100BASE-TX Support:

7

1 = 100BASE-TX is supported by the local device.

0 = 100BASE-TX not supported.

6

10_FD

10

10BASE-T Full Duplex Support:

1 = 10BASE-T Full Duplex is supported by the local device.

0 = 10BASE-T Full Duplex not supported.

10BASE-T Support:

5

1 = 10BASE-T is supported by the local device.

0 = 10BASE-T not supported.

4:0

Selector

<00001>, RW Protocol Selection Bits:

These bits contain the binary encoded protocol selector supported

by this port. <00001> indicates that this device supports IEEE

802.3u.

33

www.national.com

This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content

changes after the successful autonegotiation if Next-pages are supported.

Table 12. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05

Bit

Bit Name

Default

Description

15

NP

0, RO

Next Page Indication:

0 = Link Partner does not desire Next Page Transfer.

1 = Link Partner desires Next Page Transfer.

Acknowledge:

14

13

ACK

RF

0, RO

1 = Link Partner acknowledges reception of the ability data word.

0 = Not acknowledged.

The Device's Auto-Negotiation state machine will automatically

control the this bit based on the incoming FLP bursts.

Remote Fault:

1 = Remote Fault indicated by Link Partner.

0 = No Remote Fault indicated by Link Partner.

RESERVED for Future IEEE use:

12:10

9

RESERVED

T4

0, RO

Write as 0, read as 0.

100BASE-T4 Support:

1 = 100BASE-T4 is supported by the Link Partner.

0 = 100BASE-T4 not supported by the Link Partner.

100BASE-TX Full Duplex Support:

8

7

TX_FD

TX

0, RO

1 = 100BASE-TX Full Duplex is supported by the Link Partner.

0 = 100BASE-TX Full Duplex not supported by the Link Partner.

100BASE-TX Support:

1 = 100BASE-TX is supported by the Link Partner.

0 = 100BASE-TX not supported by the Link Partner.

10BASE-T Full Duplex Support:

6

10_FD

10

1 = 10BASE-T Full Duplex is supported by the Link Partner.

0 = 10BASE-T Full Duplex not supported by the Link Partner.

10BASE-T Support:

5

1 = 10BASE-T is supported by the Link Partner.

0 = 10BASE-T not supported by the Link Partner.

4:0

Selector

<0 0000>, RO Protocol Selection Bits:

Link Partner’s binary encoded protocol selector.

34

www.national.com

Table 13. Auto-Negotiation Link Partner Ability Register (ANLPAR) Next Page, address 0x05

Bit

Bit Name

Default

Description

15

NP

0, RO

Next Page Indication:

1 = Link Partner desires Next Page Transfer.

0 = Link Partner does not desire Next Page Transfer.

Acknowledge:

14

ACK

0, RO

1 = Link Partner acknowledges reception of the ability data word.

0 = Not acknowledged.

The Device's Auto-Negotiation state machine will automatically

control the this bit based on the incoming FLP bursts. Software

should not attempt to write to this bit.

13

12

MP

0, RO

Message Page:

1 = Message Page.

0 = Unformatted Page.

Acknowledge 2:

ACK2

1 = Link Partner does have the ability to comply to next page mes-

sage.

0 = Link Partner does not have the ability to comply to next page

message.

11

Toggle

CODE

0, RO

Toggle:

1 = Previous value of the transmitted Link Code word equalled 0.

0 = Previous value of the transmitted Link Code word equalled 1.

10:0

<00000000000>, Code:

RO

This field represents the code field of the next page transmission.

If the MP bit is set (bit 13 of this register), then the code shall be

interpreted as a “Message Page”, as defined in annex 28C of

Clause 28. Otherwise, the code shall be interpreted as an “Unfor-

matted Page”, and the interpretation is application specific.

This register contains additional Local Device and Link Partner status information.

Table 14. Auto-Negotiate Expansion Register (ANER), address 0x06

Bit

15:5

4

Bit Name

RESERVED

PDF

Default

0, RO

Description

RESERVED: Writes ignored, Read as 0.

Parallel Detection Fault:

1 = A fault has been detected via the Parallel Detection function.

0 = A fault has not been detected.

3

LP_NP_ABLE

0, RO

Link Partner Next Page Able:

1 = Link Partner does support Next Page.

0 = Link Partner does not support Next Page.

Next Page Able:

2

1

NP_ABLE

PAGE_RX

1, RO/P

1 = Indicates local device is able to send additional “Next Pages”.

Link Code Word Page Received:

0, RO/COR

1 = Link Code Word has been received, cleared on a read.

0 = Link Code Word has not been received.

Link Partner Auto-Negotiation Able:

0

LP_AN_ABLE

0, RO

1 = indicates that the Link Partner supports Auto-Negotiation.

0 = indicates that the Link Partner does not support Auto-Negotia-

tion.

35

www.national.com

This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.

Table 15. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07

Bit

Bit Name

Default

Description

15

NP

0, RW

Next Page Indication:

0 = No other Next Page Transfer desired.

1 = Another Next Page desired.

RESERVED: Writes ignored, read as 0.

Message Page:

14

13

RESERVED

MP

0, RO

1, RW

1 = Message Page.

0 = Unformatted Page.

12

11

ACK2

0, RW

0, RO

Acknowledge2:

1 = Will comply with message.

0 = Cannot comply with message.

Acknowledge2 is used by the next page function to indicate that Lo-

cal Device has the ability to comply with the message received.

TOG_TX

Toggle:

1 = Value of toggle bit in previously transmitted Link Code Word

was 0.

0 = Value of toggle bit in previously transmitted Link Code Word

was 1.

Toggle is used by the Arbitration function within Auto-Negotiation

to ensure synchronization with the Link Partner during Next Page

exchange. This bit shall always take the opposite value of the Tog-

gle bit in the previously exchanged Link Code Word.

10:0

CODE

<00000000001>, This field represents the code field of the next page transmission.

RW

If the MP bit is set (bit 13 of this register), then the code shall be

interpreted as a "Message Page”, as defined in annex 28C of IEEE

802.3u. Otherwise, the code shall be interpreted as an "Unformat-

ted Page”, and the interpretation is application specific.

The default value of the CODE represents a Null Page as defined

in Annex 28C of IEEE 802.3u.

36

www.national.com

5.2 Extended Registers

This register provides a single location within the register set for quick access to commonly accessed information.

Table 16. PHY Status Register (PHYSTS), address 0x10

Bit

15:14

13

Bit Name

RESERVED

Default

0, RO

Description

RESERVED: Write ignored, read as 0.

Receive Error Latch:

Receive Error Latch

0, RO/LH

This bit will be cleared upon a read of the RECR register.

1 = Receive error event has occurred since last read of RXERCNT

(address 0x15, Page 0).

0 = No receive error event has occurred.

12

11

Polarity Status

0, RO

Polarity Status:

This bit is a duplication of bit 4 in the 10BTSCR register. This bit will

be cleared upon a read of the 10BTSCR register, but not upon a

read of the PHYSTS register.

1 = Inverted Polarity detected.

0 = Correct Polarity detected.

False Carrier Sense

Latch

0, RO/LH

False Carrier Sense Latch:

This bit will be cleared upon a read of the FCSR register.

1 = False Carrier event has occurred since last read of FCSCR (ad-

dress 0x14).

0 = No False Carrier event has occurred.

100Base-TX unconditional Signal Detect from PMD.

100Base-TX Descrambler Lock from PMD.

Link Code Word Page Received:

10

9

Signal Detect

Descrambler Lock

Page Received

0, RO/LL

0, RO

8

This is a duplicate of the Page Received bit in the ANER register,

but this bit will not be cleared upon a read of the PHYSTS register.

1 = A new Link Code Word Page has been received. Cleared on

read of the ANER (address 0x06, bit 1).

0 = Link Code Word Page has not been received.

37

www.national.com

Table 16. PHY Status Register (PHYSTS), address 0x10 (Continued)

Bit

7

Bit Name

RESERVED

Remote Fault

Default

0, RO

Description

RESERVED: Writes ignored, Read as 0.

Remote Fault:

6

1 = Remote Fault condition detected (cleared on read of BMSR (ad-

dress 01h) register or by reset). Fault criteria: notification from Link

Partner of Remote Fault via Auto-Negotiation.

0 = No remote fault condition detected.

5

Jabber Detect

0, RO

Jabber Detect: This bit only has meaning in 10 Mb/s mode

This bit is a duplicate of the Jabber Detect bit in the BMSR register,

except that it is not cleared upon a read of the PHYSTS register.

1 = Jabber condition detected.

0 = No Jabber.

4

3

2

Auto-Neg Complete

Loopback Status

Duplex Status

0, RO

Auto-Negotiation Complete:

1 = Auto-Negotiation complete.

0 = Auto-Negotiation not complete.

Loopback:

1 = Loopback enabled.

0 = Normal operation.

Duplex:

This bit indicates duplex status and is determined from Auto-Nego-

tiation or Forced Modes.

1 = Full duplex mode.

0 = Half duplex mode.

Note: This bit is only valid if Auto-Negotiation is enabled and com-

plete and there is a valid link or if Auto-Negotiation is disabled and

there is a valid link.

1

Speed Status

0, RO

Speed10:

This bit indicates the status of the speed and is determined from

Auto-Negotiation or Forced Modes.

1 = 10 Mb/s mode.

0 = 100 Mb/s mode.

Note: This bit is only valid if Auto-Negotiation is enabled and com-

plete and there is a valid link or if Auto-Negotiation is disabled and

there is a valid link.

0

Link Status

0, RO

Link Status:

This bit is a duplicate of the Link Status bit in the BMSR register,

except that it will no be cleared upon a read of the PHYSTS regis-

ter.

1 = Valid link established (for either 10 or 100 Mb/s operation).

0 = Link not established.

This counter provides information required to implement the “FalseCarriers” attribute within the MAU managed object

class of Clause 30 of the IEEE 802.3u specification.

Table 17. False Carrier Sense Counter Register (FCSCR), address 0x14

Bit

15:8

7:0

Bit Name

RESERVED

FCSCNT[7:0]

Default

0, RO

Description

RESERVED: Writes ignored, Read as 0

False Carrier Event Counter:

0, RW / COR

This 8-bit counter increments on every false carrier event. This

counter sticks when it reaches its max count (FFh).

38

www.national.com

This counter provides information required to implement managed object class of Clause 30 of the IEEE 802.3u

the “SymbolErrorDuringCarrier” attribute within the PHY specification.

Table 18. Receiver Error Counter Register (RECR), address 0x15

Bit

15:8

7:0

Bit Name

RESERVED

RXERCNT[7:0]

Default

0, RO

Description

RESERVED: Writes ignored, Read as 0

RX_ER Counter:

0, RW / COR

This 8-bit counter increments for each receive error detected.

When a valid carrier is present and there is at least one occurrence

of an invalid data symbol. This event can increment only once per

valid carrier event. If a collision is present, the attribute will not in-

crement. The counter sticks when it reaches its max count.

Table 19. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16

Bit

15:13

12

Bit Name

RESERVED

BYP_4B5B

Default

<00>, RO

0, RW

Description

RESERVED: Writes ignored, Read as 0.

Bypass 4B/5B Encoding:

1 = 4B5B encoder functions bypassed.

0 = Normal 4B5B operation.

11

10

9

FREE_CLK

TQ_EN

0, RW

1, RW

Receive Clock:

1 = RX_CK is free-running.

0 = RX_CK phase adjusted based on alignment.

100Mbs True Quiet Mode Enable:

1 = Transmit True Quiet Mode.

0 = Normal Transmit Mode.

SD FORCE PMA

SD_OPTION

Signal Detect Force PMA:

1 = Forces Signal Detection in PMA.

0 = Normal SD operation.

8

Signal Detect Option:

1 = Enhanced signal detect algorithm.

0 = Reduced signal detect algorithm.

39

www.national.com

Table 19. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 (Continued)

Bit

7

Bit Name

Unused

Default

0,RO

0

Description

6

RESERVED

RESERVED:

Must be zero.

5

FORCE_100_OK

0, RW

Force 100Mb/s Good Link:

1 = Forces 100Mb/s Good Link.

0 = Normal 100Mb/s operation.

RESERVED:

4

3

2

RESERVED

0

Must be zero.

RESERVED:

Must be zero.

NRZI_BYPASS

0, RW

NRZI Bypass Enable:

1 = NRZI Bypass Enabled.

0 = NRZI Bypass Disabled.

Scrambler Bypass Enable:

1 = Scrambler Bypass Enabled.

0 = Scrambler Bypass Disabled.

Descrambler Bypass Enable:

1 = Descrambler Bypass Enabled.

0 = Descrambler Bypass Disabled.

1

0

SCRAM_BYPASS

0, RW

DESCRAM_BYPASS

Table 20. Reserved Registers, addresses 0x17, 0x18

Bit

Bit Name

Default

Description

RESERVED: Must not be written to during normal operation.

15:0

RESERVED

none, RW

40

www.national.com

Table 21. PHY Control Register (PHYCTRL), address 0x19

Bit

15:12

11

Bit Name

Unused

Default

0, RO

Description

PSR_15

0, RW

BIST Sequence select:

1 = PSR15 selected.

0 = PSR9 selected.

BIST Test Status:

1 = BIST pass.

10

9

BIST_STATUS

BIST_START

BP_STRETCH

0, RO/LL

0, RW

0 = BIST fail. Latched, cleared by write to BIST_ START bit.

BIST Start:

1 = BIST start.

0 = BIST stop.

8

0, RW

Bypass LED Stretching:

This will bypass the LED stretching for the Receive, Transmit and

Collision LEDs.

1 = Bypass LED stretching.

0 = Normal operation.

7

PAUSE_STS

0, RO

Pause Compare Status:

0 = Local Device and the Link Partner are not Pause capable.

1 = Local Device and the Link Partner are both Pause capable.

Reserved: Must be 1.

6

5

RESERVED

LED_CNFG

1, RO/P

This bit is used to bypass the selective inversion on the LED output

for DPLX - this enables its use in non-LED applications.

Strap, RW

Mode Description

1 = Led polarity adjusted - DPLX selected.

0 = DPLX active HIGH.

4:0

PHYADDR[4:0]

Strap, RW

PHY Address: PHY address for port.

41

www.national.com

Table 22. 10Base-T Status/Control Register (10BTSCR), Address 0x1A

Bit

15:9

8

Bit Name

Unused

Default

0, RO

Description

LOOPBACK_10_DIS

0, RW

10BASE-T Loopback Disable:

If bit 14 (Loopback) in the BMCR is 0:

1 = 10 Mb/s Loopback is disabled.

If bit 14 (Loopback) in the BMCR is 1:

1 = 10 Mb/s Loopback is enabled.

Normal Link Pulse Disable:

1 = Transmission of NLPs is disabled.

0 = Transmission of NLPs is enabled.

Force 10Mb Good Link:

7

6

LP_DIS

0, RW

FORCE_LINK_10

1 = Forced Good 10Mb Link.

0 = Normal Link Status.

5

4

RESERVED

POLARITY

0, RW

RESERVED:

Must be zero.

RO/LH

10Mb Polarity Status:

This bit is a duplication of bit 12 in the PHYSTS register. Both bits

will be cleared upon a read of 10BTSCR register, but not upon a

read of the PHYSIS register.

1 = Inverted Polarity detected.

0 = Correct Polarity detected.

RESERVED:

3

2

1

RESERVED

0, RW

1, RW

0, RW

Must be zero.

RESERVED:

Must be set to one.

HEARTBEAT_DIS

Heartbeat Disable: This bit only has influence in half-duplex 10Mb

mode.

1 = Heartbeat function disabled.

0 = Heartbeat function enabled.

When the device is operating at 100Mb or configured for full

duplex operation, this bit will be ignored - the heartbeat func-

tion is disabled.

0

JABBER_DIS

0, RW

Jabber Disable:

Applicable only in 10BASE-T.

1 = Jabber function disabled.

0 = Jabber function enabled.

42

www.national.com

Table 23. CD Test Register (CDCTRL), Address 0x1B

Bit

Bit Name

Default

Description

15

CD_ENABLE

1, RW

CD Enable:

1 = CD Enabled - power-down mode, outputs high impedance.

0 = CD Disabled.

14

13

DCDCOMP

FIL_TTL

0, RW

Duty Cycle Distortion Compensation:

1 = Increases the amount of DCD compensation.

Waveshaper Current Source Test:

To check ability of waveshaper current sources to switch on/off.

1 = Test mode; waveshaping is done, but the output is a square

wave. All sources are either on or off.

0 = Normal mode; sinusoidal.

12

RESERVED

none, RW

Reserved: This bit should be written with a 0 if write access is re-

quired on this register.

11

10

RISETIME

Strap, RW

none, RW

CD Rise Time Control:

RESERVED

Reserved: This bit should be written with a 0 if write access is re-

quired on this register.

9

8

FALLTIME

Strap, RW

0, RW

CD Fall Time Control:

CD Test Mode Enable:

CDTESTEN

1 = Enable CD test mode - differs based on speed of operation

(10/100Mb).

0 = Normal operation.

RESERVED:

7:5

4

RESERVED[2:0]

CDPATTEN_10

000, RW

0, RW

Must be zero.

CD Pattern Enable for 10meg:

1 = Enabled.

0 = Disabled.

3

2

CDPATTEN_100

10MEG_PATT_GAP

CDPATTSEL[1:0]

0, RW

CD Pattern Enable for 100meg:

1 = Enabled.

0 = Disabled.

Defines gap between data or NLP test sequences:

1 = 15 µs.

0 = 10 µs.

1:0

00, RW

CD Pattern Select[1:0]:

If CDPATTEN_100 = 1:

00 = All 0’s (True quiet)

01 = All 1’s

10 = 2 1’s, 2 0’s repeating pattern

11 = 14 1’s, 6 0’s repeating pattern

If CDPATTEN_10 = 1:

00 = Data, EOP0 sequence

01 = Data, EOP1 sequence

10 = NLPs

11 = Constant Manchester 1s (10mhz sine wave) for harmonic dis-

tortion testing.

43

www.national.com

6.0 Electrical Specifications

Recommended Operating Conditions

Supply voltage (V_CC

Absolute Maximum Ratings

)

3.3 Volts + 0.3V

Supply Voltage (V_CC

)

-0.5 V to 4.2 V

-0.5V to 5.5V

Ambient Temperature (T_A)

DC Input Voltage (V_IN)

0 to 70 °C

150 °C

Max. die temperature (Tj)

Max case temp

DC Output Voltage (V_OUT

)

TBD °C

-65^oC to 150°C

240 °C

Storage Temperature (T_STG

)

Absolute maximum ratings are those values beyond which

the safety of the device cannot be guaranteed. They are

not meant to imply that the device should be operated at

these limits.

Lead Temp. (TL)

(Soldering, 10 sec)

ESD Rating

(R_ZAP= 1.5k, C_ZAP= 120 pF)

2.0 kV

1.0 kV

TPTD+/- ESD Rating

Max

Units

Thermal Characteristic

Theta Junction to Case (T_jc)

3.75

°C / W

Theta Junction to Ambient (T_ja) degrees Celsius/Watt - No Airflow @ 1.0W

Note:0 DC Electrical Specification

27.2

°C / W

Symbol

V_IH

Pin Types

Parameter

Conditions

Min

Typ

Max

Units

I

Input High Voltage Nominal V_CC

1.5

V

I/O

V_IL

I

Input Low Voltage

1.1

V

I/O

I_IH

I

Input High Current V_IN= V_CC

Input Low Current V_IN= GND

1.1

µA

V

I/O

I_IL

I

-.15

I/O

V_OL

O,

I/O

Output Low

Voltage

I_OL= 4 mA

.09

.4

V_OH

O,

I/O

Output High

Voltage

I_OH= -4 mA

* I_OL= 2.5 mA

I_OH= -2.5 mA

V_OUT= V_CC

V_IN= 5.25 V

V_OUT= 5.25 V

Vcc - 0.5

Vcc - 0.25

V

V_ledOL

V_ledOH

I_OZH

LED

Output Low

Voltage

V

LED

Output High

Voltage

V

I/O,

O

TRI-STATE

Leakage

.13

5.5

µA

kΩ

V

I_5IH

I/O,

O

5 Volt Tolerant

MII Leakage

I_5OZH

R_INdiff

V_{TPTD_100}

V_TPTDsym

I/O,

O

5 Volt Tolerant

MII Leakage

5.5

RD+/−

TD+/−

Differential Input

Resistance

1.2

100M Transmit

Voltage

.99

100M Transmit

+/-.5

%

Voltage Symmetry

44

www.national.com

Symbol

Pin Types

Parameter

Conditions

Min

Typ

Max

Units

V_{TPTD_10}

TD+/−

10M Transmit

Voltage

2.2

2.5

2.8

V

C_IN1

I

CMOS Input

Capacitance

Parameter is not

100% tested

1

pF

SD_THon

RD+/−

100BASE-TX

Signal detect turn-

on threshold

295

1000 mV diff

pk-pk

SD_THoff

RD+/−

100BASE-TX

Signal detect turn-

off threshold

200

300

mV diff

pk-pk

V_TH1

RD+/−

10BASE-T Re-

ceive Threshold

476

106

585

mV

mA

I_dd100

Supply

100BASE-TX

(Full Duplex)

I_OUT= 0 mA

See Note

I_dd10

Supply

10BASE-T

(Full Duplex)

I_OUT= 0 mA

See Note

90.5

mA

Note: For Idd Measurements, outputs are not loaded.

45

www.national.com

6.1 Reset Timing

V_CC

X1 Clock

T1.0.1

T1.0.4

HARDWARE

RSTN

32 CLOCKS

MDC

T1.0.2

Latch-In of Hardware

Configuration Pins

T1.0.3

INPUT

OUTPUT

Dual Function Pins

Become Enabled As Outputs

Parameter

Description

Notes

Min

Typ Max Units

T1.0.1

Post RESET Stabilization time MDIO is pulled high for 32-bit serial man-

prior to MDC preamble for reg- agement initialization.

ister accesses

3

µs

T1.0.2

Hardware Configuration Latch- Hardware Configuration Pins are de-

in Time from the Deassertion of scribed in the Pin Description section.

RESET (either soft or hard)

3

µs

T1.0.3

T1.0.4

Hardware Configuration pins

transition to output drivers

3.5

µs

RESET pulse width

X1 Clock must be stable for at min. of

160us during RESET pulse low time.

160

Note1: Software Reset should be initiated no sooner then 500 µs after power-up or the deassertion of hardware reset.

Note2: It is important to choose pull-up and/or pull-down resistors for each of the hardware configuration pins that provide

fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver.

46

www.national.com

6.2 PGM Clock Timing

X1

TX_CLK

T2.0.1

Parameter

Description

TX_CLK Duty Cycle

Notes

Min

Typ

Max

Units

T2.0.1

35

65

%

6.3 MII Serial Management Timing

MDC

T3.0.1

T3.0.4

MDIO (output)

MDC

T3.0.2

T3.0.3

Valid Data

MDIO (input)

Parameter

T3.0.1

Description

Notes

Min

0

Typ

Max

Units

ns

MDC to MDIO (Output) Delay Time

MDIO (Input) to MDC Setup Time

MDIO (Input) to MDC Hold Time

MDC Frequency

300

T3.0.2

10

ns

T3.0.3

ns

T3.0.4

2.5

MHz

47

www.national.com

6.4 100 Mb/s Timing

6.4.1 100 Mb/s MII Transmit Timing

TX_CLK

T4.1.2

T4.1.1

TXD[3:0]

TX_EN

TX_ER

Valid Data

Parameter

Description

TXD[3:0], TX_EN, TX_ER Data Setup to

Notes

Min Typ Max Units

T4.1.1

10

ns

TX_CLK

T4.1.2

TXD[3:0], TX_EN, TX_ER Data Hold from

TX_CLK

5

ns

6.4.2 100 Mb/s MII Receive Timing

T4.2.1

RX_CLK

T4.2.2

RXD[3:0]

RX_DV

RX_ER

Valid Data

Parameter

T4.2.1

Description

RX_CLK Duty Cycle

RX_CLK to RXD[3:0], RX_DV, RX_ER Delay

Notes

Min Typ Max Units

35

10

65

30

%

T4.2.2

ns

48

www.national.com

6.4.3 100BASE-TX Transmit Packet Latency Timing

TX_CLK

TX_EN

TXD

T4.3.1

IDLE

(J/K)

DATA

TD±

Parameter

Description

TX_CLK to TD± Latency

Notes

Min

Typ Max

Units

T4.3.1

6.0 bit times

Note: Latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of

TX_EN to the first bit of the “J” code group as output from the TD± pins.

6.4.4 100BASE-TX Transmit Packet Deassertion Timing

TX_CLK

TX_EN

TXD

T4.4.1

(T/R)

DATA

IDLE

TD±

DATA

Parameter

Description

Notes

Min

Typ Max

Units

T4.4.1

TX_CLK to TD± Deassertion

6.0 bit times

Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deasser-

tion of TX_EN to the first bit of the “T” code group as output from the TD± pins.

49

www.national.com

6.4.5 100BASE-TX Transmit Timing (t_R/F& Jitter)

T4.5.1

+1 rise

90%

10%

TD±

10%

90%

+1 fall

T4.5.1

-1 fall

-1 rise

T4.5.1

T4.5.2

TD±

eye pattern

T4.5.2

Parameter

Description

Notes

Min

Typ Max Units

T4.5.1

100 Mb/s TD± t_Rand t_F

3

4

5

ns

ps

ns

100 Mb/s t_Rand t_FMismatch

500

1.4

T4.5.2

100 Mb/s TD± Transmit Jitter

Note1: Normal Mismatch is the difference between the maximum and minimum of all rise and fall times.

Note2: Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude.

50

www.national.com

6.4.6 100BASE-TX Receive Packet Latency Timing

RD±

IDLE

(J/K)

Data

T4.6.1

CRS

T4.6.2

RXD[3:0]

RX_DV

RX_ER/RXD[4]

Parameter

T4.6.1

Description

Carrier Sense ON Delay

Receive Data Latency

Notes

Min

Typ Max

Units

17.5 bit times

21 bit times

T4.6.2

Note: Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion

of Carrier Sense.

Note: RD± voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.

6.4.7 100BASE-TX Receive Packet Deassertion Timing

RD±

DATA

(T/R)

IDLE

T4.7.1

CRS

RXD[3:0]

RX_DV

RX_ER/RXD[4]

Parameter

T4.7.1

Description

Carrier Sense OFF Delay

Notes

Min

Typ Max

Units

21.5 bit times

Note: Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deasser-

tion of Carrier Sense.

51

www.national.com

6.5 10 Mb/s Timing

6.5.1 10 Mb/s MII Transmit Timing

TX_CLK

T5.1.2

T5.1.1

TXD[3:0]

TX_EN

Valid Data

Parameter

T5.1.1

Description

Notes

Min Typ Max Units

TXD[3:0], TX_EN Data Setup to TX_CLK

TXD[3:0], TX_EN Data Hold from TX_CLK

25

5

ns

T5.1.2

6.5.2 10 Mb/s MII Receive Timing

T5.2.1

RX_CLK

T5.2.2

RXD[3:0]

RX_DV

Valid Data

Parameter

T5.2.1

Description

RX_CLK Duty Cycle

RX_CLK to RXD[3:0], RX_DV

Notes

Min Typ Max Units

35

65

%

T5.2.2

190

210

ns

52

www.national.com

6.5.3 10BASE-T Transmit Timing (Start of Packet)

TX_CLK

T5.3.1

TX_EN

TXD[0]

T5.3.2

T5.3.3

TPTD±

T5.3.4

Parameter

Description

Notes

Min

Typ

Max

Units

T5.3.1

Transmit Enable Setup Time from the

Falling Edge of TX_CLK

25

ns

T5.3.2

T5.3.3

T5.3.4

Transmit Data Setup Time from the

Falling Edge of TX_CLK

25

5

ns

Transmit Data Hold Time from the

Falling Edge of TX_CLK

Transmit Output Delay from the

Falling Edge of TX_CLK

6.8 bit times

6.5.4 10BASE-T Transmit Timing (End of Packet)

TX_CLK

TX_EN

T5.4.1

T5.4.2

0

TPTD±

T5.4.3

1

Parameter

Description

Notes

Min

Typ Max Units

T5.4.1

Transmit Enable Hold Time from the

Falling Edge of TX_CLK

5

ns

T5.4.2

T5.4.3

End of Packet High Time

(with ‘0’ ending bit)

250

ns

End of Packet High Time

(with ‘1’ ending bit)

250

53

www.national.com

6.5.5 10BASE-T Receive Timing (Start of Packet)

1st SFD bit decoded

1

0

1

TPRD±

T5.5.1

CRS

T5.5.2

RX_CLK

RXD[0]

T5.5.4

T5.5.3

RX_DV

Parameter

Description

Notes

Min

Typ Max

Units

T5.5.1

Carrier Sense Turn On Delay

1

µs

(TPRD± to CRS)

T5.5.2

T5.5.3

T5.5.4

Decoder Acquisition Time

Receive Data Latency

SFD Propagation Delay

3.6

µs

17.3 bit times

10 bit times

Note: 10BASE-T receive Data Latency is measured from first bit of preamble on the wire to the assertion of RX_DV.

6.5.6 10BASE-T Receive Timing (End of Packet)

IDLE

1

0

1

TPRD±

RX_CLK

T5.6.1

CRS

Parameter

Description

Carrier Sense Turn Off Delay

Notes

Min

Typ Max Units

1.1 µs

T5.6.1

54

www.national.com

6.5.7 10 Mb/s Heartbeat Timing

TXE

TXC

COL

T5.7.2

T5.7.1

Parameter

T5.7.1

Description

Notes

Min

600

500

Typ Max Units

CD Heartbeat Delay

1600

1500

ns

T5.7.2

CD Heartbeat Duration

6.5.8 10 Mb/s Jabber Timing

TXE

T5.8.1

T5.8.2

TPTD±

COL

Parameter

T5.8.1

Description

Jabber Activation Time

Jabber Deactivation Time

Notes

Min

20

Typ Max Units

150

750

ms

T5.8.2

250

6.5.9 10BASE-T Normal Link Pulse Timing

T5.9.2

T5.9.1

Normal Link Pulse(s)

Parameter

Description

Notes

Min

Typ Max Units

T5.9.1

T5.9.2

Pulse Width

Pulse Period

100

16

ns

8

24

ms

55

www.national.com

6.5.10 Auto-Negotiation Fast Link Pulse (FLP) Timing

T5.10.2

T5.10.3

T5.10.1

Fast Link Pulse(s)

clock

pulse

data

pulse

clock

pulse

T5.10.6

T5.10.5

T5.10.4

FLP Burst

Parameter

T5.10.1

Description

Notes

Min

Typ Max Units

Clock, Data Pulse Width

100

125

ns

T5.10.2

Clock Pulse to Clock Pulse

Period

111

55.5

17

139

69.5

33

µs

T5.10.3

Clock Pulse to Data Pulse

Period

Data = 1

µs

T5.10.4

T5.10.5

T5.10.6

Number of Pulses in a Burst

Burst Width

#

2

ms

FLP Burst to FLP Burst Period

8

24

6.5.11 100BASE-TX Signal Detect Timing

RD±

T5.11.1

T5.11.2

SD+ internal

Parameter

T5.11.1

Description

Notes

Min

Typ Max Units

SD Internal Turn-on Time

SD Internal Turn-off Time

1

ms

T5.11.2

300

µs

Note: The signal amplitude at RD± is TP-PMD compliant.

56

www.national.com

6.6 Loopback Timing

6.6.1 100 Mb/s Internal Loopback Mode

TX_CLK

TX_EN

TXD[3:0]

CRS

T6.1.1

RX_CLK

RX_DV

RXD[3:0]

Parameter

Description

Notes

100 Mb/s internal loopback mode

Min

Typ Max Units

240 ns

T6.1.1

TX_EN to RX_DV Loopback

Note1: Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time”

of up to 550 µs during which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is

based on device delays after the initial 550µs “dead-time”.

Note2: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.

57

www.national.com

6.6.2 10 Mb/s Internal Loopback Mode

TX_CLK

TX_EN

TXD[3:0]

CRS

T6.2.1

RX_CLK

RX_DV

RXD[3:0]

Parameter

Description

Notes

10 Mb/s internal loopback mode

Min

Typ Max Units

µs

T6.2.1

TX_EN to RX_DV Loopback

2

Note: Measurement is made from the first falling edge of TX_CLK after assertion of TX_EN.

58

www.national.com

6.7 Isolation Timing

Clear bit 10 of BMCR

(return to normal operation

from Isolate mode)

T7.0.1

H/W or S/W Reset

(with PHYAD = 00000)

T7.0.2

MODE

NORMAL

ISOLATE

Parameter

Description

Notes

Min

Typ Max Units

T7.0.1

From software clear of bit 10 in

the BMCR register to the transi-

tion from Isolate to Normal Mode

100

µs

T7.0.2

From Deassertion of S/W or H/W

Reset to transition from Isolate to

Normal mode

500

µs

59

www.national.com

7.0

Physical Dimensions

Leadless Leadframe Package (LLP)

Order Number DP83847 LQA56A

NS Package Number LQA-56A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

National Semiconductor

Corporation

Americas

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Email: support@nsc.com

National Semiconductor

Europe

National Semiconductor

Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

National Semiconductor

Japan Ltd.

Tel: 81-3-5639-7560

Fax: 81-3-5639-7507

Fax: +49 (0) 180-530 85 86

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208

English Tel: +44 (0) 870 24 0 2171

Francais Tel: +33 (0) 1 41 91 8790

Email: ap.support@nsc.com

www.national.com

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a

warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual

property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied

by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive

business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional

restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing

such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be

provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Audio

Applications

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

www.ti.com/industrial

www.ti.com/medical

www.ti.com/security

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

Medical

Security

Logic

Space, Avionics and Defense www.ti.com/space-avionics-defense

Transportation and Automotive www.ti.com/automotive

Power Mgmt

Microcontrollers

RFID

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Video and Imaging

www.ti.com/video

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community Home Page

e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DP83847ALQA56AX/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	10/100Mbps 以太网 PHY 收发器，具有可耐受 5V 电压的 I/O \| NJZ \| 56 \| 0 to 70 以太网局域网（LAN）标准以太网：16GBASE-T 电信电信集成电路
文件：	总62页 (文件大小：410K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DP83847ALQA56AX/NOPB [TI]

相关型号：

DP83847LQA56A

DP83848-EP

DP83848-HT

DP83848C

DP83848C

DP83848CVV

DP83848CVV/NOPB

DP83848CVV/NOPB

DP83848CVVX

DP83848CVVX/NOPB

DP83848CW

DP83848C_07