DM54L95W/883 [TI]
TTL/H/L SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP14, CERAMIC, FP-14;
| 型号： | DM54L95W/883 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TTL/H/L SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP14, CERAMIC, FP-14 CD 输出元件 逻辑集成电路 触发器 |
| 文件： | 总4页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1989
DM54L95 4-Bit Parallel Access Shift Registers
General Description
These 4-bit registers feature parallel and serial inputs, paral-
lel output, mode control, and two clock inputs. The registers
have three modes of operation.
mode control is high by connecting the output of each flip-
flop to the parallel input of the previous flip-flop (Q to input
D
C, etc.) and serial data is entered at input D. The clock input
may be applied simultaneously to clock 1 and clock 2 if both
modes can be clocked from the same source.
Parallel (broadside) load
Shift right (the direction Q toward Q )
A
Shift left (the direction Q toward Q )
D
Changes at the mode control input should normally be
made while both clock inputs are low; however, conditions
described in the last three lines of the truth table will also
ensure that register contents are protected.
D
A
Parallel loading is accomplished by applying the four bits of
data and taking the mode control input high. The data is
loaded into the associated flip-flops and appears at the out-
puts after the high-to-low transition of the clock-2 input. Dur-
ing loading, the entry of serial data is inhibited.
Features
Y
Typical maximum clock frequency 14 MHz
Shift right is accomplished on the high-to-low transition of
clock 1 when the mode control is low; shift left is accom-
plished on the high-to-low transition of clock 2 when the
Y
Typical power dissipation mW
Connection Diagram
Dual-In-Line Package
Order Number DM54L95J
or DM54L95W
See NS Package Number
J14A or W14B
TL/F/6638–1
Function Table
Inputs
Outputs
Clocks
Parallel
B
Mode
Control
Serial
Q
A
Q
Q
Q
D
B
C
2 (L) 1 (R)
A
C
D
H
H
H
L
L
H
v
v
L
X
X
L
L
L
H
H
X
X
X
H
v
v
L
L
H
L
X
X
X
X
H
L
X
X
X
X
X
X
a
X
b
X
c
X
d
d
Q
a
Q
Q
b
Q
Q
Q
AO
BO
CO
c
DO
d
²
²
²
Q
Q
Q
D
X
Q
d
Q
B
C
Bn
Cn
Dn
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Q
AO
Q
BO
Q
CO
DO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
An
An
Bn
Bn
Bn
Cn
Cn
L
Q
u
v
v
u
u
AO
AO
AO
AO
AO
CO
CO
CO
CO
CO
DO
DO
DO
DO
DO
Q
Q
Q
Q
BO
BO
BO
BO
Q
Q
Q
H
²
Shifting left requires external connection of Q to A, Q to B, Q to C. Serial data is entered at input D.
B
C
D
e
e
e
Low Level (Steady State), X
H
High Level (Steady State), L
Don’t Care (Any input, including transitions).
Transition from low to high level.
The level of steady state input at inputs A, B, C, or D, respectively.
e
v
a, b, c, d,
e
Transition from high to low level.
u
e
e
The level of Q , Q , Q , or Q , respectively, before the indicated steady state input conditions were established.
A B C D
Q , Q , Q , Q
AO BO CO
DO
e
Q
An
, Q , Q , Q
Bn Cn
The level of Q , Q , Q , or Q , respectively, before the most recent
B
transition of the clock.
v
Dn
A
C
D
C
1995 National Semiconductor Corporation
TL/F/6638
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Supply Voltage
Input Voltage
8V
5.5V
Operating Free Air Temperature Range
DM54L
b
b
a
55 C to 125 C
§
§
a
65 C to 150 C
Storage Temperature Range
§
§
Recommended Operating Conditions
DM54L95
Units
Symbol
Parameter
Min
4.5
2
Nom
Max
V
V
V
Supply Voltage
5
5.5
V
V
CC
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 1)
Pulse Width of Clock (Note 1)
Data Setup Time (Note 1)
IH
0.7
V
IL
b
I
I
0.2
mA
mA
MHz
ns
OH
OL
2
6
f
t
t
t
0
90
50
120
100
0
CLK
W(CLK)
SU
ns
Time to Enable
Clock (Note 1)
Clock 1
Clock 2
ns
EN
ns
t
t
Data Hold Time (Note 1)
ns
H
Time to Inhibit Clock 1 or Clock 2 (Note 1)
Free Air Operating Temperature
0
ns
IN
b
T
A
55
125
C
§
e
e
5V.
Note 1: T
25 C and V
§
A
CC
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
CC
e
e
V
High Level Output
Voltage
V
Min, I
OH
Max
Min
OH
OL
2.4
3.1
V
e
V
Max, V
IL
IH
e
e
e
e
V
Low Level Output
Voltage
V
V
Min, I
Max
Min
CC
OL
0.13
0.3
V
Max, V
IH
IL
@
Input Current Max
e
I
I
I
V
V
Max
Mode
Others
Mode
Others
Mode
Others
0.2
0.1
20
I
CC
mA
e
Input Voltage
5.5V
I
e
High Level Input
Current
V
V
Max
Max
Max
IH
IL
CC
mA
e
2.4V
I
10
e
b
Low Level Input
Current
V
V
0.36
0.18
CC
mA
e
0.3V
I
b
e
I
I
Short Circuit
V
CC
OS
CC
b
b
15
3
mA
mA
Output Current
(Note 2)
e
Supply Current
V
CC
Max (Note 3)
4.8
8
e
Note 1: All typicals are at V
5V, T 25 C
§
A
CC
Note 2: Not more than one output should be shorted at a time.
Note 3: I is measured with all outputs and serial input open; A, B, C, and D inputs grounded; mode control at 4.5V; and a momentary 3V, then ground, applied to
CC
both clock inputs.
2
e
Switching Characteristics at V
5V and T 25 C (See Section 1 for Test Waveforms and Output Load)
A
§
CC
e
e
4X, C
L
R
50 pF
Max
From (Input)
To (Output)
L
Symbol
Parameter
Units
Min
f
t
Maximum Clock Frequency
6
MHz
ns
MAX
Propagation Delay Time
Low to High Level Output
Clock to
Output
PLH
90
90
t
Propagation Delay Time
High to Low Level Output
Clock to
Output
PHL
ns
Logic Diagram
TL/F/6638–2
Physical Dimensions inches (millimeters)
14-Lead Ceramic Dual-In-Line Package (J)
Order Number DM54L95J
NS Package Number J14A
3
Physical Dimensions inches (millimeters) (Continued)
14-Lead Ceramic Flat Package (W)
Order Number DM54L95W
NS Package Number W14B
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