DLPC4420ZPC [TI]
DLP® display controller for 4K UHD DMD | ZPC | 516 | 0 to 55;型号: | DLPC4420ZPC |
厂家: | TEXAS INSTRUMENTS |
描述: | DLP® display controller for 4K UHD DMD | ZPC | 516 | 0 to 55 PC |
文件: | 总48页 (文件大小:1627K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DLPC4420
ZHCSO15A –DECEMBER 2021 –REVISED FEBRUARY 2023
DLPC4420 DLP® 显示控制器
• 集成时钟生成电路
1 特性
– 通过单个20MHz 晶体提供时钟
– 集成扩频时钟
• 外部存储器支持
• 采用数字微镜器件(DMD),为高达4K 的超高清
(UHD) 分辨率显示提供双DLP 控制器支持:
– 用于微处理器和PWM 序列的并行闪存
• 516 引脚Plastic Ball Grid Array (PBGA) 封装
• 支持LED 和激光混合照明
– 60Hz 时高达4K
– 240Hz 时高达1080p
– 120Hz 时高达1080p (3D)
• 提供一个30 位或两个60 位输入像素接口:
2 应用
– RGB 数据格式
• 激光电视
• 智能投影仪
• 数字标牌
• 企业投影仪
– 每种颜色占8、9 或10 位
– 在双控制器双30 位模式下像素时钟高达
600MHz
• 高速低电压差分信号(LVDS) DMD 接口
• 150-MHz ARM946™ 微处理器
• 微处理器外设
3 说明
DLPC4420 是用于 DLP® 显示芯片组的数字显示控制
器。该芯片组包含 DLPC4420 显示控制器、DLP 数字
微镜器件 (DMD)、DLPA100 控制器电源管理器件和
DLPA300 DMD 微镜驱动器(请参阅 DMD 数据表)。
这款解决方案非常适合需要高分辨率、高亮度和系统简
易性的显示系统。为了确保可靠运行,必须始终将
DLPC4420 显示控制器与 DLP DMD 和相应的 DLP 电
源管理器件配合使用。
– 可编程脉宽调制(PWM) 和捕捉计时器
– 三个I2C 端口、三个UART 端口和三个SSP 端
口
– 一个USB 1.1 次级端口
• 图像处理
– 多种图像处理算法
– 帧速率转换
– 色彩坐标调整
– 可编程色彩空间转换
– 可编程degamma 和启动界面
– 针对3D 显示的集成支持
– 1-D 梯形校正
器件信息
器件型号(1)
DLPC4420
封装尺寸(标称值)
封装
ZPC (516)
27.00mm × 27.00mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
简化版原理图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: DLPS222
DLPC4420
www.ti.com.cn
ZHCSO15A –DECEMBER 2021 –REVISED FEBRUARY 2023
Table of Contents
7 Detailed Description......................................................26
7.1 Overview...................................................................26
7.2 Functional Block Diagram.........................................26
7.3 Feature Description...................................................26
7.4 Device Functional Modes..........................................29
8 Application and Implementation..................................31
8.1 Application Information............................................. 31
8.2 Typical Application.................................................... 31
9 Power Supply Recommendations................................34
9.1 System Power Regulations.......................................34
9.2 System Power-Up Sequence....................................34
9.3 Power-On Sense (POSENSE) Support.................... 34
9.4 System Environment and Defaults............................35
10 Layout...........................................................................36
10.1 Layout Guidelines................................................... 36
11 Device and Documentation Support..........................42
11.1 第三方产品免责声明................................................42
11.2 Device Support........................................................42
11.3 Documentation Support.......................................... 43
11.4 接收文档更新通知................................................... 44
11.5 支持资源..................................................................44
11.6 Trademarks............................................................. 44
11.7 静电放电警告...........................................................44
11.8 术语表..................................................................... 44
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications................................................................ 13
6.1 Absolute Maximum Ratings...................................... 13
6.2 ESD Ratings............................................................. 13
6.3 Recommended Operating Conditions.......................14
6.4 Thermal Information..................................................14
6.5 Electrical Characteristics...........................................14
6.6 System Oscillators Timing Requirements................. 17
6.7 Test and Reset Timing Requirements.......................17
6.8 JTAG Interface: I/O Boundary Scan Application
Timing Requirements.................................................. 18
6.9 Port 1 Input Pixel Timing Requirements....................18
6.10 Port 3 Input Pixel Interface (via GPIO) Timing
Requirements..............................................................19
6.11 DMD LVDS Interface Timing Requirements............21
6.12 Synchronous Serial Port (SSP) Interface
Timing Requirements.................................................. 21
6.13 Programmable Output Clocks Switching
Characteristics.............................................................22
6.14 Synchronous Serial Port Interface (SSP)
Switching Characteristics............................................ 22
6.15 JTAG Interface: I/O Boundary Scan Application
Switching Characteristics............................................ 23
Information.................................................................... 45
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2021) to Revision A (February 2023)
Page
• 更新了特性中的措辞,使之更加清晰................................................................................................................. 1
• 更新了说明........................................................................................................................................................1
• Updated Device Nomenclature and Device Marking sections .........................................................................43
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5 Pin Configuration and Functions
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表5-1. Pin Functions
PIN(1)
TYPE(2)
DESCRIPTION
NAME
NO.
Power-on sense, high true, signal provided from an external voltage monitor circuit. This signal is driven active (high) when
all ASIC supply voltages have reached 90% of their specified minimum voltage. This signal is driven inactive (low) after the
falling edge of PWRGOOD as specified.
POSENSE
P22
I4
Power good, high true, signal from external power supply or voltage monitor. A high value indicates all power is within
operating voltage specs and the system is safe to exit its reset state. A transition from high to low is used to indicate that the
controller or DMD supply voltage drops below their rated minimum level. This transition must occur prior to the supply
voltage drop as specified. During this interval, POSENSE must remain active high. This is a warning of an imminent power
loss condition. This warning is required to enhance long term DMD reliability. A DMD park followed by a full controller reset
is performed by the DLPC4420 controller when PWRGOOD goes low for the specified minimum, protecting the DMD. This
minimum deassertion time is used to protect the input from glitches. Following this the DLPC4420 controller is held in its
reset state as long as PWRGOOD is low. PWRGOOD must be driven high for normal operation. The DLPC4420 controller
acknowledges PWRGOOD as active once it has been driven high for a specified minimum time. Uses hysteresis
PWRGOOD
T26
I4
General purpose, low true, reset output. This output is asserted low immediately upon asserting power-up reset (POSENSE)
low and remains low while POSENSE remains low. EXT_ARSTZ continues to be held low after the release of power-up
reset (that is, POSENSE set high) until released by software. EXT_ARSTZ is also asserted low approximately 5 µs after the
detection of a PWRGOOD or any internally generated reset. In all cases it remains active for a minimum of 2 ms. Note that
the ASIC contains a software register that can be used to independently drive this output.
EXT_ARTZ
MTR_ARTZ
T24
T25
O2
Color wheel motor controller, low true, reset output. This output is asserted low immediately upon asserting power-up reset
(POSENSE) low and remains low while POSENSE remains low. MTR_ARSTZ continues to be held low after the release of
power-up reset (that is, POSENSE is set high) until released by software. MTR_ARSTZ is also optionally asserted low
approximately 5 µs after the detection of a PWRGOOD or any internally generated reset. In all cases, it remains active for a
minimum of 2 ms. Note that the ASIC contains a software register that can be used to independently drive this output. The
ASIC also contains a software register that can be used to disable the assertion of motor reset upon a lamp strike reset.
O2
BOARD LEVEL TEST AND INITIALIZATION (3)
TDI
N25
N24
P25
P26
N23
N22
I4
I4
JTAG serial data in
TCK
JTAG serial data clock
JTAG test mode select
JTAG test mode select
JTAG serial data out
JTAG serial data out
TMS1
TMS2
TDO1
TDO2
I4
I4
O5
O5
JTAG reset. This signal includes an internal pullup and utilizes hysteresis. This pin is pulled high (or left unconnected) when
the JTAG interface is in use for boundary scan or ARM debug. Connect this pin to ground otherwise. Failure to tie this pin
low during normal operation causes startup and initialization problems.
TRSTZ
M23
I4
RTCK
E4
A4
B5
C6
O2
B2
B2
B2
JTAG return clock
ETM_PIPESTAT_2
ETM_PIPESTAT_1
ETM_PIPESTAT_0
ETM trace port pipeline status. Indicates the pipeline status of the ARM core. These signals include internal pulldowns.
ETM trace port synchronization signal, indicating the start of a branch sequence on the trace packet port. This signal
includes an internal pulldown.
ETM_TRACESYNC
ETM_TRACECLK
ICTSEN
A5
D7
B2
B2
I4
ETM trace port clock. This signal includes an internal pulldown.
IC tristate enable (active high). Asserting high tristates all outputs except the JTAG interface. This signal includes an internal
pulldown, however an external pulldown is recommended for added protection. Uses hysteresis.
M24
Test pin 7. This signal provides internal pulldowns.
TSTPT_7
TSTPT_6
TSTPT_5
TSTPT_4
TSTPT_3
E8
B4
C4
E7
D5
B2
B2
B2
B2
B2
Normal use: reserved for test output. Recommended to be left open or unconnected for normal use
Test pin 6. This signal provides internal pulldowns.
Normal use: reserved for test output. Recommended to be left open or unconnected for normal use
Test pin 5. This signal provides internal pulldowns.
Normal use: reserved for test output. Recommended to be left open or unconnected for normal use
Test pin 4. This signal provides internal pulldowns.
Normal use: reserved for test output. Recommended to be left open or unconnected for normal use
Test pin 3. This signal provides internal pulldowns.
Normal use: reserved for test output. Recommended to be left open or unconnected for normal use.
Test pin 2. This signal provides internal pulldowns. Additionally, it is recommended that jumper options be provided for
connecting TSTPT(2:0) to external pullups.
TSTPT_2
TSTPT_1
E6
D3
C2
B2
B2
B2
Test pin 1. This signal provides internal pulldowns. Additionally, it is recommended that jumper options be provided for
connecting TSTPT(2:0) to external pullups.
Test pin 0. This signal provides internal pulldowns. Additionally, it is recommended that jumper options be provided for
connecting TSTPT(2:0) to external pullups.
TSTPT_0
DEVICE TEST
HW_TEST_EN
Device manufacturing test enable. This signal includes an internal pulldown and utilizes hysteresis. It is recommended that
this signal be tied to an external ground in normal operation for added protection.
M25
I4
PORT1 and PORT 2 CHANNEL DATA and CONTROL (4) (5) (6) (7)
Input Port Data Pixel Write Clock (selectable as rising or falling edge triggered, and which port it is associated with (A or B or
(A and B)). This signal includes an internal pulldown.
P_CLK1
AE22
I4
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表5-1. Pin Functions (continued)
PIN(1)
TYPE(2)
DESCRIPTION
NAME
P_CLK2
NO.
Input Port Data Pixel Write Clock (selectable as rising or falling edge triggered, and which port it is associated with (A or B or
(A and B)). This signal includes an internal pulldown.
W25
I4
I4
I4
I4
Input Port Data Pixel Write Clock (selectable as rising or falling edge triggered, and which port it is associated with (A or B or
(A and B)). This signal includes an internal pulldown.
P_CLK3
AF23
AF22
W24
Active High Data Enable. Selectable as to which port it is associated with (A or B or (A and B)).This signal includes an
internal pulldown.
P_DATAEN1
P_DATAEN2
Active High Data Enable. Selectable as to which port it is associated with (A or B or (A and B)).This signal includes an
internal pulldown.
P1_A_9
P1_A_8
P1_A_7
P1_A_6
P1_A_5
P1_A_4
P1_A_3
P1_A_2
P1_A_1
P1_A_0
P1_B_9
P1_B_8
P1_B_7
P1_B_6
P1_B_5
P1_B_4
P1_B_3
P1_B_2
P1_B_1
P1_B_0
P1_C_9
P1_C_8
P1_C_7
P1_C_6
P1_C_5
P1_C_4
P1_C_3
P1_C_2
P1_C_1
P1_C_0
AD15
AE15
AE14
AE13
AD13
AC13
AF14
AF13
AF12
AE12
AF18
AB18
AC15
AC16
AD16
AE16
AF16
AF15
AC14
AD14
AD20
AE20
AE21
AF21
AD19
AE19
AF19
AF20
AC19
AE19
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
Port 1 A Channel Input Pixel Data (bit weight 128)
Port 1 A Channel Input Pixel Data (bit weight 64)
Port 1 A Channel Input Pixel Data (bit weight 32)
Port 1 A Channel Input Pixel Data (bit weight 16)
Port 1 A Channel Input Pixel Data (bit weight 8)
Port 1 A Channel Input Pixel Data (bit weight 4)
Port 1 A Channel Input Pixel Data (bit weight 2)
Port 1 A Channel Input Pixel Data (bit weight 1)
Port 1 A Channel Input Pixel Data (bit weight 0.5)
Port 1 A Channel Input Pixel Data (bit weight 0.25)
Port 1 B Channel Input Pixel Data (bit weight 128)
Port 1 B Channel Input Pixel Data (bit weight 64)
Port 1 B Channel Input Pixel Data (bit weight 32)
Port 1 B Channel Input Pixel Data (bit weight 16)
Port 1 B Channel Input Pixel Data (bit weight 8)
Port 1 B Channel Input Pixel Data (bit weight 4)
Port 1 B Channel Input Pixel Data (bit weight 2)
Port 1 B Channel Input Pixel Data (bit weight 1)
Port 1 B Channel Input Pixel Data (bit weight 0.5)
Port 1 B Channel Input Pixel Data (bit weight 0.25)
Port 1 C Channel Input Pixel Data (bit weight 128)
Port 1 C Channel Input Pixel Data (bit weight 64)
Port 1 C Channel Input Pixel Data (bit weight 32)
Port 1 C Channel Input Pixel Data (bit weight 16)
Port 1 C Channel Input Pixel Data (bit weight 8)
Port 1 C Channel Input Pixel Data (bit weight 4)
Port 1 C Channel Input Pixel Data (bit weight 2)
Port 1 C Channel Input Pixel Data (bit weight 1)
Port 1 C Channel Input Pixel Data (bit weight 0.5)
Port 1 C Channel Input Pixel Data (bit weight 0.25)
Port 1 Vertical Sync. This signal includes an internal pulldown. While intended to be associated with Port 1, it can be
programmed for use with Port 2.
P1_VSYNC
P1_HSYNC
AC20
AD21
B2
B2
Port 1 Horizontal Sync. This signal includes an internal pulldown. While intended to be associated with Port 1, it can be
programmed for use with Port 2.
P2_A_9
P2_A_8
P2_A_7
P2_A_6
P2_A_5
P2_A_4
P2_A_3
P2_A_2
P2_A_1
P2_A_0
P2_B_9
P2_B_8
P2_B_7
P2_B_6
AD26
AD25
AB21
AC22
AD23
AB20
AC21
AD22
AE23
AB19
Y22
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
Port 2 A Channel Input Pixel Data (bit weight 128)
Port 2 A Channel Input Pixel Data (bit weight 64)
Port 2 A Channel Input Pixel Data (bit weight 32)
Port 2 A Channel Input Pixel Data (bit weight 16)
Port 1 A Channel Input Pixel Data (bit weight 8)
Port 2 A Channel Input Pixel Data (bit weight 4)
Port 2 A Channel Input Pixel Data (bit weight 2)
Port 2 A Channel Input Pixel Data (bit weight 1)
Port 2 A Channel Input Pixel Data (bit weight 0.5)
Port 2 A Channel Input Pixel Data (bit weight 0.25)
Port 2 B Channel Input Pixel Data (bit weight 128)
Port 2 B Channel Input Pixel Data (bit weight 64)
Port 2 B Channel Input Pixel Data (bit weight 32)
Port 2 B Channel Input Pixel Data (bit weight 16)
AB26
AA23
AB25
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表5-1. Pin Functions (continued)
PIN(1)
TYPE(2)
DESCRIPTION
NAME
P2_B_5
NO.
AA22
AB24
AC26
AB23
AC25
AC24
W23
V22
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
I4
Port 2 B Channel Input Pixel Data (bit weight 8)
Port 2 B Channel Input Pixel Data (bit weight 4)
Port 2 B Channel Input Pixel Data (bit weight 2)
Port 2 B Channel Input Pixel Data (bit weight 1)
Port 2 B Channel Input Pixel Data (bit weight 0.5)
Port 2 B Channel Input Pixel Data (bit weight 0.25)
Port 2 C Channel Input Pixel Data (bit weight 128)
Port 2 B Channel Input Pixel Data (bit weight 64)
Port 2 C Channel Input Pixel Data (bit weight 32)
Port 2 B Channel Input Pixel Data (bit weight 16)
Port 2 C Channel Input Pixel Data (bit weight 8)
Port 2 B Channel Input Pixel Data (bit weight 4)
Port 2 C Channel Input Pixel Data (bit weight 2)
Port 2 B Channel Input Pixel Data (bit weight 1)
Port 2 C Channel Input Pixel Data (bit weight 0.5)
Port 2 B Channel Input Pixel Data (bit weight 0.25)
P2_B_4
P2_B_3
P2_B_2
P2_B_1
P2_B_0
P2_C_9
P2_C_8
P2_C_7
P2_C_6
P2_C_5
P2_C_4
P2_C_3
P2_C_2
P2_C_1
P2_C_0
Y26
Y25
Y24
Y23
W22
AA26
AA25
AA24
Port 2 Vertical Sync. This signal includes an internal pulldown. While intended to be associated with Port 2, it can be
programmed for use with Port 1.
P2_VSYNC
P2_HSYNC
U22
B2
B2
Port 2 Horizontal Sync. This signal includes an internal pulldown. While intended to be associated with Port 2, it can be
programmed for use with Port1.
W26
ALF INPUT PORT CONTROL
ALF_VSYNC
ALF_HSYNC
ALF_CSYNC
AF11
I4
I4
I4
Autolock dedicated vertical sync. This signal includes an internal pulldown and uses hysteresis.
Autolock dedicated horizontal sync. This signal includes an internal pulldown and uses hysteresis.
Autolock dedicated composite sync (sync on green). This signal includes an internal pulldown and uses hysteresis.
AD11
AE11
DMD RESET and BIAS CONTROL
DADOEZ
AE7
AD6
AE5
AF4
AB8
AD7
AE6
AE4
AC7
AF5
AC8
O5
O5
O5
O5
O5
O5
O5
O5
O5
O5
I4
DAD (DLPA200 / DLPA300) Output Enable (active low)
DAD address
DADADDR_3
DADADDR_2
DADADDR_1
DADADDR_0
DADMODE_1
DADMODE_0
DADSEL_1
DADSEL_0
DADSTRB
DAD_INTZ
DMD LVDS INTERFACE
DCKA_P
DAD modes
DAD select
DAD strobe
DAD interrupt (active low). This signal typically requires an external pullup and uses hysteresis.
V4
V3
V2
V1
P4
P3
P2
P1
R1
T4
T3
T2
T1
U4
U3
U2
U1
W4
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
DMD, LVDS I/F channel A, differential clock
DCKA_N
SCA_P
DMD, LVDS I/F channel A, differential serial control
SCA_N
DDA_P_15
DDA_N_15
DDA_P_14
DDA_N_14
DDA_N_12
DDA_P_11
DDA_N_11
DDA_P_10
DDA_N_10
DDA_P_9
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DDA_N_9
DDA_P_8
DDA_N_8
DDA_P_7
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表5-1. Pin Functions (continued)
PIN(1)
TYPE(2)
DESCRIPTION
NAME
DDA_N_7
NO.
W3
W2
W1
Y2
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
O7
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential serial data
DMD, LVDS I/F channel A, differential clock
DDA_P_6
DDA_N_6
DDA_P_5
DDA_N_5
DDA_P_4
DDA_N_4
DDA_P_3
DDA_N_3
DDA_P_2
DDA_N_2
DDA_P_1
DDA_N_1
DDA_P_0
DDA_N_0
DCKB_P
Y1
Y4
Y3
AA2
AA1
AA4
AA3
AB2
AB1
AC2
AC1
J3
DCKB_N
J4
DMD, LVDS I/F channel A, differential clock
SCB_P
J1
DMD, LVDS I/F channel A, differential serial control
DMD, LVDS I/F channel A, differential serial control
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
DMD, LVDS I/F channel B, differential serial data
SCB_N
J2
DDB_P_15
DDB_N_15
DDB_P_14
DDB_N_14
DDB_P_13
DDB_N_13
DDB_P_12
DDB_N_12
DDB_P_11
DDB_N_11
DDB_P_10
DDB_N_10
DDB_P_9
DDB_N_9
DDB_P_8
DDB_N_8
DDB_P_7
DDB_N_7
DDB_P_6
DDB_N_6
DDB_P_5
DDB_N_5
DDB_P_4
DDB_N_4
DDB_P_3
DDB_N_3
DDB_P_2
DDB_N_2
DDB_P_1
DDB_N_1
DDB_P_0
DDB_N_0
N1
N2
N3
N4
M2
M1
M3
M4
L1
L2
L3
L4
K1
K2
K3
K4
H1
H2
H3
H4
G1
G2
G3
G4
F1
F2
F3
F4
E1
E2
D1
D2
PROGRAM MEMORY (Flash and SRAM) INTERFACE
PM_CSZ_0 D13 O5
Input Bus D Data bit 3.
100-Ωinternal LVDS termination
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表5-1. Pin Functions (continued)
PIN(1)
TYPE(2)
DESCRIPTION
NAME
PM_CSZ_1
NO.
E12
O5
O5
Input Bus D Data bit 5.
100-Ωinternal LVDS termination
PM_CSZ_2
A13
A12
PM_ADDR_22
(GPIO 36)
B5
Input Bus D Data bit 10.
100-Ωinternal LVDS termination
PM_ADDR_21
(GPIO 35)
E11
D12
C12
B5
O5
O5
PM_ADDR_20
PM_ADDR_19
Input Bus D Data bit 11.
100-Ωinternal LVDS termination
PM_ADDR_18
PM_ADDR_17
PM_ADDR_16
PM_ADDR_15
PM_ADDR_14
PM_ADDR_13
PM_ADDR_12
PM_ADDR_11
PM_ADDR_10
PM_ADDR_9
PM_ADDR_8
PM_ADDR_7
PM_ADDR_6
PM_ADDR_5
PM_ADDR_4
PM_ADDR_3
PM_ADDR_2
PM_ADDR_1
PM_ADDR_0
PM_WEZ
B11
A11
D11
C11
E10
D10
C10
B9
O5
O5
O5
O5
O5
O5
O5
O5
O5
O5
O5
O5
O5
O5
O5
O5
O5
O5
O5
O5
O5
O5
O5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
Input Bus D Data bit 12.
100-Ωinternal LVDS termination
Input Bus D Data bit 13.
100-Ωinternal LVDS termination
Input Bus D Data bit 14.
100-Ωinternal LVDS termination
Input Bus D Data bit 15.
100-Ωinternal LVDS termination
A9
E9
Output Bus A Data bit 0 to DMD
Output Bus A Data bit 1 to DMD
Output Bus A Data bit 2 to DMD
Output Bus A Data bit 3 to DMD
Output Bus A Data bit 4 to DMD
Output Bus A Data bit 5 to DMD
Output Bus A Data bit 6 to DMD
Output Bus A Data bit 7 to DMD
Output Bus A Data bit 8 to DMD
Output Bus A Data bit 9 to DMD
Output Bus A Data bit 10 to DMD
Output Bus A Data bit 11 to DMD
Output Bus A Data bit 12 to DMD
Output Bus A Data bit 13 to DMD
Output Bus A Data bit 14 to DMD
D9
C9
B8
A8
D8
C8
B7
A7
C7
B12
C13
B6
PM_OEZ
PM_BLSZ_1
PM_BLSZ_0
PM_DATA_15
PM_DATA_14
PM_DATA_13
PM_DATA_12
PM_DATA_11
PM_DATA_10
PM_DATA_9
PM_DATA_8
PM_DATA_7
PM_DATA_6
PM_DATA_5
PM_DATA_4
PM_DATA_3
PM_DATA_2
PM_DATA_1
PM_DATA_0
A6
C17
B16
A16
A15
B15
D16
C16
E14
D15
C15
B14
A14
E13
D14
C14
B13
PERIPHERAL INTERFACE
I2C Bus 0, Clock. This bus support 400 kHz, fast mode operation. This signal requires an external pullup to 3.3 V. The
minimum acceptable pullup value is 1 kΩ. This input is not 5-V tolerant.
IIC0_SCL
A10
B10
B8
B8
2C Bus 0, Data. This bus support 400 kHz, fast mode operation. This signal requires an external pullup to 3.3 V. The
minimum acceptable pullup value is 1 kΩ. This input is not 5-V tolerant.
IIC0_SDA
SSP0_CLK
SSP0_RXD
AD4
AD5
B5
I4
Synchronous Serial Port 0, clock
Synchronous Serial Port 0, receive data in
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表5-1. Pin Functions (continued)
PIN(1)
TYPE(2)
DESCRIPTION
NAME
SSP0_TXD
NO.
AB7
AC5
AB6
AC3
AB3
AD1
AD2
AE2
C5
O5
B5
B5
B5
O5
O5
O5
I4
Synchronous Serial Port 0, transmit data out
Synchronous Serial Port 0, chip select 0 (active low)
Synchronous Serial Port 0, chip select 1 (active low)
Synchronous Serial Port 0, chip select 2 (active low)
UART0 transmit data output
SSP0_CSZ_0
SSP0_CSZ_1
SSP0_CSZ_2
UART0_TXD
UART0_RXD
UART0_RTSZ
UART0_CTSZ
USB_DAT_N
USB_DAT_P
PMD_INTZ
UART0 receive data input
UART0 ready to send hardware flow control output (active low)
UART0 clear to send hardware flow control input (active low)
USB D- I/O
B9
B9
I4
D6
USB D+ I/O
AE8
AD8
AF7
Interrupt from DLPA100 (active low). This signal requires an external pullup. Uses hysteresis
Color wheel control PWM output
CW_PWM
O5
O5
CW_INDEX
Color wheel index. Uses hysteresis
GENERAL PURPOSE I/O (GPIO) (8)
ALTERNATE FUNCTION 1
N/A
ALTERNATE FUNCTION 2
GPIO_82
GPIO_81
GPIO_80
GPIO_79
GPIO_78
GPIO_77
GPIO_76
GPIO_75
GPIO_74
GPIO_73
GPIO_72
GPIO_71
GPIO_70
GPIO_69
GPIO_68
GPIO_67
GPIO_66
GPIO_65
GPIO_64
GPIO_63
GPIO_62
GPIO_61
GPIO_60
GPIO_59
GPIO_58
GPIO_57
GPIO_56
GPIO_55
GPIO_54
GPIO_53
GPIO_52
GPIO_51
GPIO_50
GPIO_49
GPIO_48
GPIO_47
GPIO_46
GPIO_45
GPIO_44
GPIO_43
E3
AB10
AD9
AE9
AF9
AB11
AC10
AD10
AE10
AF10
K24
K23
K22
J26
B5
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
N/A
Reserved
N/A
IR_ENABLE (O)
Reserved
N/A
N/A
FIELD_3D_LR (I)
SAS_INTGTR_EN (O)
SAS_CSZ (O)
SAS_DO (O)
N/A
SENSE_PWM_OUT (O)
N/A
SENSE_FREQ_IN (I)
SENSE_COMP_IN (I)
N/A
SAS_DI (I)
SAS_CLK (O)
SSP2_DI (I)
N/A
SSP2_CLK (B)
SSP2_CSZ_1 (B)
SSP2_CSZ_0 (B)
SSP2_DO (O)
SP_Data_7 (O)
SP_Data_6 (O)
SP_Data_5 (O)
SP_Data_4 (O)
SP_Data_3 (O)
SP_Data_2 (O)
SP_Data_1 (O)
SP_Data_0 (O)
SP_WG_CLK (O)
LED_SENSE_PULSE (O)
Reserved
N/A
N/A
N/A
J25
N/A
J24
SSP2_CSZ_2 (B)
SSP0_CSZ_5 (B)
N/A
J23
J22
H26
H25
H24
H23
H22
G26
G25
F25
CW_PWM_2 (O)
CW_INDEX_2 (I)
SP_VC_FDBK (I)
N/A
N/A
N/A
N/A
N/A
G24
G23
F26
UART2_RXD (O)
UART2_TXD (O)
PROG_AUX_7 (O)
PROG_AUX_6 (O)
CSP_Data (O)
CSP_CLK (O)
Reserved
N/A
N/A
N/A
E26
AB12
AC11
V23
V24
V25
V26
T22
N/A
ALF_CLAMP (O)
ALF_COAST (O)
HBT_CLKOUT (O)
HBT_DO (O)
HBT_CLKIN_2 (I)
HBT_DI_2 (I)
HBT_CLKIN_1 (I)
HBT_DI_1 (I)
HBT_CLKIN_0 (I)
HBT_DI_0 (I)
Reserved
Reserved
Reserved
Reserved
U23
U24
U25
Reserved
Reserved
Reserved
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表5-1. Pin Functions (continued)
PIN(1)
TYPE(2)
DESCRIPTION
NAME
GPIO_42
NO.
U26
R22
T23
F24
E25
G22
A12
E11
F23
D26
E24
F22
D25
E23
C26
AB4
D24
C25
B26
E21
D22
E20
C23
D21
B24
C22
B23
E19
D20
C21
B22
A23
A22
B21
A21
A20
C20
B20
B19
A19
E18
D19
C19
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
Reserved
Reserved
SSP0_CSZ4 (B)
DASYNC (I)
GPIO_41
GPIO_40
GPIO_39
GPIO_38
GPIO_37
GPIO_36
GPIO_35
GPIO_34
GPIO_33
GPIO_32
GPIO_31
GPIO_30
GPIO_29
GPIO_28
GPIO_27
GPIO_26
GPIO_25
GPIO_24
GPIO_23
GPIO_22
GPIO_21
GPIO_20
GPIO_19
GPIO_18
GPIO_17
GPIO_16
GPIO_15
GPIO_14
GPIO_13
GPIO_12
GPIO_11
GPIO_10
GPIO_9
Reserved
FSD12 (O)
SW reserved (Boot Hold)
SW reserved (USB Enumeration Enable)
N/A
SW reserved (Boot Hold)
SW reserved (USB Enumeration Enable)
N/A
PM_ADDR_22 (O)
PM_ADDR_21 (O)
SSP1_CSZ_1 (B)
SSP1_CSZ_0 (B)
SSP1_DO (O)
I2C_2 SDA (B)
I2C_2 SCL (B)
N/A
N/A
N/A
SSP1_DI (I)
N/A
SSP1_CLK (B)
N/A
IR1 (I)
SSP2 BC CSZ (B)
IR0 (I)
SSP2 BC CSZ (B)
SSP0_CSZ3 (B)
Blue LED enable (O)
Green LED enable (O)
Red LED enable (O)
LED Dual Current Control (O)
LED Dual Current Control (O)
LED Dual Current Control (O)
N/A
N/A
UART2 TXD (O)
LAMPSYNC (O)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
General Purpose Clock 2 (O)
General Purpose Clock 1 (O)
I2C_1 SDA (B)
N/A
N/A
N/A
I2C_1 SCL (B)
N/A
PWM IN_1 (I)
I2C_2 SDA (B)
I2C_2 SCL (B)
N/A
PWM IN_0 (I)
PWM STD_7 (O)
PWM STD_6 (O)
PWM STD_5 (O)
PWM STD_4 (O)
PWM STD_3 (O)
PWM STD_2 (O)
PWM STD_1 (O)
PWM STD_0 (O)
UART1_RTSZ (O)
UART1_CTSZ (I)
UART1_RXD (I)
UART1_TXD (O)
N/A
N/A
GPIO_8
N/A
GPIO_7
N/A
GPIO_6
N/A
GPIO_5
N/A
GPIO_4
N/A
GPIO_3
N/A
GPIO_2
N/A
GPIO_1
N/A
GPIO_0
N/A
CLOCK and PLL SUPPORT
System clock oscillator input (3.3-V LVTTL). Note that MOSC must be stable a maximum of 25 ms after POSENSE
transitions from low to high.
MOSC
M26
N26
I10
MOSCN
O10
MOSC crystal return
General purpose output clock A. Targeted for driving the CW motor controller. The frequency is software programmable.
Power-up default 787 KHz. Note that the output frequency is not affected by non-power-up reset operations (it will hold the
last value programmed).
OCLKA
AF6
O5
DUAL CONTROLLER SUPPORT
Sequence sync. This signal is used in multi-controller configurations only, in which case the SEQSYNC signal from each
controller is connected together with an external pullup. This signal is either pulled high or pulled low and not allowed to float
for single controller configurations.
SEQ_SYNC
AB9
B3
POWER and GROUND
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表5-1. Pin Functions (continued)
PIN(1)
TYPE(2)
DESCRIPTION
NAME
NO.
F20, F17, F11,
F8, L21, R21,
Y21, AA19, AA16,
AA10, AA7
VDD33
POWER
3.3-V I/O power
C1, F5, G6, K6,
M5, P5, T5, W6,
AA5, AE1, H5,
N6, T6, AA13,
U21, P21, H21,
F14
VDD18
VDD11
POWER
POWER
1.8-V internal DRAM and LVDS I/O power
F19, F16, F13,
F10, F7, H6, L6,
P6, U6, Y6, AA8,
AA11, AA14,
1.1-V core power
AA17, AA20,
W21, T21, N21,
K21, G21, L11,
T11, T16, L16
VDD_PLLD
VSS_PLLD
VAD_PLLD
VAS_PLLD
VDD_PLLM1
VSS_PLLM1
VAD_PLLM1
VAS_PLLM1
VDD_PLLM2
VSS_PLLM2
VAD_PLLM2
VAS_PLLM2
VAD_PLLS
VAS_PLLS
L22
L23
K25
K26
L26
M22
L24
L25
P23
P24
R25
R26
R23
R24
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
1.1-V DMD clock generator PLL digital power
1.1-V DMD clock generator PLL digital ground
1.8-V DMD clock generator PLL analog power
1.8-V DMD clock generator PLL analog ground
1.1-V master-LS clock generator PLL digital power
1.1-V master-LS clock generator PLL digital ground
1.8-V master-LS clock generator PLL analog power
1.8-V master-LS clock generator PLL analog ground
1.1-V master-HS clock generator PLL digital power
1.1-V master-HS clock generator PLL digital ground
1.8-V master-HS clock generator PLL analog power
1.8-V master-HS clock generator PLL analog ground
1.1-V video-2X clock generator PLL analog power
1.1-V video-2X clock generator PLL analog ground
B18, D18, B17,
E17, A18, C18,
A17, D17, AE17,
AC17, AF17,
AC18, AB16,
AD17, AB17,
AD18
L-VDQPAD_[7:0],
R-VDQPAD_[7:0]
RESERVED
These pins have to be tied directly to ground for normal operation.
CFO_VDD33
AE26
RESERVED
RESERVED
This pin has to be tied directly to 3.3 I/O power (VDD33) for normal operation.
These pins have to be tied directly to ground for normal operation.
VTEST1, VTEST2, AB14, AB15, E15,
VTEST3, VTEST4
E16
V5, K5
AC6
LVDS_AVS1,
LVDS_AVS2
POWER
POWER
These pins have to be tied directly to ground for normal operation.
This pin has to be tied directly to ground for normal operation.
VPGM
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表5-1. Pin Functions (continued)
PIN(1)
TYPE(2)
DESCRIPTION
NAME
NO.
A26, A25, A24,
B25, C24, D23,
E22, F21, F18,
F15, F12, F9, F6,
E5, D4, C3, B3,
A3, B2, A2, B1,
A1 G5, J5, J6, L5,
M6, N5, R5, R6,
U5, V6, W5, Y5,
AA6, AB5, AC4,
AD3, AE3, AF3,
AF2, AF1, AA9,
AA12, AA15,
AA18, AA21,
AB22, AC23,
AD24, AE24,
GROUND
GROUND
Common ground
AF24, AE25,
AF25, AF26, V21,
M21, J21, L15,
L14, L13, L12,
M16, M15, M14,
M13, M12, M11,
N16, N15, N14,
N13, N12, N11,
P16, P15, P14,
P13, P12, P11,
R16, R15, R14,
R13, R12, R11,
T15, T14, T13,
T12
(1) For instructions on handling unused pins, see General Handling Guidelines for Unused CMOS-Type Pins.
(2) I/O Type: I = Input, O = Output, B = Bidirectional, and H = Hysteresis. See 表5-2 for subscript explanation.
(3) All JTAG signals are LVTTL compatible.
(4) Ports 1 and 2 can each be used to support multiple source options for a given product (for example AFE and HDMI). To do so, the data
bus from both source components must be connected to the same port pins (1 or 2) and control given to the DLPC4420 device to
tristate the "inactive" source. Tying them together like this causes some signal degradation due to reflections on the tristated path.
Given the clock is the most critical signal, three Port clocks (1, 2, and 3) are provided to provide an option to improve the signal
integrity.
(5) Ports 1 and 2 can be used separately as two 30-bit ports, or can be combined into one 60-bit port (typically for high data rate sources)
for transmission of two pixels per clock.
(6) The A, B, C input data channels of Ports 1 and 2 can be internally reconfigured/ remapped for optimum board layout.
(7) Sources feeding less than the full 10-bits per color component channel have to be MSB justified when connected to the DLPC4420
controller and the LSBs tied off to zero. For example an 8-bit per color input has to be connected to bits 9:2 of the corresponding A, B,
C input channel.
(8) GPIO signals must be configured by software for input, output, bidirectional, or open-drain. Some GPIOs have one or more alternate
use modes, which are also software configurable. The reset default for all optional GPIOs is as an input signal. However, any alternate
function connected to these GPIO pins with the exception of general-purpose clocks and PWM generation, are reset. An external
pullup to the 3.3-V supply is required for each signal configured as open-drain. External pullup or pulldown resistors may be required to
ensure stable operation before software is able to configure these ports.
表5-2. I/O Type Subscript Definition
SUBSCRIPT
DESCRIPTION
3.3-V LVTTL I/O buffer with 8-mA drive
3.3-V LVTTL I/O buffer with 12-mA drive
3.3-V LVTTL receiver
ESD STRUCTURE
2
3
4
5
3.3-V LVTTL I/O buffer with 8-mA drive, with slew rate control
3.3-V LVTTL I/O buffer, with programmable 4-mA, 8-mA, or 12-
mA drive
6
ESD diode to VDD33 and GROUND
7
8
1.8-V LVDS (DMD I/F)
3.3-V I2C with 3 mA sink
9
USB Compatible (3.3 V)
10
OSC 3.3-V I/O Compatible LVTTL
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
ELECTRICAL
VDD11 (Core)
1.60
2.50
3.90
–0.30
–0.30
–0.30
VDD18 (LVDS I/O and Internal DRAM)
VDD33 (I/O)
VDD_PLLD (1.1-V DMD clock
generator - Digital)
1.60
1.60
1.60
2.50
2.50
2.50
1.40
–0.30
–0.30
–0.30
–0.30
–0.30
–0.30
–0.50
VDD_PLLM1 (1.1-V Master - LS
clock generator - Digital)
VDD_PLLM2 (1.1-V Master - HS
clock generator - Digital)
Supply Voltage(1)
V
VDD_PLLD (1.8-V DMD clock
generator - Analog)
VDD_PLLM1 (1.8-V Master - LS
clock generator - Analog)
VDD_PLLM2 (1.8-V Master - HS
clock generator - Analog)
VDD_PLLS (1.1-V Video 2X -
Analog)
USB
5.25
VDD33 + 0.3
3.6
–1.0
–0.3
–0.3
–0.5
–1.0
–0.3
–0.3
–0.5
OSC
VI Input Voltage(2)
V
V
3.3-V LVTTL
3.3-V I2C
USB
3.8
5.25
OSC
VO Output Voltage
2.2
3.3-V LVTTL
3.6
3.3-V I2C
ENVIRONMENTAL
3.8
TJ operating junction temperature
Tstg storage temperature range
0
111
125
°C
°C
–40
(1) All voltage values are with respect to GROUND.
(2) Applies to external input and bidirectional buffers
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
± 1000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
+500/–300
(1) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
(2) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
I/O(1)
MIN
NOM
ELECTRICAL
VDD33
3.3-V supply voltage, I/O
3.135
1.71
1.045
1.71
1.71
1.71
1.050
1.045
1.045
1.045
0
3.3
1.8
1.1
1.8
1.8
1.8
1.10
1.1
1.1
1.1
3.465
1.89
V
V
V
V
V
V
V
V
V
V
VDD18
1.8-V supply voltage, LVDS and DRAM
1.1-V supply voltage, core logic
1.8-V supply voltage, PLL analog
1.8-V supply voltage, PLL analog
1.8-V supply voltage, PLL analog
1.8-V supply voltage, PLL Analog
1.8-V supply voltage, PLL analog
1.8-V supply voltage, PLL analog
1.8-V supply voltage, PLL analog
VDD11
1.155
1.89
VDD_PLLD
VDD_PLLM1
VDD_PLLM2
VDD_PLLS
VDD_PLLD
VDD_PLLM1
VDD_PLLM2
1.89
1.89
1.150
1.155
1.155
1.155
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
55
USB (9)
OSC (10)
0
VI
Input voltage
V
V
3.3-V LVTTL (1,2,3,4)
3.3-V I2C (8)
USB (8)
0
0
0
3.3-V LVTTL (1,2,3,4)
3.3-V I2C (8)
1.8-V LVDS (7)
See(2) (3)
0
vo
Output voltage
0
0
TA
TC
TJ
Operating ambient temperature range
Operating top center case temperature
Operating junction temperature
0
°C
°C
°C
See(3) (4)
0
109.16
111
0
(1) The number inside each parenthesis for the I/O refers to the type defined in the I/O type subscript definition section.
(2) Assumes minimum 1 m/s airflow along with the JEDEC thermal resistance and associated conditions listed at www.ti.com/packaging.
Thus, this is an approximate value that varies with environment and PCB design.
(3) Maximum thermal values assume max power of 4.6 watts.
(4) Assume PsiJT equals 0.4 C/W
6.4 Thermal Information
DLPC4420
THERMAL METRIC(1)
ZPC (BGA)
516 PINS
14.4
UNIT
RθJA
RθJC
Junction-to-ambient thermal resistance(2)
Junction-to-case thermal resistance
°C/W
°C/W
4.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application
Report.
(2) In still air
6.5 Electrical Characteristics
over recommended operating conditions
TEST
CONDITIONS
PARAMETER
MIN TYP
MAX UNIT
USB (9)
2.0
2.0
2.0
2.4
OSC (10)
High-level input
voltage
VIH
V
3.3-V LVTTL (1,2,3,4)
3.3-V I2C (8)
VDD33VDD33+0.5
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6.5 Electrical Characteristics (continued)
over recommended operating conditions
TEST
CONDITIONS
PARAMETER
MIN TYP
MAX UNIT
USB (9)
0.8
OSC (10)
0.8
V
Low-level input
voltage
VIL
3.3-V LVTTL (1,2,3,4)
3.3-V I2C (8)
0.8
1.0
mV
–0.5
Differential Input
Voltage
VDIS
VICM
USB(9)
USB(9)
200
Differential cross
point voltage
0.8
2.5
V
USB(9)
200
400
Hysteresis (VT+
V T-
–
VHYS
3.3-V LVTTL (1,2,3,4)
3.3-V I2C (8)
USB (9)
mV
)
300 550
2.8
600
High-level output
voltage
1.8-V LVDS (7)
1.520
VOH
V
IOH = Max
Rated
3.3-V LVTTL (1,2,3)
2.7
0.0
USB (9)
0.3
1.8-V LVDS (7)
0.880
Low-level output
voltage
VOL
V
V
IOL = Max
Rated
3.3-V LVTTL (1,2,3)
3.3-V I2C (8)
1.8-V LVDS (7)
USB(9)
0.4
0.4
IOL = 3-mA sink
Output differential
voltage
VOD
0.065
0.440
200
10
–
10.0
OSC (10)
High-level input
current
3.3-V LVTTL (1-4) without internal
pulldown
–
10.0
IIH
VIH = VDD33
10 µA
200.0
3.3-V LVTTL (1-4) with internal
pulldown
VIH = VDD33
VIH = VDD33
10.0
3.3-V I2C (8)
10.0
10.0
–
10.0
USB(9)
–
10.0
OSC (10)
10.0
10.0
Low-level input
current
IIL
3.3-V LVTTL (1–4) without internal
pulldown
µA
–
10.0
VOH = VDD33
3.3-V LVTTL (1-4) with internal
pulldown
–
10.0
VOH = VDD33
VOH = VDD33
–200
3.3-V I2C (8)
–10.0
–
19.1
USB(9)
1.8-V LVDS (7) (VOD = 300 mV)
3.3-V LVTTL (1)
VO = 1.4 V
VO = 2.4 V
VO = 2.4 V
6.5
–4.0
–8.0
High-level output
current
IOH
mA
3.3-V LVTTL (2)
–
12.0
3.3-V LVTTL (3)
VO = 2.4 V
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ZHCSO15A –DECEMBER 2021 –REVISED FEBRUARY 2023
6.5 Electrical Characteristics (continued)
over recommended operating conditions
TEST
CONDITIONS
PARAMETER
MIN TYP
USB (9)
19.1
6.5
1.8-V LVDS (7) (VOD = 300 mV)
VO = 1.0 V
VO = 0.4 V
VO = 0.4 V
VO = 0.4 V
3.3-V LVTTL (1)
3.3-V LVTTL (2)
3.3-V LVTTL (3)
3.3-V I2C (8)
USB (9)
4.0
Low-level output
current
IOL
8.0
12.0
3.0
–10
–10
–10
–10
11.84
3.75
3.75
3.75
5.26
LVDS (7)
High-impedance
leakage current
IOZ
pF
3.3-V LVTTL (1,2,3)
3.3-V I2C (8)
USB (9)
17.07
3.3-V LVTTL (1)
3.3-V LVTTL (2)
3.3-V LVTTL (4)
3.3-V I2C (8)
5.52
CI
Input capacitance
5.52 pF
5.52
6.54
ICC11
ICC18
Supply voltage, 1.1-V core power
Normal Mode
Normal Mode
1474 mA
Supply voltage, 1.8-V power (LVDS I/O and internal
DRAM)
1005 mA
ICC33
Supply voltage, 3.3-V I/O power
Normal Mode
Normal Mode
33 mA
6.2 mA
ICC11_PLLD
Supply voltage, DMD PLL Digital Power ( 1.1V)
4.4
4.4
Supply voltage, Master-LS Clock Generator PLL Digital
power ( 1.1V)
ICC11_PLLM1
Normal Mode
6.2 mA
Supply voltage, Master-HS Clock Generator PLL Digital
power ( 1.1V)
ICC11_PLLM2
ICC18_PLLD
ICC18_PLLM1
Normal Mode
Normal Mode
Normal Mode
4.4
8.0
8.0
6.2 mA
10.2 mA
10.2 mA
Supply voltage, DMD PLL Analog Power (1.8 V)
Supply voltage, Master-LS Clock Generator PLL Analog
power (1.8 V)
Supply voltage, Master-HS Clock Generator PLL Analog
power (1.8 V)
ICC18_PLLM2
ICC11_PLLS
Normal Mode
8.0
10.2 mA
2.9 mA
Supply voltage, Video-2X PLL Analog Power ( 1.1 V)
Total Power
Normal Mode
Normal Mode
3.73
21 mA
mA
W
Low Power
Mode
ICC11
Supply voltage, 1.1V core power
Supply voltage, 1.8-V power (LVDS I/O and internal
DRAM)
Low Power
Mode
ICC18
0
Low Power
Mode
ICC33
Supply voltage, 3.3-V I/O power
18 mA
2.03 mA
2.03 mA
2.03 mA
5.42 mA
5.42 mA
Low Power
Mode
ICC11_PLLD
ICC11_PLLM1
ICC11_PLLM2
ICC18_PLLD
ICC18_PLLM1
Supply voltage, DMD PLL Digital Power ( 1.1V)
Supply voltage, Master-LS Clock Generator PLL Digital
power ( 1.1V)
Low Power
Mode
Supply voltage, Master-HS Clock Generator PLL Digital
power ( 1.1V)
Low Power
Mode
Low Power
Mode
Supply voltage, DMD PLL Analog Power (1.8 V)
Supply voltage, Master-LS Clock Generator PLL Analog
power (1.8 V)
Low Power
Mode
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6.5 Electrical Characteristics (continued)
over recommended operating conditions
TEST
CONDITIONS
PARAMETER
MIN TYP
MAX UNIT
5.42 mA
.03 mA
Supply voltage, Master-HS Clock Generator PLL Analog
Low Power
Mode
ICC18_PLLM2
power (1.8 V)
Low Power
Mode
ICC11_PLLS
Supply voltage, Video-2X PLL Analog Power ( 1.1V)
Total Power
Low Power
Mode
106 mW
6.6 System Oscillators Timing Requirements
over operating free-air temperature range(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
SYSTEM OSCILLATORS
fclock
tc
Clock frequency, MOSC(1)
19.998
49.995
20
20.002
50.005
MHz
MHz
ns
Cycle time, MOSC(1)
tw(H)
Pulse duration(2), MOSC, high
50% to 50% reference points
(signal)
tw(L)
tt
Pulse duration(2), MOSC, low
50% to 50% reference points
(signal)
20
ns
ns
ps
Transition time(2), MOSC, tt = tf /tr
20% to 80% reference points
(signal)
12
18
tjp
Period Jitter(2), MOSC (This is the deviation
in period from the ideal period due solely to
high frequency jitter).
(1) The frequency range for MOSC is 20 MHz with +/-100 PPM accuracy (it includes impact to accuracy due to aging, temperature and
trim sensitivity). The MOSC input cannot support spread spectrum clock spreading.
(2) Applies only when driven via an external digital oscillator.
6.7 Test and Reset Timing Requirements
MIN
MAX
UNIT
tW1(L)
tW1(L)
tt1
Pulse duration, inactive low, PWRGOOD
Pulse duration, inactive low, PWRGOOD
Transition time, PWRGOOD, tt1= tf/tr
Pulse duration, inactive low, POSENSE
Pulse duration, inactive low, POSENSE
Transition time, POSENSE, tt1= tf/tr
50% to 50% reference points
(signal)
4.0
µs
50% to 50% reference points
(signal)
1000(2)
625
ms
µs
µs
ms
µs
µs
µs
ms
20% to 80% reference points
(signal)
tW2(L)
tW2(L)
tt2
50% to 50% reference points
(signal)
500
50% to 50% reference points
(signal)
1000(2)
25(1)
20% to 80% reference points
(signal)
tPH
Power Hold time, POSENSE remains active after
PWRGOOD is de-asserted
20% to 80% reference points
(signal)
500
500
tEW
Early Warning time, PWRGOOD goes inactive low prior to
any power supply voltage going below its specification
tW1(L)
The sum of PWRGOOD and POSENSE inactive time
1050(2)
+tW2(L)
(1) As long as noise on this signal is below the hysteresis threshold.
(2) With 1.8 V power applied. If the 1.8 V power is disabled by the controller command (For example –if system is placed in Low Power
mode where the controller disables 1.8 V power), these signals can be placed and remain in their inactive state indefinitely.
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6.8 JTAG Interface: I/O Boundary Scan Application Timing Requirements
MIN
MAX
10
UNIT
MHZ
ns
fclock
tC
Clock frequency, TCK
Cycle time, TCK
100
40
tW(H)
Pulse duration, high
50% to 50% reference points
(signal)
ns
tW(L)
tt
Pulse duration, low
50% to 50% reference points
(signal)
40
ns
ns
Transition time, tt= tf/tr
20% to 80% reference points
(signal)
5
tSU
th
tSU
th
8
2
8
2
ns
ns
ns
ns
Setup time, TDI valid before TCK↑
Hold time, TDI valid after TCK↑
Setup time, TMS1 valid before TCK↑
Hold time, TMS1 valid before TCK↑
6.9 Port 1 Input Pixel Timing Requirements
TEST CONDITIONS
MIN
12
MAX
175
UNIT
MHz
MHz
ns
fclock
fclock
tC
Clock frequency, P_CLK1, P_CLK2, P_CLK3 (30-bit bus)
Clock frequency, P_CLK1, P_CLK2, P_CLK3 (60-bit bus)
Cycle Time, P_CLK1, P_CLK2, P_CLK3
Pulse Duration, high
12
160
5.714
2.3
83.33
tW(H)
50% to 50% reference points
(signal)
ns
tW(L)
Pulse Duration, low
50% to 50% reference points
(signal)
2.3
ns
tjp
tt
Clock period jitter, P_CLK1, P_CLK2, P_CLK3
Transition time, tt=tf/tr, P_CLK1, P_CLK2, P_CLK3
See (2)
2.0
ps
ns
Max ƒclock
20% to 80% reference points
(signal)
0.6
0.6
0.6
tt
tt
Transition time, tt=tf/tr, P1_A(9-0), P1_B(9-0), P1_C(9-0),
P1_HSYNC, P1_VSYNC, P1_DATAEN
20% to 80% reference points
(signal)
3.0
3.0
ns
ns
Transition time, tt=tf/tr, ALF_HSYNC, ALF_VSYNC,
ALF_CSYNC(1)
20% to 80% reference points
(signal)
SETUP AND HOLD TIMES
tsu
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
Setup time, P1_A(9-0), valid before P_CLK1↑↓, P_CLK2
↑↓, or P_CLK3↑↓
th
Hold time, P1_A(9-0), valid before P_CLK1↑↓, P_CLK2
↑↓, or P_CLK3↑↓
tsu
Setup time, P1_B(9-0), valid before P_CLK1↑↓, P_CLK2
↑↓, or P_CLK3↑↓
th
Hold time, P1_B(9-0), valid before P_CLK1↑↓, P_CLK2
↑↓, or P_CLK3↑↓
tsu
Setup time, P1_C(9-0), valid before P_CLK1↑↓, P_CLK2
↑↓, or P_CLK3↑↓
th
Hold time, P1_C(9-0), valid before P_CLK1↑↓, P_CLK2
↑↓, or P_CLK3↑↓
tsu
Setup time, P1_VSYNC, valid before P_CLK1↑↓,
P_CLK2↑↓, or P_CLK3↑↓
th
Hold time, P1_VSYNC valid before P_CLK1↑↓, P_CLK2
↑↓, or P_CLK3↑↓
tsu
Setup time, P1_HSYNC, valid before P_CLK1↑↓,
P_CLK2↑↓, or P_CLK3↑↓
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6.9 Port 1 Input Pixel Timing Requirements (continued)
TEST CONDITIONS
MIN
MAX
UNIT
th
0.8
ns
Hold time, P1_HSYNC valid before P_CLK1↑↓, P_CLK2
↑↓, or P_CLK3↑↓
tsu
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
ns
Setup time, P2_A(9-0), valid before P_CLK1↑↓, P_CLK2
↑↓, or P_CLK3↑↓
th
ns
Hold time, P2_A(9-0), valid before P_CLK1↑↓, P_CLK2
↑↓, or P_CLK3↑↓
tsu
ns
Setup time, P2_B(9-0), valid before P_CLK1↑↓, P_CLK2
↑↓, or P_CLK3↑↓
th
ns
Hold time, P2_B(9-0), valid before P_CLK1↑↓, P_CLK2
↑↓, or P_CLK3↑↓
tsu
ns
Setup time, P2_C(9-0), valid before P_CLK1↑↓, P_CLK2
↑↓, or P_CLK3↑↓
th
ns
Hold time, P2_C(9-0), valid before P_CLK1↑↓, P_CLK2
↑↓, or P_CLK3↑↓
tsu
ns
Setup time, P2_VSYNC, valid before P_CLK1↑↓,
P_CLK2↑↓, or P_CLK3↑↓
th
ns
Hold time, P2_VSYNC valid before P_CLK1↑↓, P_CLK2
↑↓, or P_CLK3↑↓
tsu
ns
Setup time, P2_HSYNC, valid before P_CLK1↑↓,
P_CLK2↑↓, or P_CLK3↑↓
th
ns
Hold time, P2_HSYNC valid before P_CLK1↑↓, P_CLK2
↑↓, or P_CLK3↑↓
tsu
ns
Setup time, P_DATAEN1, valid before P_CLK1↑↓,
P_CLK2↑↓, or P_CLK3↑↓
th
ns
ns
Hold time, P_DATAEN1 valid before P_CLK1↑↓,
P_CLK2↑↓, or P_CLK3↑↓
tsu
Setup time, P_DATAEN2, valid before P_CLK1↑↓,
P_CLK2↑↓, or P_CLK3↑↓
th
ns
Hold time, P_DATAEN2 valid before P_CLK1↑↓,
P_CLK2↑↓, or P_CLK3↑↓
tw(A)
tw(A)
VSYNC Active Pulse Width
HSYNC Active Pulse Width
1
Video Line
16
Pixel
Clocks
(1) ALF_CSYNC, ALF_VSYNC and ALF_HSYNC are Asynchronous signals.
(2) For frequencies (fclock) less than 175 MHZ, use following formula to obtain the jitter: Max Clock Jitter = +/- [ (1/ƒclock) –5414 ps]
6.10 Port 3 Input Pixel Interface (via GPIO) Timing Requirements
PARAMETER
Clock Frequency, P3_CLK
TEST CONDITIONS
MIN
27
MAX
54
UNIT
MHz
ns
fclock
tc
Cycle time, P3_CLK
Pulse Duration, high
18.5
7.4
37.1
tW(H)
50% to 50% reference points
(signal)
ns
tW(L)
Pulse Duration, low
50% to 50% reference points
(signal)
7.4
ns
tjp
tt
Clock period jitter, P3_CLK
See (1)
1.0
See (1)
5.0
ps
ns
Max ƒclock
Transition time, tt= tf/tr, P3_CLK
20% to 80% reference points
(signal)
tt
Transition time, tt= tf/tr, P3_DATA(9-0)
20% to 80% reference points
(signal)
1.0
2.0
5.0
ns
ns
tsu
Setup time, P3_DATA(9-0) valid before P3_CLK↑↓
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PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
th
2.0
ns
Hold time, P3_DATA(9-0) valid after P3_CLK↑↓
(1) For frequencies less than 54 MHZ, use following formula to obtain the jitter: Jitter = [ (1/F) –5414 ps].
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6.11 DMD LVDS Interface Timing Requirements
FROM (INPUT)
TO (OUTPUT)
DCK_A
MIN
100
MAX UNIT
fclock
tC
Clock frequency, DCK_A
Cycle time, DCK_A(1)
N/A
N/A
N/A
N/A
N/A
400 MHz
DCK_A
2475.3
1093
1093
100
ps
ps
ps
tW(H)
tW(L)
tt
Pulse duration, high
DCK_A
Pulse duration, low
DCK_A
Transition time, tt= tf/tr
DCK_A
400
ps
ps
ps
tosu
toh
fclock
tC
Output Setup time at max clock rate(2)
Output hold time at max clock rate(2)
Clock frequency, DCK_B
Cycle time, DCK_B(1)
SCA, DDA(15:0)
SCA, DDA(15:0)
DCK_B
438
DCK_A↑↓
DCK_A↑↓
N/A
438
100
400 MHz
N/A
DCK_B
2475.3
1093
1093
100
ps
ps
ps
tW(H)
tW(L)
tt
Pulse duration, high
N/A
DCK_B
Pulse duration, low
N/A
DCK_B
Transition time, tt= tf/tr
N/A
DCK_B
400
250
ps
ps
ps
ps
tosu
toh
Output Setup time at max clock rate(2)
Output hold time at max clock rate(2)
Output Skew, Channel A to Channel B
SCA, DDB(15:0)
SCA, DDB(15:0)
438
DCK_B↑↓
DCK_B↑↓
DCK_A↑
438
tsk
DCK_B↑
(1) The minimum cycle time (tc) for DCK_A and DCL_B includes 1.0% spread spectrum modulation. User must verify that DMD can
support this rate.
(2) Output Setup and Hold times for DMD clock frequencies below the maximum can be calculated as follows: tosu(fclock) = tosu(fmax) +
250000 × (1/fclock –1/400) and toh(fclock) = toh(fmax) + 250000 × (1/fclock –1/400) where fclock is in MHz.
6.12 Synchronous Serial Port (SSP) Interface Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
SSP Primary
tsu
tsu
th
Setup time, SSPx_DI valid before SSPx_CLK
Setup time, SSPx_DI valid before SSPx_CLK
Hold time, SSPx_DI valid after SSPx_CLK
Hold time, SSPx_DI valid after SSPx_CLK
Transition time, SSPx_DI, tt= tf/tr
15
15
0
ns
ns
ns
ns
ns
th
0
tt
20% to 80% reference points
(signal)
1.5
SSP Secondary
tsu
tsu
th
Setup time, SSPx_DI valid before SSPx_CLK
12
12
12
12
ns
ns
ns
ns
ns
Setup time, SSPx_DI valid before SSPx_CLK
Hold time, SSPx_DI valid after SSPx_CLK
Hold time, SSPx_DI valid after SSPx_CLK
Transition time, SSPx_DI, tt= tf/tr
th
tt
20% to 80% reference points
(signal)
1.5
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6.13 Programmable Output Clocks Switching Characteristics
over operating free air temperature range, CL(min timing) = 5 pF, CL(max timing) = 50 pF (unless otherwise noted)
PARAMETER
Clock frequency, OCLKA(1)
Cycle Time, OCLKA
TEST CONDITIONS
TO (OUTPUT)
OCLKA
OCLKA
MIN
MAX UNIT
fclock
tC
0.787
50 MHz
20 1270.6
ns
ns
tW(H)
Pulse Duration, high(2)
50% to 50% reference points OCLKA
(signal)
(tC/2_-2)
tW(L)
Pulse Duration, low(2)
50% to 50% reference points OCLKA
(signal)
(tC/2_-2)
ns
ps
Jitter
OCLKA
OCLKB
OCLKB
350
fclock
tC
Clock frequency, OCLKB(1)
Cycle Time, OCLKB
Pulse Duration, high(2)
0.787
50 MHz
20 1270.6
ns
ns
tW(H)
50% to 50% reference points OCLKB
(signal)
(tC/2_-2)
tW(L)
Pulse Duration, low(2)
50% to 50% reference points OCLKB
(signal)
(tC/2_-2)
ns
ps
Jitter
OCLKB
OCLKC
OCLKC
350
fclock
tC
Clock frequency, OCLKC(1)
Cycle Time, OCLKC(2)
Pulse Duration, high
0.787
50 MHz
20 1270.6
ns
ns
tW(H)
50% to 50% reference points OCLKC
(signal)
(tC/2_-2)
tW(L)
Pulse Duration, low(2)
Jitter
50% to 50% reference points OCLKC
(signal)
(tC/2_-2)
ns
ps
OCLKC
350
(1) The frequency of OCLKA thru OCLKC is programmable.
(2) The Duty Cycle of OCLKA thru OCLKC is within +/- 2 ns of 50%.
6.14 Synchronous Serial Port Interface (SSP) Switching Characteristics
over operating free-air temperature range, CL(min timing) = 5 pF, CL(max timing) = 50 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
FROM (INPUT)
TO (OUTPUT)
MIN
MAX UNIT
fclock
Clock Frequency,
SSPx_CLK
N/A
N/A
SSPx_CLK
73 25000
kHz
tc
Cycle time, SSPx_CLK
Pulse Duration, high
SSPx_CLK
SSPx_CLK
0.040
40%
13.6
µs
tW(H)
50% to 50% reference N/A
points (signal)
tW(L)
Pulse Duration, low
50% to 50% reference N/A
points (signal)
SSPx_CLK
40%
SSP Primary (1)
tpd
Output Propagation, Clock
SSPx_DO
SSPx_DO
-5
-5
5
5
ns
ns
SSPx_CLK↓
to Q, SSPx_DO(2)
tpd
Output Propagation, Clock
to Q, SSPx_DO(2)
SSPx_CLK↑
SSP Secondary (1)
tpd
Output Propagation, Clock
SSPx_DO
SSPx_DO
0
0
34
34
ns
ns
SSPx_CLK↓
SSPx_CLK↑
to Q, SSPx_DO(2)
tpd
Output Propagation, Clock
to Q, SSPx_DO(2)
(1) The SSP can be used as an SSP Primary, or as an SSP Secondary. When used as a Primary, the SSP can be configured to sample DI
with the same internal clock edge used to transmit the next DO, which provides a full cycle rather than a half cycle timing path, allowing
operation at higher SPI clock frequencies.
(2) The SSP can be configured into four different operational modes/configurations.
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表6-1. SSP Clock Operational Modes
SPI Clocking Mode
SPI Clock Polarity (CPOL)
SPI Clock Phase (CPHA)
0
1
2
3
0
0
1
1
0
1
0
1
6.15 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
over operating free-air temperature range, CL(min timing) = 5 pF, CL(max timing) = 85 pF (unless otherwise noted)
PARAMETER
FROM INPUT
TO OUTPUT
MIN
MAX
UNIT
tpd
Output Propagation, Clock to Q
TDO1
3
12
ns
TCK↓
图6-1. System Oscillators
图6-2. Power Up
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图6-3. Power Down
图6-4. I/O Boundary Scan
图6-5. Programmable Output Clocks
图6-6. Port1, Port2, and Port3 Input Interface
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图6-7. Synchronous Serial Port Interface—Primary
图6-8. Synchronous Serial Port Interface—Secondary
图6-9. DMD LVDS Interface
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7 Detailed Description
7.1 Overview
As with prior DLP electronics solutions, image data is 100% digital from the DLPC4420 input port to the image
projected on to the display screen. The image stays in digital form and is never converted into an analog signal.
The DLPC4420 processes the digital input image and converts the data into bit-plane format as needed by the
DMD. The DLPC4420 display controller is optimized for high-resolution and high-brightness display applications.
Applications include 4K ultra high definition (UHD) display, home theatre, smart display, digital signage, and
laser TV.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 System Reset Operation
7.3.1.1 Power-Up Reset Operation
Immediately following a power-up event, the DLPC4420 hardware automatically brings up the primary PLL and
places the controller in normal power mode. Then, the hardware follows the standard system reset procedure
(see 节7.3.1.2).
7.3.1.2 System Reset Operation
Immediately following any type of system reset (power-up reset, PWRGOOD reset, watchdog timer timeout,
lamp-strike reset), the DLPC4420 device automatically returns to NORMAL power mode in the following state:
• All GPIO are tristated.
• The primary PLL remains active (it is reset only after a power-up reset sequence) and most of the derived
clocks are active. However, only those resets associated with the ARM9 processor and its peripherals are
released (the ARM9 is responsible for releasing all other resets).
• ARM9 associated clocks default to their full clock rates. (Boot-up is a full speed.)
• All front-end clocks derived are disabled.
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• The PLL feeding the LVDS DMD I/F (PLLD) defaults to its power-down mode and all derived clocks are
inactive with corresponding resets asserted. (The ARM9 is responsible for enabling these clocks and
releasing associated resets.)
• LVDS I/O defaults to its power-down mode with outputs tristated.
• All resets output by the DLPC4420 device remain asserted until released by the ARM9 (after boot-up).
• The ARM9 processor boots-up from external flash.
When the ARM9 boots-up, the ARM9 API:
• Configures the programmable DDR Clock Generator (DCG) clock rates (that is, the DMD LVDS I/F rate)
• Enables the DCG PLL (PLLD) while holding divider logic in reset
• When the DCG PLL locks, ARM9 software sets DMD clock rates
• API software then releases DCG divider logic resets, which in turn, enable all derived DCG clocks
• Release external resets
Application software then typically waits for a wake-up command (through the soft power switch on the projector)
from the end user. When the projector is requested to wake-up, the software places the ASIC back in normal
mode, re-initialize clocks, and resets as required.
7.3.2 Spread Spectrum Clock Generator Support
The DLPC4420 controller supports limited, internally-controlled, spread spectrum clock spreading on the DMD
interface. The purpose of this is to frequency spread all signals on this high-speed, external interface to reduce
EMI emissions. Clock spreading is limited to triangular waveforms. The DLPC4420 controller provides
modulation options of 0%, +/-0.5% and +/-1.0% (center-spread modulation).
7.3.3 GPIO Interface
The DLPC4420 controller provides 83 software-programmable, general-purpose I/O pins. Each GPIO pin is
individually configurable as either input or output. In addition, each GPIO output can be either configured as
push-pull or open-drain. Some GPIO have one or more alternate-use modes, which are also software
configurable. The reset default for all GPIO is as an input signal. However, any alternate function connected to
these GPIO pins, with the exception of general purpose clocks and PWM generation, stay in reset. When
configured as open-drain, the outputs must be externally pulled-up (to the 3.3-V supply). External pull-up or
pulldown resistors may be required to ensure stable operation before software is able to configure these ports.
7.3.4 Source Input Blanking
Vertical and horizontal blanking requirements for both input ports are defined as follows (See Video Timing
Parameter Definitions).
• Minimum port 1 and port 2 vertical blanking
– Vertical back porch (VBP): 370 µs
– Vertical front porch (VFP): 1 line
– Total vertical blanking (TVB): 370 µs + 2 lines
• Minimum port1 and port 2 horizontal blanking
– Horizontal back porch (HBP): 10 pixels
– Horizontal front porch (HFP): 0 pixels
– Total horizontal blanking (THB): 80 pixels
7.3.5 Video Graphics Processing Delay
The DLPC4420 controller introduces a variable number of field/ frame delays dependent on the source type and
selected processing steps performed on the source. For optimum audio/ video synchronization this delay must
be matched in the audio path. The following tables define various video delay scenarios to aid in audio matching.
Frame and Fields in table refer to source frames and fields.
• For 2-D sources, “N”is defined to be the ratio of the primary channel source frame rate (or field rate for
interlaced video) to the display frame/ field rate.
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• For 3-D sources, “M”is defined to be the ratio of the primary channel source frame rate (or field rate for
interlaced video) required to obtain both the left and right image, to the display frame/field rate (The rate at
which each eye is displayed).
表7-1. Primary Channel/Video-Graphics Processing Delay
Source
48 Hz Graphics
Frame Rate Conversion
FRC Type
Sync (1:1)
Sync (1:1)
Sync (1:1)
Sync (1:1)
Formatter Buffer
Total Delay
1 + N Frames
1 + N Frames
1 + N Frames
1 + N Frames
1 Frame
N Frames
50 Hz Graphics
1 Frame
N Frames
60 Hz Graphics
1 Frame
N Frames
100 and 120 Hz Graphics
1 Frame
N Frames
100 and 120 Hz Graphics
(3D)
1 Frame
1 Frame
Sync (1:2)
Sync (1:1)
M Frames
N Frames
1 + M Frames
1 + N Frames
240 Hz Graphics
(2xDLPC4420)
7.3.6 Program Memory Flash/SRAM Interface
The DLPC4420 controller provides three external program memory chip selects:
• PM_CSZ_0 –available for optional SRAM or flash device (≤128 Mb)
• PM_CSZ_1 –dedicated CS for boot flash device (ie. Standard NOR-type flash, ≤128 Mb)
• PM_CSZ_2 –available for optional SRAM or flash device (≤128 Mb)
Flash and SRAM access timing is software programmable up to 31 wait states. Wait state resolution is 6.7 ns in
normal mode and 53.33 ns in low power modes. Wait state program values for typical flash access times are
shown in the 表7-2.
表7-2. Wait State Program Values for Typical Flash Access Times
Normal Mode (1)
Low Power Mode(1)
Formula to Calculate the
Required Wait State Value
= Roundup
(Device_Access_Time / 53.33 ns)
= Roundup (Device_Access_Time / 6.7 ns)
Max Supported Device Access
Time
207 ns
1660 ns
(1) Assumes a maximum single direction trace length of 75 mm.
Note that when another device such as an SRAM or additional flash is used in conjunction with the boot flash,
care must be taken to keep stub length short and located as close as possible to the flash end of the route.
The DLPC4420 controller provides enough Program Memory Address pins to support a flash or SRAM device up
to 128 Mb. For systems not requiring this capacity, up to two address pins can be used as GPIO instead.
Specifically, the two most significant address bits (i.e. PM_ADDR_22 and PM_ADDR_21) are shared on pins
GPIO_36 and GPIO_35 respectively. Like other GPIO pins, these pins float in a high-impedance input state
following reset; therefore, if these GPIO pins are to be reconfigured as Program Memory Address pins, they
require board-level pull-down resistors to prevent any flash address bits from floating until software is able to
reconfigure the pins from GPIO to Program Memory Address. Also note that until software reconfigures the pins
from GPIO to Program Memory Address, upper portions of flash memory are not accessible.
表7-3 shows typical GPIO_35 and GPIO36 pin configuration for various flash sizes.
表7-3. Typical GPIO_35 and GPIO_36 Pin Configurations for Various Flash Sizes
FLASH SIZE
32 Mb or less
64 Mb
GPIO_36 Pin Configuration
GPIO_35 Pin Configuration
GPIO_36
GPIO_35
GPIO_36
PM_ADDR_21(1)
PM_ADDR_21(1)
128 Mb
PM_ADDR_22(1)
(1) Board-level pulldown resistor required.
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7.3.7 Calibration and Debug Support
The DLPC4420 controller contains a test point output port, TSTPT_(7:0), which provides selected system
calibration support as well as ASIC debug support. These test points are inputs while reset is applied and switch
to outputs when reset is released. The state of these signals is sampled upon the release of system reset and
the captured value configures the test mode until the next time reset is applied. Each test point includes an
internal pull-down resistor and thus external pull-ups are used to modify the default test configuration. The
default configuration (x00) corresponds to the TSTPT_(7:0) outputs being driven low for reduce switching activity
during normal operation. For maximum flexibility, an option to jumper to an external pull-up is recommended for
TSTPT_(3:0). Note that adding pull-up to TSTPT_(7:4) may have adverse affects for normal operation and are
not recommended. Note that these external pull-ups are only sampled upon a zero to one transition on
POSENSE and thus changing their configuration after reset has been released does not have any effect until the
next time reset is asserted and released. 表 7-4 defines the test mode selection for 3 of the 16 programmable
scenarios defined by TSTPT_(3:0):
表7-4. Test Mode Selection
No Switching Activity
System Calibration
ARM Debug Signal Set
x1
TSTPT(3:0) Capture Value
TSTPT(0)
x0
0
x8
Vertical Sync
ARM9_Debug (0)
ARM9_Debug (1)
ARM9_Debug (2)
ARM9_Debug (3)
ARM9_Debug (4)
ARM9_Debug (5)
ARM9_Debug (6)
ARM9_Debug (7)
TSTPT(1)
0
Delayed CW Index
Sequence Index
CW Spoke Test Pt
CW Revolution Test Pt
Reset Seq. Aux Bit 0
Reset Seq. Aux Bit 1
Reset Seq. Aux Bit 2
TSTPT(2)
0
TSTPT(3)
0
TSTPT(4)
0
TSTPT(5)
0
TSTPT(6)
0
TSTPT(7)
0
7.3.8 Board Level Test Support
The in-circuit tristate enable signal (ICTSEN) is a board level test control signal. By driving ICTSEN to a logic
high state, all controller outputs (except TDO1 and TDO2) are tristated.
The DLPC4420 controller also provides JTAG boundary scan support on all I/O except non-digital I/O and a few
special signals. 表7-5 defines these exceptions.
表7-5. DLPC4420 —Signals Not Covered by JTAG
SIGNAL NAME
HW_TEST_EN
MOSC
PKG BALL
M25
M26
N26
MOSCN
USB_DAT_N
USB_DAT_P
TCK
C5
D6
N24
TDI
N25
TRSTZ
M23
N23
TDO1
TDO2
N22
TMS1
P25
TMS2
P26
7.4 Device Functional Modes
The DLPC4420 has two functional modes which are enabled via software command via the Host control
interface. These modes are Standby and Active.
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7.4.1 Standby Mode
The system is powered up and active, however, some blocks within the controller have been shut down to
conserve power. Only the µProcessor and its peripherals are active (supporting a dormant projector waiting to be
woken up). In this mode the DMD is parked and no image can be displayed.
7.4.2 Active Mode
The system is powered up and fully operational, capable of projecting internal or external video sources.
7.4.2.1 Normal Configuration
This configuration enables the full functionality of the DLPC4420.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
The DLPC4420 display controller coupled with supported DMDs comprise the chipset. The controller integrates
all system image processing, DMD control and data formatting onto a single integrated circuit (IC), as well as
LED or LPCW illumination systems and multiple image processing algorithms. Applications include 4K Ultra High
Definition (UHD) Display, Home Theatre, Smart Display, Digital Signage, and Laser TV.
8.2 Typical Application
The DLPC4420 controller is ideal for applications requiring high brightness and high resolution displays. When
two DLPC4420 display controllers are combined with the DLP 4K DMD, an FPGA, a power management and
motor driver device (DLPA100), and other electrical, optical and mechanical components the chipset enables
bright, affordable, 4K UHD display solutions. A typical DLP system application using the DLPC4420 controller
and supported DLP DMD is shown below.
1.1V
FPGA
Voltage
Regulators
1.15V
1.8V
2.5V
3.3V
12V
PWM Driver
Flash
EPROM
I2C
1.1V
1.8V
3.3V
(23) (16)
DLPA100
Controller
PMIC
ADDR
DATA
12V
RGB_EN
CTRL
(3)
RGB_PWM
(3)
FE CTRL
DDR3
USB CTRL
DATA
GPIO
3.3 V
CTRL
DDR3
DLPC4420
Controller
Primary
VBIAS, VOFFSET, VRESET
(3)
ADDR
DMD PMIC
(Power Management IC)
DATA
Front End Device
3D
L/R
SCP CTRL
2xLVDS
I2C
SPI
HBT
4K UHD DMD
Vx1:
XPR FPGA
Vx1
3840 × 2160 @ 60Hz
2xLVDS
I2C
1.8 V
DATA
GPIO
DLPC4420
Controller
Secondary
SPI
Flash
JTAG
ACTUATOR CTRL
Actuator
Driver
4-Position
Actuator
CTRL
1.1V
1.8V
3.3V
DLPA100
Controller
PMIC
ADDR
DATA
I2C
(23) (16)
12V
TI DLP chipset
Flash
EPROM
Third party component
图8-1. Typical 4K UHD LED Display Application
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1.1V
12V
12V
1.21V
1.21V
1.8V
3.3V
FPGA
Voltage
Regulators
1.15V
1.8V
2.5V
3.3V
DLPA100
Controller PMIC
CW Driver
1.8V
3.3V
5V
DLPA100
Controller PMIC
CW Driver
12V
Flash
EPROM
I2C
5V
(23) (16)
ADDR
DATA
CTRL
GPIO
Wheel Motor #2
Wheel Motor #1
CTRL
FE CTRL
DDR3
USB CTRL
DATA
DDR3
DLPC4420
Controller
Primary
VBIAS, VOFFSET, VRESET
(3)
3.3 V
ADDR
1.1V
DMD PMIC
(Power Management IC)
CTRL
1.8V
3.3V
DATA
Front End Device
3D
L/R
SCP CTRL
2xLVDS
I2C
SPI
HBT
Vx1:
4K UHD DMD
XPR FPGA
Vx1
3840 × 2160 @ 60Hz
2xLVDS
I2C
1.8 V
DATA
GPIO
DLPC4420
Controller
Secondary
SPI
Flash
JTAG
ACTUATOR CTRL
Actuator
Driver
4-Position
Actuator
1.1V
1.8V
3.3V
ADDR
DATA
I2C
(23) (16)
TI DLP chipset
Flash
EPROM
Third party component
图8-2. Typical 4K UHD LPCW Display Application
8.2.1 Design Requirements
The display controller is the digital interface between the DMD and the rest of the system. The display controller
takes digital input from front end digital receivers and drives the DMD over a high speed interface. The display
controller also generates the necessary signals (data, protocols, timings) required to display images on the
DMD. Some systems require a dual controller to format the incoming data before sending it to the DMD. Reliable
operation of the DMD is only insured when the DMD and the controller are used together in a system. In addition
to the DLP devices included in the chipset, other devices may be needed such as a flash part to store the
software and firmware.
8.2.1.1 Recommended MOSC Crystal Oscillator Configuration
表8-1. Crystal Port Characteristics
PARAMETER
NOMINAL
UNIT
pF
MOSC TO GROUND Capacitance
MOSCZ TO GROUND Capacitance
1.5
1.5
pF
表8-2. Recommended Crystal Configuration
PARAMETER
Crystal circuit configuration
Crystal type
RECOMMENDED
Parallel resonant
Fundamental (1st harmonic)
20
UNIT
Crystal nominal frequency
Crystal frequency temperature stability
MHz
PPM
+/–30
Overall crystal frequency tolerance (including
accuracy, stability, aging, and trim sensitivity)
PPM
+/–100
Crystal Equivalent Series Resistor (ESR)
Crystal load
50 max
20
Ω
pF
pF
Crystal shunt load
7 max
100
RS drive resistor (nominal)
Ω
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表8-2. Recommended Crystal Configuration (continued)
PARAMETER
RECOMMENDED
UNIT
MΩ
pF
RFB feedback resistor (nominal)
CL1 external crystal load capacitor (MOSC)
CL2 external crystal load capacitor (MOSCN)
1
See (1)
See (1)
.
.
pF
A ground isolation ring around the crystal is
recommended.
PCB layout
(1) Typical drive level with the XSA020000FK1H-OCX Crystal (ESRmax = 40 Ω) = 50 µW.
图8-3. Recommended Crystal Oscillator Configuration
Typically, the external crystal oscillator stabilizes within 50 ms after stable power is applied.
8.2.2 Detailed Design Procedure
For connecting the DLPC4420 controller and the DLP DMD together, see the reference design schematic. The
layout guidelines must be followed to achieve a reliable system. To complete the DLP system, an optical module
or light engine is required that contains the DLP DMD, associated illumination sources, optical elements, and
necessary mechanical components.
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9 Power Supply Recommendations
9.1 System Power Regulations
It is strongly recommended that the VDD18_PLLD, VDD18_PLLM1, and VDD18_PLLM2 power feeding internal
PLLs be derived from an isolated linear regulator in order to minimize the AC Noise component. The
VDD11_PLLD, VDD11_PLLM1, VDD11_PLLM2, and VDD11_PLLS can be derived from the same regulator as
the core VDD11, but they have to be filtered.
9.2 System Power-Up Sequence
Although the DLPC4420 controller requires an array of power supply voltages (1.1V, 1.8V, 3.3V), there are no
restrictions regarding the relative order of power supply sequencing for both power-up and power-down
scenarios. Similarly, there is no minimum time between powering-up or powering-down the different supplies
feeding the DLP controller. However, note that it is not uncommon for there to be power sequencing
requirements for the devices that share the supplies with the DLP controller.
• 1.1V core power is applied whenever any I/O power is applied to ensures the state of the associated I/O that
are powered are controlled to a known state. Thus, it is recommended to apply core power first. Other
supplies are applied only after the 1.1V core has ramped up.
• All DLPC4420 device power must be applied before POSENSE is asserted to ensure proper power-up
initialization.
Typically the DLPC4420 controller power-up sequencing is handled by external hardware. An external power
monitor will hold the controller in system reset during power-up (i.e. POSENSE = 0). During this time all DLP
controller I/Os are tri-stated. The primary PLL (PLLM1) is released from reset upon the low to high transition of
POSENSE but the controller keeps the rest of the device in reset for an additional 60 ms to allow the PLL to lock
and stabilize its outputs. After this 60 ms delay the ARM-9 related internal resets are de-asserted causing the
microprocessor to begin its boot-up routine.
图9-1. System Power-Up Sequence
9.3 Power-On Sense (POSENSE) Support
In order to set up the power monitor to trip within the DLPC4420 controller minimum supply voltage
specifications, it is recommended that the external power monitor generating POSENSE targets its threshold to
90% of the minimum supply voltage specifications and ensures that POSENSE remains low a sufficient amount
of time for all supply voltages to reach minimum device requirements and stabilize. Note that the trip voltage for
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detecting the loss of power, as well as the reaction time to respond to a low voltage condition is not critical for
POSENSE as PWRGOOD is used for this purpose. As such, PWRGOOD has critical requirements in these
areas.
9.4 System Environment and Defaults
9.4.1 DLPC4420 System Power-Up and Reset Default Conditions
Following system power-up, the DLPC4420 controller performs a power-up initialization routine that defaults the
device to a normal power mode, in which ARM9-related clocks are enabled at their full rate and associated
resets are released. Most other clocks default to disabled state with associated resets asserted until released by
the processor. In addition, the default for system power gating enables all power. These same defaults are also
applied as part of all system reset events (Watch Dog timer timeout etc.) that occur without removing or cycling
power, with the possible exception of power for the LVDS I/O and internal DRAM. For an extended reset
condition, the OEM is expected to place the controller in Low Power mode prior to reset, in which case the 1.8V
power for the LVDS I/O and internal DRAM are disabled. When this reset is released, the 1.8V power does not
get enabled until the ARM9 has been initialized and is executing the system initialization routines.
Following power-up or system reset initialization, the ARM9 boots from an external flash memory after which it
enables the 1.8V power (from the DLPA100), enables the rest of the controller clocks, and initializes the internal
DRAM. Once system initialization is complete the Application software determines if and when to enter low
power mode.
9.4.2 1.1V System Power
The DLPC4420 controller can support a low cost power delivery system with a single 1.1V power source derived
from a switching regulator. To enable this approach, appropriate filtering must be provided for the 1.1V power
pins of the PLLs.
9.4.3 1.8V System Power
It is recommended that the DLPC4420 controller power delivery system provides two independent 1.8V power
sources. One of the 1.8V power sources is used to supply 1.8V power to the controller LVDS I/O and internal
DRAM. Power for these functions is fed from a common source which is recommended to be a linear regulator.
The second 1.8V power source is used (along with appropriate filtering as discussed in the PCB layout
guidelines for internal ASIC PLL power section of this document) to supply all of the DLPC4420 controller
internal PLLs. In order to keep this power as clean as possible, a dedicated linear regulator for the 1.8V power to
the PLLs is recommended.
9.4.4 3.3V System Power
The DLPC4420 controller can support a low cost power delivery system with a single 3.3V power source derived
from a switching regulator. This 3.3V source supplies power to all LVTTL I/O and the Crystal Oscillator cell. The
3.3V power must remain active in all power modes for which 1.1V core power is applied.
9.4.5 Power Good (PWRGOOD) Support
The PWRGOOD signal is defined as an early warning signal that alerts the DLPC4420 controller a specified
amount of time before the DC supply voltages drop below specifications, which allows the controller to park the
DMD and to place the system into reset, ensuring the integrity of future operation. For practical reasons, it is
recommended that the monitor sensing PWRGOOD be on the input side of supply regulators.
9.4.6 5V Tolerant Support
With the exception of USB_DAT, the DLPC4420 controller does not support any other 5V tolerant I/Os. However,
note that source signals ALF_HSYNC, ALF_VSYNC and I2C typically have 5V requirements and special
measures must be taken to support them. Also, 5V to 3.3V level shifter is recommended.
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10 Layout
10.1 Layout Guidelines
To achieve the needed thermal connectivity, 2-ounce copper planes in the PCB design are recommended.
10.1.1 PCB Layout Guidelines for Internal DLPC4420 Power
The following guidelines to achieve desired controller performance relative to internal PLLs are recommended:
• The DLPC4420 controller contains four PLLs (PLLM1, PLLM2, PLLD and PLLS), each of which have a
dedicated 1.1V digital supply, and three (PLLM1, PLLM2 and PLLD) which have a dedicated 1.8-V analog
supply. It is important to have filtering on the supply pins that covers a broad frequency range. Each 1.1V PLL
supply pin must have individual high frequency filtering in the form of a ferrite bead and a 0.1µF ceramic
capacitor. These components must be located very close to the individual PLL supply balls. The impedance
of the ferrite bead must be greater than that of the capacitor at frequencies above 10MHz. The 1.1V to the
PLL supply pins must also have low frequency filtering in the form of an RC filter. This filter can be common
to all the PLLs. The voltage drop across the resistor is limited by the 1.1V regulator tolerance and the
DLPC4420 device voltage tolerance. A resistance of 0.36 Ωand a 100 µF ceramic are recommended.
• The analog 1.8V PLL power pins must have a similar filter topology as the 1.1V. In addition, it is
recommended that the 1.8V be generated with a dedicated linear regulator.
• When designing the overall supply filter network, care must be taken to ensure no resonance occurs.
Particular care must be taken around the 1 to 2MHz band, as this coincides with the PLL natural loop
frequency.
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图10-1. PLL Filter Layout
High frequency decoupling is required for both 1.1V and 1.8V PLL supplies and must be provided as close as
possible to each of the PLL supply package pins. It is recommended to place decoupling capacitors under the
package on the opposite side of the board. Use high quality, low-ESR, monolithic, surface mount capacitors.
Typically 0.1µF for each PLL supply is sufficient. The length of a connecting trace increases the parasitic
inductance of the mounting and thus, tracing should be avoided, allowing the via to butt up against the land
itself. Additionally, the connecting trace has to be made as wide as possible. Further improvement can be made
by placing vias to the side of the capacitor lands or doubling the number of vias.
The location of bulk decoupling depends on the system design.
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10.1.2 PCB Layout Guidelines for Auto-Lock Performance
One of the most important factors in getting good performance from Auto-Lock is to design the PCB with the
highest signal integrity possible by following the recommendations below:
• Place the ADC chip as close to the VESA/Video connectors as possible.
• Avoid crosstalk to the analog signals by keeping them away from digital signals
• Do not place the digital ground or power planes under the analog area between the VESA connector to the
ADC chip.
• Avoid crosstalk onto the RGB analog signals, by separating them from the VESA Hsync and Vsync signals.
• Analog power must not be shared with the digital power directly.
• Try to keep the trace lengths of the RGB as equal as possible.
• Use good quality (1%) termination resistors for the RGB inputs to the ADC
• If the green channel must be connected to more than the ADC green input and ADC sync-on-green input,
provide a good quality high impendence buffer to avoid adding noise to the green channel.
10.1.3 DMD Interface Considerations
High speed interface waveform quality and timing on the DLPC4420 controller (that is, the LVDS DMD Interface)
is dependent on the total length of the interconnect system, the spacing between traces, the characteristic
impedance, etch losses, and how well matched the lengths are across the interface. Thus ensuring positive
timing margin requires attention to many factors.
As an example, DMD Interface system timing margin can be calculated as follows:
• Setup Margin = (DLPC4420 output setup) –(DMD input setup) –(PCB routing mismatch) –(PCB SI
degradation)
• Hold-time Margin = (DLPC4420 output hold) –(DMD input hold) –(PCB routing mismatch) –(PCB SI
degradation)
Where PCB SI degradation is signal integrity degradation due to PCB effects, which include simultaneously
switching output (SSO) noise, cross-talk and inter-symbol interference (ISI) noise. The controller I/O timing
parameters as well as DMD I/O timing parameters can be easily found in their corresponding data sheets.
Similarly, PCB routing mismatch can be budgeted and met through controlled PCB routing. However, PCB SI
degradation is not so straight forward.
In an attempt to minimize the signal integrity analysis, the following PCB design guidelines are provided as a
reference of an interconnect system that satisfies both waveform quality and timing requirements (accounting for
both PCB routing mismatch and PCB SI degradation). Variation from these recommendations may also work, but
have to be confirmed with PCB signal integrity analysis or lab measurements
PDB Design:
Asymmetric Dual Stripline
1.0 oz copper (1.2 mil)
0.5 oz copper (0.6 mil)
50 ohms (+/–10%)
●Configuration
●Etch Thickness
●Flex Etch Thickness
●Single Ended Signal Impedance
●Differential Signal Impedance
100 ohms differential (+/–10%)
PCB Stackup:
●Reference plane 1 is assumed to be a ground plane for proper return
path
●Reference plane 2 is assumed to be the I/O power plane or ground
●Dielectric FR4, (Er):
4.2 (nominal)
5.0 mil (nominal)
34.2 mil (nominal)
●Signal trace distance to reference plane 1 (H1)
●Signal trace distance to reference plane 2 (H2)
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图10-2. PCB Stackup Geometries
表10-1. General PCB Routing (Applies to All Corresponding PCB Signals)
PARAMETER
APPLICATION
SINGLE-ENDED SIGNAL DIFFERENTIAL PAIRS
UNIT
Escape Routing in Ball
Field
4 (0.1)
4 (0.1)
mil (mm)
Line width (W)(1)
PCB Etch Data or Control
PCB Etch Clocks
7 (0.18)
7 (0.18)
4.25 (0.11)
4.25 (0.11)
mil (mm)
mil (mm)
Escape Routing in Ball
Field
4 (0.1)
4 (0.1)
mil (mm)
Minimum Line spacing to
other signals (S)
PCB Etch Data or Control
PCB Etch Clocks
10 (0.25)
20 (0.51)
20 (0.51)
20 (0.51)
mil (mm)
mil (mm)
(1) Line width is expected to be adjusted to achieve impedance requirements.
表10-2. DMD I/F, PCB Interconnect Length Matching Requirements
SIGNAL GROUP LENGTH MATCHING
I/F
SIGNAL GROUP
REFERENCE SIGNAL
MAX MISMATCH
UNIT
SCA_P,SCA_N,
DDA_P(15:0),
DDA_N(15:0)
DMD (LVDS)
DCKA_P, DCKA_N
mil (mm)
+/-150 (+/–3.81)
SCB_P,SCB_N,
DDB_P(15:0),
DDB_N(15:0)
DMD (LVDS)
DCKB_P, DCKB_N
mil (mm)
+/-150 (+/–3.81)
Number of layer changes:
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• Single ended signals: Minimize
• Differential signals: Individual differential pairs can be routed on different layers but the signals of a given pair
typically does not change layers.
Termination requirements:
• DMD Interface—None, the DMD receiver is differentially terminated to 100 ohms internally
Connector (DMD-LVDS I/F bus only)—High Speed Connectors that meet the following requirements must be
used:
●Differential Crosstalk
<5 %
●Differential Impedance
75 ohms–125 ohms
Routing requirements for right angle connectors:
When using right angle connectors, P-N pairs have to be routed in same row to minimize delay mismatch and
propagation delay difference for each row has to be accounted for on associated PCB etch lengths.
10.1.4 Layout Example
图10-3. Layer 3
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图10-4. Layer 4
10.1.5 Thermal Considerations
The underlying thermal limitation for the DLPC4420 controller is that the maximum operating junction
temperature (TJ) not be exceeded (this is defined in the 节 6.3). This temperature is dependent on operating
ambient temperature, airflow, PCB design (including the component layout density and the amount of copper
used), power dissipation of the DLPC6421 device and power dissipation of surrounding components. The
DLPC4420 package is designed primarily to extract heat through the power and ground planes of the PCB, thus
copper content and airflow over the PCB are important factors.
The recommended maximum operating ambient temperature (TA) is provided primarily as a design target and is
based on maximum DLPC4420 power dissipation and RθJA at 1 m/s of forced airflow, where RθJA is the thermal
resistance of the package as measured using a JEDEC defined standard test PCB. This JEDEC test PCB is not
necessarily representative of the DLPC4420 PCB, and thus the reported thermal resistance may not be accurate
in the actual product application. Although the actual thermal resistance may be different, it is the best
information available during the design phase to estimate thermal performance. However, after the PCB is
designed and the product is built, it is highly recommended that thermal performance be measured and
validated.
To do this, the top center case temperature has to be measured under the worst case product scenario (max
power dissipation, max voltage, max ambient temp) and validated not to exceed the maximum recommended
case temperature (TC). This specification is based on the measured φJT for the DLPC4420 package and
provides a relatively accurate correlation to junction temperature. Note that care must be taken when measuring
this case temperature to prevent accidental cooling of the package surface. A small (approximately 40 gauge)
thermocouple is recommended. The bead and the thermocouple wire must contact the top of the package and
be covered with a minimal amount of thermally conductive epoxy. The wires must be routed closely along the
package and the board surface to avoid cooling the bead through the wires.
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11 Device and Documentation Support
11.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 Device Support
11.2.1 Video Timing Parameter Definitions
• Active Lines Per Frame (ALPF)—Defines the number of lines in a Frame containing displayable data: ALPF
is a subset of the TLPF.
• Active Pixels Per Line (APPL)—Defines the number of pixel clocks in a line containing displayable data:
APPL is a subset of the TPPL
• Horizontal Back Porch Blanking (HBP)—Number of blank pixel clocks after Horizontal Sync but before the
first active pixel. Note: HBP times are reference to the leading (active) edge of the respective sync signal
• Horizontal Front Porch Blanking (HFP)—Number of blank pixel clocks after the last active pixel but before
Horizontal Sync.
• Horizontal Sync (HS)—Timing reference point that defines the start of each horizontal interval (line). The
absolute reference point is defined by the “active”edge of the HS signal. The “active”edge (either
rising or falling edge as defined by the source) is the reference from which all Horizontal Blanking parameters
are measured.
• Total Lines Per Frame (TLPF)—Defines the Vertical Period (or Frame Time) in lines: TLPF = Total number
of lines per frame (active and inactive).
• Total Pixel Per Line (TPPL)—Defines the Horizontal Line Period in pixel clocks: TPPL = Total number of
pixel clocks per line (active and inactive).
• Vertical Back Porch Blanking (VBP)—Number of blank lines after Vertical Sync but before the first active
line.
• Vertical Front Porch Blanking (VFP)—Number of blank lines after the last active line but before Vertical
Sync.
• Vertical Sync (VS)—Timing reference point that defines the start of the vertical interval (frame). The absolute
reference point is defined by the “active”edge of the VS signal. The “active”edge (either rising or falling
edge as defined by the source) is the reference from which all Vertical Blanking parameters are measured.
TPPL
Vertical Back Porch (VBP)
APPL
Horizontal
Back
Porch
(HBP)
Horizontal
Front
Porch
TLPF
ALPF
(HFP)
Vertical Front Porch (VFP)
图11-1. Timing Parameter Diagram
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11.2.2 Device Nomenclature
表11-1. Part Number Description
TI PART NUMBER
DESCRIPTION
DLPC4420
DLPC4420 Digital Controller
11.2.3 Device Markings
11.2.3.1 Device Marking
图11-2. DLPC4420 Device Markings
Marking Definitions:
Line 1: DLP Device Name followed by TI Part Number
• XXX: ZPC Package designator
Line 2: Vendor Information
Line 3: SSSSSSYYWWMMM-QQ Package Assembly information
• SSSSSS: Vendor Country
• YYWW: Vendor Year and Week Code (YY = Year :: WW = Week)
• MMM: Vendor Manufacturing code (ex. HAL, HBL, HAF)
• QQ: Qualification level (optional)
Line 4: LLLLLLLe1 Manufacturing Information
• LLLLLLL: Manufacturing Lot code
• G1: Green package designator
11.3 Documentation Support
11.3.1 Related Documentation
The following documents contain additional information related to the chipset components used with the
DLPC4420:
• DLPA100 Controller Power Management and Motor Driver Data Sheet
• DLPA300 DMD Power Management and Motor Driver Data Sheet
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11.4 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.5 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.6 Trademarks
ARM946™ is a trademark of ARM.
TI E2E™ is a trademark of Texas Instruments.
DLP® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.7 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.8 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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17-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DLPC4420ZPC
ACTIVE
BGA
ZPC
516
40
TBD
Call TI
Call TI
0 to 55
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
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保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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