DLPA1000YFFT [TI]
用于 DLP2000 (0.2 nHD) DMD 的 PMIC/LED 驱动器 | YFF | 49 | -10 to 85;
| 型号： | DLPA1000YFFT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于 DLP2000 (0.2 nHD) DMD 的 PMIC/LED 驱动器 | YFF | 49 | -10 to 85 驱动 集成电源管理电路 驱动器 |
| 文件： | 总48页 (文件大小：1787K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DLPA1000
ZHCSGS6A –FEBRUARY 2017–REVISED MAY 2017
DLPA1000 电源管理和 LED 驱动器 IC
1 特性
–
过流和欠压保护
•
间距为 0.4mm 的 49 焊球 DSBGA 封装
1
•
具有降压/升压直流/直流转换器和集成式 MOSFET
的高效 RGB LED 驱动器
2 应用
•
通过六个低阻抗 (<100mΩ) MOSFET 开关进行通
道选择
•
•
DLP® Pico™投影仪
•
•
每个通道具有独立的 10 位电流控制
DMD 调节器
嵌入式移动投影
–
–
–
–
智能手机
平板电脑
摄像机
–
–
–
–
仅需一个电感器
VOFS：8.5V
VBIAS：16V
VRST：–10V
笔记本电脑
•
•
•
移动附件
•
•
复位信号生成和电源定序
可佩戴（近眼）显示
电池供电投影仪
RGB LED 闪光灯解码器支持：
–
–
共阳极 RGB
3 说明
阴极-阴极-阳极 RGB
DLPA1000 是一款专用于 DLP2000 数字微镜器件
(DMD) 的 PMIC/RGB LED 驱动器，与 DLPC2607 数
字控制器搭配使用。为确保这些芯片组可靠运行，必须
使用 DLPA1000。
•
•
33MHz 串行外设接口 (SPI)
用于测量模拟信号的多路复用器
–
–
–
–
电池电压
LED 电压，LED 电流
光传感器（用于白点修正）
外部温度传感器
器件信息(1)
器件型号
DLPA1000
封装
封装尺寸（标称值）
•
监控和保护电路
DSBGA (49)
2.40mm × 2.40mm
–
–
热模警告和热关断
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
电池电量不足和欠压锁定
简化电路原理图
Main System
Processor
(MPU)
RESETZ
INTZ
VBIAS
VOFS
VRST
DLP2000
DMD
SPI (4)
LED_SEL0
LED_SEL1
PWM_IN
CMP_OUT
DLPC2607
Pico Processor
VLED
SW4
SW5
SW6
DLPA1000
RGB LED
Assembly
PWR_EN
VINA
DPP
Power Supplies
Single Cell Li-Ion
Light
Sensor
Temp.
Sensor
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDP7
DLPA1000
ZHCSGS6A –FEBRUARY 2017–REVISED MAY 2017
www.ti.com.cn
目录
7.5 Programming........................................................... 20
7.6 Register Maps......................................................... 21
Application and Implementation ........................ 35
8.1 Application Information............................................ 35
8.2 Typical Application .................................................. 35
Power Supply Recommendations...................... 39
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements................................................ 9
6.7 Typical Characteristics............................................ 10
Detailed Description ............................................ 11
7.1 Overview ................................................................ 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 19
8
9
10 Layout................................................................... 40
10.1 Layout Guidelines ................................................. 40
10.2 Layout Example .................................................... 41
11 器件和文档支持 ..................................................... 42
11.1 文档支持................................................................ 42
11.2 接收文档更新通知 ................................................. 42
11.3 社区资源................................................................ 42
11.4 商标....................................................................... 42
11.5 静电放电警告......................................................... 42
11.6 Glossary................................................................ 42
12 机械、封装和可订购信息....................................... 42
7
4 修订历史记录
Changes from Original (February 2017) to Revision A
Page
•
•
已更改 应用 部分 .................................................................................................................................................................... 1
已添加 文档支持 部分 ........................................................................................................................................................... 42
2
Copyright © 2017, Texas Instruments Incorporated
DLPA1000
www.ti.com.cn
ZHCSGS6A –FEBRUARY 2017–REVISED MAY 2017
5 Pin Configuration and Functions
YFF
49-Pin DSBGA
Bottom View
1
2
3
4
5
6
7
G
F
SW1
SW2
SW3
VINA
SW4
SW5
SW6
V6V
VLED
L2
VLED
VLED
L2
LED_SEL0
LED_SEL1
PWR_EN
SPI_CLK
RESETZ
AGND1
TEST
SENS1
CMP_OUT
SPI_CSZ
INTZ
RLIM_K
SENS2
PWM_IN
SPI_DIN
VSPI
RLIM
RLIM
V2V5
E
D
C
B
A
PROJ_ON
DGND
AGND
VOFS
VBIAS
PGNDL
PGNDL
SPI_DOUT
REF_VRST
PGNDR
L1
L1
VINL
VINL
VINR
SWN
SWP
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
VINL
NO.
A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
POWER
POWER
GND
Power supply input for VLED BUCK-BOOST power stage. Connect to system power.
Power supply input for VLED BUCK-BOOST power stage. Connect to system power.
Analog ground. Connect to ground plane.
VINL
AGND1
VINR
POWER
IN (A)
Power supply input for DMD switch mode power supply. Connect to system power.
Connection for the DMD SMPS-inductor (high-side switch).
SWN
PGNDR
SWP
GND
Power ground for DMD SMPS. Connect to ground plane.
IN(A)
Connection for the DMD SMPS-inductor (low-side switch).
L1
IN (A)
Connection for VLED BUCK-BOOST inductor.
L1
IN(A)
Connection for VLED BUCK-BOOST inductor.
RESETZ
INTZ
OUT(D)
OUT(D)
POWER
IN(A)
Reset output to the DLP system (active low). Pin is held low to reset DLP system.
Interrupt output signal (open drain). Connect to pull-up resistor or short to ground.
Power Supply input for SPI interface. Connect to system I/O voltage.
Reference pin for the VRST regulator. Connect to VRST rail through 100-kΩ resistor.
VSPI
REF_VRST
Copyright © 2017, Texas Instruments Incorporated
3
DLPA1000
ZHCSGS6A –FEBRUARY 2017–REVISED MAY 2017
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
B7
C1
C2
C3
C4
C5
C6
C7
D1
D2
D3
D4
D5
D6
D7
E1
E2
E3
E4
E5
E6
E7
F1
F2
F3
F4
VBIAS
OUT(A)
GND
VBIAS output rail. Connect to ceramic capacitor.
Power ground for VLED BUCK-BOOST. Connect to ground plane.
Power ground for VLED BUCK-BOOST. Connect to ground plane.
Clock input for SPI interface.
PGNDL
PGNDL
SPI_CLK
SPI_CSZ
SPI_DIN
SPI_DOUT
VOFS
GND
IN(D)
IN(D)
SPI chip select (active low).
IN(D)
SPI data input.
OUT(D)
OUT(A)
IN(A)
SPI data output.
VOFS output rail. Connect to ceramic capacitor.
Connection for VLED BUCK-BOOST inductor.
Connection for VLED BUCK-BOOST inductor.
Enable pin for the external power supplies (active high).
Analog-comparator output.
L2
L2
IN(A)
PWR_EN
CMP_OUT
PWM_IN
DGND
OUT(D)
OUT(A)
IN(D)
Reference voltage input for analog comparator.
Digital ground. Connect to ground plane.
Analog ground. Connect to ground plane.
VLED BUCK-BOOST converter output pin.
VLED BUCK-BOOST converter output pin.
Digital input to the RGB STROBE DECODER.
Input signal from light sensor.
GND
AGND
GND
VLED
OUT (A)
OUT(A)
IN(D)
VLED
LED_SEL1
SENS1
SENS2
PROJ_ON
V2V5
IN(A)
IN(A)
Input signal from temperature sensor.
IN(D)
Input signal to enable/disable the IC and DLP projector.
Internal supply filter pin for digital logic. Typical 2.45 V.
Internal supply filter pin for gate driver circuitry. Typical 6 V.
VLED BUCK-BOOST converter output pin.
Digital input to the RGB STROBE DECODER.
Test pin for digital, must be tied to the output capacitor of V2V5.
OUT (D)
OUT(D)
OUT(A)
IN(D)
V6V
VLED
LED_SEL0
TEST
IN(D)
Kelvin sense connection for LED current sense resistor. For best accuracy, route signal with a
dedicated trace separated from F6/F7 and connect directly at sense resistor.
RLIM_K
F5
IN(A)
RLIM
RLIM
F6
F7
OUT(A)
OUT(A)
Connection to LED current sense resistor. Connect to a 100-mΩ resistor.
Connection to LED current sense resistor. Connect to pin F6.
High-side MOSFET switch for LED anode. Connect to RGB LED assembly.
If output is not used, short to VLED.
SW1
SW2
SW3
G1
G2
G3
OUT(A)
OUT(A)
OUT(A)
High-side MOSFET switch for LED anode. Connect to RGB LED assembly.
If output is not used, short to VLED.
High-side MOSFET switch for LED anode. Connect to RGB LED assembly.
If output is not used, short to VLED.
VINA
SW4
SW5
SW6
G4
G5
G6
G7
POWER
OUT(A)
OUT(A)
OUT(A)
Power supply input for sensitive analog circuitry.
Low-side MOSFET switch for LED cathode. Connect to RGB LED assembly.
Low-side MOSFET switch for LED cathode. Connect to RGB LED assembly.
Low-side MOSFET switch for LED cathode. Connect to RGB LED assembly.
4
Copyright © 2017, Texas Instruments Incorporated
DLPA1000
www.ti.com.cn
ZHCSGS6A –FEBRUARY 2017–REVISED MAY 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
–0.3
–0.3
–18
MAX
7
UNIT
V
Input voltage
VINL, VINA, VINR
Ground pins to system ground
0.3
7
V
SWN
SWP, VBIAS
VOFS
–0.3
–0.3
20
10
Voltage
V
V6V, VLED, L1, L2, SW1, SW2, SW3, SW4, SW5, SW6,
INTZ, PROJ_ON
–0.3
–0.3
7
All pins unless noted otherwise
Source current
3.6
V
RESETZ, PWR_EN, CMP_OUT
SPI_DOUT
1
5.5
1
mA
RESETZ, PWR_EN, CMP_OUT
SPI_DOUT, INTZ
Sink current
mA
5.5
Peak output current
Internally limited
Internally limited
mA
W
Continuous total power dissipation
Operating ambient temperature
Storage temperature
TA
–30
–65
85
°C
°C
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Full functional and parametric performance
2.7
3.6
6
Input voltage at VINL, VINA, VINR
V
Extended operation, limited parametric
performance
2.3
3.6
1.8
6
Voltage at VSPI
1.7
–10
–10
3.6
85
V
TA
TJ
Operating ambient temperature
Operating junction temperature
°C
°C
125
Copyright © 2017, Texas Instruments Incorporated
5
DLPA1000
ZHCSGS6A –FEBRUARY 2017–REVISED MAY 2017
www.ti.com.cn
6.4 Thermal Information
DLPA1000
THERMAL METRIC(1)
YFF (DSBGA)
UNIT
49 PINS
49
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
0.1
6.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.1
ψJB
6.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
VIN = 3.6 V, TA = –10°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
INPUT VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX UNIT
Input voltage range
Extended input voltage range(1)
Low battery warning threshold
Hysteresis
2.7
2.3
3.6
3.6
3
6
V
6
VIN
VINA, VINR, VINL
VINA falling
V
mV
V
VLOW_BAT
VINA rising
100
2.3
100
Undervoltage lockout threshold
Hysteresis
VINA falling
VUVLO
VINA rising
mV
V
VSTARTUP
Startup voltage
VBIAS, VOFS, VRST loaded with 2 mA
2.5
INPUT CURRENT
IQ
ACTIVE2 mode
STANDBY mode
SLEEP mode
12
360
10
mA
µA
µA
ISTD
ISLEEP
INTERNAL SUPPLIES
VV6V
Internal supply, analog
6.25
100
2.5
V
nF
V
CLDO_V6V
VV2V5
Filter capacitor for V6V LDO
Internal supply, logic
CLDO_V2V5 Filter capacitor for V2V5 LDO
2.2
µF
DMD REGULATOR
Switch E (from VINR to SWN)
Switch F (from SWP to PGND)
Switch G (from SWP to VBIAS)(2)
1000
320
RDS(ON)
MOSFET on resistance
Forward voltage drop
mΩ
1.3
1.3
VINR = 5 V, VSWP = 2 V, IF = 100 mA
VFW
V
Switch H (from SWP to VOFS)
VINR = 5 V, VSWP = 2 V, IF = 100 mA
RDIS
tPG
Discharge resistor (SWP to GND)
Power-good timeout
Switch current limit
Active when all rails are disabled
Not tested in production
2
6
kΩ
ms
mA
µH
ILIMIT
L
200(3)
Inductor value
10
(1) Full functional but limited parametric performance.
(2) Including rectifying diode.
(3) Contact factory for 100-mA and 300-mA options.
6
Copyright © 2017, Texas Instruments Incorporated
DLPA1000
www.ti.com.cn
ZHCSGS6A –FEBRUARY 2017–REVISED MAY 2017
Electrical Characteristics (continued)
VIN = 3.6 V, TA = –10°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
VOFS REGULATOR
Output voltage
TEST CONDITIONS
MIN
TYP
MAX UNIT
8.5
V
2%
DC output voltage accuracy
DC load regulation
IOUT = 2 mA
–2%
VOFS
VIN = 3.6 V, IOUT= 0 mA to 4 mA
–19
35
V/A
VINA, VINL, VINR 2.7 V to 6 V,
IOUT = 2 mA
DC line regulation
mV/V
mV
VRIPPLE
IOUT
Output ripple
VIN = 3.6 V, IOUT = 4 mA, COUT = 220 nF
240
Output current
0
3
mA
VOFS rising
85%
62%
2
Power-good threshold
(fraction of nominal output voltage)
PG
VOFS falling
RDIS
C
Output discharge resistor
Output capacitor
Active when rail is disabled
Recommended value
kΩ
110
220
nF
VBIAS REGULATOR
Output voltage
16
V
DC output voltage accuracy
DC load regulation
IOUT = 2 mA
–2%
2%
VBIAS
VIN = 3.6 V, IOUT = 0 mA to 4 mA
–14
18
V/A
VINA, VINL, VINR 2.7 V to 6 V,
IOUT = 2 mA
DC line regulation
mV/V
VRIPPLE
IOUT
Output ripple
VIN = 3.6 V, IOUT = 4 mA, COUT = 220 nF
240
mV
mA
Output current
0
4
VOFS rising
85%
62%
2
Power-good threshold
(fraction of nominal output voltage)
PG
VOFS falling
RDIS
C
Output discharge resistor
Output capacitor
Active when rail is disabled
Recommended value
kΩ
110
220
nF
VRST REGULATOR
Output voltage
–10
V
DC output voltage accuracy
DC load regulation
IOUT = 2 mA
–2%
2%
VRST
VIN = 3.6 V, IOUT = 0 mA to 4 mA
13
V/A
VINA, VINL, VINR 2.7 V to 6 V,
IOUT = 2 mA
DC line regulation
Output ripple
–21
mV/V
VRIPPLE
VIN = 3.6 V, IOUT = 4 mA, COUT = 220 nF
240
500
mV
mV
mA
V
VREF_VRST Reference voltage
IOUT
PG
C
Output current
0
110
1.2
4
5.9
2.5
Power-good threshold
Output capacitor
–9.1
220
Recommended value
nF
VLED BUCK-BOOST
Output voltage range
VLED
V
Default output voltage
Output overvoltage protection
Fault detection threshold
Switch current limit
SW4/5/6 in OPEN position
Clamps buck-boost output
Triggers VLED_OVP interrupt
3.5
5.9
VOVP
V
V
A
VLED_OVP
ISW
5.4
1.65
2.2
Switch A (from VINL to L1)
Switch B (from L1 to GND)
Switch C (from L2 to GND)
Switch D (from L2 to VLED)
100
100
RDS(ON)
MOSFET on resistance
mΩ
100
100
fSW
Switching frequency
Output capacitance
2.25
2 × 10
MHz
µF
COUT
Copyright © 2017, Texas Instruments Incorporated
7
DLPA1000
ZHCSGS6A –FEBRUARY 2017–REVISED MAY 2017
www.ti.com.cn
MAX UNIT
Electrical Characteristics (continued)
VIN = 3.6 V, TA = –10°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
RGB STROBE CONTROLLER SWITCHES
SW1, SW2, SW3
50
40
100
mΩ
100
RDS(ON)
ILEAK
Drain-source on resistance
Off-state leakage current
SW4, SW5, SW6
VDS = 5 V
1
µA
LED CURRENT CONTROL
Vf
LED forward voltage
ILED = 1 A
4.8
V
VIN = 3.1 V, VLED = 4.4 V
VIN = 4 V, VLED = 4.4 V
700
Maximum LED drive current
DC current accuracy, SW4, 5, 6
Transient LED current limit range
Current rise time(4)
mA
1000
SWx_IDAC[9:0] = 0x100h
RLIM = 100 mΩ, 0.1%, TA = 25°C
ILED
258
272
286
50
mA
mA
µs
ILIM[2:0] = 000
ILIM[2:0] = 111
260
1250
ILED from 5% to 95%, ILED = 300 mA, transient
current limit disabled
trise
MEASUREMENT SYSTEM (AFE)
AFE_GAIN[1:0] = 01
AFE_GAIN[1:0] = 10
AFE_GAIN[1:0] = 11
PGA, AFE_CAL_DIS = 1
Comparator
1
9.5
18
G
Amplifier gain (PGA)
V/V
–1
1
VOFS
Input referred offset voltage(4)
mV
µs
–1.5
1.5
To 1% of final value
To 0.1% of final value
15
52
tsettle
Settling time(4)
fsample
Sampling rate(4)
19 kHz
LOGIC LEVELS AND TIMING CHARACTERISTICS
IO = 0.5 mA, sink current
(RESETZ, PWR_EN, CMP_OUT)
0
0
0.3
V
VOL
Output low-level
Output high-level
IO = 5 mA, sink current
(SPI_DOUT, INTZ)
0.3
IO = 0.5 mA, source current
(RESETZ, PWR_EN, CMP_OUT)
1.3
1.3
2.5
V
VOH
IO = 5 mA, sink current
(SPI_DOUT)
2.5
TEST, PROJ_ON, LED_SEL0, LED_SEL1,
SPI_CSZ, SPI_CLK, SPI_DIN
VIL
Input low-level
Input high-level
Input bias current
0.4
0.5
V
V
TEST, PROJ_ON, LED_SEL0, LED_SEL1,
SPI_CSZ, SPI_CLK, SPI_DIN
VIH
1.2
VIO = 3.3 V
Any input pin
I(bias)
µA
(PROJ_ON, TEST) pins
1
ms
ns
tdeglitch
Deglitch time(4)
(LED_SEL0, LED_SEL1) pins
300
(4) Not tested in production.
8
Copyright © 2017, Texas Instruments Incorporated
DLPA1000
www.ti.com.cn
ZHCSGS6A –FEBRUARY 2017–REVISED MAY 2017
Electrical Characteristics (continued)
VIN = 3.6 V, TA = –10°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
INTERNAL OSCILLATOR
TEST CONDITIONS
MIN
TYP
MAX UNIT
fOSC
Oscillator frequency
Frequency accuracy
9
MHz
10%
TA = –40°C to 85°C
–10%
THERMAL SHUTDOWN
Thermal warning (HOT threshold)
120
10
TWARN
°C
°C
Hysteresis
Thermal shutdown (TSD threshold)
Hysteresis
150
15
TSHTDWN
6.6 Timing Requirements
VBAT = 3.6 V ±5%, TA = 25°C, CL = 10 pF (unless otherwise noted)
PARAMETER
MIN
0
TYP
MAX
UNIT
MHz
ns
fCLK
tCLKL
tCLKH
tt
Serial clock frequency
33.34
Pulse width low, SPI_CLK, 50% level
Pulse width high, SPI_CLK, 50% level
Transition time, 20% to 80% level, all signals
SPI_CSZ falling to SPI_CLK rising, 50% level
SPI_CLK falling to SPI_CSZ rising, 50% level
SPI_DIN data setup time, 50% level
SPI_DIN data hold time, 50% level
10
10
0.2
8
ns
4
1
ns
tCSCR
tCFCS
tCDS
tCDH
tiS
ns
ns
7
6
ns
ns
SPI_DOUT data setup time(1), 50% level
SPI_DOUT data hold time(1), 50% level
SPI_CLK falling to SPI_DOUT data valid, 50% level
SPI_CSZ rising to SPI_DOUT HiZ
10
0
ns
tiH
ns
tCFDO
tCSZ
13
6
ns
ns
(1) The DPPxxxx processors send and receive data on the falling edge of the clock.
SPI_CSZ
(SS)
tCSCR
tCLKL
tCLKH
tCFCS
SPI_CLK
(SCLK)
tCDS
tCDH
SPI_DIN
(MOSI)
tCFDO
tiH
tCSZ
tiS
SPI_DOUT
(MISO)
HiZ
HiZ
Figure 1. SPI Timing Diagram
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6.7 Typical Characteristics
The maximum output current of the buck-boost is a function of input voltage (VIN), and output voltage (VLED). The
relationship between VIN, VLED, and MAX ILED is shown in Figure 2. Please note that VLED is the output of the buck-boost
regulator which includes the voltage drop across the sense resistor (100 mΩ), internal strobe control switch (100-mΩ max),
and the forward voltage of the LED. For example, to drive 1-A of current through a LED with Vf = 4.2 V, the minimum input
voltage needs to be ≥ 3.7 V (VLED = 4.2 V + 1 A × 100 mΩ + 1 A × 100 mΩ = 4.4 V). For an input voltage of 3.1 V and a drive
current of 700 mA, the max VLED voltage cannot exceed 4.4 V.
1100
1000
VLED=3.6V
900
800
VLED=4.0V
700
600
VLED=4.4V
500
400
VLED=4.8V
300
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VIN [V]
Measured on a typical unit. Note that VLED is the output of the buck-boost regulator and includes the voltage drop across the sense resistor,
internal strobe control switch, and the forward voltage of the LED.
Figure 2. Maximum LED Output Current as a Function of Input Voltage (VIN) and BB Output Voltage (VLED)
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7 Detailed Description
7.1 Overview
DLPA1000 is a power management IC optimized for TI DLP® Pico™ Projector systems and meant for use in
either embedded or accessory mobile phone applications. For embedded applications, the projector is built into
the mobile phone and operates from the mobile phone’s single cell battery. In accessory applications, the
projector resides in its own enclosure and has its own battery or external power supply and operates as a stand-
alone device.
DLPA1000 contains a complete LED driver and can supply up to 1 A per LED. Integrated high-current switches
are included for sequentially selecting a red, green, or blue LED. The DLPA1000 also contains three regulated
DC supplies for the DMD: VBIAS, VRST and VOFS.
The DLPA1000 contains a serial periphery interface (SPI) used for setting the configuration. Using SPI, currents
can be set independently for each LED with 10-bit resolution. Other features included are the generation of the
system reset, power sequencing, input signals for sequentially selecting the active LED, IC self-protection, and
an analog multiplexer and comparator to support A/D conversion of system parameters.
7.2 Functional Block Diagram
VINA
V2V5
V6V
Reference
System
From system power
LDO_V2V5
LDO_V6V
VLED
2.2 ꢀF
1 ꢀF
VREF
UVLO
VLED_OVP
100 nF
VINL
VINL
LOW_BAT
VREF
From system power
A
B
C
D
AGND
1 ꢀF
L1
L1
AFE_GAIN [1:0]
AFE_SEL[2:0]
AGND1
AFE
VINA/3
VLED/3
SW4
SW5
SW6
PWM_IN
PGNDL
PGNDL
From host
To host
2.2 ꢀF
CMP_OUT
VLED
Buck-Boost
MUX
RLIM_K
L2
L2
SENS1
SENS2
From light sensor
VLED
VLED
VLED
From temperature sensor
10 ꢀF
VINR
From system power
10 ꢀF
E
10 ꢀF
SWN
REF_VRST
SWP
SW1
SW2
SW3
SW4
SW5
SW6
VRST (œ10 V)
100k
220 nF
RGB
Strobe
Decoder
DMD
Reset
Regulators
10 ꢀF
H
G
RGB LED
Assembly
F
220 nF
PGNDR
VBIAS
VOFS
RLIM
VBIAS (16 V)
VOFS (8.5 V)
RLIM
100 m
RLIM_K
220 nF
TEST
PROJ_ON
LED_SEL0
LED_SEL1
V2V5
LDO_V2V5
From host
From host
From host
RESETZ
PWR_EN
To system
To system
V2V5
0.1 ꢀF
Digital
Core
VSPI
SPI_CSZ
SPI_CLK
SPI_DIN
From host
From host
From host
From host
To host
VIO
INTZ
To DPP (optional)
SPI
SPI_DOUT
DGND
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7.3 Feature Description
7.3.1 DMD Regulators
DLPA1000 contains three switch-mode power supplies that power the DMD. These rails are VOFS, VBIAS, and
VRST. 100 ms after pulling the PROJ_ON pin high, VOFS is powered up, followed by VBIAS and VRST with an
additional 10-ms delay. Only after all three rails are enabled can the LED driver and STROBE DECODER circuit
be enabled. If any one of the rails encounters a fault such as an output short, all three rails are disabled
simultaneously. The detailed power-up and power-down diagram is shown in Figure 3.
5 ms (min.)
5 ms (min.)
System Power 2.5 V
PROJ_ON
2.3 V
3.5 ms fixed delay
PWR_EN
129 ms
100 ms
RESETZ
PROJ_ON interrupt bit
INTZ pin
VOFS
VBIAS
VRST
HiZ
HiZ
12 ms
PRECHARGE
25 ms
10 ms
PRECHARGE
VLED
OFF
ACTIVE1
ACTIVE2
ACTIVE1
OFF
Power-up or down is initiated by pulling the PROJ_ON pin high or low, respectively. Upon pulling PROJ_ON high, the
device enters ACTIVE2 mode immediately because DMD_EN and VLED_EN bits default to 1.
Figure 3. Power-Up and Power-Down Timing of the DMD REGULATOR and VLED Supplies
7.3.2 RGB Strobe Decoder
DLPA1000 contains RGB color-sequential circuitry that is composed of six NMOS switches, the LED driver, the
strobe decoder and the LED current control. The NMOS switches are connected to the terminals of the external
LED package and turn the currents through the LEDs on and off. The strobe decoder controls the gates of the
NMOS switches according to the LED_SEL[1:0] input signals and the MAP bit of the SYSTEM register. The MAP
bit selects one of two package configurations. A ‘1’ indicates a cathode-cathode-anode package and a ‘0’
indicates the common anode package. The two package connections are shown in Figure 4 and the
corresponding switch map in Table 1 and Table 2.
12
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Feature Description (continued)
The LED_SEL[1:0] signals typically receive a rotating code switching from RED to GREEN to BLUE and then
back to RED. When the LED_SEL[1:0] input signals select a specific color, the NMOSFETs are controlled based
on the color selected, and a 10-bit current control DAC for this color is selected that provides a color correction
current to the RGB LEDs feedback control network.
VLED
VLED
SW3
SW2
SW1
SW3
SW2
SW1
SW1
SW2
SW3
SW1
SW2
SW3
SW4
SW5
SW6
SW4
SW5
SW6
R
G
B
G
B
R
SW4
SW5
SW6
SW4
SW5
SW6
RLIM
RLIM
100m
100m
RLIM_K
RLIM_K
Figure 4. LEFT: Switch Connection for a Common-Anode LED Assembly
RIGHT: Switch Connection for a Cathode-Cathode-Anode LED Assembly
Table 1. Switch Positions for Common Anode RGB LEDs (MAP = 0)
MAP = 0 (Common Anode, Default)
LED_SEL[1:0]
0x00h
SW6
open
open
open
SW5
open
open
closed
open
SW4
open
closed
open
open
SW3
SW2
SW1
IDAC input
closed
closed
closed
closed
closed
closed
closed
closed
closed
closed
closed
closed
N/A
0x01h
SW4_IDAC[9:0]
SW5_IDAC[9:0]
SW6_IDAC[9:0]
0x02h
0x03h
closed
Table 2. Switch Positions for Cathode-Cathode-Anode RGB LEDs (MAP = 1)
MAP = 1 (Cathode-Cathode-Anode LED Arrangement)
LED_SEL[1:0]
0x00h
SW6
open
closed
open
open
SW5
open
SW4
open
SW3
open
open
closed
open
SW2
open
open
open
closed
SW1
open
closed
open
open
IDAC input
N/A
0x01h
open
open
SW4_IDAC[9:0]
SW5_IDAC[9:0]
SW6_IDAC[9:0]
0x02h
closed
closed
closed
closed
0x03h
The switching of the six NMOS switches is controlled such that switches are returned to the OPEN position first
before the CLOSED connections are made (Break Before Make). The dead time between opening and closing
switches is controlled through the BBM register. Switches that already are in the CLOSED position and are to
remain in the CLOSED state according to the SWCNTRL register, are not opened during the BBM delay time.
7.3.3 LED Current Control
DLPA1000 provides time-sequential circuitry to drive three LEDs with independent current control. A system
based on a common anode LED configuration is shown in Figure 6 and consists of a buck-boost converter which
provides the voltage to drive the LEDs, three switches connected to the cathodes of the LEDs, a 100-mΩ resistor
used to sense the LED current, and a current DAC to control the LED current.
The STROBE DECODER controls the switch positions as described in the section above. With all switches in the
OPEN position, the buck-boost output assumes an output voltage of 3.5 V.
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For a common-anode RGB LED configuration (MAP = 0, default), the BUCK-BOOST output voltage (VLED)
assumes a value such that the voltage drop across the sense resistor equals (SW4_IDAC[9:0] × 100 mΩ) when
SW4 is closed. The exact value of VLED depends on the current setting and the voltage drop across the LED but
is limited to 6.5 V. When the STROBE decoder switches from SW4 to SW5, the Buck-Boost assumes a new
output voltage such that the sense voltage equals (SW5_IDAC[9:0] × 100 mΩ), and finally, when SW6 is
selected, V(RLIM_K) is regulated to (SW6_IDAC[9:0] × 100 mΩ).
Similarly, the regulation current setting switches from SW4_IDAC[9:0] to SW5_IDAC[9:0] to SW6_IDAC[9:0]
depending on the LED_SEL[1:0] setting with a MAP setting of 1 (cathode-cathode-anode configuration). See
Table 2 for details.
7.3.3.1 LED Current Accuracy
LED drive current is controlled by a current DAC (digital to analog converter) and can be set independently for
switch SW4, SW5, and SW6. The DAC is trimmed to achieve a LED drive current of 272 mA at code 0x100h with
an accuracy of ±14 mA. The first order gain-error of the DAC can be neglected, therefore the LED driver current
accuracy of ±14 mA can be assumed over the full current range. For example, at full-scale (SWx_IDAC[9:0] =
0x3FFh) the LED current is regulated to 1030 mA ±14 mA or ±1.4%. At the lowest setting (0x001h) the LED
current is regulated to 20 mA ±14 mA and the resulting relative error is large; however this is not a typical
operating point for a projector application. A typical drive current for projection LEDs is 300 mA and the resulting
regulation error is < 5%.
7.3.3.2 Transient Current Limiting
Typically the forward voltages of the GREEN and BLUE diodes are close to each other (~3 V to 4 V) but Vf of the
RED diode is significantly lower (1.8 V to 2.5 V). This can lead to a current spike in the RED diode when the
strobe controller switches from GREEN or BLUE to RED because VLED is regulated to a higher voltage than
required to drive the RED diode. DLPA1000 provides transient current limiting for each switch to limit the current
in the LEDs during the transition. The transient current limit value is controlled through the ILIM[2:0] bits in the
IREG register. The same register also contains three bits to select which switch employs the transient current
limiting feature. In a typical application it is required only for the RED diode and the ILIM[2:0] value should be set
approximately 10% higher than the DC regulation current. The effect that the transient current limit has on the
LED current is shown in Figure 5.
1500
1200
900
600
300
0
1500
1200
900
600
300
0
Current overshoot due
to Buck-Boost output
voltage change.
Transient current
limit active
TIME
TIME
LEFT: RED LED current without transient current limit. The current overshoots because the buck-boost voltage starts
at the (higher) level of the GREEN or BLUE LED.
RIGHT: LED current with transient current limit.
Figure 5. RED LED Current With and Without Transient Current Limit
14
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VLED
SW4
VLED
BUCK-BOOST
FB
SW4LIM_EN
0
ILIM[2:0]
VDAC
E/A
1
SW5LIM_EN
SW5
0
E/A
1
SW6LIM_EN
SW6
RLIM
0
LED_SEL[1:0]
STROBE
DECODER
MAP
E/A
1
SW4_IDAC[9:0]
SW5_IDAC[9:0]
SW6_IDAC[9:0]
RLIM_K
IDAC
200 W
100 mW
Copyright © 2017, Texas Instruments Incorporated
Figure 6. Block Diagram of the LED Driver Circuitry
7.3.4 Measurement System
The measurement system is composed of a 8:1 analog multiplexer (MUX), a programmable-gain amplifier and a
comparator. It works together with the DPP processor to provide:
•
White-point correction (WPC) by independently adjusting the R/G/B LED currents, after measuring the
brightness of each color from an external light sensor.
•
•
•
•
A measurement of the battery voltage.
A measurement of the LED forward voltage.
A measurement of the exact LED current.
A measurement of temperature as derived by measuring the voltage across an external thermistor.
A block diagram of the measurement system is shown in Figure 7.
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VINA VLED
AFE_GAIN [1:0]
AFE_SEL[2:0]
2R
2R
AFE
PWM_IN
From host
To host
SW4
SW5
SW6
RLIM_K
CMP_OUT
MUX
1R
1R
SENS1
SENS2
From light sensor
From temperature sensor
Copyright © 2017, Texas Instruments Incorporated
Figure 7. Block Diagram of the Measurement System
Table 3. Recommended Configuration of the AFE for Different Input Selections
RECOMMENDED GAIN SETTING
AFE-GAIN[1:0]
RECOMMENDED SETTING OF
AFE_CAL_DIS BIT
AFE_SEL[2:0]
SELECTED INPUT
0x00h
0x01h
0x02h
0x03h
SENS2
VLED
0x01h (1x)
0x01h (1x)
0x01h (1x)
0x01h (1x)
Setting has no effect on measurement
Setting has no effect on measurement
Setting has no effect on measurement
Setting has no effect on measurement
VINA
SENS1
Set to 1 if sense voltage is > 100 mV,
otherwise set to 0 (default).
0x04h
0x05h
0x06h
0x07h
RLIM_K
SW4
0x03h (18x)
0x02h (9.5x)
0x02h (9.5x)
0x02h (9.5x)
Set to 1 if sense voltage is > 200 mV,
otherwise set to 0 (default).
Set to 1 if sense voltage is > 200 mV,
otherwise set to 0 (default).
SW5
Set to 1 if sense voltage is > 200 mV,
otherwise set to 0 (default).
SW6
7.3.5 Protection Circuits
DLPA1000 has several protection circuits to protect the IC as well as the system from damage due to excessive
power consumption, die temperature, or over-voltages. These circuits are described below.
7.3.5.1 Thermal Warning (HOT) and Thermal Shutdown (TSD)
DLPA1000 continuously monitors the junction temperature and issues a HOT interrupt if temperature exceeds
the HOT threshold. If the temperature continues to increase above the thermal shutdown threshold, all rails are
disabled and the TSD bit in the INT register is set. Once the temperature drops by 15°C, the output rails are
powered up in sequence and normal operation resumes (DMD_EN bit is not reset by TSD fault).
Thermal shutdown
threshold
hysteresis
Thermal warning
threshold
hysteresis
Temperature
HOT
(internal signal)
TSD
(internal signal)
Available time for controlled
shutdown of System
Figure 8. Definition of the Thermal Shutdown and Hot-Die Temperature Warning
16
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7.3.5.2 Low Battery Warning (BAT_LOW) and Undervoltage Lockout (UVLO)
If the battery voltage drops below the BAT_LOW threshold (typically 3 V) the BAT_LOW interrupt is issued but
normal operation continues. Once the battery drops below the undervoltage threshold (typically 2.3 V) the UVLO
interrupt is issued, all rails are powered down in sequence, the DMD_EN bit is reset, and the part enters
STANDBY mode. The power rails cannot be re-enabled before the input voltage recovers to > 2.4 V. To re-
enable the rails, the PROJ_ON pin must be toggled.
VINA
hysteresis
BAT_LOW threshold
hysteresis
UVLO threshold
ACTIVE
BAT LOW
(internal signal)
INACTIVE
200 ms
ACTIVE
deglitch
UVLO
(internal signal)
INACTIVE
200 ms
deglitch
Figure 9. Undervoltage Lockout is Asserted When the Input Supply Drops Below the UVLO Threshold
7.3.5.3 DMD Regulator Fault (DMD_FLT)
The DMD regulator is continuously monitored to check if the output rails are in regulation and if the inductor
current increases as expected during a switching cycle. If either one of the output rails drops out of regulation
(e.g. due to a shorted output) or the inductor current does not increase as expected during a switching cycle (due
to a disconnected inductor), the DMD_FLT interrupt bit is set in the INT register, the DMD_EN bit is reset, and
the DMD regulator is shut down. Resetting the DMD_EN bit also causes the LED driver to power down. To
restart the system, the PROJ_ON pin must be toggled.
7.3.5.4 V6V Power-Good (V6V_PGF) Fault
The VLED buck-boost requires the V6V rail for proper operation. The rail is continuously monitored and should
the output drop below the power-good threshold, the V6V_PGF bit is set. The buck-boost is disabled and
attempts to restart automatically.
7.3.5.5 VLED Over-Voltage (VLED_OVP) Fault
If the buck-boost output voltage rises above 6.5 V, the VLED_OVP interrupt is set but the buck-boost regulator is
not turned off. A typical condition to cause this fault is an open LED.
7.3.6 Interrupt Pin (INTZ)
The interrupt pin is used to signal events and fault conditions to the host processor. Whenever a fault or event
occurs in the IC, the corresponding interrupt bit is set in the INT register, and the open-drain output is pulled low.
The INTZ pin is released (returns to HiZ state) and fault bits are cleared when the INT register is read by the
host. However, if a failure persists, the corresponding INT bit remains set and the INTZ pin is pulled low again
after a maximum of 32 µs.
Interrupt events include fault conditions such as power-good faults, over-voltage, over-temperature shut-down,
and under-voltage lock-out.
The MASK register is used to mask events from generating interrupts, i.e. from pulling the INTZ pin low. The
MASK settings affect the INTZ pin only and have no impact on protection and monitor circuits themselves. When
an interrupt is masked, the event causing the interrupt still sets the corresponding bit in the INT register.
However, it does not pull the INTZ pin low.
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Note that persisting fault conditions such as thermal shutdown can cause the INTZ pin to be pulled low for an
extended period of time which can keep the host in a loop trying to resolve the interrupt. If this behavior is not
desired, set the corresponding mask bit after receiving the interrupt and keep polling the INT register to see
when the fault condition has disappeared. After the fault is resolved, unmask the interrupt bit again.
7.3.7 Serial Peripheral Interface (SPI)
DLPA1000 provides a 4-wire SPI port that supports high-speed serial data transfers up to 33.3 MHz. Register
and data buffer write and read operations are supported. The SPI_CSZ input serves as the active low chip select
for the SPI port. The SPI_CSZ input must be forced low in order to write or read registers and data buffers.
When SPI_CSZ is forced high, the data at the SPI_DIN input is ignored, and the SPI_DOUT output is forced to a
high-impedance state. The SPI_DIN input serves as the serial data input for the port; the SPI_DOUT output
serves as the serial data output. The SPI_CLK input serves as the serial data clock for both the input and output
data. Data is latched at the SPI_DIN input on the rising edge of SPI_CLK, while data is clocked out of the
SPI_DOUT output on the falling edge of SPI_CLK. Figure 10 illustrates the SPI port protocol. Byte 0 is referred to
as the command byte, where the most significant bit is the write/not read bit. For the W/nR bit, a 1 indicates a
write operation, while a 0 indicates a read operation. The remaining seven bits of the command byte are the
register address targeted by the write or read operation. The SPI port supports write and read operations for
multiple sequential register addresses through the implementation of an auto-increment mode. As shown in
Figure 10, the auto-increment mode is invoked by simply holding the SPI_CSZ input low for multiple data bytes.
The register address is automatically incremented after each data byte transferred, starting with the address
specified by the command byte. After reaching address 0x7Fh the address pointer jumps back to 0x00h.
Set SPI_CSZ=1 here to write/read one register location
Hold SPI_CSZ=0 to enable auto-increment mode
SPI_CSZ
SPI_DIN
Header
Register Data (write)
Byte0
Byte1
Byte2
Byte3
ByteN
Register Data (read)
Data for A[6:0]
Data for A[6:0]+1
Data for A[6:0]+(N-2)
SPI_DOUT
SPI_CLK
Byte 0
Byte 1
W/nR
W/nR
SPI_DIN
A6 A5 A4 A3 A2 A1 A0 N7 N6 N5 N4 N3 N2 N1 N0
Set high for write, low for read
Register Address
SPI_CLK
Figure 10. SPI Protocol
18
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7.4 Device Functional Modes
Table 4. Modes of Operation
MODE
DESCRIPTION
This is the lowest-power mode of operation. All power functions are turned off, registers are reset to their default values and
the IC does not respond to SPI commands. RESETZ and PWR_EN pins are pulled low. The IC will enter OFF mode
whenever the PROJ_ON pin is pulled low.
OFF
Logic core and registers are reset to default values, the IC does not respond to SPI commands, RESETZ and PWR_EN pins
are pulled low, but the analog reference system is kept alive. The device enters RESET state when the input voltage drops
below the UVLO threshold.
RESET
STANDBY
All power functions are turned off but the IC does respond to the SPI interface. The device enters STANDBY mode when
PROJ_ON pins is high, but DMD_EN bit is set to 0. Also, device enters STANDBY mode when a fault on the DMD regulator
occurs or the temperature increases above thermal shutdown threshold (TSD).(1)
The DMD supplies are powered up but LED power (VLED) and the STROBE DECODER are disabled. PROJ_ON pin must
be high, DMD_EN bit must be set to 1, and VLED_EN bit set to 0.
ACTIVE1
ACTIVE2
DMD supplies, LED power and STROBE DECODER are enabled. PROJ_ON pin must be high and DMD_EN and VLED_EN
bits must both be set to 1.
(1) DMD_EN power-up default is 1. Once the bit is set to 0, the PROJ_ON pin must be toggled to recover the bit to 1.
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POWER DOWN
Valid power source connected
VRST = OFF &
VBIAS = OFF &
VOFS = OFF &
VLED = OFF &
PROJ_ON = low
ANY STATE
OFF
STROBE DECODER disabled &
SPI interface disabled
PWR_EN is low
RESETZ is low
All registers reset to default values
PROJ_ON = high
VRST= OFF &
VBIAS= OFF &
VOFS = OFF &
VRST = OFF &
VBIAS = OFF &
VOFS = OFF &
VLED = OFF &
STROBE DECODER disabled &
SPI interface enabled
PWR_EN is high
PROJ_ON = high &
not UVLO
VLED = OFF &
STROBE DECODER disabled&
SPI interface disabled
PWR_EN is low
RESETZ is low
All registers reset to default values
RESET
STANDBY
DMD_EN = 0(1) ||
FAULT
RESETZ is high
DMD_EN = 1(1)
No FAULT
&
UVLO
VRST = ON &
VBIAS = ON &
VOFS = ON &
VLED = OFF &
ACTIVE1
STROBE DECODER disabled &
SPI interface enabled
PWR_EN is high
RESETZ is high
VLED_EN= 0
VLED_EN = 1
VRST = ON &
VBIAS = ON &
VOFS = ON &
VLED = ON &
ACTIVE2
STROBE DECODER enabled
SPI interface enabled
PWR_EN is high
RESETZ is high
NOTES:
|| = OR, & = AND, ( ) = rising edge, ( ) = falling edge
¯
FAULT = Undervoltage on VRST, VBIAS, VOFS, or DMD regulator curren-tlimit fault(DMD_FLT) ||
Thermal Shut Down (TSD)
DMD_PG and UVLO faults reset the DMD_EN bit and keep the part in STANDBY mode.
TSD does not reset DMD_EN bit, so part resumes normal operation after the part has cooled o.ff
(1) :
DMD_EN bit power-up default is1. The bit can be reset by writing to the ENABLE register but to set
the bit back to1 requires toggling of PROJ_ON
Figure 11. State Diagram
7.5 Programming
7.5.1 Password Protected Registers
Register address 0x11h through 0x27h can be read-accessed the same way as any other register but are
protected against accidental write operations through the PASSWORD register (address 0x10h). To write to a
protected register, first:
•
•
Write data 0xBAh to register address 0x10h, then
Write data 0xBEh to register address 0x10h.
20
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ZHCSGS6A –FEBRUARY 2017–REVISED MAY 2017
Programming (continued)
Both writes must be consecutive, i.e. there must be no other read or write operation in between sending the two
bytes. Once the password has been successfully written, register 0x11h through 0x27h are unlocked and can be
write accessed using the regular SPI protocol. They remain unlocked until any byte other than 0xBAh is written to
the PASSWORD register or the part is power cycled.
To check if the registers are unlocked, read back the PASSWORD register. If the data returned is 0x00h, the
registers are locked. If the PASSWORD register returns 0x01h, the registers are unlocked.
7.6 Register Maps
Table 5. Register Address Map
Address
0x00h
0x01h
0x02h
0x03h
0x04h
0x05h
0x06h
0x07h
0x08h
0x09h
0x0Ah
0x0Bh
0x0Ch
0x0Dh
0x10h
0x11h
0x20h
0x21h
0x22h
0x23h
0x24h
0x25h
0x26h
0x27h
Acronym
CHIPID
ENABLE
IREG
Register Name
Section
Go
Chip revision register
Enable register
Go
Transient-current limit settings
Regulation current MSBs, SW4
Regulation current LSBs, SW4
Regulation current MSBs, SW5
Regulation current LSBs, SW5
Regulation current MSBs, SW6
Regulation current LSBs, SW6
Reserved
Go
SW4MSB
SW4LSB
SW5MSB
SW5LSB
SW6MSB
SW6LSB
RESERVED
AFE
Go
Go
Go
Go
Go
Go
AFE (MUX) control
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
BBM
Break before make timing
Interrupt register
INT
INT MASK
PASSWORD
SYSTEM
BYTE0
Interrupt mask register
Password register
System configuration register
User EEPROM, Byte0
User EEPROM, Byte1
User EEPROM, Byte2
User EEPROM, Byte3
User EEPROM, Byte4
User EEPROM, Byte5
User EEPROM, Byte6
User EEPROM, Byte7
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
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7.6.1 Chip ID (CHIPID) Register (address = 0x00h) [reset = A6h]
Figure 12. CHIPID Register
7
6
5
4
3
2
1
0
CHIPID[7:0]
R-A6h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6. CHIPID Register Field Descriptions
Bit
Field
Type
Reset
Description
1010 0000b = DLPA1000 (Rev 1p0)
1010 0010b = DLPA1000 (Rev 1p1)
1010 0110b = DLPA1000 (Rev 1p2)
7-0
CHIPID
R
A6h
7.6.2 Enable (ENABLE) Register (address = 0x01h) [reset = 3h]
Figure 13. ENABLE Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
DMD_EN
R/W-1h
VLED_EN
R/W-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. ENABLE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
0h
N/A
DMD Regulator enable/status bit
0b = disabled (OFF)
1b = enabled (ON)
1
0
DMD_EN
VLED_EN
R/W
R/W
1h
1h
NOTE: Power-up default is 1. Once set to 0, the PROJ_ON pin
must be toggled to set the bit back to 1. If bit is set to 0, VLED
buck-boost will automatically be disabled.
VLED Buck-Boost enable bit
0b = disabled (OFF)
1b = enabled (ON)
NOTE: Bit does not reflect current status of VLED buck-boost.
NOTE: If VLED is disabled, RGB Strobe Decoder will automatically
be disabled
22
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ZHCSGS6A –FEBRUARY 2017–REVISED MAY 2017
7.6.3 Switch Transient Current Limit (IREG) Register (address = 0x02h) [reset = 28h]
Figure 14. IREG Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
ILIM[2:0]
R/W-5h
SW6LIM_EN
R/W-0h
SW5LIM_EN
R/W-0h
SW4LIM_EN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. IREG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R
0h
N/A
Transient current-limit
000b = 260 mA
001b = 300 mA
010b = 345 mA
011b = 385 mA
100b = 440 mA
101b = 660 mA
110b = 880 mA
111b = 1250 mA
5-3
ILIM[2:0]
R/W
5h
NOTE: Transient current limit should always be set higher than
regulation current
Transient current-limit enable for SW6
0b = transient current-limit is disabled
1b = transient current-limit is enabled
2
1
0
SW6LIM_EN
SW5LIM_EN
SW4LIM_EN
R/W
R/W
R/W
0h
0h
0h
Transient current-limit enable for SW5
0b = transient current-limit is disabled
1b = transient current-limit is enabled
Transient current-limit enable for SW4
0b = transient current-limit is disabled
1b = transient current-limit is enabled
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7.6.4 SW4 LED DC Regulation Current, MSB (SW4MSB) Register (address = 0x03h) [reset = 0h]
Figure 15. SW4MSB Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
SW4_IDAC[9:8]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. SW4MSB Register Field Descriptions
Bit
7-2
1-0
Field
Type
R
Reset
0h
Description
RESERVED
SW4_IDAC[9:8]
N/A
R/W
0h
Switch4 DC regulation, most significant byte (MSB)
7.6.5 SW4 LED DC Regulation Current, LSB (SW4LSB) Register (address = 0x04h) [reset = 0h]
Figure 16. SW4LSB Register
7
6
5
4
3
2
1
0
SW4_IDAC[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. SW4LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
SW4_IDAC[7:0]
R/W
0h
Switch4 DC current limit, least significant byte (MSB)
LED
LED
LED
LED
SW4_IDAC[9:0]
SW4_IDAC[9:0]
SW4_IDAC[9:0]
SW4_IDAC[9:0]
CURRENT(1)
CURRENT(1)
272 mA
CURRENT(1)
525 mA
CURRENT(1)
0x000h
0x001h
0x002h
...
0 mA
19.99 mA
20.98 mA
...
0x100h
0x101h
0x102h
...
0x200h
0x201h
0x202h
...
0x300h
0x301h
0x302h
...
777.99 mA
778.98 mA
779.97 mA
...
272.99 mA
273.98 mA
...
525.98 mA
526.97 mA
...
0x0FEh
0x0FFh
270.02 mA
271.01 mA
0x1FEh
0x1FFh
523.602 mA
524.01 mA
0x2FEh
0x2FFh
776.02 mA
777 mA
0x3FEh
0x3FFh
1029.01 mA
1030 mA
(1) Values shown are for a typical unit at TA = 25°C. Typical step size is 988 µA.
24
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ZHCSGS6A –FEBRUARY 2017–REVISED MAY 2017
7.6.6 SW5 LED DC Regulation Current, MSB (SW5MSB) Register (address = 0x05h) [reset = 0h]
Figure 17. SW5MSB Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
SW5_IDAC[9:8]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. SW5MSB Register Field Descriptions
Bit
7-2
1-0
Field
Type
R
Reset
0h
Description
RESERVED
SW5_IDAC[9:8]
N/A
R/W
0h
Switch5 DC regulation, most significant byte (MSB)
7.6.7 SW5 LED DC Regulation Current, LSB (SW5LSB) Register (address = 0x06h) [reset = 0h]
Figure 18. SW5LSB Register
7
6
5
4
3
2
1
0
SW5_IDAC[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. SW5LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
SW5_IDAC[7:0]
R/W
0h
Switch5 DC current limit, least significant byte (LSB)
LED
LED
LED
LED
SW5_IDAC[9:0]
SW5_IDAC[9:0]
SW5_IDAC[9:0]
SW5_IDAC[9:0]
CURRENT(1)
CURRENT(1)
272 mA
CURRENT(1)
525 mA
CURRENT(1)
0x000h
0x001h
0x002h
...
0 mA
19.99 mA
20.98 mA
...
0x100h
0x101h
0x102h
...
0x200h
0x201h
0x202h
...
0x300h
0x301h
0x302h
...
777.99 mA
778.98 mA
779.97 mA
...
272.99 mA
273.98 mA
...
525.98 mA
526.97 mA
...
0x0FEh
0x0FFh
270.02 mA
271.01 mA
0x1FEh
0x1FFh
523.602 mA
524.01 mA
0x2FEh
0x2FFh
776.02 mA
777 mA
0x3FEh
0x3FFh
1029.01 mA
1030 mA
(1) Values shown are for a typical unit at TA = 25°C. Typical step size is 988 µA.
Copyright © 2017, Texas Instruments Incorporated
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7.6.8 SW6 LED DC Regulation Current, MSB (SW6MSB) Register (address = 0x07h) [reset = 0h]
Figure 19. SW6MSB Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
SW6_IDAC[9:8]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. SW6MSB Register Field Descriptions
Bit
7-2
1-0
Field
Type
R
Reset
0h
Description
RESERVED
SW6_IDAC[9:8]
N/A
R/W
0h
Switch6 DC regulation, most significant byte (MSB)
7.6.9 SW6 LED DC Regulation Current, LSB (SW6LSB) Register (address = 0x08h) [reset = 0h]
Figure 20. SW6LSB Register
7
6
5
4
3
2
1
0
SW6_IDAC[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. SW6LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
SW6_IDAC[7:0]
R/W
0h
Switch6 DC current limit, least significant byte (LSB)
LED
LED
LED
LED
SW6_IDAC[9:0]
SW6_IDAC[9:0]
SW6_IDAC[9:0]
SW6_IDAC[9:0]
CURRENT(1)
CURRENT(1)
272 mA
CURRENT(1)
525 mA
CURRENT(1)
0x000h
0x001h
0x002h
...
0 mA
19.99 mA
20.98 mA
...
0x100h
0x101h
0x102h
...
0x200h
0x201h
0x202h
...
0x300h
0x301h
0x302h
...
777.99 mA
778.98 mA
779.97 mA
...
272.99 mA
273.98 mA
...
525.98 mA
526.97 mA
...
0x0FEh
0x0FFh
270.02 mA
271.01 mA
0x1FEh
0x1FFh
523.602 mA
524.01 mA
0x2FEh
0x2FFh
776.02 mA
777 mA
0x3FEh
0x3FFh
1029.01 mA
1030 mA
(1) Values shown are for a typical unit at TA = 25°C. Typical step size is 988 µA.
26
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ZHCSGS6A –FEBRUARY 2017–REVISED MAY 2017
7.6.10 Analog Front End Control (AFE) Register (address = 0x0Ah) [reset = 0h]
Figure 21. AFE Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
AFE_EN
R-0h
AFE_CAL_DIS
R/W-0h
AFE_GAIN[1:0]
R/W-0h
AFE_SEL[2:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. AFE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R
0h
N/A
Enable bit for AFE
0b = AFE is disabled
1b = AFE is enabled
6
5
AFE_EN
R
0h
0h
NOTE: Comparator output is in HiZ state when disabled.
Calibration disable bit. Set this bit high to disable the factory
calibration setting. May result in lower offset error if sensed input
voltage level is significantly greater than 40 mV (see Table 3).
0b = Factory calibration setting is enabled
AFE_CAL_DIS
R/W
1b = Factory calibration setting is disabled
Gain setting of the programmable gain amplifier
00b = amplifier is off
01b = 1x
10b = 9.5x
4-3
2-0
AFE_GAIN
R/W
R/W
0h
0h
11b = 18x
AFE Multiplexer control
000b = SENS2
001b = VLED
010b = VINA
011b = SENS1
100b = RLIM_K
101b = SW4
AFE_SEL[2:0]
110b = SW5
111b = SW6
7.6.11 Strobe Decode - Break Before Make Timing Control (BBM) Register (address = 0x0Bh) [reset =
0h]
Figure 22. BBM Register
7
6
5
4
3
2
1
0
BBM[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. BBM Register Field Descriptions
Bit
Field
Type
Reset
Description
Break before make timing. Time between opening one set of switches and closing
the next set.(1)
0x00 = 222 ns
0x01 = 333 ns
0x02 = 444 ns
...
0x40 = 7326 ns
0x41 = 7437 ns
0x42 = 7548 ns
...
0x80 = 14430 ns
0x81 = 14451 ns
0x82 = 14652 ns
...
0xC0 = 21534 s
0xC1 = 21645 ns
0xC2 = 21756 ns
...
7-0
BBM[7:0]
R/W
0h
0x3E = 7104 ns
0x3F = 7215 ns
0x7E = 14208 ns
0x7F = 14319 ns
0xBE = 21312 ns
0xBF = 21423 ns
0xFE = 28416 ns
0xFF = 28527 ns
(1) It takes 333 ns to 444 ns to turn off the switches from the time a change occurs on LED_SEL[1:0].
Copyright © 2017, Texas Instruments Incorporated
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7.6.12 Interrupt (INT) Register (address = 0x0Ch) [reset = X]
Figure 23. INT Register
7
6
5
4
3
2
1
0
VLED_OVP
R-X
V6V_PGF
R-X
PROJ_ON
R-X
DMD_FLT
R-X
UVLO
R-X
BAT_LOW
R-X
TSD
R-X
HOT
R-X
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; X = undefined
Table 17. INT Register Field Descriptions
Bit
Field
Type
Reset
Description
VLED BUCK_BOOST over-voltage fault interrupt (normal
operation resumes)
0b = No fault
7
VLED_OVP
R
X
1b = BUCK-BOOST output is above OVP threshold
V6V power-good fault interrupt. (normal operation resumes)
0b = No fault
1b = V6V is not in regulation
6
5
V6V_PGF
PROJ_ON
R
R
X
X
PROJ_ON interrupt (part enters OFF mode)
0b = PROJ_ON pin is pulled high, normal mode
1b = PROJ_ON pin is pulled low. Alerts the DPP that DMD
regulator is about to shut down.
DMD REGULATOR FAULT (part enters STANDBY mode and
DMD_EN bit is cleared)
0b = No fault
1b = The inductor current is not increasing at the correct rate.
Likely to be caused by an open inductor or one of the regulator
outputs has dropped below the power-good threshold. Likely to be
caused by a short.
4
3
DMD_FLT
R
R
X
X
NOTE: DMD_FLT resets DMD_EN bit to 0.
Undervoltage lockout threshold (sensed at VINA pin) (part enters
RESET state)
0b = Battery voltage is above the UVLO threshold
1b = Battery voltage has dropped below the UVLO threshold
NOTE: UVLO resets DMD_EN bit to 0. 25ms after UVLO interrupt
part enters RESET state with SPI disabled.
UVLO
Low-Battery warning (sensed at VINA pin) (normal operation
resumes)
0b = Battery voltage is above the low-battery threshold
1b = Battery voltage has dropped below the low-battery threshold
2
1
0
BAT_LOW
TSD
R
R
R
X
X
X
Thermal Shutdown interrupt (part enters STANDBY mode,
DMD_EN bit is not cleared)
0b = Die temperature is below the thermal shut-down threshold
1b = Die temperature is above thermal shut-down threshold or has
not cooled down enough to recover from TSD
Thermal warning interrupt (normal operation resumes)
0b = Die temperature is normal operating range
1b = Die temperature is above the HOT threshold or has not
cooled down enough to recover from HOT
HOT
28
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ZHCSGS6A –FEBRUARY 2017–REVISED MAY 2017
7.6.13 Interrupt Mask (MASK) Register (address = 0x0Dh) [reset = 0h]
Figure 24. MASK Register
7
6
5
4
3
2
1
0
VLED_OVPM
R/W-0h
V6V_PGM
R/W-0h
PROJ_ONM
R/W-0h
DMD_FLTM
R/W-0h
UVLOM
R/W-0h
BAT_LOWM
R/W-0h
TSDM
R/W-0h
HOTM
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. MASK Register Field Descriptions
Bit
Field
Type
Reset
Description
VLED BUCK_BOOST over-voltage fault interrupt mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
7
VLED_OVPM
R/W
0h
VLED BUCK_BOOST power-good fault interrupt mask
0b = no fault
6
5
4
3
2
1
0
V6V_PGM
PROJ_ONM
DMD_FLTM
UVLOM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
PROJ_ON interrupt mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
DMD REGULATOR fault mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
Undervoltage lockout threshold (sensed at VINA pin) mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
Low-Battery warning (sensed at VINA pin) mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
BAT_LOWM
TSDM
Thermal Shutdown interrupt mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
Thermal warning interrupt mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
HOTM
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www.ti.com.cn
7.6.14 Password (PASSWORD) Register (address = 0x10h) [reset = 0h]
Figure 25. PASSWORD Register
7
6
5
4
3
2
1
0
PASSWORD[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. PASSWORD Register Field Descriptions
Bit
Field
Type
Reset
Description(1)
To write-access protected registers write 0xBAh followed by
0xBEh to the register. Both writes need to be consecutive.
To lock protected registers, write 0x00h.
Reading the PASSWORD register returns 0x00h if the protected
registers are locked for write access and 0x01h if they are
unlocked.
7-0
PASSWORD[7:0]
R/W
0h
(1) Protected registers can be read-accessed without writing to the PASSWORD register.
7.6.15 System Configuration (SYSTEM) Register (address = 0x11h) [reset = 0h]
Figure 26. SYSTEM Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
EEPROG
R/W-0h
RESERVED
R/W-0h
MAP
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. SYSTEM Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R
0h
N/A
EEPROM programming bit. When set high, BYTE0 through BYTE7
settings are committed to EEPROM and become new power-up
default values.
To program the EEPROM, set this bit high and back low after 50
ms. Power must not be interrupted during EEPROM programming
to prevent loss of data.
2
EEPROG
R/W
0h
1
0
RESERVED
MAP
R/W
R/W
0h
0h
This bit should always be set to 0.
Switch map selector bit:
0b = Common anode configuration
1b = Cathode-cathode-anode configuration
NOTE: See switch control section for details.
30
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ZHCSGS6A –FEBRUARY 2017–REVISED MAY 2017
7.6.16 EEPROM User Register, Byte0 (BYTE0) (address = 0x20h) [reset = 0h]
Figure 27. BYTE0 Register
7
6
5
4
3
2
1
0
BYTE0[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. BYTE0 Register Field Descriptions
Bit
Field
Type
Reset
Description
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
7-0
BYTE0[7:0]
R/W
0h
7.6.17 EEPROM User Register, Byte1 (BYTE1) (address = 0x21h) [reset = 0h]
Figure 28. BYTE1 Register
7
6
5
4
3
2
1
0
BYTE1[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. BYTE1 Register Field Descriptions
Bit
Field
Type
Reset
Description
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
7-0
BYTE1[7:0]
R/W
0h
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7.6.18 EEPROM User Register, Byte2 (BYTE2) (address = 0x22h) [reset = 0h]
Figure 29. BYTE2 Register
7
6
5
4
3
2
1
0
BYTE2[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23. BYTE2 Register Field Descriptions
Bit
Field
Type
Reset
Description
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
7-0
BYTE2[7:0]
R/W
0h
7.6.19 EEPROM User Register, Byte3 (BYTE3) (address = 0x23h) [reset = 0h]
Figure 30. BYTE3 Register
7
6
5
4
3
2
1
0
BYTE3[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. BYTE3 Register Field Descriptions
Bit
Field
Type
Reset
Description
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
7-0
BYTE3[7:0]
R/W
0h
32
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ZHCSGS6A –FEBRUARY 2017–REVISED MAY 2017
7.6.20 EEPROM User Register, Byte4 (BYTE4) (address = 0x24h) [reset = 0h]
Figure 31. BYTE4 Register
7
6
5
4
3
2
1
0
BYTE4[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25. BYTE4 Register Field Descriptions
Bit
Field
Type
Reset
Description
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
7-0
BYTE4[7:0]
R/W
0h
7.6.21 EEPROM User Register, Byte5 (BYTE5) (address = 0x25h) [reset = 0h]
Figure 32. BYTE5 Register
7
6
5
4
3
2
1
0
BYTE5[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 26. BYTE5 Register Field Descriptions
Bit
Field
Type
Reset
Description
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
7-0
BYTE5[7:0]
R/W
0h
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7.6.22 EEPROM User Register, Byte6 (BYTE6) (address = 0x26h) [reset = 0h]
Figure 33. BYTE6 Register
7
6
5
4
3
2
1
0
BYTE6[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 27. BYTE6 Register Field Descriptions
Bit
Field
Type
Reset
Description
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
7-0
BYTE6[7:0]
R/W
0h
7.6.23 EEPROM User Register, Byte7 (BYTE7) (address = 0x27h) [reset = 0h]
Figure 34. BYTE7 Register
7
6
5
4
3
2
1
0
BYTE7[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 28. BYTE7 Register Field Descriptions
Bit
Field
Type
Reset
Description
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
7-0
BYTE7[7:0]
R/W
0h
34
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DLPA1000
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ZHCSGS6A –FEBRUARY 2017–REVISED MAY 2017
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
A DLPC2607 controller can be used with a DLP2000 DMD to provide a compact, reliable, high-efficiency display
solution for many different video display applications. DMDs are spatial light modulators which reflect incoming
light from an illumination source to one of two directions with the primary direction being into collection optics
within a projection lens. The projection lens sends the light to the destination needed for the application. Each
application is derived primarily from the optical architecture of the system and the format of the pixel data being
input into the DLPC2607.
In display applications using the DLP2000 DMD, the DLPA1000 provides necessary analog functions including
analog power supplies and an RGB LED driver to provide a robust and efficient display solution. Display
applications of interest include pico-projectors embedded in display devices like smart phones, tablets, cameras,
and camcorders. Other applications include wearable (near-eye) displays, battery-powered mobile accessory,
interactive display, low latency gaming displays, and digital signage.
8.2 Typical Application
A common application when using DLPA1000 with DLP2000 DMD and DLPC2607 controller is creating a pico-
projector embedded in a handheld product. For example, a pico-projector may be embedded in a smart phone, a
tablet, a camera, or camcorder. The DLPC2607 in the pico-projector embedded module typically receives images
from a host processor within the product as shown in Figure 35. DLPA1000 provides power supply sequencing
and controls the LED currents as required by the application.
Projector Module Electronics
BAT
L5
2.3 V œ 5.5 V
DC
Supplies
1.8 V
Dual
1 V
Connector
PWR_EN
Reg.
MIC
On/Off
SYSPWR
PROJ_ON
L6
LCD
Panel
VDD
VLED
RESETZ
INTZ
L1
L2
PARKZ
RF
I/F
DLPA1000
Analog
RED
PROJ_ON
Flash
GREEN
BLUE
ASIC
INIT_DONE
GPIO4
SPI(4)
FLASH,
SDRAM,
etc.
BIAS, RST, OFS
3
Illumination
Optics
Host
Processor
Parallel or
BT.656
LED_SEL(2)
CLRL
4
DLPC2607
PWM_IN
RGB
28
24/16/8
DATA
CMP_OUT
I2C
Keypad
Thermistor
nHD/WVGA
DDR DMD
CTRL
DATA
DDR
1.8 V
1 V
VIO
VCORE
GPIO5
DDR
Mobile SDRAM
Copyright © 2017, Texas Instruments Incorporated
Figure 35. Typical Standalone Projector System Block Diagram
Copyright © 2017, Texas Instruments Incorporated
35
DLPA1000
ZHCSGS6A –FEBRUARY 2017–REVISED MAY 2017
www.ti.com.cn
Typical Application (continued)
8.2.1 Design Requirements
A pico-projector is created by using a DLP chipset comprised of a DMD such as the DLP2000, a controller such
as the DLPC2607, and a PMIC/LED driver such as the DLPA1000. The DLPA1000 provides the needed analog
functions for the projector, the DLPC2607 does the digital image processing, and the DMD is the display device
for producing the projected image. In addition to the three critical DLP components, other chips may be needed
for the full system design, such as the battery (SYSPWR), a regulated 1.8-V supply for the controller VIO, and a
regulated 1-V supply for the controller VCORE.
The DLPA1000 provides power to the illumination source for the DMD, typically from red, green, and blue LEDs.
These are often contained in three separate packages, but sometimes more than one color of LED die may be in
the same package to reduce the overall size of the pico-projector. The entire pico-projector can be turned on and
off by using a single signal called PROJ_ON. When PROJ_ON is high, the projector turns on and begins
displaying images. When PROJ_ON is set low, the projector turns off and draws just microamps of current on
SYSPWR. When PROJ_ON is set low, the 1.8-V and 1-V supplies can remain active to be used by other non-
projector sections of the product.
8.2.2 Detailed Design Procedure
The DLPA1000 contains a buck-boost regulator for the LEDs, boost regulators for the DMD rails, and internal
LDOs for logic state control and operation. Each regulator requires a few external components to operate,
referenced by their designators in Figure 36 and Figure 38, and all capacitors should maintain the recommended
values at expected operating temperatures and bias voltages.
36
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DLPA1000
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Typical Application (continued)
TEST
V2V5
From system power
VINA
R1
100 kꢁ
C2
1 ꢀF
AGND
C1
2.2 ꢀF
AGND1
R2
1 kꢁ
V6V
C3
100 nF
From host
PWM_IN
C4
1 ꢀF
From system power
VINL
VINL
C6
1 ꢀF
To host
CMP_OUT
From light sensor
SENS1
SENS2
L1
L1
From temperature sensor
PGNDL
PGNDL
From system power
L2
2.2 ꢀH
VINR
C7
10 ꢀF
L2
L2
D6
VRST (œ10 V)
SWN
REF_VRST
SWP
VLED
VLED
VLED
C8
220 nF
R27
100 kꢁ
C9
C10
L1
10 ꢀH
10 ꢀF
10 ꢀF
DLPA1000
PGNDR
VBIAS
SW1
SW2
SW3
SW4
SW5
SW6
VBIAS (16 V)
VOFS (8.5 V)
C11
220 nF
RGB LED
Assembly
VOFS
C12
220 nF
RLIM
RLIM
R34
100 mꢁ
VIO
RLIM_K
R3
100 kꢁ
From host
From host
From host
PROJ_ON
LED_SEL0
LED_SEL1
INTZ
RESETZ
PWR_EN
From host
VSPI
From host
From host
From host
To host
SPI_CSZ
SPI_CLK
SPI_DIN
SPI_DOUT
C5
0.1 ꢀF
DGND
Copyright © 2017, Texas Instruments Incorporated
Figure 36. Schematic
8.2.2.1 VLED Buck-Boost
The VLED buck-boost provides the necessary voltages for the LED array capable of supporting both common
anode and cathode-cathode-anode RGB LEDs. Configurations for both packages are detailed in the RGB Strobe
Decoder section. Alternatively, a design could utilize an optical engine from an OEM that specializes in designing
optics for DLP projectors, which typically integrate the LEDs and DMD into a single module. Current sensing
through the LEDs is accomplished with a high-precision (0.1%) 100-mΩ sense resistor (R34) connecting RLIM to
GND, with a separate trace providing a Kelvin connection to RLIM_K directly from the pad of the sense resistor.
Copyright © 2017, Texas Instruments Incorporated
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Typical Application (continued)
The VLED buck-boost utilizes a single 2.2-µH inductor (L2) to generate the voltages for the LED array, bridging
the pins labeled L1 to the pins labeled L2. The buck-boost also requires a 1-µF input bypass capacitor (C6)
connecting VINL to GND, and two 10-µF output filter capacitors (C9 and C10) connecting VLED to GND. Ensure
the inductor can handle the expected operating currents and refer to Calculating Inductor Peak Current to
calculate the expected peak current for a design that can saturate the inductor's core.
8.2.2.1.1 Calculating Inductor Peak Current
To properly configure the DLPA1000 device, a 2.2-µH inductor (L2) must be connected between pins L1 and L2.
The peak current for the inductor in steady state operation can be calculated.
Equation 1 shows how to calculate the peak current I1 in step down mode operation and Equation 2 shows how
to calculate the peak current I2 in boost mode operation. VIN1 is the maximum input voltage VIN2 is the
minimum input voltage, f is the switching frequency (2.25 MHz) and L the inductor value (2.2 µH).
VOUT VIN1 -VOUT
(
2´VIN1 ´ f ´ L
IOUT
)
I1 =
+
0.8
(1)
VIN 2
V
-VIN 2
VOUT ´ IOUT
0.8´VIN 2
(
2´VOUT ´ f ´ L
)
OUT
I2 =
+
(2)
The critical current value for selecting the right inductor is the higher value of I1 and I2. It also needs to be taken
into account that load transients and error conditions may cause higher inductor currents. This also needs to be
taken into account when selecting an appropriate inductor. Internally the switching current is limited to 2.2 A.
8.2.2.2 DMD Supplies
The PMIC also utilizes a single inductor (L1) to generate the low-current –10-V, 16-V, and 8.5-V supplies.
Connect the inductor from SWP to SWN, and use a Schottky diode (D6) to generate the –10 V by connecting the
cathode of the diode to the SWN side of the inductor and the anode of the diode to the load (VRST). Place a
220-nF filter cap (C8) from VRST to GND and bridge VRST to the feedback pin (REF_VRST) using a 100-kΩ
resistor (R27). Bypass VINR to GND using a 10-µF capacitor (C7), and ensure VBIAS and VOFS each have
dedicated 220-nF output filter capacitors (C11 and C12).
8.2.2.3 LDOs and Digital Logic
Ensure V2V5 has a 2.2-µF output capacitor (C1), and that V6V has a 100-nF output capacitor (C3). It is critical
that V2V5 externally connects to the TEST pin (R1), otherwise the PMIC will be unable to operate. UVLO for this
device is typically 2.3 V.
8.2.3 Application Curve
Figure 37. Power-Up Sequence: PROJ_ON Asserted
38
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DLPA1000
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9 Power Supply Recommendations
The DLPA1000 is designed to operate from a 2.3-V to 6-V input voltage supply or battery. To avoid insufficient
supply current due to line drop, ringing due to trace inductance at the VIN terminal, or supply peak current
limitations, additional bulk capacitance may be required. Electrolytic or tantalum type capacitors can dampen
ringing often caused by ceramic input capacitors. The amount of bulk capacitance required should be evaluated
such that the input voltage can remain in specification long enough for a proper fast shutdown to occur for the
VOFS, VRST, and VBIAS supplies. The shutdown begins when the input voltage drops below the programmable
UVLO threshold such as when the external power supply or battery supply is suddenly removed from the system.
Copyright © 2017, Texas Instruments Incorporated
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DLPA1000
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10 Layout
10.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulators could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. Input capacitors, output capacitors, and inductors should be placed as close as possible to the IC.
40
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DLPA1000
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ZHCSGS6A –FEBRUARY 2017–REVISED MAY 2017
10.2 Layout Example
Place L1 as
Place D6 close to
L1 and C8 close
to D6.
Place L2 (VLED)
C6 and C7
close to the IC as
possible. Max
trace current is
200 mA.
as close to the IC
as possible. Route
on top level and
avoid vias. Max
current is 2 A.
should be placed
close to the IC
(supply caps).
Keep traces
separated and
star-connect to
system power.
Keep trace from
R27 to pin [B6]
shielded from
[A5]-L1 trace as
much as possible
to avoid noise
coupling.
Place C11, and
C12, (VBIAS,
VOFS) close to
the IC. Average
current is <5 mA.
Place C9 and
C10 (VLED) as
close to the IC as
possible. Use
wide metal (1 A
current) and
Place C1, as
close to the IC as
possible. This is
an internal
avoid vias.
reference pin and
needs to be
shielded from
noise.
Keep trace [F5]
R34 separated from
trace [F6, F7] - R34
and connect them
directly at R34. R34
is the LED sense
resistor.
Place C2 (supply
cap) as close to
the IC as possible.
Star-connect to
system power.
Place C3 (V6V)
close to IC and
route on top metal.
This is low-current
trace.
Figure 38. Layout
Table 29. Layout Components
LABEL
DESCRIPTION
C1
C2
V2V5 output filter cap
VINA input cap
C3
V6V output filter cap
VINL input cap
C6
C7
VINR input cap
C8
VRST output filter cap
VLED output filter cap
VLED output filter cap
VBIAS output filter cap
VOFS output filter cap
VRST rectifying diode
DMD supply inductor
C9
C10
C11
C12
D6
L1
L2
VLED buck-boost inductor
100k VRST feedback resistor
100m RLIM sense resistor
R27
R34
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11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
《DLPC2607 DLP PICO 处理器 2607 ASIC》
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
Pico, E2E are trademarks of Texas Instruments.
DLP is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。
42
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DLPA1000YFFR
DLPA1000YFFT
ACTIVE
ACTIVE
DSBGA
DSBGA
YFF
YFF
49
49
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-10 to 85
-10 to 85
100
100
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DLPA1000YFFR
DLPA1000YFFT
DSBGA
DSBGA
YFF
YFF
49
49
3000
250
180.0
180.0
8.4
8.4
3.16
3.16
3.16
3.16
0.71
0.71
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DLPA1000YFFR
DLPA1000YFFT
DSBGA
DSBGA
YFF
YFF
49
49
3000
250
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
D: Max = 3.184 mm, Min =3.124 mm
E: Max = 2.988 mm, Min =2.928 mm
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