DLP660TEAAFYG_技术文档

DLP660TE

ZHCSLT4C –APRIL 2019 –REVISED FEBRUARY 2023

DLP660TE 0.66 4K UHD 数字微镜器件

1 特性

3 说明

• 0.66 英寸对角线微镜阵列

TI DLP^®DLP660TE 数字微镜器件 (DMD) 是一款数控

微光机电系统(MOEMS) 空间光调制器(SLM)，可实现

明亮、经济实惠的全 4K UHD 显示解决方案。与适当

的光学系统配合使用时，DLP660TE DMD 可显示真

4K UHD 分辨率（830 万屏幕像素），并能够向各种显

示介质上投射准确且清晰的图像。DLP660TE DMD 通

过与DLPC4420 显示控制器、DLPA100 控制器电源和

电机驱动器配合使用，可实现高性能系统，而且非常适

合4K UHD 高亮度显示应用。

– 系统可在屏幕上显示4K 超高清(UHD) 3840 ×

2160 像素

– 5.4 微米微镜间距

– ±17° 微镜倾斜度（相对于平坦表面）

– 底部照明

• 2xLVDS 输入数据总线

• DLP660TE 芯片组包括:

– DLP660TE DMD

– DLPC4420 控制器

器件信息⁽¹⁾

– DLPA100 控制器电源管理和电机驱动器IC

封装尺寸（标称值）

器件型号

DLP660TE

封装

FYG (350)

35mm × 32mm

2 应用

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 4K 超高清显示

• 数字标牌

• 激光电视

• 投影映射

DLP660TE 简化应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS163

DLP660TE

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ZHCSLT4C –APRIL 2019 –REVISED FEBRUARY 2023

Table of Contents

7.5 Optical Interface and System Image Quality

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................4

Pin Functions - Test Pads............................................... 11

6 Specifications................................................................ 12

6.1 Absolute Maximum Ratings...................................... 12

6.2 Storage Conditions................................................... 13

6.3 ESD Ratings............................................................. 13

6.4 Recommended Operating Conditions.......................13

6.5 Thermal Information..................................................18

6.6 Electrical Characteristics...........................................18

6.7 Capacitance at Recommended Operating

Conditions................................................................... 18

6.8 Timing Requirements................................................19

6.9 System Mounting Interface Loads............................ 22

6.10 Micromirror Array Physical Characteristics.............22

6.11 Micromirror Array Optical Characteristics............... 24

6.12 Window Characteristics.......................................... 25

6.13 Chipset Component Usage Specification............... 25

7 Detailed Description......................................................26

7.1 Overview...................................................................26

7.2 Functional Block Diagram.........................................26

7.3 Feature Description...................................................27

7.4 Device Functional Modes..........................................27

Considerations............................................................ 27

7.6 Micromirror Array Temperature Calculation.............. 28

7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 29

8 Application and Implementation..................................32

8.1 Application Information............................................. 32

8.2 Typical Application.................................................... 32

8.3 DMD Die Temperature Sensing................................ 34

9 Power Supply Recommendations................................36

9.1 DMD Power Supply Power-Up Procedure................36

9.2 DMD Power Supply Power-Down Procedure........... 36

10 Layout...........................................................................39

10.1 Layout Guidelines................................................... 39

10.2 Layout Example...................................................... 39

11 Device and Documentation Support..........................41

11.1 第三方产品免责声明................................................41

11.2 Device Support........................................................41

11.3 Documentation Support.......................................... 42

11.4 接收文档更新通知................................................... 42

11.5 支持资源..................................................................42

11.6 Trademarks............................................................. 42

11.7 静电放电警告...........................................................42

11.8 术语表..................................................................... 42

12 Mechanical, Packaging, and Orderable

Information.................................................................... 43

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (July 2022) to Revision C (February 2023)

Page

• 将控制器更改为DLPC4420，将芯片组元件链接到产品页面..............................................................................1

• 将控制器更改为DLPC4420，更新了图..............................................................................................................1

• Added the lamp illumination section................................................................................................................. 13

• Added the DMD efficiency specification............................................................................................................24

• Changed controller to DLPC4420.....................................................................................................................26

• Changed controller to DLPC4420.....................................................................................................................27

• Changed controller to DLPC4420, added a table with legacy part numbers and mechanical ICD...................32

• Changed controller to DLPC4420.....................................................................................................................34

• Changed controller to DLPC4420.....................................................................................................................39

• Changed controller to DLPC4420.....................................................................................................................42

Changes from Revision A (September 2020) to Revision B (July 2022)

Page

• Changed SCP specifications to reflect 'Rise/Fall Time'.................................................................................... 19

• Corrected 图6-3 .............................................................................................................................................. 19

• Changed controller to DLPC4420, updated the application diagrams..............................................................32

Changes from Revision (April 2019) to Revision A (September 2020)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

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ZHCSLT4C –APRIL 2019 –REVISED FEBRUARY 2023

• Revised Pin Functions table to add LVDS and LVCMOS types to previously pins.............................................4

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5 Pin Configuration and Functions

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

X

Y

Z

AA

25 23 21 19 17 15 13 11

26 24 22 20 18 16 14 12 10

9

7

5

3

1

8

6

4

2

图5-1. Series 610 350-pin FYG Bottom View

CAUTION

To ensure reliable, long-term operation of the 0.66-inch UHD S610 DMD, it is critical to properly manage the layout and

operation of the signals identified in the table below. For specific details and guidelines, refer to the PCB Design

Requirements for TI DLP Standard TRP Digital Micromirror Devices application report before designing the board.

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表5-1. Pin Functions

TYPE

SIGNAL DATA RATE

DESCRIPTION

NAME

NO.

DATA INPUTS

D_AN(0)

D_AP(0)

D_AN(1)

D_AP(1)

D_AN(2)

D_AP(2)

D_AN(3)

D_AP(3)

D_AN(4)

D_AP(4)

D_AN(5)

D_AP(5)

D_AN(6)

D_AP(6)

D_AN(7)

D_AP(7)

D_AN(8)

D_AP(8)

D_AN(9)

D_AP(9)

D_AN(10)

D_AP(10)

D_AN(11)

D_AP(11)

D_AN(12)

D_AP(12)

D_AN(13)

D_AP(13)

D_AN(14)

D_AP(14)

D_AN(15)

D_AP(15)

C7

C8

D4

E4

C5

C4

D6

C6

D8

D7

D3

E3

B3

C3

E11

E10

E6

Input

2xLVDS

LVDS pair for Data Bus A (15:0)

E5

B10

C10

B8

B9

C13

C14

D15

E15

B12

B13

B15

B16

C16

C17

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表5-1. Pin Functions (continued)

TYPE

SIGNAL DATA RATE

DESCRIPTION

NAME

NO.

Y8

D_BN(0)

D_BP(0)

D_BN(1)

D_BP(1)

D_BN(2)

D_BP(2)

D_BN(3)

D_BP(3)

D_BN(4)

D_BP(4)

D_BN(5)

D_BP(5)

D_BN(6)

D_BP(6)

D_BN(7)

D_BP(7)

D_BN(8)

D_BP(8)

D_BN(9)

D_BP(9)

D_BN(10)

D_BP(10)

D_BN(11)

D_BP(11)

D_BN(12)

D_BP(12)

D_BN(13)

D_BP(13)

D_BN(14)

D_BP(14)

D_BN(15)

D_BP(15)

Y7

X4

W4

Z3

Y3

X6

Y6

X8

X7

X3

W3

W15

X15

W11

W10

W6

W5

AA9

AA10

Z8

Input

2xLVDS

LVDS pair for Data Bus B (15:0)

Z9

Y13

Y14

Z10

Y10

Z12

Z13

Z15

Z16

Y16

Y17

6

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表5-1. Pin Functions (continued)

TYPE

SIGNAL DATA RATE

DESCRIPTION

NAME

NO.

C18

C19

A20

A19

L23

K23

C23

B23

G23

H23

H24

G24

B18

B19

C21

B21

D23

E23

D25

C25

L24

K24

K25

J25

D_CN(0)

D_CP(0)

D_CN(1)

D_CP(1)

D_CN(2)

D_CP(2)

D_CN(3)

D_CP(3)

D_CN(4)

D_CP(4)

D_CN(5)

D_CP(5)

D_CN(6)

D_CP(6)

D_CN(7)

D_CP(7)

D_CN(8)

D_CP(8)

D_CN(9)

D_CP(9)

D_CN(10)

D_CP(10)

D_CN(11)

D_CP(11)

D_CN(12)

D_CP(12)

D_CN(13)

D_CP(13)

D_CN(14)

D_CP(14)

D_CN(15)

D_CP(15)

Input

2xLVDS

LVDS pair for Data Bus C (15:0)

B24

A24

D26

C26

G25

F25

K26

J26

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表5-1. Pin Functions (continued)

TYPE

SIGNAL DATA RATE

DESCRIPTION

NAME

NO.

Y18

Y19

AA20

AA19

N23

P23

Y23

Z23

U23

T23

T24

U24

Z18

Z19

Y21

Z21

X23

W23

X25

Y25

N24

P24

P25

R25

Z24

AA24

X26

Y26

U25

V25

P26

R26

B6

D_DN(0)

D_DP(0)

D_DN(1)

D_DP(1)

D_DN(2)

D_DP(2)

D_DN(3)

D_DP(3)

D_DN(4)

D_DP(4)

D_DN(5)

D_DP(5)

D_DN(6)

D_DP(6)

D_DN(7)

D_DP(7)

D_DN(8)

D_DP(8)

D_DN(9)

D_DP(9)

D_DN(10)

D_DP(10)

D_DN(11)

D_DP(11)

D_DN(12)

D_DP(12)

D_DN(13)

D_DP(13)

D_DN(14)

D_DP(14)

D_DN(15)

D_DP(15)

DCLK_AN

DCLK_AP

DCLK_BN

DCLK_BP

DCLK_CN

DCLK_CP

DCLK_DN

DCLK_DP

Input

2xLVDS

LVDS pair for Data Bus D (15:0)

Input

LVDS

LVDS pair for Data Clock A

LVDS pair for Data Clock B

LVDS pair for Data Clock C

LVDS pair for Data Clock D.

B5

Z6

Z5

G26

F26

U26

V26

DATA CONTROL INPUTS

SCTRL_AN

A10

A9

Input

LVDS

LVDS pair for Serial Control (Sync) A

SCTRL_AP

8

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表5-1. Pin Functions (continued)

TYPE

Input

SIGNAL DATA RATE

DESCRIPTION

NAME

NO.

Y4

SCTRL_BN

SCTRL_BP

SCTRL_CN

SCTRL_CP

SCTRL_DN

SCTRL_DP

LVDS

LVDS pair for Serial Control (Sync) B

LVDS pair for Serial Control (Sync) C

LVDS pair for Serial Control (Sync) D

Y5

E24

D24

W24

X24

DAD CONTROL INPUTS

RESET_ADDR(0)

RESET_ADDR(1)

RESET_ADDR(2)

RESET_ADDR(3)

RESET_MODE(0)

RESET_MODE(1)

R3

R4

T3

U2

P4

V3

Reset Driver Address Select. Bond Pad

connects to an internal Pull Down circuit

Input

LVCMOS

Reset Driver Mode Select. Bond Pad

connects to an internal Pull Down circuit

Input

LVCMOS

Active Low. Output Enable signal for internal

Reset Driver circuitry. Bond Pad connects to

an internal Pull Up circuit

RESET_OEZ

R2

RESET_SEL(0)

RESET_SEL(1)

P3

V2

Reset Driver Level Select. Bond Pad

connects to an internal Pull Down circuit

Rising edge on RESET_STROBE latches in

the control signals. Bond Pad connects to an

internal Pull Down circuit

RESET_STROBE

W8

U4

Active Low. Places reset circuitry in known

VOFFSET state. Bond Pad connects to an

internal Pull Down circuit

RESETZ

Input

LVCMOS

SCP CONTROL

SCPCLK

Serial Communications Port Clock. SCPCLK

is only active when SCPENZ goes low. Bond

Pad connects to an internal Pull Down circuit

W17

W18

Input

LVCMOS

Serial Communications Port Data.

Synchronous to the Rising Edge of SCPCLK.

Bond Pad connects to an internal Pull Down

circuit

SCPDI

Active Low Serial Communications Port

Enable. Bond Pad connects to an internal

Pull Down circuit

SCPENZ

SCPDO

X18

Input

LVCMOS

W16

Output

Serial Communications Port output

EXTERNAL REGULATOR SIGNALS

Active High. Enable signal for external VBIAS

regulator

EN_BIAS

J4

H3

J3

Output

LVCMOS

Active High. Enable signal for external

VOFFSET regulator

EN_OFFSET

Active High. Enable signal for external

VRESET regulator

EN_RESET

OTHER SIGNALS

RESET_IRQZ

Active Low. Output Interrupt to DLP controller

(ASIC)

U3

Output

LVCMOS

TEMP_PLUS

TEMP_MINUS

POWER

E16

E17

Analog

Temperature Sensor Diode Anode.⁽¹⁾

Temperature Sensor Diode Cathode. ⁽¹⁾

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表5-1. Pin Functions (continued)

TYPE

SIGNAL DATA RATE

DESCRIPTION

NAME

NO.

Power supply for Positive Bias level of

micromirror reset signal

VBIAS

A5, A6, A7

Power

A8, B2, C1, D1, D10,

D12, D19, E1, E19,

E20, E21, F1, K1, L1,

M1, N1, P1,V1, W1,

W19, W20, W21, X1,

X10, X12, X19, Y1,

Z1, Z2, AA2, AA8,

Power supply for low voltage CMOS logic.

Power supply for normal high voltage at

micromirror address electrodes. Power

supply for Offset level during power down

sequence

V_CC

Power

A11, A16, A17, A18,

A21, A22, A23, AA11,

AA16, AA17, AA18,

AA21, AA22, AA23,

Power supply for low voltage CMOS LVDS

interface

V_CCI

Power supply for high voltage CMOS logic.

Power supply for stepped high voltage at

micromirror address electrodes. Power

supply for Offset level of MBRST(15:0)

A3, A4, A25, B26,

L26, M26, N26, Z26,

AA3, AA4, AA25

V_OFFSET

Power

G1, H1, J1, R1, T1,

U1

Power supply for Negative Reset level of

micromirror reset signal

V_RESET

B4, B7, B11, B14,

B17, B20, B22, B25,

C2, C9, C20, C22,

C24, D2, D5, D9,

D11, D14, D18, D20,

D21, D22, E2, E7,

E9, E22, E25, E26,

F4, F23, F24, H2, H4,

H25, H26, J23, J24,

K2, L2, L3, L4, L25,

M2, M3, M4, M23,

M24, M25, N2, N3,

N25, P2,R23, R24,

T2, T4, T25, T26, V4,

V23, V24, W2, W7,

W9, W22, W25, W26,

X2, X5, X9, X11, X20,

X21, X22, Y2, Y9,

Y20, Y22, Y24, Z4,

Z7, Z11, Z14, Z17,

Z20, Z22, Z25

V_SS(Ground)

Ground

Common Return for all power

RESERVED SIGNALS

Connect to ground on the printed circuit

board (PCB). Bond Pad connects to an

internal Pull Down circuit

RESERVED_PFE

E18

G4

Ground

Connect to ground on the printed circuit

board (PCB). Bond Pad connects to an

internal Pull Down circuit

RESERVED_TM

Do Not Connect on the printed circuit board

(PCB)

RESERVED_TP0

RESERVED_TP1

RESERVED_TP2

RESERVED_BA

RESERVED_BB

E8

J2

Input

Do Not Connect on the printed circuit board

(PCB)

Do Not Connect on the printed circuit board

(PCB)

G2

N4

K4

Input

Do Not Connect on the printed circuit board

(PCB)

Output

Do Not Connect on the printed circuit board

(PCB)

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表5-1. Pin Functions (continued)

TYPE

SIGNAL DATA RATE

DESCRIPTION

NAME

NO.

Do Not Connect on the printed circuit board

(PCB)

RESERVED_BC

X17

Output

Do Not Connect on the printed circuit board

(PCB)

RESERVED_BD

D17

(1) VSS must be connected for proper DMD operation.

Pin Functions - Test Pads

Pin Number

E13

System Board

Do not connect

C12

D13

C11

E14

E12

C15

D16

W13

Y12

X13

Y11

W14

W12

Y15

X16

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

MAX

UNIT

Supply Voltages

V_CC

Supply voltage for LVCMOS core logic⁽²⁾

Supply voltage for LVDS receivers⁽²⁾

2.3

11

V

–0.5

–15

V_CCI

V_OFFSET

V_BIAS

Supply voltage for HVCMOS and micromirror electrode^{(2) (3)}

Supply voltage for micromirror electrode⁽²⁾

Supply voltage delta (absolute value)⁽⁴⁾

Supply voltage delta (absolute value)⁽⁵⁾

Supply voltage delta (absolute value)⁽⁶⁾

19

V_RESET

|V_CC–V_CCI

–0.3

0.3

11

|

|V_BIAS–V_OFFSET

|

34

|V_BIAS–V_RESET

|

Input Voltages

Input voltage for all other LVCMOS input pins⁽²⁾

Input voltage for all other LVDS input pins^{(2) (6)}

Input differential voltage (absolute value)⁽⁶⁾

Input differential current⁽⁷⁾

V_CC+ 0.5

V_CCI+ 0.5

500

V

–0.5

|V_ID

|

mV

mA

I_ID

6.25

Clocks

Clock frequency for LVDS interface, DCLK_A

Clock frequency for LVDS interface, DCLK_B

Clock frequency for LVDS interface, DCLK_C

Clock frequency for LVDS interface, DCLK_D

400

MHz

ƒ_CLOCK

Environmental

T_ARRAYand T_WINDOW

0

90

°C

Temperature, operating⁽⁸⁾

Temperature, non–

–40

operating⁽⁸⁾

Absolute Temperature delta between any point on the

window edge and the ceramic test point TP1 ⁽⁹⁾

|T_DELTA

T_DP

|

30

81

°C

Dew Point Temperature, operating and non–operating

(noncondensing)

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and

this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltages are referenced to common ground V_SS. V_BIAS, V_CC, V_CCI, V_OFFSET, and V_RESETpower supplies are all required for proper

DMD operation. V_SSmust also be connected.

(3) V_OFFSETsupply transients must fall within specified voltages.

(4) Exceeding the recommended allowable voltage difference between V_CCand V_CCImay result in excessive current draw.

(5) Exceeding the recommended allowable voltage difference between V_BIASand V_OFFSETmay result in excessive current draw.

(6) Exceeding the recommended allowable voltage difference between V_BIASand V_RESETmay result in excessive current draw.

(7) LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(8) The highest temperature of the active array (as calculated using 节7.6 ) or of any point along the window edge as defined in 图7-2.

The locations of thermal test points TP2, TP3, TP4 and TP5 in 图7-2 are intended to measure the highest window edge temperature.

If a particular application causes another point on the window edge to be at a higher temperature, that point is used.

(9) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图

7-2. The window test points TP2, TP3, TP4 and TP5 shown in 图7-2 are intended to result in the worst case delta. If a particular

application causes another point on the window edge to result in a larger delta temperature, that point is be used.

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6.2 Storage Conditions

Applicable for the DMD as a component or non-operating in a system

MIN

MAX

80

UNIT

°C

T_stg

DMD storage temperature

–40

T_DP-AVGAverage dew point temperature, (non-condensing) ⁽¹⁾

28

°C

T_DP-MAXElevated dew point temperature range , (non-condensing) ⁽²⁾

28

36

°C

CT_ELR

Cumulative time in elevated dew point temperature range

24 Months

(1) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(2) Exposure to dew point temperatures in the elevated range during storage and operation is limited to less than a total cumulative time of

CT_ELR

.

6.3 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in

this data sheet is achieved when operating the device within the limits defined by recommended operating conditions . No

level of performance is implied when operating the device above or below the limits.

MIN

NOM

MAX

UNIT

Voltage Supply

V_CC

LVCMOS logic supply voltage⁽¹⁾

1.65

1.8

10

1.95

10.5

18.5

–13.5

0.3

V

V_CCI

LVCMOS LVDS Interface supply voltage⁽¹⁾

Mirror electrode and HVCMOS voltage^{(1) (2)}

Mirror electrode voltage⁽¹⁾

V_OFFSET

V_BIAS

9.5

17.5

18

V_RESET

Mirror electrode voltage⁽¹⁾

–14.5

–14

0

Supply voltage delta (absolute value)⁽³⁾

Supply voltage delta (absolute value)⁽⁴⁾

Supply voltage delta (absolute value)⁽⁵⁾

|V_CC–V_CCI

|V_BIAS–V_OFFSET

|V_BIAS–V_RESET

|

10.5

33

|

LVCMOS Interface

V_IH(DC)

DC input high voltage⁽⁶⁾

DC input low voltage⁽⁶⁾

AC input high voltage⁽⁶⁾

AC input low voltage⁽⁶⁾

PWRDNZ pulse width⁽⁷⁾

0.7 × V_CC

–0.3

V_CC+ 0.3

0.3 × V_CC

V_CC+ 0.3

0.2 × V_CC

V

V_IL(DC)

V_IH(AC)

0.8 × V_CC

–0.3

V

V_IL(AC)

V

t_PWRDNZ

10

ns

SCP Interface

ƒ_SCPCLK

SCP clock frequency⁽⁸⁾

500

900

kHz

ns

µs

ns

µs

t_{SCP_PD}

Propagation delay, clock to Q, from rising edge of SCPCLK to valid SCPDO⁽⁹⁾

Time between the falling edge of SCPENZ and the first rising edge of SCPCLK

Time between the falling edge of SCPCLK and the rising edge of SCPENZ

SCPDI clock setup time (before SCPCLK falling edge)⁽⁹⁾

SCPDI hold time (after SCPCLK falling edge)⁽⁹⁾

0

2

t_{SCP_NEG_ENZ}

t_{SCP_POS_ENZ}

t_{SCP_DS}

2

800

900

2

t_{SCP_DH}

t_{SCP_PW_ENZ}

LVDS Interface

ƒ_CLOCK

SCPENZ inactive pulse width (high level)

Clock frequency for LVDS interface (all channels), DCLK⁽¹¹⁾

Input differential voltage (absolute value)⁽¹²⁾

Common mode voltage⁽¹²⁾

400

440

MHz

mV

ns

|V_ID

|

150

1100

880

300

V_CM

1200

1300

1520

2000

120

V_LVDS

t_{LVDS_RSTZ}

Z_IN

LVDS voltage⁽¹²⁾

Time required for LVDS receivers to recover from PWRDNZ

Internal differential termination resistance

80

100

Ω

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6.4 Recommended Operating Conditions (continued)

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in

this data sheet is achieved when operating the device within the limits defined by recommended operating conditions . No

level of performance is implied when operating the device above or below the limits.

MIN

NOM

MAX

UNIT

Z_LINE

Line differential impedance (PWB/trace)

90

100

110

Ω

Environmental

Array temperature, long-term operational^{(14) (15) (16) (17)}

Array temperature, short-term operational^{(15) (18)}

Window temperature—operational

10

0

40 to 70⁽¹⁶⁾

°C

T_ARRAY

10

85

T_WINDOW

Absolute temperature delta between any point on the window edge and the ceramic test

point TP1^{(19) (20)}

|T_DELTA

|

14

°C

T_{DP -AVG}

T_DP-MAX

CT_ELR

Average dew point average temperature (non-condensing)⁽²¹⁾

Elevated dew point temperature range (non-condensing)⁽²²⁾

Cumulative time in elevated dew point temperature range

28

36

°C

28

24

Months

UNIT

MIN

NOM

MAX

VOLTAGE SUPPLY

V_CC

LVCMOS logic supply voltage⁽¹⁾

1.65

9.5

1.8

10

1.95

10.5

18.5

–13.5

10.5

33

V

V_OFFSET

V_BIAS

Mirror electrode and HVCMOS voltage^{(1) (2)}

Mirror electrode voltage⁽¹⁾

17.5

18

V_RESET

Mirror electrode voltage⁽¹⁾

–14.5

–14

Supply voltage difference (absolute value)⁽³⁾

Supply voltage difference (absolute value)⁽⁴⁾

|V_BIAS–V_OFFSET

|V_BIAS–V_RESET

LVCMOS INTERFACE

|

V_IH(DC)

DC input high voltage⁽⁵⁾

0.7 × V_CC

–0.3

V_CC+ 0.3

0.3 × V_CC

V_CC+ 0.3

0.2 × V_CC

V

V_IL(DC)

DC input low voltage⁽⁵⁾

AC input high voltage⁽⁵⁾

AC input low voltage⁽⁵⁾

PWRDNZ pulse duration⁽⁶⁾

V_IH(AC)

0.8 × V_CC

–0.3

V

V_IL(AC)

V

t_PWRDNZ

10

ns

SCP INTERFACE

ƒ_SCPCLK

SCP clock frequency⁽⁷⁾

500

900

kHz

ns

t_{SCP_PD}

Propagation delay, clock to Q, from rising-edge of SCPCLK to valid SCPDO⁽⁸⁾

Time between falling-edge of SCPENZ and the first rising-edge of SCPCLK

Time between falling-edge of SCPCLK and the rising-edge of SCPENZ

SCPDI clock setup time (before SCPCLK falling edge)⁽⁸⁾

SCPDI hold time (after SCPCLK falling edge)⁽⁸⁾

SCPENZ inactive pulse duration (high level)

0

1

t_{SCP_NEG_ENZ}

t_{SCP_POS_ENZ}

t_{SCP_DS}

µs

1

µs

800

900

2

ns

t_{SCP_DH}

ns

t_{SCP_PW_ENZ}

ƒ_CLOCK

|V_ID

µs

Clock frequency for LVDS interface (all channels), DCLK⁽⁹⁾

Input differential voltage (absolute value)⁽¹⁰⁾

400

440

MHz

mV

ns

|

150

1100

880

300

V_CM

Common mode voltage⁽¹⁰⁾

1200

1300

1520

2000

120

V_LVDS

LVDS voltage⁽¹⁰⁾

t_{LVDS_RSTZ}

Time required for LVDS receivers to recover from PWRDNZ

Internal differential termination resistance

Z_IN

80

90

100

Ω

Z_LINE

Line differential impedance (PWB/trace)

110

Ω

ENVIRONMENTAL

Array temperature, long-term operational^{(11) (12) (13) (23)}

Array temperature, short-term operational^{(12) (15)}

Window temperature –operational^{(16) (17)}

10

0

40 to 70⁽²³⁾

°C

T_ARRAY

10

85

T_WINDOW

Absolute temperature delta between any point on the window edge and the ceramic test

point TP1^{(18) (19)}

|T_DELTA

|

14

°C

T_DP-AVG

T_DP-ELR

CT_ELR

Average dew point temperature (non-condensing)⁽²⁰⁾

Elevated dew point temperature range (non-condensing)⁽²¹⁾

Cumulative time in elevated dew point temperature range

28

36

°C

28

24

months

UNIT

MIN

NOM

MAX

VOLTAGE SUPPLY

V_CC

LVCMOS logic supply voltage⁽¹⁾

1.65

9.5

1.8

10

1.95

10.5

V

V_OFFSET

Mirror electrode and HVCMOS voltage^{(1) (2)}

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6.4 Recommended Operating Conditions (continued)

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in

this data sheet is achieved when operating the device within the limits defined by recommended operating conditions . No

level of performance is implied when operating the device above or below the limits.

MIN

NOM

MAX

UNIT

V_BIAS

Mirror electrode voltage⁽¹⁾

17.5

18

18.5

V

V_RESET

Mirror electrode voltage⁽¹⁾

–14.5

–14

–13.5

10.5

Supply voltage difference (absolute value)⁽³⁾

Supply voltage difference (absolute value)⁽⁴⁾

|V_BIAS–V_OFFSET

|

33

|V_BIAS–V_RESET

|

LVCMOS INTERFACE

V_IH(DC)

V_IL(DC)

V_IH(AC)

V_IL(AC)

DC input high voltage⁽⁵⁾

0.7 × V_CC

–0.3

V_CC+ 0.3

0.3 × V_CC

V_CC+ 0.3

0.2 × V_CC

V

DC input low voltage⁽⁵⁾

AC input high voltage⁽⁵⁾

AC input low voltage⁽⁵⁾

0.8 × V_CC

–0.3

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6.4 Recommended Operating Conditions (continued)

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in

this data sheet is achieved when operating the device within the limits defined by recommended operating conditions . No

level of performance is implied when operating the device above or below the limits.

MIN

NOM

MAX

UNIT

t_PWRDNZ

PWRDNZ pulse duration⁽⁶⁾

10

ns

SCP INTERFACE

ƒ_SCPCLK

SCP clock frequency⁽⁷⁾

500

900

kHz

ns

µs

ns

µs

t_{SCP_PD}

Propagation delay, Clock to Q, from rising-edge of SCPCLK to valid SCPDO⁽⁸⁾

Time between falling-edge of SCPENZ and the first rising-edge of SCPCLK

Time between falling-edge of SCPCLK and the rising-edge of SCPENZ

SCPDI Clock setup time (before SCPCLK falling edge)⁽⁸⁾

SCPDI Hold time (after SCPCLK falling edge)⁽⁸⁾

0

1

t_{SCP_NEG_ENZ}

t_{SCP_POS_ENZ}

t_{SCP_DS}

1

800

900

2

t_{SCP_DH}

t_{SCP_PW_ENZ}

LVDS INTERFACE

ƒ_CLOCK

SCPENZ inactive pulse duration (high level)

Clock frequency for LVDS interface (all channels), DCLK⁽¹⁰⁾

Input differential voltage (absolute value)⁽¹¹⁾

Common mode voltage⁽¹¹⁾

400

440

MHz

mV

ns

|V_ID

|

150

1100

880

300

V_CM

1200

1300

1520

2000

120

V_LVDS

LVDS voltage⁽¹¹⁾

t_{LVDS_RSTZ}

Time required for LVDS receivers to recover from PWRDNZ

Internal differential termination resistance

Line differential impedance (PWB/trace)

Z_IN

80

90

100

Ω

Z_LINE

110

Ω

ENVIRONMENTAL

Array temperature, long-term operational^{(13) (14) (16)}

Array temperature, short-term operational^{(14) (17)}

Window temperature –operational^{(21) (23)}

10

0

40 to 70⁽¹⁵⁾

°C

T_ARRAY

10

85

T_WINDOW

Absolute temperature delta between any point on the window edge and the ceramic test

point TP1^{(18) (19)}

|T_DELTA

|

14

°C

T_{DP -AVG}

T_DP-ELR

CT_ELR

Average dew point temperature (non-condensing)⁽²⁰⁾

Elevated dew point temperature range (non-condensing)⁽²²⁾

Cumulative time in elevated dew point temperature range

28

36

24

°C

28

Months

ILLUMINATION (Lamp)

L

Operating system luminance⁽¹⁹⁾

7000

2.00

lm

ILL_UV

ILL_VIS

ILL_IR

ILL_θ

Illumination wavelengths < 395 nm⁽¹³⁾

Illumination wavelengths between 395 nm and 800 nm

Illumination wavelengths > 800 nm

0.68

mW/cm²

deg

Thermally limited

10

55

Illumination marginal ray angle⁽²³⁾

ILLUMINATION (Solid State)

L

Operating system luminance⁽¹⁹⁾

1000

0.45

lm

ILL_UV

ILL_VIS

ILL_IR

ILL_θ

Illumination wavelengths < 436 nm⁽¹³⁾

Illumination wavelengths between 436 nm and 800 nm

Illumination wavelengths > 800 nm

mW/cm²

deg

Thermally Limited

10

55

Illumination marginal ray angle⁽²³⁾

(1) All voltages are referenced to common ground VSS. VBIAS, VCC, VCCI, VOFFSET, and VRESET power supplies are all required for

proper DMD operation. VSS must also be connected.

(2) VOFFSET supply transients must fall within specified max voltages.

(3) To prevent excess current, the supply voltage delta |VCCI –VCC| must be less than specified limit. See 节9, 图9-1, and 表9-1.

(4) To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than specified limit. See 节9, 图9-1, and 表

9-1.

(5) To prevent excess current, the supply voltage delta |VBIAS –VRESET| must be less than specified limit. See 节9, 图9-1, and 表9-1.

(6) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC

Standard No. 209B, “Low-Power Double Data Rate (LPDDR)”JESD209B.Tester Conditions for VIH and VIL.

•

Frequency = 60 MHz. Maximum Rise Time = 2.5 ns @ (20% –80%)

Frequency = 60 MHz. Maximum Fall Time = 2.5 ns @ (80% –20%)

16

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(7) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tristates the

SCPDO output pin.

(8) The SCP clock is a gated clock. Duty cycle must be 50% ± 10%. SCP parameter is related to the frequency of DCLK.

(9) See 图6-2.

(10) CP internal oscillator is specified to operate all SCP registers. For all SCP operations, DCLK is required.

(11) See LVDS Timing Requirements in 节6.8 and 图6-6.

(12) See 图6-5 LVDS Waveform Requirements.

(13) Supported for video applications only

(14) Simultaneous exposure of the DMD to the maximum 节6.4 for temperature and UV illumination will reduce device lifetime.

(15) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1

(TP1) shown in 图7-2 and the package thermal resistance 节7.6.

(16) Per 图6-1, the maximum operational array temperature will be derated based on the micromirror landed duty cycle that the DMD

experiences in the end application. See 节7.7 for a definition of micromirror landed duty cycle.

(17) Long-term is defined as the usable life of the device.

(18) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is

defined as cumulative time over the usable life of the device and is less than 500 hours.

(19) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图

7-2. The window test points TP2, TP3, TP4, and TP5 shown in 图7-2 are intended to result in the worst case delta temperature. If a

particular application causes another point on the window edge to result in a larger delta temperature, that point is used.

(20) DMD is qualified at the combination of the maximum temperature and maximum lumens specified. Operation of the DMD outside of

these limits has not been tested.

(21) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(22) Exposure to dew point temperatures in the elevated range during storage and operation will be limited to less than a total cumulative

time of CT_ELR

.

(23) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors

(POM), cannot exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been

designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been

tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) will

contribute to thermal limitations described in this document, and may negatively affect lifetime.

80

70

60

50

40

30

0/100

100/0

5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50

65/35

95/5

90/10

85/15

80/20

75/25

70/30

60/40

55/45

50/50

Micromirror Landed Duty Cycle

图6-1. Max Recommended Array Temperature—Derating Curve

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6.5 Thermal Information

DLP660TE

FYG Package

350 PINS

0.60

THERMAL METRIC

UNIT

Thermal resistance, active area to test point 1 (TP1)⁽¹⁾

°C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in the 节6.4. The total heat load on the DMD is largely driven by the

incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and

electrical power dissipation of the array. Optical systems need to be designed to minimize the light energy falling outside the window

clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC= 1.8 V, I_OH= –2 mA

V_CC= 1.95 V, I_OL= 2 mA

V_CC= 1.95 V

MIN

TYP

MAX

UNIT

V

V_OH

V_OL

I_OZ

High level output voltage

Low level output voltage

High impedance output current

Low level input current

High level input current ⁽¹⁾

Supply current VCC

0.8 x V_CC

0.2 x V_CC

25

V

-40

-1

µA

I_IL

V_CC= 1.95 V, VI = 0

V_CC= 1.95 V, VI = V_CC

V_CC= 1.95 V

µA

I_IH

110

1200

µA

I_CC

mA

mW

I_CCI

Supply current VCCI

V_CCI= 1.95 V

330

I_OFFSET

I_BIAS

I_RESET

Supply current VOFFSET ⁽²⁾

Supply current VBIAS ^{(2) (3)}

Supply current VRESET ⁽³⁾

Supply power dissipation Total

V_OFFSET= 10.5 V

13.2

V_BIAS= 18.5 V

-3.641

9.02

V_RESET= –14.5 V

3320.25

(1) Applies to LVCMOS pins only. Excludes LVDS pins and test pad pins.

(2) To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than the specified limit in 节6.4.

(3) To prevent excess current, the supply voltage delta |VBIAS –VRESET| must be less than specified limit in 节6.4.

6.7 Capacitance at Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

C_{I_lvds}

C_{I_nonlvds}

C_{I_tdiode}

C_O

LVDS Input Capacitance 2xLVDS

Non-LVDS Input capacitance 2xLVDS

Temp Diode Input capacitance 2xLVDS

Output Capacitance

20

30

20

pF

ƒ= 1 MHz

18

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6.8 Timing Requirements

MIN

NOM

MAX UNIT

SCP⁽¹⁾

t_r

Rise time

Fall time

20% to 80% reference points

80% to 20% reference points

30

ns

t_f

LVDS⁽²⁾

t_r

Rise slew rate

Fall slew rate

Clock Cycle

Pulse Width

Setup Time

Hold Time

20% to 80% reference points

80% to 20% reference points

DCLK_A, LVDS pair

0.7

1

V/ns

ns

t_f

t_C

2.5

t_C

DCLK_B, LVDS pair

2.5

t_C

DCLK_C,LVDS pair

2.5

t_C

DCLK_D, LVDS pair

2.5

t_W

DCLK_A LVDS pair

1.19

1.25

t_W

DCLK_B LVDS pair

1.19

t_W

DCLK_C LVDS pair

1.19

t_W

DCLK_D LVDS pair

1.19

t_Su

t_h

D_A(15:0) before DCLK_A, LVDS pair

D_B(15:0) before DCLK_B, LVDS pair

D_C(15:0) before DCLK_C, LVDS pair

D_D(15:0) before DCLK_D, LVDS pair

SCTRL_A before DCLK_A, LVDS pair

SCTRL_B before DCLK_B, LVDS pair

SCTRL_C before DCLK_C, LVDS pair

SCTRL_D before DCLK_D, LVDS pair

D_A(15:0) after DCLK_A, LVDS pair

D_B(15:0) after DCLK_B, LVDS pair

D_C(15:0) after DCLK_C, LVDS pair

D_D(15:0) after DCLK_D, LVDS pair

SCTRL_A after DCLK_A, LVDS pair

SCTRL_B after DCLK_B, LVDS pair

SCTRL_C after DCLK_C, LVDS pair

SCTRL_D after DCLK_D, LVDS pair

0.325

0.145

t_h

Hold Time

t_h

Hold Time

t_h

Hold Time

t_h

Hold Time

t_h

Hold Time

t_h

Hold Time

t_h

Hold Time

LVDS⁽²⁾

t_SKEW

Skew Time

Channel B relative to Channel A^{(3) (4)}, LVDS pair

Channel D relative to Channel C^{(5) (6)}, LVDS pair

+1.25

ns

–1.25

(1) See 图6-3 for Rise Time and Fall Time for SCP.

(2) See 图6-5 for Timing Requirements for LVDS.

(3) Channel A (Bus A) includes the following LVDS pairs: DCLK_AN and DCLK_AP, SCTRL_AN and SCTRL_AP, D_AN(15:0) and

D_AP(15:0).

(4) Channel B (Bus B) includes the following LVDS pairs: DCLK_BN and DCLK_BP, SCTRL_BN and SCTRL_BP, D_BN(15:0) and

D_BP(15:0).

(5) Channel C (Bus C) includes the following LVDS pairs: DCLK_CN and DCLK_CP, SCTRL_CN and SCTRL_CP, D_CN(15:0) and

D_CP(15:0).

(6) Channel D (Bus D) includes the following LVDS pairs: DCLK_DN and DCLK_DP, SCTRL_DN and SCTRL_DP, D_DN(15:0) and

D_DP(15:0).

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f_SCPCLK= 1 / t_C

t_{SCP_NEG_ENZ}

t_{SCP_POS_ENZ}

Falling Edge Capture for SCPDI

Rising Edge Launch for SCPDO

t_C

50%

SCPENZ

t_{SCP_DS}

t_{SCP_DH}

50%

SCPCLK

50%

SCPDI

50%

DI

SCPDO

50%

DO

t_{SCP_PD}

图6-2. SCP Timing Requirements

See 节6.4 for f_SCPCLK, t_{SCP_DS}, t_{SCP_DH}, and t_{SCP_PD}specifications.

SCPCLK, SCPDI,

SCPDO, SCPENZ

100%

80%

20%

0%

t_f

t_r

Time

图6-3. SCP Requirements for Rise and Fall

See 节6.8 for t_rand t_fspecifications and conditions.

Device pin

output under test

Tester channel

C_LOAD

图6-4. Test Load Circuit for Output Propagation Measurement

For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account.

System designers use IBIS or other simulation tools to correlate the timing reference load to a system

environment.

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t

f

V

ID

CM

t

r

图6-5. LVDS Waveform Requirements

A. See 方程式1 and 方程式2.

1

V_{LVDS max}= V

:

_;+ , × V

,

;

ID max

;

:

CM max

:

2

(1)

(2)

1

V_{LVDS min}= V

:

_;F , × V

,

;

ID max

;

:

CM min

:

2

See 节6.4 for V_CM, V_ID, and V_LVDSspecifications and conditions.

t

C .

t

W .

DCLK_P

DCLK_N

50%

t

H.

t

SU.

D_P(0:?)

D_N(0:?)

50%

H.

SU.

SCTRL_P

SCTRL_N

t

C .

t

SKEW.

t

W .

DCLK_P

DCLK_N

50%

t

H.

t

SU.

D_P(0:?)

D_N(0:?)

50%

H.

SU.

SCTRL_P

SCTRL_N

50%

图6-6. Timing Requirements

See 节6.8 for timing requirements and LVDS pairs per channel (bus) defining D_P(0:?) and D_N(0:?).

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6.9 System Mounting Interface Loads

表6-1. System Mounting Interface Loads

PARAMETER

MIN

NOM

MAX

11.3

0

UNIT

kg

Thermal interface area

Electrical interface area

Thermal interface area

Electrical interface area

Condition 1: Maximum load of 22.6 kg evenly

distributed within each area below: ⁽¹⁾

kg

Condition 2: Maximum load of 22.6 kg evenly

distributed within each area below: ⁽¹⁾

22.6

kg

(1) See 图6-7.

Electrical Interface Area

Thermal Interface Area

图6-7. System Mounting Interface Loads

6.10 Micromirror Array Physical Characteristics

表6-2. Micromirror Array Physical Characteristics

PARAMETER DESCRIPTION

Number of active columns ⁽¹⁾

VALUE

2716

1528

5.4

UNIT

M

N

P

micromirrors

µm

Number of active rows ⁽¹⁾

Micromirror (pixel) pitch ⁽¹⁾

Micromirror Pitch × number

of active columns

Micromirror active array width ⁽¹⁾

Micromirror active array height ⁽¹⁾

14.67

8.25

mm

Micromirror Pitch × number

of active rows

Micromirror active border (Top / Bottom) ⁽²⁾

Micromirror active border (Right / Left) ⁽²⁾

Pond of micromirrors (POM)

56

20

micromirrors / side

(1) See 图6-8.

(2) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the “Pond

Of Mirrors”(POM). These micromirrors are prevented from tilting toward the bright or “on”state but still require an electrical bias to

tilt toward “off.”

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Off-State

Light Path

0

1

2

3

Active Micromirror Array

M x N Micromirrors

N x P

Nœ 4

Nœ 3

Nœ 2

Nœ 1

M x P

P

Incident

Illumination

Light Path

P

Pond Of Micromirrors (POM) omitted for clarity.

Details omitted for clarity.

Not to scale.

P

图6-8. Micromirror Array Physical Characteristics

Refer to section 节6.10 table for M, N, and P specifications.

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6.11 Micromirror Array Optical Characteristics

表6-3. Micromirror Array Optical Characteristics

PARAMETER

MIN

NOM

MAX

18.4

0

UNIT

Mirror Tilt angle, variation device to device ^{(1) (2)}

15.6

17.0

degrees

Adjacent micromirrors

Non-Adjacent micromirrors

Number of out-of-specification

micromirrors ⁽³⁾

micromirrors

%

10

68

DMD Efficiency (420 nm –680 nm)

(1) Limits on variability of micromirror tilt angle are critical in the design of the accompanying optical system. Variations in tilt angle within a

device may result in apparent nonuniformities, such as line pairing and image mottling, across the projected image. Variations in the

average tilt angle between devices may result in colorimetric and system contrast variations.

(2) See 图6-9.

(3) An out-of-specification micromirror is defined as a micromirror that is unable to transition between the two landed states within the

specified Micromirror Switching Time.

Border micromirrors omitted for clarity

Off State

Light Path

Details omitted for clarity.

Not to scale.

0

1

2

3

Tilted Axis of

Pixel Rotation

Off-State

Landed Edge

On-State

Landed Edge

Nœ 4

Nœ 3

Nœ 2

Nœ 1

Incident

Illumination

Light Path

图6-9. Micromirror Landed Orientation and Tilt

Refer to section 节6.10 table for M, N, and P specifications.

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6.12 Window Characteristics

表6-4. DMD Window Characteristics

PARAMETER

MIN

NOM

MAX

UNIT

Corning Eagle

XG

Window Material Designation S610

Window Refractive Index at 546.1 nm

1.5119

Window Transmittance, minimum within the wavelength range 420–680 nm.

Applies to all angles 0–30° AOI. ^{(1) (2)}

97%

Window Transmittance, average over the wavelength range 420–680 nm.

Applies to all angles 30–45° AOI. ^{(1) (2)}

(1) Single-pass through both surfaces and glass.

(2) AOI –angle of incidence is the angle between an incident ray and the normal to a reflecting or refracting surface.

6.13 Chipset Component Usage Specification

Reliable function and operation of the DLP660TE DMD requires that it be used in conjunction with the other

components of the applicable DLP chipset, including those components that contain or implement TI DMD

control technology. TI DMD control technology is the TI technology and devices for operating or controlling a

DLP DMD.

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7 Detailed Description

7.1 Overview

The DMD is a 0.66-inch diagonal spatial light modulator which consists of an array of highly reflective aluminum

micromirrors. The DMD is an electrical input, optical output micro-electrical-mechanical system (MEMS). The

electrical interface is Low Voltage Differential Signaling (LVDS). The DMD consists of a two-dimensional array of

1-bit CMOS memory cells. The array is organized in a grid of M memory cell columns by N memory cell rows.

Refer to the 节7.2. The positive or negative deflection angle of the micromirrors can be individually controlled by

changing the address voltage of underlying CMOS addressing circuitry and micromirror reset signals (MBRST).

The DLP660TE DMD is part of the chipset comprising of the DLP660TE DMD, the DLPC4420 display controller

and the DLPA100 power and motor driver. To ensure reliable operation, the DLP660TE DMD must always be

used with the DLPC4420 display controller and the DLPA100 power and motor driver.

7.2 Functional Block Diagram

Not to Scale. Details Omitted for Clarity. See Accompanying Notes in this Section.

Channel A

Interface

Control

Column Read & Write

Control

(0,0)

Voltages

Word Lines

Voltage

Generators

Row

Micromirror Array

(M-1, N-1)

Control

Column Read & Write

Control

Channel B

Interface

For pin details on Channels A, B, C, and D, refer to Pin Configurations and Functions 节5 and LVDS Interface section of 节6.8.

RESET_CTRL is utilized in applications when an external reset signal is required.

图7-1. Functional Block Diagram

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7.3 Feature Description

7.3.1 Power Interface

The DMD requires 5 DC voltages: DMD_P3P3V, DMD_P1P8V, VOFFSET, VRESET, and VBIAS. DMD_P3P3V

is created by the DLPA100 power and motor driver and is used on the DMD board to create the other 4 DMD

voltages, as well as powering various peripherals (TMP411, I2C, and TI level translators). DMD_P1P8V is

created by the TI PMIC LP38513S and provides the VCC voltage required by the DMD. VOFFSET (10V),

VRESET (-14V), and VBIAS(18V) are made by the TI PMIC TPS65145 and are supplied to the DMD to control

the micromirrors.

7.3.2 Timing

The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. 图 6-4 shows an equivalent test load circuit for the output

under test. Timing reference loads are not intended as a precise representation of any particular system

environment or depiction of the actual load presented by a production test. System designers use IBIS or other

simulation tools to correlate the timing reference load to a system environment. The load capacitance value

stated is only for characterization and measurement of AC timing signals. This load capacitance value does not

indicate the maximum load the device is capable of driving.

7.4 Device Functional Modes

DMD functional modes are controlled by the DLPC4420 display controller. See the DLPC4420 display controller

data sheet or contact a TI applications engineer.

7.5 Optical Interface and System Image Quality Considerations

7.5.1 Optical Interface and System Image Quality

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment

optical performance involves making trade-offs between numerous component and system design parameters.

Optimizing system optical performance and image quality strongly relate to optical system design parameter

trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical

performance is contingent on compliance to the optical system operating conditions described in the following

sections.

7.5.1.1 Numerical Aperture and Stray Light Control

The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area are

the same. This angle cannot exceed the nominal device micromirror tilt angle unless appropriate apertures are

added in the illumination or projection pupils to block out flat-state and stray light from the projection lens. The

micromirror tilt angle defines DMD capability to separate the "ON" optical path from any other light path,

including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other

system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the

micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger than the

illumination numerical aperture angle, objectionable artifacts in the display’s border and active area can occur.

7.5.1.2 Pupil Match

TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally

centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable

artifacts in the display’s border and active area, which may require additional system apertures to control,

especially if the numerical aperture of the system exceeds the pixel tilt angle.

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7.5.1.3 Illumination Overfill

The active area of the device is surrounded by an aperture on the inside DMD window surface that masks

structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating

conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window

aperture opening and other surface anomalies that may be visible on the screen. Design he illumination optical

system to limit light flux incident anywhere on the window aperture from exceeding approximately 10% of the

average flux level in the active area. Depending on the particular system’s optical architecture, overfill light may

have to be further reduced below the suggested 10% level in order to be acceptable.

7.6 Micromirror Array Temperature Calculation

Array

TP2

2X 17.0

TP4

TP5

2X 18.7

Window Edge

TP3

TP3 (TP2)

(4 surfaces)

TP5

TP4

TP1

8.6

17.5

TP1

图7-2. DMD Thermal Test Points

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Micromirror array temperature can be computed analytically from measurement points on the outside of the

package, the package thermal resistance, the electrical power, and the illumination heat load. The relationship

between micromirror array temperature and the reference ceramic temperature is provided by the following

equations:

T_ARRAY= T_CERAMIC+ (Q_ARRAY× R_{ARRAY-TO-CERAMIC}

)

Q_ARRAY= Q_ELECTRICAL+ Q_ILLUMINATION

where

• T_ARRAY= computed array temperature (°C)

• T_CERAMIC= measured ceramic temperature (°C) (TP1 location)

• R_{ARRAY-TO-CERAMIC}= thermal resistance of package from array to ceramic TP1 (°C/Watt)

• Q_ARRAY= Total DMD power on the array (Watts) (electrical + absorbed)

• Q_ELECTRICAL= nominal electrical power

• Q_ILLUMINATION= (C_L2W× SL)

• C_L2W= Conversion constant for screen lumens to power on DMD (Watts/Lumen)

• SL = measured screen lumens

The electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating

frequencies. A nominal electrical power dissipation to use when calculating array temperature is 3.0 Watts. The

absorbed power from the illumination source is variable and depends on the operating state of the micromirrors

and the intensity of the light source. The equations shown above are valid for a 1-Chip DMD system with

projection efficiency from the DMD to the screen of 87%.

The conversion constant C_L2Wis based on array characteristics. It assumes a spectral efficiency of 300 lumens/

Watt for the projected light and illumination distribution of 83.7% on the active array, and 16.3% on the array

border.

Sample calculations for typical projection application:

Q_ELECTRICAL= 3.0 W

C_L2W= 0.00266

SL = 5000 lm

T_CERAMIC= 55.0°C

Q_ARRAY= 3.0 W + (0.00266 × 5000 lm) = 16.3 W

T_ARRAY= 55.0°C + (16.3 W × 0.60°C/W) = 64.78°C

7.7 Micromirror Landed-On/Landed-Off Duty Cycle

7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle

The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a

percentage) that an individual micromirror is landed in the On state versus the amount of time the same

micromirror is landed in the Off state.

As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On state 100% of the

time (and in the Off state 0% of the time); whereas 0/100 indicates that the pixel is in the Off state 100% of the

time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.

Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other

state (OFF or ON) is considered negligible and is thus ignored.

Since a micromirror can only be landed in one state or the other (On or Off), the two numbers (percentages)

always add to 100.

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7.7.2 Landed Duty Cycle and Useful Life of the DMD

Knowing the long-term average landed duty cycle (of the end product or application) is important because

subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric

landed duty cycle for a prolonged period of time can reduce the DMD’s usable life.

Note that it is the symmetry or asymmetry of the landed duty cycle that is of relevance. The symmetry of the

landed duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a

landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly

asymmetrical.

7.7.3 Landed Duty Cycle and Operational DMD Temperature

Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this

interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s

usable life. This is quantified in the de-rating curve shown in 图6-1. The importance of this curve is that:

• All points along this curve represent the same usable life.

• All points above this curve represent lower usable life (and the further away from the curve, the lower the

usable life).

• All points below this curve represent higher usable life (and the further away from the curve, the higher the

usable life).

In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD ideally will be operated

at for a given long-term average Landed Duty Cycle.

7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application

During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being

displayed by that pixel.

For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel

will experience a 100/0 Landed Duty Cycle during that time period. Likewise, when displaying pure-black, the

pixel will experience a 0/100 Landed Duty Cycle.

Between the two extremes (ignoring for the moment color and any image processing that may be applied to an

incoming image), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in 表7-1.

表7-1. Grayscale Value and Landed Duty Cycle

Grayscale Value

Landed Duty Cycle

0%

0/100

10%

10/90

20%

20/80

30%

30/70

40%

40/60

50%

50/50

60%

60/40

70%

70/30

80%

80/20

90%

90/10

100%

100/0

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Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from

0% to 100%) for each constituent primary color (red, green, and blue) for the given pixel as well as the color

cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a

given primary must be displayed in order to achieve the desired white point.

During a given period of time, the landed duty cycle of a given pixel can be calculated as follows:

Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_%

×

Blue_Scale_Value)

where

• Red_Cycle_% represents the percentage of the frame time that Red displays to achieve the desired white

point.

• Green_Cycle_% represents the percentage of the frame time that Green displays to achieve the desired

white point.

• Blue_Cycle_% represents the percentage of the frame time that Blue displays to achieve the desired white

point.

For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in

order to achieve the desired white point), then the Landed Duty Cycle for various combinations of red, green,

blue color intensities will be as shown in 表7-2 and 表7-3.

表7-2. Example Landed Duty Cycle for Full-Color, Color Percentage

Red Cycle Percentage

Green Cycle Percentage

Blue Cycle Percentage

50%

20%

30%

表7-3. Example Landed Duty Cycle for Full-Color

Red Scale Value

Green Scale Value

Blue Scale Value

Landed Duty Cycle

0/100

0%

100%

0%

50/50

100%

0%

20/80

0%

100%

0%

30/70

12%

0%

6/94

35%

0%

7/93

0%

60%

0%

18/82

100%

0%

100%

0%

70/30

100%

0%

50/50

100%

12%

0%

80/20

35%

0%

13/87

60%

100%

25/75

12%

100%

24/76

100%

100/0

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

Texas Instruments DLP technology is a micro-electro-mechanical systems (MEMS) technology that modulates

light using a digital micromirror device (DMD). DMDs vary in resolution and size and can contain over 8-million

micromirrors. Each micromirror of a DMD can represent either one or more pixels on the display and is

independently controlled, synchronized with color sequential illumination, to create stunning images on any

surface. DLP technology enables a wide variety of display products worldwide, from tiny projection modules

embedded in smartphones to high powered digital cinema projectors, and emerging display products such as

digital signage and laser TV.

The most recent class of chipsets from Texas Instruments is based on a breakthrough micromirror technology,

called TRP. With a smaller pixel pitch of 5.4 μm and increased tilt angle of 17 degrees, TRP chipsets enable

higher resolution in a smaller form factor and enhanced image processing features while maintaining high optical

efficiency. DLP chipsets are a great fit for any system that requires high resolution and high brightness displays.

The following orderables have been replaced by the DLP660TE.

Device Information⁽¹⁾

PART NUMBER

2715-7132P

PACKAGE

BODY SIZE (NOM)

MECHANICAL ICD

2514366

FYG (350)

35 mm × 32 mm

2514366

2715-7137P

2715-7139P

2715-713AP

FYG (350)

8.2 Typical Application

The DLP660TE DMD is the first full 4K UHD DLP digital micromirror device. When combined with two display

controllers (DLPC4420), an FPGA, a power management device (DLPA100), and other electrical, optical and

mechanical components the chipset enables bright, affordable, full 4K UHD display solutions. 图 8-1 shows a

typical 4K UHD system application using the DLP660TE DMD.

1.1V

FPGA

Voltage

Regulators

1.15V

1.8V

2.5V

3.3V

12V

PWM Driver

Flash

EPROM

I²

1.1V

1.8V

3.3V

(23) (16)

DLPA100

Controller

PMIC

C

ADDR

DATA

12V

RGB_EN

CTRL

(3)

RGB_PWM

(3)

FE CTRL

Flash

DDR3

USB CTRL

DATA

GPIO

3.3 V

CTRL

DDR3

DLPC4420

Controller

Primary

V^BIAS,V^OFFSET,V^RESET

(3)

ADDR

DMD PMIC

(Power Management IC)

DATA

Front End Device

3D

L/R

SCP CTRL

2xLVDS

I²

C

SPI

HBT

Vx1:

XPR FPGA

4K UHD DMD

Vx1

3840 × 2160 @ 60Hz

2xLVDS

I²

DATA

C

1.8 V

GPIO

DLPC4420

Controller

Secondary

SPI

Flash

JTAG

ACTUATOR CTRL

Actuator

Driver

4-Position

Actuator

CTRL

1.1V

1.8V

3.3V

DLPA100

Controller

PMIC

ADDR

(23) (16)

DATA

I²

C

12V

TI DLP chipset

Flash

EPROM

Third party component

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1.1V

1.15V

1.8V

2.5V

3.3V

12V

1.21V

1.8V

3.3V

1.21V

1.8V

3.3V

FPGA

Voltage

Regulators

DLPA100

Controller PMIC

CW Driver

DLPA100

Controller PMIC

CW Driver

12V

Flash

EPROM

I²C

5V

(23) (16)

ADDR

DATA

CTRL

GPIO

Wheel Motor #2

Wheel Motor #1

CTRL

FE CTRL

Flash

DDR3

Flash

USB CTRL

DATA

DDR3

DLPC4420

Controller

Primary

V^BIAS,V^OFFSET,V^RESET

(3)

3.3 V

ADDR

1.1V

DMD PMIC

(Power Management IC)

CTRL

1.8V

3.3V

DATA

Front End Device

3D

L/R

SCP CTRL

2xLVDS

I²C

SPI

HBT

Vx1:

4K UHD DMD

XPR FPGA

Vx1

3840 × 2160 @ 60Hz

2xLVDS

I²C

1.8 V

DATA

GPIO

DLPC4420

Controller

Secondary

SPI

Flash

JTAG

ACTUATOR CTRL

Actuator

Driver

4-Position

Actuator

1.1V

1.8V

3.3V

ADDR

DATA

I²C

(23) (16)

TI DLP chipset

Flash

EPROM

Third party component

图8-1. Typical DLPC4420 4K UHD Application (LED, Top; LPCW, Bottom)

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8.2.1 Design Requirements

At the high level, DLP660TE DMD systems will include an illumination source, a light engine, electronic

components, and software. The designer must first choose an illumination source and design the optical engine

taking into consideration the relationship between the optics and the illumination source. The designer must then

understand the electronic components of a DLP660TE DMD system, which is made up of a DMD board and

formatter board. The DMD board channels image data to and powers the DMD chip. The formatter board

supports the rest of the electronic components, which can include an FPGA, the DLPC4420 display controller,

power supplies, and drivers for illumination sources, color wheels, fans, and dynamic optical components.

8.2.2 Detailed Design Procedure

For connecting together the DLPC4420 display controller and the DLP660TE DMD, see the reference design

schematic. Layout guidelines need be followed to achieve a reliable projector. To complete the DLP system an

optical module or light engine is required that contains the DLP660TE DMD, associated illumination sources,

optical elements, and necessary mechanical components.

8.2.3 Application Curves

图8-2. Luminance vs. Current

8.3 DMD Die Temperature Sensing

The DMD features a built-in thermal diode that measures the temperature at one corner of the die outside the

micromirror array. The thermal diode can be interfaced with the TMP411 temperature sensor as shown in 图8-3.

The serial bus from the TMP411 can be connected to the DLPC4420 display controller to enable its temperature

sensing features. See the DLPC4420 Programmers’ Guide for instructions on installing the DLPC4420

controller support firmware bundle and obtaining the temperature readings.

The software application contains functions to configure the TMP411 to read the DMD temperature sensor diode.

This data can be leveraged to incorporate additional functionality in the overall system design such as adjusting

illumination, fan speeds, and so forth. All communication between the TMP411 and the DLPC4420 controller will

be completed using the I²C interface. The TMP411 connects to the DMD via pins E16 and E17 as outlined in 节

5.

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3.3V

R1

R2

TMP411

DLP660TE

SCL

VCC

D+

R3

R5

TEMP_P

SDA

ALERT

THERM

GND

C1

R4

R6

D-

TEMP_N

GND

A. Details omitted for clarity, see the TI Reference Design for connections to the DLPC4420 controller.

B. See the TMP411 data sheet for system board layout recommendation.

C. See the TMP411 data sheet and the TI reference design for suggested component values for R1, R2, R3, R4, and C1.

D. R5 = 0 Ω. R6 = 0 Ω. Zero ohm resistors need to be located close to the DMD package pins.

图8-3. TMP411 Sample Schematic

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9 Power Supply Recommendations

The following power supplies are all required to operate the DMD:

• VSS

• VCC

• VCCI

• VBIAS

• VOFFSET

• VRESET

DMD power-up and power-down sequencing is strictly controlled by the DLP display controller.

CAUTION

For reliable operation of the DMD, the following power supply sequencing requirements must be

followed. Failure to adhere to any of the prescribed power-up and power-down requirements may

affect device reliability. See 图9-1 DMD Power Supply Sequencing Requirements.

VBIAS, VCC, VCCI, VOFFSET, and VRESET power supplies must be coordinated during power-up

and power-down operations. Failure to meet any of the below requirements will result in a significant

reduction in the DMD’s reliability and lifetime. Common ground VSS must also be connected.

9.1 DMD Power Supply Power-Up Procedure

• During power-up, VCC and VCCI must always start and settle before VOFFSET plus Delay1 specified in 表

9-1, VBIAS, and VRESET voltages are applied to the DMD.

• During power-up, it is a strict requirement that the voltage delta between VBIAS and VOFFSET must be

within the specified limit shown in 节6.4.

• During power-up, there is no requirement for the relative timing of VRESET with respect to VBIAS.

• Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the

requirements specified in 节6.1, in 节6.4, and in 图9-1.

• During power-up, LVCMOS input pins must not be driven high until after VCC and VCCI have settled at

operating voltages listed in 节6.4.

9.2 DMD Power Supply Power-Down Procedure

• During power-down, VCC and VCCI must be supplied until after VBIAS, VRESET, and VOFFSET are

discharged to within the specified limit of ground. See 表9-1.

• During power-down, it is a strict requirement that the voltage delta between VBIAS and VOFFSET must be

within the specified limit shown in 节6.4.

• During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS.

• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the

requirements specified in 节6.1, in 节6.4, and in 图9-1.

• During power-down, LVCMOS input pins must be less than specified in 节6.4.

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图9-1. DMD Power Supply Requirements

1. See 节6.4, 节5

2. To prevent excess current, the supply voltage delta |VCCI –VCC| must be less than specified limit in 节6.4.

3. To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than specified in 节

6.4.

4. To prevent excess current, the supply voltage delta |VBIAS –VRESET| must be less than specified limit in

节6.4.

5. VBIAS must power up after VOFFSET has powered up, per the Delay1 specification in 表9-1.

6. PG_OFFSET must turn off after EN_OFFSET has turned off, per the Delay2 specification in 表9-1.

7. DLP controller software enables the DMD power supplies to turn on after RESET_OEZ is at logic high.

8. DLP controller software initiates the global VBIAS command.

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9. After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware

power-down that activates PWRDNZ and disables VBIAS, VRESET and VOFFSET.

10. Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the

DLP controller hardware, EN_OFFSET may turn off after PG_OFFSET has turned off. The OEZ signal may

go high prior to PG_OFFSET turning off to indicate the DMD micromirror has completed the emergency park

procedures.

表9-1. DMD Power-Supply Requirements

Parameter

Delay1

Description

Min

NOM

Max

Unit

ms

ns

Delay from VOFFSET settled at recommended operating voltage to

VBIAS and VRESET power up

1

2

Delay2

PG_OFFSET hold time after EN_OFFSET goes low

100

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10 Layout

10.1 Layout Guidelines

The DLP660TE DMD is part of a chipset that is controlled by the DLPC4420 display controller in conjunction with

the DLPA100 power and motor driver. These guidelines help to design a PCB board with the DLP660TE DMD.

The DLP660TE DMD board is a high-speed multilayer PCB, with primarily high-speed digital logic using dual-

edge clock rates up to 400 MHz for DMD LVDS signals. The remaining traces are comprised of low speed digital

LVTTL signals. TI recommends that mini power planes are used for VOFFSET, VRESET, and VBIAS. Solid

planes are required for DMD_P3P3V(3.3 V), DMD_P1P8V, and Ground. The target impedance for the PCB is 50

Ω ±10% with the LVDS traces being 100-Ω ±10% differential. TI recommends using an 8-layer stack-up as

described in 表10-1.

10.2 Layout Example

10.2.1 Layers

The layer stack-up and copper weight for each layer is shown in 表10-1. Small sub-planes are allowed on signal

routing layers to connect components to major sub-planes on top or bottom layers if necessary.

表10-1. Layer Stack-Up

LAYER

NO.

LAYER NAME

Side A - DMD only

COPPER WT. (oz.)

COMMENTS

1

1.5

1

DMD, escapes, low frequency signals, power sub-planes.

Solid ground plane (net GND).

2

Ground

3

Signal

0.5

1

50 Ωand 100 Ωdifferential signals

4

Ground

Solid ground plane (net GND)

5

DMD_P3P3V

1

+3.3-V power plane (net DMD_P3P3V)

50 Ωand 100 Ωdifferential signals

6

Signal

0.5

1

7

Ground

Solid ground plane (net GND).

8

Side B - All other Components

1.5

Discrete components, low frequency signals, power sub-planes

10.2.2 Impedance Requirements

TI recommends that the board has matched impedance of 50 Ω ±10% for all signals. The exceptions are listed

in 表10-2.

表10-2. Special Impedance Requirements

Signal Type

Signal Name

Impedance (ohms)

D_AP(0:15), D_AN(0:15)

DCLKA_P, DCLKA_N

SCTRL_AP, SCTRL_AN

D_BP(0:15), D_BN(0:15)

DCLKB_P, DCLKB_N

SCTRL_BP, SCTRL_BN

D_CP(0:15), D_CN(0:15)

DCLKC_P, DCLKC_N

SCTRL_CP, SCTRL_CN

D_DP(0:15), D_DN(0:15)

DCLKD_P, DCLKD_N

SCTRL_DP, SCTRL_DN

100 ±10% differential across

each pair

A channel LVDS differential pairs

100 ±10% differential across

each pair

B channel LVDS differential pairs

C channel LVDS differential pairs

D channel LVDS differential pairs

100 ±10% differential across

each pair

100 ±10% differential across

each pair

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10.2.3 Trace Width, Spacing

Unless otherwise specified, TI recommends that all signals follow the 0.005-inch/0.005-inch design rule.

Minimum trace clearance from the ground ring around the PWB has a 0.1-inch minimum. An analysis of

impedance and stack-up requirements determine the actual trace widths and clearances.

10.2.3.1 Voltage Signals

表10-3. Special Trace Widths, Spacing Requirements

MINIMUM TRACE WIDTH TO

SIGNAL NAME

GND

LAYOUT REQUIREMENT

Maximize trace width to connecting pin

PINS (MIL)

15

DMD_P3P3V

DMD_P1P8V

VOFFSET

VRESET

Maximize trace width to connecting pin

Create mini plane from U2 to U3

VBIAS

All U3 control

connections

10

Use 10 mil etch to connect all signals/voltages to DMD pads

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11 Device and Documentation Support

11.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

11.2 Device Support

11.2.1 Device Nomenclature

DLP660TE AA FYG

Package Type

TI Internal Numbering

Device Descriptor

图11-1. Part Number Description

11.2.2 Device Markings

The device marking will include both human-readable information and a 2-dimensional matrix code. The human-

readable information is described in 图11-2. The 2-dimensional matrix code is an alpha-numeric character string

that contains the DMD part number, Part 1 of Serial Number, and Part 2 of Serial Number. The first character of

the DMD Serial Number (part 1) is the manufacturing year. The second character of the DMD Serial Number

(part 1) is the manufacturing month. The last character of the DMD Serial Number (part 2) is the bias voltage bin

letter.

Example: *2715-7032 GHXXXXX LLLLLLM

TI Internal Numbering

2-Dimension Matrix Code

(Part Number and

Serial Number)

DMD Part Number

YYYYYYY

*2715-713xP

GHXXXXX LLLLLLM

Part 1 of Serial Number

(7 characters)

Part 2 of Serial Number

(7 characters)

图11-2. DMD Marking Locations

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11.3 Documentation Support

11.3.1 Related Documentation

The following documents contain additional information related to the chipset components used with the

DLP660TE:

• DLPC4420 Display Controller

• DLPA100 Power and Motor Driver Data Sheet

11.4 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.5 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.6 Trademarks

TI E2E^™is a trademark of Texas Instruments.

DLP^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.7 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.8 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DLP660TEAAFYG
厂家：	TEXAS INSTRUMENTS
描述：	0.66-inch, 4K UHD, 2XLVDS DLP® digital micromirror device (DMD) \| FYG \| 350 \| 0 to 70
文件：	总49页 (文件大小：1849K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLP660TEAAFYG [TI]

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DLP670REA0FYE

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DLP7000

DLP7000BFLP

DLP7000UV

DLP7000UVFLP

DLP780NE

DLP780NEA0FYU

DLP780TE

DLP780TEA0FYU