DLP6500FLQ [TI]
DLP® 0.65 1080p A 型 DMD;型号: | DLP6500FLQ |
厂家: | TEXAS INSTRUMENTS |
描述: | DLP® 0.65 1080p A 型 DMD |
文件: | 总48页 (文件大小:861K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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DLP6500FLQ
ZHCSD21 –OCTOBER 2014
DLP6500FLQ 0.65 1080p MVSP A 型 DMD
1 特性
3 说明
1
•
高分辨率 1080p (1920×1080) 阵列,
微镜数超过 2 百万
高分辨率 0.65 1080p 数字微镜器件 (DMD) 是一款可
调制入射光幅度、方向和位相的空间照明调制器
(SLM),其采用气密封装,微镜数达 2 百万以上。
DLP6500FLQ 具有独特的功能和价值(包括在 405nm
波长下工作),非常适用于广泛的工业、医疗和高级成
像应用。 DLP6500FLQ 需要与 DLPC900 数字控制器
结合使用才能实现可靠功能和操作。 此专用芯片组可
在高速条件下提供全高清 (HD) 分辨率,并且能够轻松
集成到多种终端设备解决方案中。
–
–
–
–
–
0.65 英寸微镜阵列对角线
7.56µm 微镜间距
±12° 微镜倾斜角(相对于平面)
2.5µs 微镜交叉时间
设计用于边缘照明
•
设计用于宽频带可见光 (400nm – 700nm)
–
–
–
–
窗口传输 97%(单通、通过双窗面)
微镜反射率 88%
器件信息(1)
阵列衍射效率 86%
器件型号
DLP6500
封装
封装尺寸(标称值)
阵列填充因子 92%
40.6mm × 31.8mm ×
6mm
FLQ (203)
•
•
两条 16 位低压差分信令 (LVDS)、双倍数据速率
(DDR) 输入数据总线
(1) 如需了解所有可用封装,请见数据表末尾的可订购产品附录。
专用 DLPC900 控制器,支持 9500Hz(1 位二进
制)和 250Hz(8 位灰度)高速模式速率
简化图表
Red,Green,Blue PWM
•
•
•
高达 400MHz 的输入数据时钟速率
集成微镜驱动器电路
气密封装
LED
Driver
PCLK, DE
LED Strobes
HSYNC, VSYNC
24-bit RGB Data
Flash
DLPC900
FAN
2 应用
USB
I2C
•
工业
–
–
–
–
针对机器视觉和质量控制的 3D 扫描仪
DMD CTL, DATA
SCP
OSC
3D 打印
DLP6500FLQ
直接成像平版印刷术
激光打标和修复
Voltage
Supplies
•
•
医疗
–
–
–
眼科
针对四肢和皮肤测量的 3D 扫描仪
高光谱成像
显示屏
–
–
3D 成像显微镜
智能和自适应照明
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: DLPS040
DLP6500FLQ
ZHCSD21 –OCTOBER 2014
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 28
7.5 Window Characteristics and Optics ....................... 28
7.6 Micromirror Array Temperature Calculation............ 29
7.7 Micromirror Landed-on/Landed-Off Duty Cycle ...... 30
Application and Implementation ........................ 32
8.1 Application Information............................................ 32
8.2 Typical Application ................................................. 32
Power Supply Recommendations...................... 33
9.1 DMD Power Supply Requirements ........................ 33
9.2 DMD Power Supply Power-Up Procedure.............. 33
9.3 DMD Power Supply Power-Down Procedure ......... 33
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 9
6.1 Absolute Maximum Ratings ...................................... 9
6.2 Handling Ratings....................................................... 9
6.3 Recommended Operating Conditions..................... 10
6.4 Thermal Information................................................ 12
6.5 Electrical Characteristics......................................... 13
6.6 Timing Requirements.............................................. 14
6.7 Typical Characteristics............................................ 18
6.8 System Mounting Interface Loads .......................... 19
6.9 Micromirror Array Physical Characteristics ............ 20
6.10 Micromirror Array Optical Characteristics ............ 21
6.11 Window Characteristics......................................... 22
6.12 Chipset Component Usage Specification ............. 22
Detailed Description ............................................ 23
7.1 Overview ................................................................. 23
7.2 Functional Block Diagram ....................................... 24
7.3 Feature Description................................................. 25
8
9
10 Layout................................................................... 36
10.1 Layout Guidelines ................................................. 36
10.2 Layout Example .................................................... 36
11 器件和文档支持 ..................................................... 41
11.1 器件支持................................................................ 41
11.2 文档支持 ............................................................... 42
11.3 商标....................................................................... 42
11.4 静电放电警告......................................................... 42
11.5 术语表 ................................................................... 42
12 机械封装和可订购信息 .......................................... 42
7
4 修订历史记录
日期
修订版本
注释
2014 年 10 月
*
最初发布。
2
Copyright © 2014, Texas Instruments Incorporated
DLP6500FLQ
www.ti.com.cn
ZHCSD21 –OCTOBER 2014
5 Pin Configuration and Functions
Package Connector Terminals
(Bottom View) for FLQ (203)
Copyright © 2014, Texas Instruments Incorporated
3
DLP6500FLQ
ZHCSD21 –OCTOBER 2014
www.ti.com.cn
Pin Functions
PIN(1)
TYPE
(I/O/P)
DATA
INTERNAL
TERM(3)
TRACE
(mils)(4)
SIGNAL
DESCRIPTION
RATE(2)
NAME
DATA BUS A
D_AN(0)
D_AN(1)
D_AN(2)
D_AN(3)
D_AN(4)
D_AN(5)
D_AN(6)
D_AN(7)
D_AN(8)
D_AN(9)
D_AN(10)
D_AN(11)
D_AN(12)
D_AN(13)
D_AN(14)
D_AN(15)
D_AP(0)
D_AP(1)
D_AP(2)
D_AP(3)
D_AP(4)
D_AP(5)
D_AP(6)
D_AP(7)
D_AP(8)
D_AP(9)
D_AP(10)
D_AP(11)
D_AP(12)
D_AP(13)
D_AP(14)
D_AP(15)
DATA BUS B
D_BN(0)
D_BN(1)
D_BN(2)
D_BN(3)
D_BN(4)
D_BN(5)
D_BN(6)
D_BN(7)
NO.
B10
A13
D16
C17
B18
A17
A25
D22
C29
D28
E27
F26
G29
H28
J27
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
557.27
558.46
556.87
555.6
555.33
555.76
556.47
555.79
556.54
555.23
555.55
556.48
555.91
556.38
559.01
556.11
555.99
556.02
556.31
555.88
556.08
556.33
556.13
555.21
555.58
555.39
556.11
555.88
556.58
556.3
K26
B12
A11
D14
C15
B16
A19
A23
D20
A29
B28
C27
D26
F30
H30
J29
557.67
555.32
K28
AB10
AC13
Y16
Input
Input
Input
Input
Input
Input
Input
Input
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
552.46
556.99
545.06
555.44
556.34
547.1
AA17
AB18
AC17
AC25
Y22
557.92
544.03
(1) The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be
connected.
(2) DDR = Double Data Rate.
SDR = Single Data Rate.
Refer to the Timing Requirements for specifications and relationships.
(3) Internal term = CMOS level internal termination.
Refer to Recommended Operating Conditions for differential termination specification.
(4) Dielectric Constant for the DMD Type A ceramic package is approximately 9.6.
For the package trace lengths shown:
Propagation Speed = 11.8 / sqrt(9.6) = 3.808 in/ns.
Propagation Delay = 0.262 ns/in = 262 ps/in = 10.315 ps/mm.
4
Copyright © 2014, Texas Instruments Incorporated
DLP6500FLQ
www.ti.com.cn
ZHCSD21 –OCTOBER 2014
Pin Functions (continued)
PIN(1)
TYPE
(I/O/P)
DATA
INTERNAL
TERM(3)
TRACE
(mils)(4)
SIGNAL
DESCRIPTION
RATE(2)
NAME
D_BN(8)
NO.
AA29
Y28
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Negative
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
Differential Data, Positive
555.9
555.42
556.26
555.52
556
D_BN(9)
D_BN(10)
D_BN(11)
D_BN(12)
D_BN(13)
D_BN(14)
D_BN(15)
D_BP(0)
W27
V26
T30
R29
557.17
555.25
555.19
551.93
557.1
R27
N27
AB12
AC11
Y14
D_BP(1)
D_BP(2)
544.38
555.98
555.56
547.17
556.47
543.25
555.71
556.32
555.35
555.65
555.28
557.25
555.83
556.67
D_BP(3)
AA15
AB16
AC19
AC23
Y20
D_BP(4)
D_BP(5)
D_BP(6)
D_BP(7)
D_BP(8)
AC29
AB28
AA27
Y26
D_BP(9)
D_BP(10)
D_BP(11)
D_BP(12)
D_BP(13)
D_BP(14)
D_BP(15)
SERIAL CONTROL
SCTRL_AN
SCTRL_BN
SCTRL_AP
SCTRL_BP
CLOCKS
DCLK_AN
DCLK_BN
DCLK_AP
DCLK_BP
U29
T28
P28
P26
C21
AA21
C23
Input
Input
Input
Input
LVDS
LVDS
LVDS
LVDS
DDR
DDR
DDR
DDR
Differential Serial Control, Negative
Differential Serial Control, Negative
Differential Serial Control, Positive
Differential Serial Control, Positive
555.14
555.14
555.13
555.13
AA23
B22
AB22
B24
Input
Input
Input
Input
LVDS
LVDS
LVDS
LVDS
Differential Clock Negative
Differential Clock Negative
Differential Clock Positive
Differential Clock Positive
555.12
555.12
555.13
555.12
AB24
SERIAL COMMUNICATIONS PORT (SCP)
SCP_DO
SCP_DI
B2
F4
E3
D4
Output
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
SDR
SDR
Serial Communications Port Output
525.78
509.96
403.93
464.17
Pull-Down Serial Communications Port Data Input
Pull-Down Serial Communications Port Clock
SCP_CLK
SCP_ENZ
Pull-Down Active-low Serial Communications Port
Enable
MICROMIRROR RESET CONTROL
RESET_ADDR(0)
RESET_ADDR(1)
RESET_ADDR(2)
RESET_ADDR(3)
RESET_MODE(0)
RESET_MODE(1)
RESET_SEL(0)
C5
E5
Input
Input
Input
Input
Input
Input
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Pull-Down Reset Driver Address Select
Pull-Down Reset Driver Address Select
Pull-Down Reset Driver Address Select
Pull-Down Reset Driver Address Select
Pull-Down Reset Driver Mode Select
Pull-Down Reset Driver Mode Select
Pull-Down Reset Driver Level Select
Pull-Down Reset Driver Level Select
1088.3
979.26
900.45
658.56
1012.52
789.83
539.64
400.3
G5
AC3
D8
C11
T4
RESET_SEL(1)
U5
RESET_STROBE
V2
Pull-Down Reset Address, Mode, & Level latched on
rising-edge
446.34
Copyright © 2014, Texas Instruments Incorporated
5
DLP6500FLQ
ZHCSD21 –OCTOBER 2014
www.ti.com.cn
Pin Functions (continued)
PIN(1)
TYPE
(I/O/P)
DATA
RATE(2)
INTERNAL
TERM(3)
TRACE
(mils)(4)
SIGNAL
DESCRIPTION
NAME
NO.
ENABLES & INTERRUPTS
PWRDNZ
C3
Input
Input
LVCMOS
LVCMOS
Pull-Down Active-low Device Reset
390.76
513.87
RESET_OEZ
W1
G3
T6
Pull-Down Active-low output enable for DMD reset
driver circuits
RESETZ
Input
LVCMOS
LVCMOS
Pull-Down Active-low sets Reset circuits in known
VOFFSET state
941.63
403.34
RESET_IRQZ
Output
Active-low, output interrupt to ASIC
VOLTAGE REGULATOR MONITORING
PG_BIAS
AA11
Y10
V4
Input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Pull-Up
Pull-Up
Pull-Up
Active-low fault from external VBIAS
regulator
858.86
822.06
1186.98
167.53
961.04
566.05
PG_OFFSET
PG_RESET
EN_BIAS
Active-low fault from external VOFFSET
regulator
Input
Active-low fault from external VRESET
regulator
D12
AB8
H2
Output
Output
Output
Active-high enable for external VBIAS
regulator
EN_OFFSET
EN_RESET
Active-high enable for external VOFFSET
regulator
Active-high enable for external VRESET
regulator
LEAVE PIN UNCONNECTED
MBRST(0)
MBRST(1)
MBRST(2)
MBRST(3)
MBRST(4)
MBRST(5)
MBRST(6)
MBRST(7)
MBRST(8)
MBRST(9)
MBRST(10)
MBRST(11)
MBRST(12)
MBRST(13)
MBRST(14)
MBRST(15)
P2
AB4
AA7
N3
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Pull-Down For proper DMD operation, do not connect
Pull-Down For proper DMD operation, do not connect
Pull-Down For proper DMD operation, do not connect
Pull-Down For proper DMD operation, do not connect
Pull-Down For proper DMD operation, do not connect
Pull-Down For proper DMD operation, do not connect
Pull-Down For proper DMD operation, do not connect
Pull-Down For proper DMD operation, do not connect
Pull-Down For proper DMD operation, do not connect
Pull-Down For proper DMD operation, do not connect
Pull-Down For proper DMD operation, do not connect
Pull-Down For proper DMD operation, do not connect
Pull-Down For proper DMD operation, do not connect
Pull-Down For proper DMD operation, do not connect
Pull-Down For proper DMD operation, do not connect
Pull-Down For proper DMD operation, do not connect
1167.69
1348.04
1240.35
1030.51
870.63
M4
AB6
AA5
L3
1267.73
1391.22
1064.01
552.89
Y6
K4
992.63
L5
1063.13
641.44
AC5
Y8
428.07
J5
962.91
K6
1093.63
577.13
AC7
LEAVE PIN UNCONNECTED
RESERVED_PFE
RESERVED_TM
RESERVED_XI1
RESERVED_TP0
RESERVED_TP1
RESERVED_TP2
AA1
Input
Input
Input
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
Analog
Pull-Down For proper DMD operation, do not connect
Pull-Down For proper DMD operation, do not connect
Pull-Down For proper DMD operation, do not connect
For proper DMD operation, do not connect
1293.6
365.64
689.96
667.66
623.99
564.35
B6
D2
Y2
P6
W3
Analog
For proper DMD operation, do not connect
Analog
For proper DMD operation, do not connect
LEAVE PIN UNCONNECTED
RESERVED_BA
RESERVED_BB
RESERVED_TS
U3
C9
Output
Output
Output
LVCMOS
LVCMOS
LVCMOS
For proper DMD operation, do not connect
For proper DMD operation, do not connect
For proper DMD operation, do not connect
684.44
223.73
90.87
D10
LEAVE PIN UNCONNECTED
NO CONNECT H6
For proper DMD operation, do not connect
6
Copyright © 2014, Texas Instruments Incorporated
DLP6500FLQ
www.ti.com.cn
ZHCSD21 –OCTOBER 2014
PIN
TYPE (I/O/P)
SIGNAL
DESCRIPTION
NAME(1)
NO.
NO.
NO.
Supply voltage for positive Bias
level of Micromirror reset signal.
VBIAS
N5
R5
P4
R3
Power
Power
Analog
Analog
Supply voltage for positive Bias
level of Micromirror reset signal.
VBIAS
Supply voltage for HVCMOS logic.
Supply voltage for stepped high
voltage at Micromirror address
electrodes.
Supply voltage positive Offset level
of Micromirror reset signal.
VOFFSET
G1
J1
L1
B4
Power
Analog
VOFFSET
VRESET
VRESET
N1
A3
C7
R1
A5
Power
Power
Power
Analog
Analog
Analog
Power supply for negative reset
level of mirror reset signal
Power supply for negative reset
level of mirror reset signal
Supply voltage for LVCMOS core
logic.
VCC
VCC
A7
E1
A15
U1
C1
Power
Power
Analog
Analog
Supply voltage for normal high level
at Micromirror address electrodes.
AB2
Supply voltage for positive Offset
level of Micromirror reset signal
during Power Down sequence.
VCC
AC9
AC15
Power
Analog
VCCI
VCCI
VCCI
A21
M30
A27
Y30
D30
Power
Power
Power
Analog
Analog
Analog
Power supply for LVDS Interface
Power supply for LVDS Interface
Power supply for LVDS Interface
AC21
AC27
Device Ground. Common return for
all power.
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A1
A9
B8
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Device Ground. Common return for
all power.
B14
B30
C25
D24
F28
H26
K2
B20
C13
D6
B26
C19
D18
F2
Device Ground. Common return for
all power.
Device Ground. Common return for
all power.
Device Ground. Common return for
all power.
E29
G27
J3
Device Ground. Common return for
all power.
H4
Device Ground. Common return for
all power.
J25
L25
M2
Device Ground. Common return for
all power.
K30
L29
M26
N29
T2
Device Ground. Common return for
all power.
L27
M6
Device Ground. Common return for
all power.
M28
P30
T26
V30
Y4
Device Ground. Common return for
all power.
N25
R25
U27
W5
Device Ground. Common return for
all power.
Device Ground. Common return for
all power.
V28
W29
Device Ground. Common return for
all power.
(1) The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be
connected.
Copyright © 2014, Texas Instruments Incorporated
7
DLP6500FLQ
ZHCSD21 –OCTOBER 2014
www.ti.com.cn
PIN
TYPE (I/O/P)
SIGNAL
DESCRIPTION
NAME(1)
VSS
NO.
NO.
NO.
Device Ground. Common return for
all power.
Y12
AA3
Y18
Y24
Power
Power
Power
Power
Analog
Analog
Analog
Analog
Device Ground. Common return for
all power.
VSS
VSS
VSS
AA9
AA13
AB14
AB30
Device Ground. Common return for
all power.
AA19
AB20
AA25
AB26
Device Ground. Common return for
all power.
8
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ZHCSD21 –OCTOBER 2014
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)
(1)
SUPPLY VOLTAGES
MIN
–0.5
–0.5
–0.5
–0.5
–11
MAX
4
UNIT
V
(2)
VCC
Supply voltage for LVCMOS core logic
(2)
VCCI
Supply voltage for LVDS receivers
4
V
VOFFSET
Supply voltage for HVCMOS and micromirror electrode(2) (3)
9
V
(2)
VBIAS
Supply voltage for micromirror electrode
17
0.5
0.3
8.75
V
VRESET
Supply voltage for micromirror electrode(2)
V
(4)
| VCC – VCCI |
| VBIAS – VOFFSET |
INPUT VOLTAGES
Supply voltage delta (absolute value)
Supply voltage delta (absolute value)(5)
V
V
(2)
Input voltage for all other LVCMOS input pins
–0.5
–0.5
VCC + 0.3
VCCI + 0.3
700
V
V
Input voltage for all other LVDS input pins(2)
Input differential voltage (absolute value)(2) (6)
|VID
|
mV
mA
(7)
IID
Input differential current
7
CLOCKS
Clock frequency for LVDS interface, DCLK_A
Clock frequency for LVDS interface, DCLK_B
Clock frequency for LVDS interface, DCLK_C
Clock frequency for LVDS interface, DCLK_D
460
460
460
460
MHz
MHz
MHz
MHz
ƒclock
ENVIRONMENTAL
Case temperature: operational(8)(9)
0
70
80
°C
°C
°C
TCASE
(9)
Case temperature: non–operational
Differential temperature(8)
–40
10
Operating relative humidity ( non-condensing )
0
95%
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure above Recommended Operating Conditions for extended periods may affect device reliability.
(2) All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for
proper DMD operation. VSS must also be connected.
(3) VOFFSET supply transients must fall within specified voltages.
(4) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.
(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply
Recommendations for additional information.
(6) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.
(7) LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(8) Exposure of the DMD simultaneously to any combination of the maximum operating conditions for case temperature, differential
temperature, or illumination power density will reduce device lifetime. Refer to Handling Ratings.
(9) DMD Temperature is the worst-case of any thermal test point in Figure 15, or the active array as calculated by the Micromirror Array
Temperature Calculation.
6.2 Handling Ratings
MIN
–40
0%
MAX
80
UNIT
°C
Storage temperature range (non-operating)(1)(2)(3)
Storage humidity, non – condensing(1)(2)(3)
Tstg
95%
RH
All pins, human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(4)
V(ESD)
Electrostatic discharge
2000
V
(1) Simultaneous exposure to high storage temperature and high storage humidity may affect device reliability.
(2) As a best practice, TI recommends storing the DMD in a temperature and humidity controlled environment.
(3) Optimal, long-term performance of the DMD can be affected by ambient storage temperature and ambient storage humidity.
(4) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
SUPPLY VOLTAGES(1)(2)
VCC
Supply voltage for LVCMOS core logic
Supply voltage for LVDS receivers
3.0
3.0
3.3
3.3
3.6
3.6
V
V
VCCI
Supply voltage for HVCMOS and micromirror
electrodes(3)
VOFFSET
8.25
8.5
8.75
V
VBIAS
Supply voltage for micromirror electrodes
Mirror electrode voltage
15.5
–9.5
16
16.5
–10.5
0.3
V
V
V
V
VRESET
–10
(4)
| VCCI–VCC |
Supply voltage delta (absolute value)
(5)
| VBIAS–VOFFSET |
Supply voltage delta (absolute value)
8.75
LVCMOS PINS
VIH
High level Input voltage(6)
Low level Input voltage(6)
1.7
2.5
VCC + 0.3
V
V
VIL
–0.3
0.7
–20
15
IOH
High level output current at VOH = 2.4 V
Low level output current at VOL = 0.4 V
PWRDNZ pulse width(7)
mA
mA
ns
IOL
TPWRDNZ
10
SCP INTERFACE(5)
ƒclock
SCP clock frequency(8)
500
800
kHz
ns
Time between valid SCPDI and rising edge of
SCPCLK(9)
tSCP_SKEW
–800
Time between valid SCPDO and rising edge of
SCPCLK(9)
tSCP_DELAY
700
ns
µs
tSCP_BYTE_INTERVAL_
tSCP_NEG_ENZ
tSCP_PW_ENZ
Time between consecutive bytes
1
30
1
Time between falling edge of SCPENZ and the first
rising edge of SCPCLK
ns
SCPENZ inactive pulse width (high level)
µs
Time required for SCP output buffer to recover after
SCPENZ (from tri-state)
tSCP_OUT_EN
1.5
ns
ƒclock
SCP circuit clock oscillator frequency(10)
9.6
11.1
MHz
LVDS INTERFACE
ƒclock
Clock frequency DCLK
400
600
MHz
mV
mV
mV
| VID
VCM
|
Input differential voltage (absolute value)(11)
Common mode(11)
LVDS voltage(11)
100
0
400
1200
VLVDS
2000
10
Time required for LVDS receivers to recover from
PWRDNZ
tLVDS_RSTZ
ns
ZIN
Internal differential termination resistance
Line differential impedance (PWB/trace)
95
90
105
110
Ω
Ω
ZLINE
100
(1) Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.
(2) All voltages are referenced to common ground VSS.
(3) VOFFSET supply transients must fall within specified max voltages.
(4) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.
(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply
Recommendations for additional information.
(6) Tester Conditions for VIH and VIL:
Frequency = 60MHz. Maximum Rise Time = 2.5ns @ (20% to 80%)
Frequency = 60MHz. Maximum Fall Time = 2.5ns @ (80% to 20%)
(7) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tri-states the
SCPDO output pin.
(8) The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK.
(9) Refer to Figure 3.
(10) SCP internal oscillator is specified to operate all SCP registers. For all SCP operations, DCLK is required.
(11) Refer to Figure 4 , Figure 5 , and Figure 6.
10
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ZHCSD21 –OCTOBER 2014
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
ENVIRONMENTAL(12)
TDMD
For Illumination Source between 420 and 700 nm
DMD temperature – operational(13)(14)
10
40 to 70(14)
°C
°C
°C
TWINDOW
Window temperature – operational
Device temperature gradient – operational(15)
70
10
TGRADIENT
Thermally
Limited(16)
ILLVIS
Illumination, wavelengths between 420 and 700 nm
mW /cm2
ENVIRONMENTAL(12)
For Illumination Source between 400 and 420 nm
TDMD
DMD temperature – operational(13)(14)
20
10
30(14)
10
°C
°C
(15)
TGRADIENT
ILLVIS
ENVIRONMENTAL(12)
Device temperature gradient – operational
Illumination, wavelengths between 400 and 420 nm
For Illumination Source <420 and >700 nm
DMD temperature – operational(13)(14)
Window temperature – operational
2.5
W/cm2
TDMD
40 to 70(14)
°C
°C
°C
TWINDOW
TGRADIENT
ILLUV
70
10
Device temperature gradient – operational(15)
Illumination, wavelength < 400 nm
0.68 mW /cm2
10 mW /cm2
ILLIR
Illumination, wavelength > 700 nm
(12) Optimal, long-term performance and optical effciency of the Digital Micromirror Device (DMD) can be affected by various application
parameters, including illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage
and operating), DMD temperature, ambient humidity (storage and operating), and power on or off duty cycle. TI recommends that
application-specific effects be considered as early as possible in the design cycle.
(13) DMD Temperature is the worst-case of any thermal test point in Figure 15, or the active array as calculated by the Micromirror Array
Temperature Calculation.
(14) Per Figure 1, the maximum operational case temperature should be derated based on the micromirror landed duty cycle that the DMD
experiences in the end application. Refer to Micromirror Landed-on/Landed-Off Duty Cycle for a definition of micromirror landed duty
cycle.
(15) As measured between any two points on the exterior of the package, or as predicted between any two points inside the micromirror
array cavity. Refer to Thermal Information and Micromirror Array Temperature Calculation.
(16) Refer to Thermal Information and Micromirror Array Temperature Calculation.
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Figure 1. Max Recommended DMD Temperature – Derating Curve
6.4 Thermal Information
DLP6500FLQ
FLQ (203)
THERMAL METRIC(1)
UNIT
MIN
MAX
(1)
Active Area to Case Ceramic Thermal resistance
0.7
°C/W
(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate
heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the
Recommended Operating Conditions.
The total heat load on the DMD is largely driven by the incident light absorbed by the active area; although other contributions include
light energy absorbed by the window aperture and electrical power dissipation of the array. Optical systems should be designed to
minimize the light energy falling outside the window clear aperture since any additional thermal load in this area can significantly
degrade the reliability of the device.
12
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
DESCRIPTION
High-level output voltage
Low level output voltage
High–level input current(2)(3)
Low level input current
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
V
VOH
VOL
IIH
VCC = 3 V, IOH = –20 mA
2.4
VCC = 3.6 V, IOL = 15 mA
VCC = 3.6 V , VI = VCC
VCC = 3.6 V, VI = 0
0.4
V
250
µA
µA
µA
IIL
–250
IOZ
High–impedance output current VCC = 3.6 V
10
CURRENT
ICC
Supply current(4)
Supply current(4)
Supply current(5)
Supply current(5)
Supply current
Supply current
VCC = 3.6 V
1076
518
4
mA
mA
mA
ICCI
VCCI = 3.6 V
VOFFSET = 8.75 V
VBIAS = 16.5 V
VRESET = –10.5 V
Total Sum
IOFFSET
IBIAS
14
IRESET
ITOTAL
POWER
PCC
11
1623
VCC = 3.6 V
3874
1865
35
PCCI
VCCI = 3.6 V
VOFFSET = 8.75 V
VBIAS = 16.5 V
VRESET = –10.5 V
Total Sum
POFFSET
PBIAS
Supply power dissipation
Supply power dissipation(6)
mW
231
PRESET
PTOTAL
CAPACITANCE
CI
116
6300
Input capacitance
Output capacitance
ƒ = 1 MHz
ƒ = 1 MHz
10
10
pF
pF
CO
Reset group capacitance
MBRST(14:0)
CM
ƒ = 1 MHz; 1920 × 72 micromirrors
330
390
pF
(1) All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for
proper DMD operation. VSS must also be connected.
(2) Applies to LVCMOS input pins only. Does not apply to LVDS pins and MBRST pins.
(3) LVCMOS input pins utilize an internal 18000 Ω passive resistor for pull-up and pull-down configurations. Refer to Pin Configuration and
Functions to determine pull-up or pull-down configuration used.
(4) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.
(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.
(6) Total power on the active micromirror array is the sum of the electrical power dissipation and the absorbed power from the illumination
source. See the Micromirror Array Temperature Calculation.
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6.6 Timing Requirements
Over Recommended Operating Conditions unless otherwise noted.
DESCRIPTION(1)
MIN
TYP MAX
UNIT
SCP INTERFACE(2)
tr
Rise time
Fall time
20% to 80%
80% to 20%
200
200
ns
ns
tƒ
LVDS INTERFACE(2)
tr
Rise time
Fall time
20% to 80%
80% to 20%
100
100
400
400
ps
ps
tƒ
LVDS CLOCKS(3)
DCLK_A, 50% to 50%
DCLK_B, 50% to 50%
DCLK_A, 50% to 50%
DCLK_B, 50% to 50%
2.5
2.5
tc
Cycle time
ns
ns
1.19
1.19
1.25
1.25
Pulse
duration
tw
LVDS INTERFACE(3)
D_A(15:0) before rising or falling edge of DCLK_A
D_B(15:0) before rising or falling edge of DCLK_B
SCTRL_A before rising or falling edge of DCLK_A
SCTRL_B before rising or falling edge of DCLK_B
D_A(15:0) after rising or falling edge of DCLK_A
D_B(15:0) after rising or falling edge of DCLK_B
SCTRL_A after rising or falling edge of DCLK_A
SCTRL_B after rising or falling edge of DCLK_B
0.2
0.2
0.2
0.2
0.5
0.5
0.5
0.5
tsu
tsu
th
Setup time
Setup time
Hold time
Hold time
ns
ns
ns
ns
th
LVDS INTERFACE(4)
Channel A includes the following LVDS
pairs:
DCLK_AP and DCLK_AN
SCTRL_AP and SCTRL_AN
D_AP(15:0) and D_AN(15:0)
tskew
Skew time
Channel B relative to Channel A
–1.25
1.25
ns
Channel B includes the following LVDS
pairs:
DCLK_BP and DCLK_BN
SCTRL_BP and SCTRL_BN
D_BP(15:0) and D_BN(15:0)
(1) Refer to Pin Configuration and Functions for pin details.
(2) Refer to Figure 7
(3) Refer to Figure 8
(4) Refer to Figure 9
Timing Diagrams
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. Figure 2 shows an equivalent test load circuit for the output
under test. The load capacitance value stated is only for characterization and measurement of AC timing signals.
This load capacitance value does not indicate the maximum load the device is capable of driving.
Timing reference loads are not intended as a precise representation of any particular system environment or
depiction of the actual load presented by a production test. System designers should use IBIS or other simulation
tools to correlate the timing reference load to a system environment. Refer to the Application and Implementation
section.
Device Pin
Tester Channel
Output Under Test
CLOAD
Figure 2. Test Load Circuit
14
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ZHCSD21 –OCTOBER 2014
t
f
= 1 / t
clock c
c
SCPCLK
50%
50%
tSCP_SKEW
SCPDI
50%
tSCP_DELAY
SCPD0
50%
Not to scale.
Refer to SCP Interface section of the Recommended Operating Conditions table.
Figure 3. SCP Timing Parameters
(VIP + VIN) / 2
DCLK_P , SCTRL_P , D_P(0:?)
LVDS
Receiver
VID
VIP
DCLK_N , SCTRL_N , D_N(0:?)
VCM
VIN
Refer to the LVDS Interface section of the Recommended Operating Conditions table.
Refer to Pin Configuration and Functions for a list of LVDS pins.
Figure 4. LVDS Voltage Definitions (References)
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VLVDS max = VCM max + | 1/2 * VID max
|
VCM
VID
VLVDS min = VCM min ± | 1/2 * VID max
|
Not to scale.
Refer to the LVDS Interface section of the Recommended Operating Conditions table.
Figure 5. LVDS Voltage Parameters
DCLK_P , SCTRL_P , D_P(0:?)
ESD
Internal
Termination
LVDS
Receiver
DCLK_N , SCTRL_N , D_N(0:?)
ESD
Refer to LVDS Interface section of the Recommended Operating Conditions table
Refer to Pin Configuration and Functions for list of LVDS pins.
Figure 6. LVDS Equivalent Input Circuit
LVDS Interface
SCP Interface
1.0 * VCC
1.0 * V
ID
V
CM
0.0 * VCC
0.0 * V
ID
tr
tf
tr
tf
Not to scale.
Refer to the Timing Requirements table.
Refer to Pin Configuration and Functions for list of LVDS pins and SCP pins.
Figure 7. Rise Time and Fall Time
16
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ZHCSD21 –OCTOBER 2014
t
c
t
t
w
w
DCLK_P
DCLK_N
50%
t
t
t
t
h
h
h
h
t
t
t
t
su
su
su
su
D_P(0:?)
D_N(0:?)
50%
SCTRL_P
SCTRL_N
50%
Not to scale.
Refer to LVDS INTERFACE section in the Timing Requirements table.
Figure 8. Timing Requirement Parameter Definitions
DCLK_P
DCLK_N
50%
D_P(0:?)
D_N(0:?)
50%
SCTRL_P
SCTRL_N
50%
t
skew
DCLK_P
DCLK_N
50%
D_P(0:?)
D_N(0:?)
50%
50%
SCTRL_P
SCTRL_N
Not to scale.
Refer to LVDS INTERFACE in the Timing Requirements table.
Figure 9. LVDS Interface Channel Skew Definition
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6.7 Typical Characteristics
The DLP6500 DMD is controlled by the DLPC900 controller. The controller has two modes of operation. The first is Video
mode where the video source is displayed on the DMD. The second is Pattern mode, where the patterns are pre-stored in
flash memory and then streamed to the DMD. The allowed DMD pattern rate depends on which mode and bit-depth is
selected.
Table 1. Bit Depth versus Pattern Rate
BIT DEPTH
VIDEO MODE RATE (Hz)
PATTERN MODE RATE (Hz)
1
2
3
4
5
6
7
8
2880
1440
960
720
480
480
360
247
9523
3289
2638
1364
823
672
500
247
18
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6.8 System Mounting Interface Loads
PARAMETER
MIN NOM MAX UNIT
Maximum system mounting interface
load to be applied to the:
Thermal Interface area
(See Figure 10)
25
95
90
lbs
lbs
lbs
Electrical Interface area
Datum “A” Interface area(1)
Thermal Interface Area
Electrical Interface Area
(all area except thermal area)
Other Areas
Datum ‘A’ Area
Figure 10. System Mounting Interface Loads
(1) Combined loads of the thermal and electrical interface areas in excess of Datum “A” load shall be evenly distributed outside the Datum
“A” area (95 + 25 – Datum “A).
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6.9 Micromirror Array Physical Characteristics
VALUE
1920
UNIT
micromirrors
micromirrors
µm
M
N
P
Number of active columns
Number of active rows
See Figure 11
1080
Micromirror (pixel) pitch
7.56
Micromirror active array width
Micromirror active array height
Micromirror active border
M × P
14.5152
8.1648
mm
N × P
mm
Pond of micromirror (POM)(1)
14 micromirrors /side
(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.
These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical
bias to tilt toward OFF.
0
1
2
3
DMD Active Array
N x P
M x N Micromirrors
N ± 4
N ± 3
N ± 2
N ± 1
M x P
P
Border micromirrors omitted for clarity.
Details omitted for clarity.
P
Not to scale.
P
P
Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.
Figure 11. Micromirror Array Physical Characteristics
20
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6.10 Micromirror Array Optical Characteristics
See Optical Interface and System Image Quality for important information.
PARAMETER
CONDITIONS
MIN NOM
MAX
UNIT
(1)
α
β
Micromirror tilt angle
DMD landed state
12
°
°
°
Micromirror tilt angle tolerance(1) (2)(3)(4)(5)
Micromirror tilt direction(5)(6) (7)
–1
44
1
46
0
Figure 12
45
Adjacent micromirrors
Non-adjacent micromirrors
Typical performance
Typical performance
(7)
Number of out-of-specification micromirrors
micromirrors
10
(8)(9)
Micromirror crossover time
2.5
5
μs
μs
(9)
Micromirror switching time
DMD efficiency within the wavelength range 400 nm to 420
nm(10)
68%
DMD photopic efficiency within the wavelength range 420 nm
to 700 nm(10)
66%
(1) Measured relative to the plane formed by the overall micromirror array.
(2) Additional variation exists between the micromirror array and the package datums.
(3) Represents the landed tilt angle variation relative to the nominal landed tilt angle.
(4) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
(5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some
system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result in
colorimetry variations, system efficiency variations or system contrast variations.
(6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of
the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON State
direction. A binary value of 0 results in a micromirror landing in the OFF State direction.
(7) An out-of-specification micromirror is defined as a micromirror that is unable to transition between the two landed states within the
specified Micromirror Switching Time
(8) Micromirror crossover time is primarily a function of the natural response time of the micromirrors.
(9) Performance as measured at the start of life.
(10) Efficiency numbers assume 24-degree illumination angle, F/2.4 illumination and collection cones, uniform source spectrum, and uniform
pupil illumination. Efficiency numbers assume 100% electronic mirror duty cycle and do not include optical overfill loss. Note that this
number is specified under conditions described above and deviations from the specified conditions could result in decreased efficiency.
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illumination
Not To Scale
0
1
2
3
On-State
Tilt Direction
Off-State
Tilt Direction
45°
N ± 4
N ± 3
N ± 2
N ± 1
Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.
Figure 12. Micromirror Landed Orientation and Tilt
6.11 Window Characteristics
PARAMETER(1)
CONDITIONS
Corning 7056
at wavelength 589 nm
See(2)
MIN
TYP
MAX UNIT
Window material designation
Window refractive index
Window aperture(2)
1.487
Illumination overfill(3)
See(3)
At wavelength 405 nm. Applies to 0° and 24° AOI
only.
95%
97%
97%
Window transmittance, single–pass
Minimum within the wavelength range 420 nm to 680
nm. Applies to all angles 0° to 30° AOI.
(4)
through both surfaces and glass
Average over the wavelength range 420 nm to 680
nm. Applies to all angles 30° to 45° AOI.
(1) See Window Characteristics and Optics for more information.
(2) For details regarding the size and location of the window aperture, see the package mechanical characteristics listed in the Mechanical
ICD in section Mechanical, Packaging, and Orderable Information.
(3) Refer to Illumination Overfill.
(4) See the TI application report DLPA031, Wavelength Transmittance Considerations for DLP™ DMD Window.
6.12 Chipset Component Usage Specification
The DLP6500FLQ is a component of one or more DLP® chipsets. Reliable function and operation of the
DLP6500FLQ requires that it be used in conjunction with the other components of the applicable DLP chipset,
including those components that contain or implement TI DMD control technology. TI DMD control technology is
the TI technology and devices for operating or controlling a DLP DMD.
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7 Detailed Description
7.1 Overview
DLP6500FLQ is a 0.65 inch diagonal spatial light modulator which consists of an array of highly reflective
aluminum micromirrors. Pixel array size and square grid pixel arrangement are shown in Figure 11.
The DMD is an electrical input, optical output micro-electrical-mechanical system (MEMS). The electrical
interface is Low Voltage Differential Signaling (LVDS), Double Data Rate (DDR).
DLP6500FLQ DMD consists of a two-dimensional array of 1-bit CMOS memory cells. The array is organized in a
grid of M memory cell columns by N memory cell rows. Refer to the Functional Block Diagram.
The positive or negative deflection angle of the micromirrors can be individually controlled by changing the
address voltage of underlying CMOS addressing circuitry and micromirror reset signals (MBRST).
Each cell of the M × N memory array drives its true and complement (‘Q’ and ‘QB’) data to two electrodes
underlying one micromirror, one electrode on each side of the diagonal axis of rotation. Refer to Micromirror
Array Optical Characteristics . The micromirrors are electrically tied to the micromirror reset signals (MBRST) and
the micromirror array is divided into reset groups.
Electrostatic potentials between a micromirror and its memory data electrodes cause the micromirror to tilt
toward the illumination source in a DLP projection system or away from it, thus reflecting its incident light into or
out of an optical collection aperture. The positive (+) tilt angle state corresponds to an 'on' pixel, and the negative
(–) tilt angle state corresponds to an 'off' pixel.
Refer to Micromirror Array Optical Characteristics for the ± tilt angle specifications. Refer to Pin Configuration
and Functions for more information on micromirror reset control.
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7.2 Functional Block Diagram
Not to Scale. Details Omitted for Clarity. See Accompanying Notes in this Section.
Channel A
Interface
Control
Column Read & Write
Control
(0,0)
Voltages
Word Lines
Voltage
Generators
Row
Micromirror Array
(M-1, N-1)
Control
Column Read & Write
Control
Channel B
Interface
For pin details on Channels A, and B, refer to Pin Configuration and Functions and Timing Requirements notes 5 thru
8.
Refer to Micromirror Array Physical Characteristics for dimensions, orientation, and tilt angle.
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7.3 Feature Description
DLP6500FLQ device consists of highly reflective, digitally switchable, micrometer-sized mirrors (micromirrors)
organized in a two-dimensional orthogonal pixel array. Refer to Figure 11 and Figure 13.
Each aluminum micromirror is switchable between two discrete angular positions, –α and +α. The angular
positions are measured relative to the micromirror array plane, which is parallel to the silicon substrate. Refer to
Micromirror Array Optical Characteristics and Figure 14.
The parked position of the micromirror is not a latched position and is therefore not necessarily perfectly parallel
to the array plane. Individual micromirror flat state angular positions may vary. Tilt direction of the micromirror is
perpendicular to the hinge-axis. The on-state landed position is directed toward the left-top edge of the package,
as shown in Figure 13.
Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a
specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell
contents, after the mirror clocking pulse is applied. The angular position (–α and +α) of the individual
micromirrors changes synchronously with a micromirror clocking pulse, rather than being coincident with the
CMOS memory cell data update.
Writing logic 1 into a memory cell followed by a mirror clocking pulse results in the corresponding micromirror
switching to a +α position. Writing logic 0 into a memory cell followed by a mirror clocking pulse results in the
corresponding micromirror switching to a – α position.
Updating the angular position of the micromirror array consists of two steps. First, update the contents of the
CMOS memory. Second, apply a micromirror reset to all or a portion of the micromirror array (depending upon
the configuration of the system). Micromirror reset pulses are generated internally by the DLP6500FLQ DMD with
application of the pulses being coordinated by the DLPC900 display controller.
For more information, see the TI application report DLPA008A, DMD101: Introduction to Digital Micromirror
Device (DMD) Technology.
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Feature Description (continued)
Incident
Illumination
Package Pin
A1 Corner
DMD
Micromirror
Array
Active Micromirror Array
(Border micromirrors eliminated for clarity)
0
N±1
Micromirror Pitch
Micromirror Hinge-Axis Orientation
P (um)
³2Q-6WDWH´
Tilt Direction
45°
³2II-6WDWH´
Tilt Direction
P (um)
Refer to Micromirror Array Physical Characteristics , Figure 11, and Figure 12.
Figure 13. Micromirror Array, Pitch, Hinge Axis Orientation
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Feature Description (continued)
Details Omitted For Clarity.
Not To Scale.
Package Pin
A1 Corner
DMD
Incident
Illumination
Two
³2Q-6WDWH´
Two
³2II-6WDWH´
Micromirrors Micromirrors
For Reference
Flat-State
( ³SDUNHG´ꢀ)
Micromirror Position
a ± b
-a ± b
Silicon Substrate
Silicon Substrate
³2Q-6WDWH´
Micromirror
³2II-6WDWH´
Micromirror
Refer to Micromirror Array Optical Characteristics , and Figure 12.
Figure 14. Micromirror States: On, Off, Flat
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7.4 Device Functional Modes
DLP6500FLQ is part of the chipset comprising of the DLP6500FLQ DMD and DLPC900 display controller. To
ensure reliable operation, DLP6500FLQ DMD must always be used with a DLPC900 display controller.
DMD functional modes are controlled by the DLPC900 digital display controller. See the DLPC900 data sheet
listed in Related Documentation. Contact a TI applications engineer for more information.
7.5 Window Characteristics and Optics
NOTE
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical
system operating conditions exceeding limits described previously.
7.5.1 Optical Interface and System Image Quality
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Optimizing system optical performance and image quality strongly relate to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
7.5.2 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate
apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the
projection lens. The mirror tilt angle defines DMD capability to separate the "ON" optical path from any other light
path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other
system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt
angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination
numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur.
7.5.3 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within 2° (two degrees) of the entrance pupil of the projection optics. Misalignment of pupils can create
objectionable artifacts in the display’s border and/or active area, which may require additional system apertures
to control, especially if the numerical aperture of the system exceeds the pixel tilt angle.
7.5.4 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical
operating conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the
window aperture opening and other surface anomalies that may be visible on the screen. The illumination optical
system should be designed to limit light flux incident anywhere on the window aperture from exceeding
approximately 10% of the average flux level in the active area. Depending on the particular system’s optical
architecture, overfill light may have to be further reduced below the suggested 10% level in order to be
acceptable.
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7.6 Micromirror Array Temperature Calculation
Figure 15. DMD Thermal Test Points
Micromirror array temperature can be computed analytically from measurement points on the outside of the
package, the ceramic package thermal resistance, the electrical power dissipation, and the illumination heat load.
The relationship between micromirror array temperature and the reference ceramic temperature is provided by
the following equations:
TARRAY = TCERAMIC + (QARRAY × RARRAY–TO–CERAMIC
QARRAY = QELECTRICAL + QILLUMINATION
QILLUMINATION = (CL2W × SL)
)
(1)
(2)
(3)
Where:
TARRAY = Computed micromirror array temperature (°C)
TCERAMIC = Measured ceramic temperature (°C), TP1 location in Figure 15
RARRAY–TO–CERAMIC = DMD package thermal resistance from micromirror array to outside ceramic (°C/W)
specified in Thermal Information
QARRAY = Total DMD power; electrical, specified in Electrical Characteristics, plus absorbed (calculated) (W)
QELECTRICAL = Nominal DMD electrical power dissipation (W), specified in Electrical Characteristics
CL2W = Conversion constant for screen lumens to absorbed optical power on the DMD (W/lm) specified
below
SL = Measured ANSI screen lumens (lm)
Electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating
frequencies. The nominal electrical power dissipation to use when calculating array temperature is 2.9 Watts .
Absorbed optical power from the illumination source is variable and depends on the operating state of the
micromirrors and the intensity of the light source. Equations shown above are valid for a 1-chip DMD system with
total projection efficiency through the projection lens from DMD to the screen of 87%.
The conversion constant CL2W is based on the DMD micromirror array characteristics. It assumes a spectral
efficiency of 300 lm/W for the projected light and illumination distribution of 83.7% on the DMD active array, and
16.3% on the DMD array border and window aperture. The conversion constant is calculated to be 0.00293
W/lm.
Sample Calculation for typical projection application:
TCERAMIC = 55°C, assumed system measurement; see Recommended Operating Conditions for specific limits
SL = 2000 lm
QELECTRICAL = 2.9 W (see the maximum power specifications in Electrical Characteristics)
CL2W = 0.00293 W/lm
QARRAY = 2.9 W + (0.00293 W/lm × 2000 lm) = 8.76 W
TARRAY = 55°C + (8.76 W × 0.7 × C/W) = 61.13 °C
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7.7 Micromirror Landed-on/Landed-Off Duty Cycle
7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the On–state versus the amount of time the same
micromirror is landed in the Off–state.
As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On–state 100% of the
time (and in the Off–state 0% of the time); whereas 0/100 would indicate that the pixel is in the Off–state 100% of
the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (On or Off), the two numbers (percentages)
always add to 100.
7.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed
duty cycle for a prolonged period of time can reduce the DMD’s usable life.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed
duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed
duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
7.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this
interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s
usable life. This is quantified in the de-rating curve shown in Figure 1. The importance of this curve is that:
•
•
All points along this curve represent the same usable life.
All points above this curve represent lower usable life (and the further away from the curve, the lower the
usable life).
•
All points below this curve represent higher usable life (and the further away from the curve, the higher the
usable life).
In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at
for a give long-term average Landed Duty Cycle.
7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
will experience a 100/0 Landed Duty Cycle during that time period. Likewise, when displaying pure-black, the
pixel will experience a 0/100 Landed Duty Cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in Table 2.
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Table 2. Grayscale Value and Landed Duty Cycle
GRAYSCALE VALUE
LANDED DUTY CYCLE
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0/100
10/90
20/80
30/70
40/60
50/50
60/40
70/30
80/20
90/10
100/0
Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from
0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color
cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a given
primary must be displayed in order to achieve the desired white point.
During a given period of time, the landed duty cycle of a given pixel can be calculated as follows:
Landed Duty Cycle =(Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) +
(Blue_Cycle_% × Blue_Scale_Value)
Where:
Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_%, represent the percentage of the frame time that Red,
Green, and Blue are displayed (respectively) to achieve the desired white point.
For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in
order to achieve the desired white point), then the Landed Duty Cycle for various combinations of red, green,
blue color intensities would be as shown in Table 3.
Table 3. Example Landed Duty Cycle for Full-Color
Red Cycle Percentage
50%
Green Cycle Percentage
20%
Blue Cycle Percentage
30%
Landed Duty Cycle
Red Scale Value
Green Scale Value
Blue Scale Value
0%
100%
0%
0%
0%
0%
0%
0/100
50/50
20/80
30/70
6/94
100%
0%
0%
0%
100%
0%
12%
0%
0%
35%
0%
0%
7/93
0%
60%
0%
18/82
70/30
50/50
80/20
13/87
25/75
24/76
100/0
100%
0%
100%
100%
0%
100%
100%
0%
100%
12%
0%
35%
35%
0%
60%
60%
100%
12%
100%
100%
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DLP6500FLQ along with the DLPC900 controller provides a solution for many applications including
structured light and video projection. The DMD is a spatial light modulator, which reflects incoming light from an
illumination source to one of two directions, with the primary direction being into a projection or collection optic.
Each application is derived primarily from the optical architecture of the system and the format of the data
coming into the DLPC900. Applications of interest include machine vision, 3D printing, and lithography.
8.2 Typical Application
A typical embedded system application using the DLPC900 controller and a DLP6500FLQ is shown in Figure 16.
In this configuration, the DLPC900 controller supports a 24-bit parallel RGB input, typical of LCD interfaces, from
an external source or processor. This system configuration supports still and motion video sources plus
sequential pattern mode. Refer to Related Documents for the DLPC900 digital controller data sheet.
HEARTBEAT
FAULT_STATUS
LED
Status
Parallel
Flash
PM_ADDR[22:0],WE
DATA[15:0],OE,CS
Host
USB
I2C
USB_DN,DP
LEDs
LED EN[2:0]
LED PWM[2:0]
I2C_SCL1, I2C_SDA1
P1_A[9:0]
P1_B[9:0]
P1_C[9:0]
PWM
FAN
Digital Receiver
HDMI
DP
DLPC900
HDMI
DISPLAYPORT
DMD_A,B[15:0]
DMD Control
DMD SSP
P1A_CLK, P1_DATEN,
P1_VSYNC, P1_HSYNC
TRIG_OUT[1:0]
TRIG_IN[1:0]
POWER RAILS
GUI
Camera
Crystal
JTAG
DLP6500FLQ
VCC
PWRGOOD
Power
MOSC
POSENSE Management
I2C_SCL0
I2C_SDA0
TDO[1:0],TRST,TCK
RMS[1:0],RTCK
I2C
12V DC IN
Figure 16. Typical Application Schematic
8.2.1 Design Requirements
Detailed design requirements are located in the DLPC900 digital controller data sheet. Refer to Related
Documents.
8.2.2 Detailed Design Procedure
See the reference design schematic for connecting together the DLPC900 display controller and the DLP6500
DMD. An example board layout is included in the reference design data base. Layout guidelines should be
followed for reliability.
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9 Power Supply Recommendations
9.1 DMD Power Supply Requirements
The following power supplies are all required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET.
VSS must also be connected. DMD power-up and power-down sequencing is strictly controlled by the DLPC900
device.
CAUTION
For reliable operation of the DMD, the following power supply sequencing
requirements must be followed. Failure to adhere to the prescribed power-up and
power-down procedures may affect device reliability. VCC, VCCI, VOFFSET, VBIAS,
and VRESET power supplies have to be coordinated during power-up and power-
down operations. VSS must also be connected. Failure to meet any of the below
requirements will result in a significant reduction in the DMD’s reliability and lifetime.
Refer to Figure 17.
9.2 DMD Power Supply Power-Up Procedure
•
During power-up, VCC and VCCI must always start and settle before VOFFSET, VBIAS, and VRESET
voltages are applied to the DMD.
•
During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the
specified limit shown in Recommended Operating Conditions . During power-up, VBIAS does not have to
start after VOFFSET.
•
•
•
During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS.
Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the
requirements listed in Absolute Maximum Ratings , in Recommended Operating Conditions, and in Figure 17.
During power-up, LVCMOS input pins shall not be driven high until after VCC and VCCI have settled at
operating voltages listed in Recommended Operating Conditions.
9.3 DMD Power Supply Power-Down Procedure
•
During power-down, VCC and VCCI must be supplied until after VBIAS, VRESET, and VOFFSET are
discharged to within the specified limit of ground. Refer to Table 4.
•
During power-down, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the
specified limit shown in Recommended Operating Conditions. During power-down, it is not mandatory to stop
driving VBIAS prior to VOFFSET.
•
•
•
During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS.
Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements listed in Absolute Maximum Ratings, in Recommended Operating Conditions , and in Figure 17.
During power-down, LVCMOS input pins must be less than specified in Recommended Operating Conditions.
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DMD Power Supply Power-Down Procedure (continued)
EN_BIAS, EN_OFFSET, and EN_RESET are disabled by
DLP Controller software or PWRDNZ signal control
Note 5
Note 3
Waveforms Not To Scale.
Details Omitted For Clarity.
Refer to Recommended Operating Conditions.
VBIAS, VOFFSET, and VRESET are disabled by
DLP Controller software
Power Off
Mirror Park Sequence
VCC / VCCI
VSS
VSS
VSS
VSS
VSS
RESET_OEZ
VCC / VCCI
VSS
PWRDNZ
VCC,
VCC / VCCI
VCC / VCCI
VSS
VCCI
EN_BIAS,
EN_OFFSET,
EN_RESET
Note 3
VSS
VBIAS
VBIAS
VBIAS
VBIAS < Specification
Note 4
Note 1
ûV < Specification
Note 1
VSS
VSS
ûV < Specification
VOFFSET
VOFFSET
VOFFSET < Specification
Note 4
VOFFSET
VSS
VSS
VSS
VSS
VRESET < Specification
Note 4
VRESET > Specification
VRESET
VRESET
VCC
VRESET
LVCMOS
Inputs
VSS
VSS
VSS
VSS
Waveforms Not To Scale.
Note 2
Refer to Recommended Operating Conditions.
LVDS
Inputs
Note 2
Figure 17. DMD Power Supply Sequencing Requirements
1. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in
Recommended Operating Conditions. OEMs may find that the most reliable way to ensure this is to power
VOFFSET prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during power-down.
2. LVDS signals are less than the input differential voltage (VID) maximum specified in Recommended
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DMD Power Supply Power-Down Procedure (continued)
Operating Conditions. During power-down, LVDS signals are less than the high level input voltage (VIH)
maximum specified in Recommended Operating Conditions.
3. When system power is interrupted, the DLP controller (DLPC900) initiates a hardware power-down that
activates PWRDNZ and disables VBIAS, VRESET and VOFFSET after the micromirror park sequence.
Software power-down disables VBIAS, VRESET, and VOFFSET after the micromirror park sequence through
software control. For either case, enable signals EN_BIAS, EN_OFFSET, and EN_RESET are used to
disable VBIAS, VOFFSET, and VRESET, respectfully.
4. Refer to DMD Power Down Sequence Requirements.
5. Figure not to scale. Details have been omitted for clarity. Refer Recommended Operating Conditions.
Table 4. DMD Power-Down Sequence Requirements
PARAMETER
VBIAS
MIN
MAX
4.0
UNIT
Supply voltage level during power–down sequence
Supply voltage level during power–down sequence
Supply voltage level during power–down sequence
V
V
V
VOFFSET
VRESET
4.0
–4.0
0.5
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10 Layout
10.1 Layout Guidelines
The DLP6500FLQ along with one DLPC900 controller provides a solution for many applications including
structured light and video projection. This section provides layout guidelines for the DLP6500FLQ.
10.1.1 General PCB Recommendations
The PCB shall be designed to IPC2221 and IPC2222, Class 2, Type Z, at level B producibility and built to
IPC6011 and IPC6012, class 2. The PCB board thickness to be 0.062 inches +/- 10%, using standard FR-4
material, and applies after all lamination and plating processes, measured from copper to copper.
Two-ounce copper planes are recommended in the PCB design in order to achieve needed thermal connectivity.
Refer to Related Documents for the DLPC900 Digital Controller Data Sheet for related information on the DMD
Interface Considerations.
High-speed interface waveform quality and timing on the DLPC900 controller (that is, the LVDS DMD interface)
is dependent on the following factors:
•
•
•
•
•
Total length of the interconnect system
Spacing between traces
Characteristic impedance
Etch losses
How well matched the lengths are across the interface
Thus, ensuring positive timing margin requires attention to many factors. As an example, DMD interface system
timing margin can be calculated as follows:
•
Setup Margin = (controller output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI
degradation)
•
Hold-time Margin = (controller output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI
degradation)
The PCB SI degradation is the signal integrity degradation due to PCB affects which includes such things as
simultaneously switching output (SSO) noise, crosstalk, and inter-symbol-interference (ISI) noise.
DLPC900 I/O timing parameters can be found in DLPC900 Digital Controller Data Sheet. Similarly, PCB routing
mismatch can be easily budgeted and met via controlled PCB routing. However, PCB SI degradation is not as
easy to determine.
In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design
guidelines provide a reference of an interconnect system that satisfies both waveform quality and timing
requirements (accounting for both PCB routing mismatch and PCB SI degradation). Deviation from these
recommendations should be confirmed with PCB signal integrity analysis or lab measurements.
10.2 Layout Example
10.2.1 Board Stack and Impedance Requirements
Refer to Figure 18 for guidance on the parameters.
PCB design:
Configuration:
Asymmetric dual stripline
1.0-oz copper (1.2 mil)
0.5-oz copper (0.6 mil)
50 Ω (±10%)
Etch thickness (T):
Flex etch thickness (T):
Single-ended signal impedance:
Differential signal impedance:
100 Ω (±10%)
36
Copyright © 2014, Texas Instruments Incorporated
DLP6500FLQ
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ZHCSD21 –OCTOBER 2014
Layout Example (continued)
PCB stack-up:
Reference plane 1 is assumed to be a ground plane
for proper return path.
Asymmetric dual stripline
1.0-oz copper (1.2 mil)
Reference plane 2 is assumed to be the I/O power
plane or ground.
Dielectric FR4, (Er):
4.2 (nominal)
Signal trace distance to reference plane 1 (H1):
Signal trace distance to reference plane 2 (H2):
5.0 mil (nominal)
34.2 mil (nominal)
Figure 18. PCB Stack Geometries
Table 5. General PCB Routing (Applies to All Corresponding PCB Signals)
PARAMETER
APPLICATION
SINGLE-ENDED SIGNALS
DIFFERENTIAL PAIRS
UNIT
4
(0.1)
4
(0.1)
mil
(mm)
Escape routing in ball field
7
4.25
(0.11)
mil
(mm)
Line width (W)
PCB etch data or control
PCB etch clocks
(0.18)
7
4.25
(0.11)
mil
(mm)
(0.18)
Copyright © 2014, Texas Instruments Incorporated
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ZHCSD21 –OCTOBER 2014
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Layout Example (continued)
Table 5. General PCB Routing (Applies to All Corresponding PCB Signals) (continued)
PARAMETER
APPLICATION
SINGLE-ENDED SIGNALS
DIFFERENTIAL PAIRS
UNIT
5.75(1)
–0.15
5.75(1)
–0.15
mil
(mm)
PCB etch data or control
N/A
Differential signal pair spacing (S)
mil
(mm)
PCB etch clocks
N/A
N/A
N/A
20
(0.51)
mil
(mm)
PCB etch data or control
PCB etch clocks
Minimum differential pair-to-pair
spacing (S)
20
(0.51)
mil
(mm)
4
(0.1)
4
(0.1)
mil
(mm)
Escape routing in ball field
PCB etch data or control
PCB etch clocks
10
(0.25)
20
(0.51)
mil
(mm)
Minimum line spacing to other
signals (S)
20
(0.51)
20
(0.51)
mil
(mm)
12
–0.3
mil
(mm)
Maximum differential pair P-to-N
length mismatch
Total data
N/A
N/A
12
–0.3
mil
(mm)
Total data
(1) Spacing may vary to maintain differential impedance requirements
Table 6. DMD Interface Specific Routing
SIGNAL GROUP LENGTH MATCHING
INTERFACE
SIGNAL GROUP
REFERENCE SIGNAL
MAX MISMATCH
UNIT
± 150
(± 3.81)
mil
(mm)
SCTRL_AN, SCTRL_AP
D_AP(15:0), D_AN(15:0)
DMD (LVDS)
DCK_AP/ DCKA_AN
± 150
(± 3.81)
mil
(mm)
SCTRL_BN, SCTRL_BP
D_BP(15:0), D_BN(15:0)
DMD (LVDS)
DCK_BP/ DCK_BN
Number of layer changes:
•
•
Single-ended signals: Minimize
Differential signals: Individual differential pairs can be routed on different layers but the signals of a given pair
should not change layers.
Table 7. DMD Signal Routing Length(1)
BUS
MIN
MAX
UNIT
DMD (LVDS)
50
375
mm
(1) Max signal routing length includes escape routing.
Stubs: Stubs should be avoided.
Termination Requirements: DMD interface: None – The DMD receiver is differentially terminated to 100 Ω
internally.
Connector (DMD-LVDS interface bus only):
High-speed connectors that meet the following requirements should be used:
•
•
Differential crosstalk: <5%
Differential impedance: 75 to 125 Ω
38
Copyright © 2014, Texas Instruments Incorporated
DLP6500FLQ
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ZHCSD21 –OCTOBER 2014
Routing requirements for right-angle connectors: When using right-angle connectors, P-N pairs should be routed
in the same row to minimize delay mismatch. When using right-angle connectors, propagation delay difference
for each row should be accounted for on associated PCB etch lengths. Voltage or low frequency signals should
be routed on the outer layers. Signal trace corners shall be no sharper than 45 degrees. Adjacent signal layers
shall have the predominant traces routed orthogonal to each other.
These guidelines will produce a maximum PCB routing mismatch of 4.41 mm (0.174 inch) or approximately 30.4
ps, assuming 175 ps/inch FR4 propagation delay.
These PCB routing guidelines will result in approximately 25-ps system setup margin and 25-ps system hold
margin for the DMD interface after accounting for signal integrity degradation as well as routing mismatch.
Both the DLPC900 output timing parameters and the DLP6500FLQ DMD input timing parameters include timing
budget to account for their respective internal package routing skew.
10.2.1.1 Power Planes
Signal routing is NOT allowed on the power and ground planes. All device pin and via connections to this plane
shall use a thermal relief with a minimum of four spokes. The power plane shall clear the edge of the PCB by
0.2”.
Prior to routing, vias connecting all digital ground layers (GND) should be placed around the edge of the rigid
PWB regions 0.025” from the board edges with a 0.100” spacing. It is also desirable to have all internal digital
ground (GND) planes connected together in as many places as possible. If possible, all internal ground planes
should be connected together with a minimum distance between connections of 0.5”. Extra vias are not required
if there are sufficient ground vias due to normal ground connections of devices. NOTE: All signal routing and
signal vias should be inside the perimeter ring of ground vias.
Power and Ground pins of each component shall be connected to the power and ground planes with one via for
each pin. Trace lengths for component power and ground pins should be minimized (ideally, less than 0.100”).
Unused or spare device pins that are connected to power or ground may be connected together with a single via
to power or ground. Ground plane slots are NOT allowed.
Route VOFFSET, VBIAS, and VRESET as a wide trace >20mils (wider if space allows) with 20 mils spacing.
10.2.1.2 LVDS Signals
The LVDS signals shall be first. Each pair of differential signals must be routed together at a constant separation
such that constant differential impedance (as in section 10.1.2) is maintained throughout the length. Avoid sharp
turns and layer switching while keeping lengths to a minimum. The distance from one pair of differential signals
to another shall be at least 2 times the distance within the pair.
10.2.1.3 Critical Signals
The critical signals on the board must be hand routed in the order specified below. In case of length matching
requirements, the longer signals should be routed in a serpentine fashion, keeping the number of turns to a
minimum and the turn angles no sharper than 45 degrees. Avoid routing long trace all around the PCB.
Table 8. Timing Critical Signals
GROUP
SIGNAL
CONSTRAINTS
ROUTING LAYERS
1
D_AP(0:15), D_AN(0:15), DCLK_AP,
DCLK_AN, SCTRL_AN, SCTRL_AP,
D_BP(0:15), D_BN (0:15), DCLK_BP,
DCLK_BN, SCTRL_BN, SCTRL_BP
Refer to Table 5 and Table 6
Internal signal layers. Avoid layer switching
when routing these signals.
2
RESET_ADDR(0:3),
RESET_MODE(0:1),
RESET_OEZ,
Internal signal layers. Top and bottom as
required.
RESET_SEL(0:1)
RESET_STROBE,
RESET_IRQZ.
3
4
SCP_CLK, SCP_DO,
SCP_DI, SCP_ENZ.
Any
Any
Others
No matching/length requirement
Copyright © 2014, Texas Instruments Incorporated
39
DLP6500FLQ
ZHCSD21 –OCTOBER 2014
www.ti.com.cn
10.2.1.4 Flex Connector Plating
Plate all the pad area on top layer of flex connection with a minimum of 35 and maximum 50 micro-inches of
electrolytic hard gold over a minimum of 150 micro-inches of electrolytic nickel.
10.2.1.5 Device Placement
Unless otherwise specified, all major components should be placed on top layer. Small components such as
ceramic, non-polarized capacitors, resistors and resistor networks can be placed on bottom layer. All high
frequency de-coupling capacitors for the ICs shall be placed near the parts. Distribute the capacitors evenly
around the IC and locate them as close to the device’s power pins as possible (preferably with no vias). In the
case where an IC has multiple de-coupling capacitors with different values, alternate the values of those that are
side by side as much as possible and place the smaller value capacitor closer to the device.
10.2.1.6 Device Orientation
It is desirable to have all polarized capacitors oriented with their positive terminals in the same direction. If
polarized capacitors are oriented both horizontally and vertically, then all horizontal capacitors should be oriented
with the “+” terminal the same direction and likewise for the vertically oriented ones.
10.2.1.7 Fiducials
Fiducials for automatic component insertion should be placed on the board according to the following guidelines
or on recommendation from manufacturer:
•
•
Fiducials for optical auto insertion alignment shall be placed on three corners of both sides of the PWB.
Fiducials shall also be placed in the center of the land patterns for fine pitch components (lead spacing
<0.05”).
•
Fiducials should be 0.050 inch copper with 0.100 inch cutout (antipad).
40
版权 © 2014, Texas Instruments Incorporated
DLP6500FLQ
www.ti.com.cn
ZHCSD21 –OCTOBER 2014
11 器件和文档支持
11.1 器件支持
11.1.1 器件命名规则
表 9. 封装具体信息
封装类型
引脚
连接器
FLQ
203
LGA
DLP6500FLQ
Package Type
Device Descriptor
图 19. 部件号说明
11.1.2 器件标记
器件标记将包括可读信息和一个二维矩阵码。 图 20 中显示了可读信息。 二维矩阵码是一个字母数字字符串,其中
包含 DMD 部件号、序列号的第 1 部分和序列号的第 2 部分。 DMD 序列号(第 1 部分)的首字符为制造年份。
DMD 序列号(第 1 部分)的第二个字符为制造月份。 DMD 序列号(第 2 部分)的最后一个字符为偏置电压二进
制字母。
TI Internal Numbering
DMD Part Number
2 Dimensional Matrix Code
(DMD Part Number
and Serial Number)
DLP6500FLQ
Part 2 of Serial Number
(7 characters)
Part 1 of Serial Number
(7 characters)
TI Internal Numbering
图 20. DMD 标记位置
版权 © 2014, Texas Instruments Incorporated
41
DLP6500FLQ
ZHCSD21 –OCTOBER 2014
www.ti.com.cn
11.2 文档支持
11.2.1 相关文档ꢀ
以下文档包含关于使用 DLP6500 器件的更多信息。
表 10. 相关文档
文档
DLPC900 数字控制器数据表
DLPC900 软件编程人员指南
DLPS037
DLPU018
11.3 商标
DLP is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
42
版权 © 2014, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
24-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DLP6500BFLQ
ACTIVE
CLGA
FLQ
203
18
RoHS & Green
NI-PD-AU
N / A for Pkg Type
0 to 65
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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