DLP160CPFQT [TI]

0.16 英寸 nHD DLP® 数字微镜器件 (DMD) | FQT | 42 | 0 to 70;


型号：	DLP160CPFQT
厂家：	TEXAS INSTRUMENTS
描述：	0.16 英寸 nHD DLP® 数字微镜器件 (DMD) \| FQT \| 42 \| 0 to 70
文件：	总45页 (文件大小：1922K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLP160CP

ZHCSP44C –OCTOBER 2021 –REVISED JULY 2023

DLP160CP 0.16 nHD DMD

1 特性

3 说明

• 超紧凑0.16-inch (3.965-mm) 对角线微镜阵列

DLP160CP 数字微镜器件 (DMD) 是一款数控微光机电

系统(MOEMS) 空间照明调制器(SLM)。当与适当的光

学系统耦合连接时，DLP160CP DMD 可显示非常清晰

的高质量图像或视频。DLP160CP 是由 DLP160CP

DMD 和DLPC3421 控制器所组成的芯片组的一部分。

DLPA2000 or DLPA2005 PMIC/LED 驱动器也支持此

芯片组。DLP160CP 外形小巧，非常适合注重小尺寸

和低功耗的便携设备。紧凑型 DLP160CP DMD 与控

制器和 PMIC/LED 驱动器共同组成完整的系统解决方

案，可实现小巧外形、低功耗以及高画质显示。

– 显示器640 × 360 分辨率

– 5.4µm 微镜间距

– 17° 微镜倾斜（相对于平坦表面）

– 采用侧面照明，实现最优的效率和光学引擎尺寸

– 偏振无关型铝微镜表面

• 4 位SubLVDS 输入数据总线

• 专用DLPC3421 显示控制器和DLPA2000 或

DLPA2005 PMIC/LED 驱动器，确保可靠运行

2 应用

器件信息

• 显示：

封装⁽¹⁾

封装尺寸（标称值）

器件型号

DLP160CP

– 超高移动性、超低功耗Pico 投影仪

– 手机、平板电脑和笔记本电脑

– 智能显示

– 智能家居

– 增强现实眼镜

– 信息显示

FQT (35)

13.39 mm × 4.97 mm × 3.18 mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

简化版应用

DLPC3421

DLP160CP DMD

Digital Micromirror Device

DLPA2000/

DLPA2005

D_P(0)

D_N(0)

Display Controller

Power Management

VOFFSET

VBIAS

D_P(1)

D_N(1)

D_P(2)

D_N(2)

600 MHz

SubLVDS

DDR

Interface

VRESET

D_P(3)

D_N(3)

DCLK_P

DCLK_N

VDDI

VDD

VSS

LS_WDATA

LS_CLK

120 MHz

SDR

Interface

LS_RDATA

DMD_DEN_ARSTZ

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS228

DLP160CP

ZHCSP44C –OCTOBER 2021 –REVISED JULY 2023

www.ti.com.cn

Table of Contents

7.5 Optical Interface and System Image Quality

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings........................................ 6

6.2 Storage Conditions..................................................... 6

6.3 ESD Ratings............................................................... 7

6.4 Recommended Operating Conditions.........................7

6.5 Thermal Information..................................................10

6.6 Electrical Characteristics...........................................10

6.7 Timing Requirements................................................ 11

6.8 Switching Characteristics..........................................16

6.9 System Mounting Interface Loads............................ 17

6.10 Micromirror Array Physical Characteristics.............18

6.11 Micromirror Array Optical Characteristics............... 19

6.12 Window Characteristics.......................................... 21

6.13 Chipset Component Usage Specification............... 21

7 Detailed Description......................................................22

7.1 Overview...................................................................22

7.2 Functional Block Diagram.........................................22

7.3 Feature Description...................................................23

7.4 Device Functional Modes..........................................23

Considerations............................................................ 23

7.6 Micromirror Array Temperature Calculation.............. 24

7.7 Micromirror Power Density Calculation.....................25

7.8 Micromirror Landed-On/Landed-Off Duty Cycle....... 27

8 Application and Implementation..................................32

8.1 Application Information............................................. 32

8.2 Typical Application.................................................... 33

9 Power Supply Recommendations................................35

9.1 Power Supply Power-Up Procedure......................... 35

9.2 Power Supply Power-Down Procedure.....................35

9.3 Power Supply Sequencing Requirements................ 36

10 Layout...........................................................................38

10.1 Layout Guidelines................................................... 38

10.2 Layout Example...................................................... 38

11 Device and Documentation Support..........................39

11.1 Device Support........................................................39

11.2 接收文档更新通知................................................... 39

11.3 支持资源..................................................................39

11.4 Trademarks............................................................. 39

11.5 静电放电警告...........................................................40

11.6 术语表..................................................................... 40

12 Mechanical, Packaging, and Orderable

Information.................................................................... 40

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (May 2022) to Revision C (July 2023)

Page

• Added section "ILLUMINATION" to Recommended Operating Conditions ....................................................... 7

• Updated Micromirror Array Temperature Calculations .....................................................................................24

• Added Micromirror Power Density Calculation ................................................................................................ 25

Changes from Revision A (January 2022) to Revision B (May 2022)

Page

• Updated Absolute Maximum Ratings disclosure to the latest TI standard......................................................... 6

• Updated Micromirror Array Optical Characteristics ......................................................................................... 19

• Added Third-Party Products Disclaimer ...........................................................................................................39

Changes from Revision * (October 2021) to Revision A (January 2022)

Page

• 将器件状态从“预告信息”更改为“量产数据”。............................................................................................ 1

English Data Sheet: DLPS228

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5 Pin Configuration and Functions

图5-1. FQT Package 35-Pin

12 14

表5-1. Connector Pins

PIN⁽¹⁾

PACKAGE NET

LENGTH (mm)⁽²⁾

NAME

DATA INPUTS

D_N(0)

NO.

TYPE

SIGNAL

DATA RATE

DESCRIPTION

SubLVDS

Double

Data, negative

Data, positive

Clock, negative

Clock, positive

1.91

3.6

D_N(1)

SubLVDS

Double

D_N(2)

3.28

1.67

2.03

3.7

D_N(3)

D_P(0)

D_P(1)

D_P(2)

3.39

1.77

2.29

2.4

D_P(3)

DCLK_N

DCLK_P

CONTROL INPUTS

LS_WDATA

C12

C13

LPSDR

Single

Write data for low- 1.55

speed interface

LS_CLK

Clock for low-

1.65

speed interface

DMD_DEN_ARST D12

Asynchronous

reset DMD signal.

A low signal

1.57

places the DMD in

reset. A high

signal releases the

DMD from reset

and places it in

active mode.

LS_RDATA

D13

A13

LPSDR

Single

1.43

POWER

(3)

V_BIAS

Power

Supply voltage for

positive bias level

at micromirrors

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表5-1. Connector Pins (continued)

PIN⁽¹⁾

PACKAGE NET

LENGTH (mm)⁽²⁾

NAME

NO.

TYPE

SIGNAL

DATA RATE

DESCRIPTION

(3)

V_OFFSET

E13

Power

Supply voltage for

HVCMOS core

logic. Supply

voltage for

stepped high level

at micromirror

address

electrodes. Supply

voltage for offset

level at

micromirrors.

(3)

V_RESET

A14

Power

Supply voltage for

negative reset

level at

micromirrors.

V_DD

B12

B14

Power

Supply voltage for

LVCMOS core

logic. Supply

voltage for LPSDR

inputs. Supply

voltage for normal

high level at

C14

micromirror

address

E14

electrodes.

V_DDI

Power

Supply voltage for

SubLVDS

receivers.

V_SS

Ground

Common return.

Ground for all

power.

A12

B13

D14

E12

(1) Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC

Standard No. 209B, Low Power Double Data Rate (LPDDR). See JESD209B.

(2) Net trace lengths inside the package:

Relative dielectric constant for the FQP ceramic package is 9.8.

Propagation speed = 11.8 / sqrt (9.8) = 3.769 in/ns.

Propagation delay = 0.265 ns/inch = 265 ps/in = 10.43 ps/mm.

(3) The following power supplies are all required to operate the DMD: V_DD, V_DDI, V_OFFSET, V_BIAS, V_RESET. All V_SSconnections are also

required.

表5-2. Test Pads

NUMBER

SYSTEM BOARD

Do not connect

English Data Sheet: DLPS228

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表5-2. Test Pads (continued)

NUMBER

A10

SYSTEM BOARD

Do not connect

A11

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6 Specifications

6.1 Absolute Maximum Ratings

see ⁽¹⁾

MIN

–0.5

MAX

2.3

UNIT

Supply voltage for LVCMOS core logic⁽²⁾

Supply voltage for LPSDR low speed interface

V_DD

V_DDI

Supply voltage for SubLVDS receivers⁽²⁾

Supply voltage for HVCMOS and micromirror

electrode^{(2) (3)}

V_OFFSET

Supply voltage for micromirror electrode⁽²⁾

Supply voltage delta (absolute value)⁽⁴⁾

Supply voltage delta (absolute value)⁽⁵⁾

Supply voltage delta (absolute value)⁽⁶⁾

0.5

0.3

Supply voltage

V_BIAS

–0.5

–15

V_RESET

|V_DDI–V_DD

|V_BIAS–V_OFFSET

|V_BIAS–V_RESET

Input voltage for other inputs LPSDR⁽²⁾

V_DD+ 0.5

V_DDI+ 0.5

810

–0.5

Input voltage

Input pins

Input voltage for other inputs SubLVDS^{(2) (7)}

|V_ID

SubLVDS input differential voltage (absolute value)⁽⁷⁾

SubLVDS input differential current

MHz

°C

I_ID

Clock frequency for low speed interface LS_CLK

Clock frequency for high speed interface DCLK

130

ƒ_clock

Clock

frequency

620

Temperature –operational ⁽⁸⁾

–20

–40

T_ARRAYand T_WINDOW

Temperature –non-operational⁽⁸⁾

°C

Environmental

Absolute temperature delta between any point on the

window edge and the ceramic test point TP1⁽⁹⁾

|T_DELTA

T_DP

°C

Dew Point - operating and non-operating

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values are with respect to the ground terminals (V_SS). The following power supplies are all required to operate the DMD:

V_DD, V_DDI, V_OFFSET, V_BIAS, and V_RESET. All V_SSconnections are also required.

(3) V_OFFSETsupply transients must fall within specified voltages.

(4) Exceeding the recommended allowable absolute voltage difference between V_DDIand V_DDmay result in excessive current draw.

(5) Exceeding the recommended allowable absolute voltage difference between V_BIASand V_OFFSETmay result in excessive current draw.

(6) Exceeding the recommended allowable absolute voltage difference between V_BIASand V_RESETmay result in excessive current draw.

(7) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential

inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(8) The highest temperature of the active array (as calculated by the 节7.6) or of any point along the window edge is defined in 图7-1.

The location of thermal test point TP2 in 图7-1 is intended to measure the highest window edge temperature. If a particular application

causes another point on the window edge to be at a higher temperature, that point should be used.

(9) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图

7-1. The window test point TP2 shown in 图7-1 is intended to result in the worst case delta. If a particular application causes another

point on the window edge to result in a larger delta temperature, that point should be used.

6.2 Storage Conditions

Applicable for the DMD as a component or non-operating in a system.

MIN

MAX

UNIT

°C

T_DMD

T_DP

DMD storage temperature

–40

Average dew point temperature (non-condensing) ⁽¹⁾

Elevated dew point temperature range (non-condensing) ⁽²⁾

°C

T_DP-ELR

°C

English Data Sheet: DLPS228

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Applicable for the DMD as a component or non-operating in a system.

MIN

MAX

UNIT

CT_ELR

Cumulative time in elevated dew point temperature range

months

(1) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(2) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total

cumulative time of CT_ELR

6.3 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-C101,

all pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

NOM

MAX

UNIT

SUPPLY VOLTAGE RANGE⁽³⁾

V_DD

Supply voltage for LVCMOS core logic

1.65

1.8

1.95

Supply voltage for LPSDR low-speed interface

V_DDI

Supply voltage for SubLVDS receivers

1.65

9.5

1.8

1.95

10.5

18.5

–13.5

0.3

V_OFFSET

V_BIAS

Supply voltage for HVCMOS and micromirror electrode⁽⁴⁾

Supply voltage for micromirror electrode

Supply voltage delta (absolute value)⁽⁵⁾

Supply voltage delta (absolute value)⁽⁶⁾

Supply voltage delta (absolute value)⁽⁷⁾

17.5

V_RESET

–14.5

–14

|V_DDI–V_DD

10.5

|V_BIAS–V_OFFSET

|V_BIAS–V_RESET

CLOCK FREQUENCY

Clock frequency for low speed interface LS_CLK⁽⁸⁾

108

300

120

540

MHz

ƒ_clock

Clock frequency for high speed interface DCLK⁽⁹⁾

Duty cycle distortion DCLK

44%

56%

SUBLVDS INTERFACE⁽⁹⁾

|V_ID

150

700

575

250

900

350

1100

1225

110

SubLVDS input differential voltage (absolute value). See 图6-8, 图6-9

Common mode voltage. See 图6-8, 图6-9

SubLVDS voltage. See 图6-8, 图6-9

V_CM

V_SUBLVDS

Z_LINE

Z_IN

Line differential impedance (PWB/trace)

100

Ω

120

Internal differential termination resistance. See 图6-10

100-Ωdifferential PCB trace

6.35

152.4

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6.4 Recommended Operating Conditions (continued)

Over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

NOM

MAX

UNIT

ENVIRONMENTAL

Array Temperature –long-term operational^{(10) (11) (12) (13)}

T_ARRAY

40 to

70⁽¹²⁾

°C

Array Temperature –short-term operational, 25 hr max^{(11) (14)}

Array Temperature –short-term operational, 500 hr max^{(11) (14)}

Window Temperature –operational^{(15) (16)}

–10

-20

-10

°C

T_WINDOW

|T_DELTA

Absolute temperature delta between any point on the window edge and the

ceramic test point TP1⁽¹⁷⁾

T_DP-AVG

T_DP-ELR

CT_ELR

Average dew point temperature (non-condensing) ⁽¹⁸⁾

Elevated dew point temperature range (non-condensing) ⁽¹⁹⁾

Cumulative time in elevated dew point temperature range

°C

months

ILLUMINATION

ILL_UV

Illumination power at wavelengths < 410 nm⁽¹⁰⁾

10 mW/cm²

26.1 W/cm²

10 mW/cm²

8.3 W/cm²

1.5 W/cm²

Illumination power at wavelengths ≥410 nm and ≤800 nm⁽²⁰⁾

Illumination power at wavelengths > 800 nm

ILL_VIS

ILL_IR

Illumination power at wavelengths ≥410 nm and ≤475 nm⁽²⁰⁾

Illumination power at wavelengths ≥410 nm and ≤445 nm⁽²⁰⁾

Illumination marginal ray angle⁽¹⁵⁾

ILL_BLU

ILL_BLU1

ILL_θ

deg

(1) The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by

the 节6.4. No level of performance is implied when operating the device above or below the 节6.4 limits.

(2) The following power supplies are all required to operate the DMD: V_DD, V_DDI, V_OFFSET, V_BIAS, and V_RESET. All V_SSconnections are also

required.

(3) All voltage values are with respect to the ground pins (V_SS).

(4) V_OFFSETsupply transients must fall within specified max voltages.

(5) To prevent excess current, the supply voltage delta |V_DDI–V_DD| must be less than the specified limit.

(6) To prevent excess current, the supply voltage delta |V_BIAS–V_OFFSET| must be less than the specified limit.

(7) To prevent excess current, the supply voltage delta |V_BIAS–V_RESET| must be less than the specified limit.

(8) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.

(9) Refer to the SubLVDS timing requirements in 节6.7.

(10) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will

reduce device lifetime.

(11) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1

(TP1) shown in 图7-1 and the package thermal resistance using 节7.6.

(12) Per 图6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD

experiences in the end application. Refer to 节7.8 for a definition of micromirror landed duty cycle.

(13) Long-term is defined as the usable life of the device.

(14) Short-term is the total cumulative time over the useful life of the device.

(15) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including at the pond of

micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not

necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance

has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array

(including POM) will contribute to thermal limitations described in this document and may negatively affect lifetime.

(16) Window temperature is the highest temperature on the window edge shown in 图7-1. The location of thermal test point TP2 in 图7-1

is intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to

be at a higher temperature, that point should be used.

(17) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge shown in 图7-1.

The window test point TP2 shown in 图7-1 is intended to result in the worst-case delta temperature. If a particular application causes

another point on the window edge to result in a larger delta temperature, that point should be used.

(18) The average over time (including storage and operating) that the device is not in the 'elevated dew point temperature range'.

(19) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total

cumulative time of CT_ELR

(20) The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength

range specified and the micromirror array temperature (T_ARRAY).

English Data Sheet: DLPS228

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0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50

90/10 85/15 80/20 75/25 70/30 65/35 60/40 55/45

100/0 95/5

D001

Micromirror Landed Duty Cycle

图6-1. Maximum Recommended Array Temperature –Derating Curve

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6.5 Thermal Information

DLP160CP

FQT

THERMAL METRIC⁽¹⁾

UNIT

35 PINS

Thermal resistance

Active area to test point 1 (TP1)⁽¹⁾

°C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in the 节6.4. The total heat load on the DMD is largely driven by the

incident light absorbed by the active area, although other contributions include light energy absorbed by the window aperture and

electrical power dissipated by the array. Optical systems should be designed to minimize the light energy falling outside the window

clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS⁽²⁾

MIN

TYP

MAX UNIT

CURRENT

V_DD= 1.95 V

(3) (4)

I_DD

Supply current: V_DD

Supply current: V_DDI

V_DD= 1.8 V

V_DDI= 1.95 V

V_DDI= 1.8 V

I_DDI

V_OFFSET= 10.5 V

V_OFFSET= 10 V

V_BIAS= 18.5 V

V_BIAS= 18 V

(5) (6)

I_OFFSET

Supply current: V_OFFSET

0.9

0.18

0.2

(5) (6)

I_BIAS

Supply current: V_BIAS

Supply current: V_RESET

-0.9

V_RESET= –14.5 V

V_RESET= –14 V

(6)

I_RESET

-0.8

POWER⁽⁷⁾

P_DD

V_DD= 1.95 V

97.5

(3) (4)

Supply power dissipation: V_DD

Supply power dissipation: V_DDI

V_DD= 1.8 V

68.4

14.4

V_DDI= 1.95 V

V_DD= 1.8 V

23.4

P_DDI

(5)

V_OFFSET= 10.5 V

V_OFFSET= 10 V

V_BIAS= 18.5 V

V_BIAS= 18 V

10.5

Supply power dissipation: V_OFFSET

P_OFFSET

(6)

3.7

(5) (6)

P_BIAS

Supply power dissipation: V_BIAS

3.2

13.1

V_RESET= –14.5 V

V_RESET= –14 V

(6)

P_RESET

Supply power dissipation: V_RESET

Supply power dissipation: Total

11.2

106

P_TOTAL

LPSDR INPUT⁽⁸⁾

148

V_IH(DC)

V_IL(DC)

V_IH(AC)

V_IL(AC)

∆V_T

DC input high voltage⁽⁹⁾

0.7 × V_DD

–0.3

V_DD+ 0.3

0.3 × V_DD

V_DD+ 0.3

0.2 × V_DD

0.4 × V_DD

DC input low voltage⁽⁹⁾

AC input high voltage⁽⁹⁾

AC input low voltage⁽⁹⁾

Hysteresis ( V_T+–V_T–

Low–level input current

0.8 × V_DD

–0.3

0.1 × V_DD

)

图6-10

I_IL

V_DD= 1.95 V; V_I= 0 V

V_DD= 1.95 V; V_I= 1.95 V

–100

I_IH

100

High–level input current

LPSDR OUTPUT⁽¹⁰⁾

V_OHDC output high voltage

0.8 × V_DD

I_OH= –2 mA

English Data Sheet: DLPS228

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6.6 Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS⁽²⁾

MIN

TYP

MAX UNIT

V_OL

DC output low voltage

I_OL= 2 mA

0.2 × V_DD

CAPACITANCE

Input capacitance LPSDR

ƒ= 1 MHz

C_IN

Input capacitance SubLVDS

Output capacitance

ƒ= 1 MHz

C_OUT

ƒ= 1 MHz

C_RESET

Reset group capacitance

140

ƒ= 1 MHz; (360 × 160 micromirrors)

(1) Device electrical characteristics are over 节6.4 unless otherwise noted.

(2) All voltage values are with respect to the ground pins (V_SS).

(3) To prevent excess current, the supply voltage delta |V_DDI–V_DD| must be less than the specified limit.

(4) Supply power dissipation based on non–compressed commands and data.

(5) To prevent excess current, the supply voltage delta |V_BIAS–V_OFFSET| must be less than the specified limit.

(6) Supply power dissipation based on 3 global resets in 300 µs.

(7) The following power supplies are all required to operate the DMD: V_DD, V_DDI, V_OFFSET, V_BIAS, V_RESET. All V_SSconnections are also

required.

(8) LPSDR specifications are for pins LS_CLK and LS_WDATA.

(9) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC

Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.

(10) LPSDR specification is for pin LS_RDATA.

6.7 Timing Requirements

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

MIN

NOM

MAX UNIT

LPSDR

Rise slew rate⁽¹⁾

Fall slew rate⁽¹⁾

Rise slew rate⁽²⁾

Fall slew rate⁽²⁾

Cycle time LS_CLK

V/ns

t_r

(30% to 80%) × V_DD, 图6-3

(70% to 20%) × V_DD, 图6-3

(20% to 80%) × V_DD, 图6-3

(80% to 20%) × V_DD, 图6-3

图6-2

t_ƒ

0.25

7.7

t_r

t_ƒ

t_c

8.3

t_W(H)

Pulse duration LS_CLK

high

3.1

50% to 50% reference points, 图6-2

t_W(L)

t_su

3.1

1.5

Pulse duration LS_CLK low

Setup time

50% to 50% reference points, 图6-2

LS_WDATA valid before LS_CLK ↑, 图6-2

LS_WDATA valid after LS_CLK ↑, 图6-2

Setup time + hold time, 图6-2

t _h

Hold time

t_WINDOW

Window time^{(1) (3)}

For each 0.25 V/ns reduction in slew rate

below 1 V/ns, 图6-5

0.35

t_DERATING

Window time derating^{(1) (3)}

SubLVDS

t_r

Rise slew rate

0.7

V/ns

20% to 80% reference points, 图6-4

80% to 20% reference points, 图6-4

图6-6

t_ƒ

Fall slew rate

t_c

Cycle time DCLK

1.79

0.79

1.85

t_W(H)

t_W(L)

Pulse duration DCLK high

Pulse duration DCLK low

50% to 50% reference points, 图6-6

Setup and Hold times are defined

by t_WINDOW

D(0:7) valid before

DCLK ↑or DCLK ↓, 图6-6

t_su

Setup time

Hold time

Setup and Hold times are defined

by t_WINDOW

D(0:7) valid after

DCLK ↑or DCLK ↓, 图6-6

t _h

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6.7 Timing Requirements (continued)

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

MIN

NOM

MAX UNIT

t_WINDOW

Window time

0.3

Setup time + hold time, 图6-6, 图6-7

t_LVDS-

Power-up receiver⁽⁴⁾

2000

ENABLE+REFGEN

(1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in 图6-3.

(2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in 图6-3.

(3) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.

(4) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.

w(L)

w(H)

LS_CLK

50%

LS_WDATA

50%

window

Low-speed interface is LPSDR and adheres to the 节6.6 and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low

Power Double Data Rate (LPDDR) JESD209B.

图6-2. LPSDR Switching Parameters

LS_CLK, LS_WDATA

DMD_DEN_ARSTZ

1.0 * VDD

0.8 * VDD

V_IH(AC)

V_IH(DC)

0.8 * VDD

0.7 * VDD

V_IL(DC)

V_IL(AC)

0.3 * VDD

0.2 * VDD

0.0 * VDD

t_r

t_f

t_r

t_f

图6-3. LPSDR Input Rise and Fall Slew Rate

English Data Sheet: DLPS228

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图6-4. SubLVDS Input Rise and Fall Slew Rate

V_{IH MIN}

LS_CLK Midpoint

V_{IL MAX}

t_SU

t_H

V_{IH MIN}

LS_WDATA Midpoint

V_{IL MAX}

t_WINDOW

V_{IH MIN}

Midpoint

LS_CLK

V_{IL MAX}

t_DERATING

t_H

t_SU

V_{IH MIN}

Midpoint

V_{IL MAX}

LS_WDATA

t_WINDOW

图6-5. Window Time Derating Concept

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图6-6. SubLVDS Switching Parameters

Note: Refer to 节7.3.3 for details.

图6-7. High-Speed Training Scan Window

图6-8. SubLVDS Voltage Parameters

English Data Sheet: DLPS228

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1.225V

= V

+ | 1/2 * V

ID max

SubLVDS max

CM max

= V

– | 1/2 * V

SubLVDS min

CM min

ID max

0.575V

图6-9. SubLVDS Waveform Parameters

图6-10. SubLVDS Equivalent Input Circuit

Not to Scale

T+

Δ V

T-

LS_CLK

LS_WDATA

图6-11. LPSDR Input Hysteresis

LS_CLK

LS_WDATA

Stop Start

t_PD

LS_RDATA

Acknowledge

图6-12. LPSDR Read Out

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Data Sheet Timing Reference Point

Device Pin

Tester Channel

Output Under Test

See 节7.3.4 for more information.

图6-13. Test Load Circuit for Output Propagation Measurement

6.8 Switching Characteristics

Over operating free-air temperature range (unless otherwise noted). ⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output propagation, clock to Q, rising

edge of LS_CLK input to LS_RDATA

output. See 图6-12.

C_L= 45 pF

t_PD

Slew rate, LS_RDATA

0.5

V/ns

Output duty cycle distortion, LS_RDATA

40%

60%

(1) Device electrical characteristics are over 节6.4 unless otherwise noted.

English Data Sheet: DLPS228

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6.9 System Mounting Interface Loads

PARAMETER

MIN

NOM

MAX

UNIT

Maximum system mounting interface load to be applied to the:

•

Thermal interface area ⁽¹⁾

Clamping and electrical interface area ⁽¹⁾

(1) Uniformly distributed within area shown in 图6-14.

Datum ‘A’ Area

(3 places)

Datum ‘E’ Area

(1 place)

Thermal Interface Area

Electrical Interface Area

图6-14. System Interface Loads

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6.10 Micromirror Array Physical Characteristics

PARAMETER

VALUE

640

UNIT

micromirrors

µm

Number of active columns

Number of active rows

Micromirror (pixel) pitch

See 图6-15

See 图6-16

360

5.4

Micromirror active array

width

3.456

Micromirror pitch × number of active columns; see 图6-15

Micromirror active array

height

1.944

Micromirror pitch × number of active rows; see 图6-15

Micromirror active border Pond of micromirror (POM)⁽¹⁾

micromirrors/side

(1) The structure and qualities of the border around the active array include a band of partially functional micromirrors called the POM.

These micromirrors are structurally or electrically prevented from tilting toward the bright or ON state, but still require an electrical bias

to tilt toward OFF.

Not to scale

3.456 mm

359

358

357

Incident

Illumination

light path

DMD active mirror array

640 mirrors x 360 mirrors

图6-15. Micromirror Array Physical Characteristics

图6-16. Mirror (Pixel) Pitch

English Data Sheet: DLPS228

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6.11 Micromirror Array Optical Characteristics

PARAMETER

Micromirror tilt angle

TEST CONDITIONS

MIN

NOM

MAX

UNIT

degree

DMD landed state⁽¹⁾

Micromirror tilt angle tolerance^{(2) (3) (4) (5)}

1.4

–1.4

Landed ON state

Landed OFF state

Typical performance

Gray 10 Screen ⁽¹²⁾

White Screen

180

270

Micromirror tilt direction ^{(6) (7)}

degree

µs

Micromirror crossover time⁽⁸⁾

Micromirror switching time⁽⁹⁾

Bright pixel(s) in active area ⁽¹¹⁾

Bright pixel(s) in the POM ⁽¹³⁾

Image

performance

Dark pixel(s) in the active area ⁽¹⁴⁾

Adjacent pixel(s) ⁽¹⁵⁾

micromirrors

(10)

Any Screen

Unstable pixel(s) in active area ⁽¹⁶⁾

Any Screen

(1) Measured relative to the plane formed by the overall micromirror array.

(2) Additional variation exists between the micromirror array and the package datums.

(3) Represents the landed tilt angle variation relative to the nominal landed tilt angle.

(4) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different

devices.

(5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some

system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field

reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result

in colorimetry variations, system efficiency variations, or system contrast variations.

(6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of

the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON state

direction. A binary value of 0 results in a micromirror landing in the OFF state direction. See 图6-17.

(7) Micromirror tilt direction is measured as in a typical polar coordinate system: Measuring counter-clockwise from a 0° reference which is

aligned with the +X Cartesian axis.

(8) The time required for a micromirror to nominally transition from one landed state to the opposite landed state.

(9) The minimum time between successive transitions of a micromirror.

(10) Conditions of Acceptance: All DMD image quality returns will be evaluated using the following projected image test conditions:

Test set degamma shall be linear

Test set brightness and contrast shall be set to nominal

The diagonal size of the projected image shall be a minimum of 20 inches

The projections screen shall be 1X gain

The projected image shall be inspected from a 38 inch minimum viewing distance

The image shall be in focus during all image quality tests

(11) Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels

(12) Gray 10 screen definition: All areas of the screen are colored with the following settings:

Red = 10/255

Green = 10/255

Blue = 10/255

(13) POM definition: Rectangular border of off-state mirrors surrounding the active area

(14) Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels

(15) Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster

(16) Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable

pixel appears to be flickering asynchronously with the image

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(359, 639)

Incident

Illumination

light path

Tilted axis of

pixel rotation

On-state

landed edge

Off-state

landed edge

(0,0)

Off-state

light path

图6-17. Landed Pixel Orientation and Tilt

English Data Sheet: DLPS228

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6.12 Window Characteristics

PARAMETER⁽¹⁾

MIN

NOM

Corning Eagle XG

1.5119

MAX UNIT

Window material

Window refractive index

Window aperture

At wavelength 546.1 nm

See ⁽¹⁾

Illumination overfill

Minimum within the wavelength range

420 to 680 nm. Applies to all angles 0° to

30° AOI.

97%

Window transmittance, single-pass

through both surfaces and glass

Average over the wavelength range 420

to 680 nm. Applies to all angles 30° to

45° AOI.

(1) See 节7.5 for more information.

6.13 Chipset Component Usage Specification

备注

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system

operating conditions exceeding limits described previously.

The DLP160CP is a component of one or more DLP chipsets. Reliable function and operation of the DLP160CP

requires that it be used in conjunction with the other components of the applicable DLP chipset, including those

components that contain or implement TI DMD control technology. TI DMD control technology consists of the TI

technology and devices used for operating or controlling a DLP DMD.

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7 Detailed Description

7.1 Overview

The is a 0.16-inch diagonal spatial light modulator of aluminum micromirrors. Pixel array size is 640 columns by

360 rows in a square grid pixel arrangement. The electrical interface is sub low voltage differential signaling

(SubLVDS) data.

The is part of the chipset comprised of the DMD, the DLPC3421ZVB display controller, and the DLPA2000/2005

PMIC/LED driver. To ensure reliable operation, the DMD must always be used with the DLPC3421ZVB display

controller and the DLPA2000/2005 PMIC/LED drivers.

7.2 Functional Block Diagram

English Data Sheet: DLPS228

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7.3 Feature Description

7.3.1 Power Interface

The power management IC DLPA2000/2005 contains three regulated DC supplies for the DMD reset circuitry:

V_BIAS, V_RESETand V_OFFSET, as well as the two regulated DC supplies for the DLPC3421ZVB controller.

7.3.2 Low-Speed Interface

The low speed interface handles instructions that configure the DMD and control reset operation. LS_CLK is the

low–speed clock, and LS_WDATA is the low speed data input.

7.3.3 High-Speed Interface

The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high speed

DDR transfer and compression techniques to save power and time. The high-speed interface is composed of

differential SubLVDS receivers for inputs with a dedicated clock.

7.3.4 Timing

The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. 图 6-13 shows an equivalent test load circuit for the output

under test. Timing reference loads are not intended as a precise representation of any particular system

environment or depiction of the actual load presented by a production test. System designers should use IBIS or

other simulation tools to correlate the timing reference load to a system environment. The load capacitance

value stated is only for characterization and measurement of AC timing signals. This load capacitance value

does not indicate the maximum load the device is capable of driving.

7.4 Device Functional Modes

DMD functional modes are controlled by the DLPC3421ZVB controller. See the DLPC3421ZVB controller data

sheet or contact a TI applications engineer.

7.5 Optical Interface and System Image Quality Considerations

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment

optical performance involves making trade-offs between numerous component and system design parameters.

Optimizing system optical performance and image quality strongly relate to optical system design parameter

trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical

performance is contingent on compliance to the optical system operating conditions described in the following

sections.

7.5.1 Numerical Aperture and Stray Light Control

The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area

should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate

apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the

projection lens. The mirror tilt angle defines DMD capability to separate the ON optical path from any other light

path, including undesirable flat–state specular reflections from the DMD window, DMD border structures, or

other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the

mirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger than the

illumination numerical aperture angle, objectionable artifacts in the display border and/or active area could occur.

7.5.2 Pupil Match

TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally

centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable

artifacts in the display border and/or active area, which may require additional system apertures to control,

especially if the numerical aperture of the system exceeds the pixel tilt angle.

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7.5.3 Illumination Overfill

The active area of the device is surrounded by an aperture on the inside DMD window surface that masks

structures of the DMD chip assembly from normal view and is sized to anticipate several optical operating

conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window

aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system

should be designed to limit the total light flux incident anywhere on the window aperture from exceeding

approximately 10% of the total light flux in the active array. Depending on the particular optical architecture,

overfill light may have to be further reduced below the suggested 10% level in order to be acceptable.

7.6 Micromirror Array Temperature Calculation

Array

TP2

Illumination

Direction

3.60

Off-state

Light

TP2

TP1

0.60

8.10

图7-1. DMD Thermal Test Points

Micromirror array temperature cannot be measured directly, therefore it must be computed analytically from

measurement points on the outside of the package, the package thermal resistance, the electrical power, and

the illumination heat load. The relationship between array temperature and the reference ceramic temperature

(thermal test point TP1 in 图7-1) is provided by the following equations:

T_ARRAY= T_CERAMIC+ (Q_ARRAY× R_{ARRAY-TO-CERAMIC}

)

Q_ARRAY= Q_ELECTRICAL+ Q_ILLUMINATION

where

•

T_ARRAY= Computed array temperature (°C)

T_CERAMIC= Measured ceramic temperature (°C) (TP1 location)

English Data Sheet: DLPS228

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•

R_{ARRAY-TO-CERAMIC}= Thermal resistance of package specified in 节6.5 from array to ceramic TP1 (°C/Watt)

Q_ARRAY= Total DMD power on the array (W) (electrical + absorbed)

Q_ELECTRICAL= Nominal electrical power (W)

Q_INCIDENT= Incident illumination optical power (W)

Q_ILLUMINATION= (DMD average thermal absorptivity × Q_INCIDENT) (W)

DMD average thermal absorptivity = 0.4

The electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating

frequencies. A nominal electrical power dissipation to use when calculating array temperature is 0.07 Watts. The

absorbed power from the illumination source is variable and depends on the operating state of the micromirrors

and the intensity of the light source. The equations shown above are valid for a single chip or multichip DMD

system. It assumes an illumination distribution of 83.7% on the active array, and 16.3% on the array border.

The sample calculation for a typical projection application is as follows:

Q_INCIDENT= 1.4 W (measured)

T_CERAMIC= 55.0°C (measured)

Q_ELECTRICAL= 0.07 W

Q_ARRAY= 0.07 W + (0.40 × 1.4 W) =0.63 W

T_ARRAY= 55.0°C + (0.63 W × 13.0°C/W) = 63.2°C

7.7 Micromirror Power Density Calculation

The calculation of the optical power density of the illumination on the DMD in the different wavelength bands

uses the total measured optical power on the DMD, percent illumination overfill, area of the active array, and

ratio of the spectrum in the wavelength band of interest to the total spectral optical power.

• ILL_UV= [OP_UV-RATIO× Q_INCIDENT] × 1000 ÷ A_ILL(mW/cm²)

• ILL_VIS= [OP_VIS-RATIO× Q_INCIDENT] ÷ A_ILL(W/cm²)

• ILL_IR= [OP_IR-RATIO× Q_INCIDENT] × 1000 ÷ A_ILL(mW/cm²)

• ILL_BLU= [OP_BLU-RATIO× Q_INCIDENT] ÷ A_ILL(W/cm²)

• ILL_BLU1= [OP_BLU1-RATIO× Q_INCIDENT] ÷ A_ILL(W/cm²)

• A_ILL= A_ARRAY÷ (1 - OV_ILL) (cm²)

where:

• ILL_UV= UV illumination power density on the DMD (mW/cm²)

• ILL_VIS= VIS illumination power density on the DMD (W/cm²)

• ILL_IR= IR illumination power density on the DMD (mW/cm²)

• ILL_BLU= BLU illumination power density on the DMD (W/cm²)

• ILL_BLU1= BLU1 illumination power density on the DMD (W/cm²)

• A_ILL= illumination area on the DMD (cm²)

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• Q_INCIDENT= total incident optical power on DMD (W) (measured)

• A_ARRAY= area of the array (cm ²) (data sheet)

• OV_ILL= percent of total illumination on the DMD outside the array (%) (optical model)

• OP_UV-RATIO= ratio of the optical power for wavelengths <410 nm to the total optical power in the illumination

spectrum (spectral measurement)

• OP_VIS-RATIO= ratio of the optical power for wavelengths ≥410 and ≤800 nm to the total optical power in the

illumination spectrum (spectral measurement)

• OP_IR-RATIO= ratio of the optical power for wavelengths >800 nm to the total optical power in the illumination

spectrum (spectral measurement)

• OP_BLU-RATIO= ratio of the optical power for wavelengths ≥410 and ≤475 nm to the total optical power in the

illumination spectrum (spectral measurement)

• OP_BLU1-RATIO= ratio of the optical power for wavelengths ≥410 and ≤445 nm to the total optical power in the

illumination spectrum (spectral measurement)

The illumination area varies and depends on the illumination overfill. The total illumination area on the DMD is

the array area and overfill area around the array. The optical model is used to determine the percent of the total

illumination on the DMD that is outside the array (OV_ILL) and the percent of the total illumination that is on the

active array. From these values the illumination area (A_ILL) is calculated. The illumination is assumed to be

uniform across the entire array.

From the measured illumination spectrum, the ratio of the optical power in the wavelength bands of interest to

the total optical power is calculated.

Sample calculation:

Q_INCIDENT= 1.40 W (measured)

A_ARRAY= (0.3456 × 0.1944) = 0.0672 cm²(data sheet)

OV_ILL= 16.3% (optical model)

OP_UV-RATIO= 0.00021 (spectral measurement)

OP_VIS-RATIO= 0.99977 (spectral measurement)

OP_IR-RATIO= 0.00002 (spectral measurement)

OP_BLU-RATIO= 0.28100 (spectral measurement)

OP_BLU1-RATIO= 0.03200 (spectral measurement)

A_ILL= 0.0672 ÷ (1 - 0.163) = 0.0803 cm²

ILL_UV= [0.00021 × 1.40W] × 1000 ÷ 0.0803 cm²= 3.66 mW/cm²

ILL_VIS= [0.99977 × 1.40W] ÷ 0.0803 cm²= 17.4 W/cm²

ILL_IR= [0.00002 × 1.40W] × 1000 ÷ 0.0803 cm²= 0.349 mW/cm²

ILL_BLU= [0.28100 × 1.40W] ÷ 0.0803 cm²= 4.90 W/cm²

ILL_BLU1= [0.03200 × 1.40W] ÷ 0.0803 cm²= 0.558 W/cm²

English Data Sheet: DLPS228

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7.8 Micromirror Landed-On/Landed-Off Duty Cycle

7.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle

The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a

percentage) that an individual micromirror is landed in the ON state versus the amount of time the same

micromirror is landed in the OFF state.

As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the ON state 100% of the

time (and in the OFF state 0% of the time), whereas 0/100 would indicate that the pixel is in the OFF state 100%

of the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time.

Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other

state (OFF or ON) is considered negligible and is thus ignored.

Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)

always add to 100.

7.8.2 Landed Duty Cycle and Useful Life of the DMD

Knowing the long-term average landed duty cycle (of the end product or application) is important because

subjecting all (or a portion) of the DMD micromirror array (also called the active array) to an asymmetric landed

duty cycle for a prolonged period of time can reduce the usable life of the DMD.

Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed

duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed

duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly

asymmetrical.

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7.8.3 Landed Duty Cycle and Operational DMD Temperature

Operational DMD temperature and landed duty cycle interact to affect the usable life of the DMD, and this

interaction can be exploited to reduce the impact that an asymmetrical landed duty cycle has on the usable life

of the DMD. The relationship between temperature and landed duty cycle is quantified in the de-rating curve

shown in 图6-1. The importance of this curve is that:

• All points along this curve represent the same usable life.

• All points above this curve represent lower usable life (and the further away from the curve, the lower the

usable life).

• All points below this curve represent higher usable life (and the further away from the curve, the higher the

usable life).

In practice, this curve specifies the maximum operating DMD temperature that the DMD should be operated at

for a given long-term average landed duty cycle.

7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application

During a given period of time, the landed duty cycle of a given pixel follows from the image content being

displayed by that pixel.

For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel

will experience close to a 100/0 landed duty cycle during that time period. Likewise, when displaying pure-black,

the pixel will experience close to a 0/100 landed duty cycle.

Between the two extremes (ignoring for the moment color and any image processing that may be applied to an

incoming image), the landed duty cycle tracks one-to-one with the gray scale value, as shown in 表7-1.

表7-1. Grayscale Value

and Nominal Landed Duty

Cycle

Grayscale

Value

Landed Duty

Cycle

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0/100

10/90

20/80

30/70

40/60

50/50

60/40

70/30

80/20

90/10

100/0

Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from

0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color

cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a

given primary must be displayed in order to achieve the desired white point.

During a given period of time, the landed duty cycle of a given pixel can be calculated as follows:

Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) +

(Blue_Cycle_%×Blue_Scale_Value)

(1)

where

English Data Sheet: DLPS228

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Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_% represent the percentage of the frame time that red, green,

and blue are displayed (respectively) to achieve the desired white point.

For example, assuming that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in

order to achieve the desired white point), then the landed duty cycle for various combinations of red, green, blue

color intensities would be as shown in 表7-2.

表7-2. Example Nominal Landed Duty Cycle for Full-

Color Pixels

Red Cycle

Percentage

Green Cycle

Percentage

Blue Cycle

Percentage

50%

20%

30%

Red Scale

Value

Green Scale

Blue Scale

Value

Landed Duty

Cycle

Value

100%

0/100

50/50

20/80

30/70

6/94

100%

12%

35%

7/93

60%

18/82

70/30

50/50

80/20

13/87

25/75

24/76

100/0

100%

12%

35%

60%

100%

12%

100%

The last factor to account for in estimating the landed duty cycle is any applied image processing. Within the

DLP controller DLPC3421ZVB, the two functions which affect the landed duty cycle are gamma and IntelliBright

™

Gamma is a power function of the form Output_Level = A × Input_Level^Gamma, where A is a scaling factor that is

typically set to 1.

In the DLPC3421ZVB controller, gamma is applied to the incoming image data on a pixel-by-pixel basis. A

typical gamma factor is 2.2, which transforms the incoming data as shown in 图7-2.

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100

Gamma = 2.2

Input Level (%)

90 100

D002

图7-2. Example of Gamma = 2.2

English Data Sheet: DLPS228

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From 图 7-2, if the gray scale value of a given input pixel is 40% (before gamma is applied), then gray scale

value will be 13% after gamma is applied. Therefore, it can be seen that since gamma has a direct impact

displayed gray scale level of a pixel, it also has a direct impact on the landed duty cycle of a pixel.

The content adaptive illumination control (CAIC) and local area brightness boost (LABB) of the IntelliBright

algorithm also apply transform functions on the gray scale level of each pixel.

But while the amount of gamma applied to every pixel of every frame is constant (the exponent, gamma, is

constant), CAIC and LABB are both adaptive functions that can apply different amounts of either boost or

compression to every pixel of every frame.

Consideration must also be given to any image processing which occurs before the DLPC3421ZVB controller.

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two

directions, with the primary direction being into a projection or collection optic. Each application is derived

primarily from the optical architecture of the system and the format of the data coming into the DLPC3421

controller. The new high tilt pixel in the side-illuminated DMD increases brightness performance and enables a

smaller system footprint for thickness-constrained applications. Applications of interest include projection

technology embedded in display devices like ultra low-power battery operated mobile accessory projectors,

phones, tablets, ultra-mobile low-end Smart TVs, and virtual assistants.

DMD power-up and power-down sequencing is strictly controlled by the DLPA2000/2005. Refer to 节 9 for

power-up and power-down specifications. To ensure reliable operation, the DMD must always be used with the

DLPC3421 display controller and a DLPA2000/2005 PMIC/LED driver.

English Data Sheet: DLPS228

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8.2 Typical Application

A common application when using a DMD and a DLPC3421 is for creating a pico projector that can be used as

an accessory to a smartphone, tablet, or a laptop. The DLPC3421 in the pico projector receives images from a

multimedia front end within the product as shown in 图8-1.

Projector Module Electronics

BAT

2.3 V - 5.5 V

1.8 V

1.0 V

DC Supplies

Dual

Reg.

PWR_EN

SYSPWR

PROJ_ON

VLED

RESETZ

INTZ

PARKZ

RED

GREEN

BLUE

PROJ_ON

Flash

PAD2000

INIT_DONE

GPIO4

SPI(4)

BIAS, RST, OFS

Illumination

Optics

Host

Processor

Parallel or

BT.656

LED_SEL(2)

CLRL

DLPC3421

PWM_IN

RGB

24/16/8

DATA

CMP_OUT

WVGA

I2C

Thermistor

0.16 nHD

DDR DMD

CTRL

DATA

½ Bus sub-LVDS

1.8 V

1.0 V

VIO

VCORE

GPIO5

Included in DLP® Chip Set along with DMD

图8-1. Typical Application Diagram

8.2.1 Design Requirements

A pico projector is created by using a DLP chipset comprised of a DMD, a DLPC3421 controller, and a

DLPA2000/2005 PMIC/LED driver. The DLPC3421 controller performs the digital image processing, the

DLPA2000/2005 provides the needed analog functions for the projector, and the DMD is the display device for

producing the projected image.

In addition to the three DLP chips in the chipset, other chips are needed. At a minimum a flash part is needed to

store the DLPC3421 controller software.

The illumination light that is applied to the DMD is typically from red, green, and blue LEDs. These are often

contained in three separate packages, but sometimes more than one color of LED die may be in the same

package to reduce the overall size of the pico projector.

The DLPC3421 controller receives image data from the multimedia front end over a 24-bit parallel interface. An

I²C interface should be connected from the multimedia front end for sending commands to the DLPC3421

controller for configuring the chipset for different features.

8.2.2 Detailed Design Procedure

For instructions on how to connect the DLPC3421 controller, the DLPA2000/2005, and the DMD together, see

the reference design schematic. When a circuit board layout is created from this schematic a very small circuit

board is possible. An example small board layout is included in the reference design data base. Layout

guidelines should be followed to achieve a reliable projector.

The optical engine that has the LED packages and the DMD mounted to it is typically supplied by an optical

OEM who specializes in designing optics for DLP projectors.

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8.2.3 Application Curve

As the LED currents that are driven time-sequentially through the red, green, and blue LEDs are increased, the

brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white

screen lumens changes with LED currents is as shown in 图8-2. For the LED currents shown, it is assumed that

the same current amplitude is applied to the red, green, and blue LEDs.

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

500

1000

1500

Current (mA)

2000

2500

3000

D001

图8-2. Luminance vs Current

English Data Sheet: DLPS228

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9 Power Supply Recommendations

The following power supplies are all required to operate the DMD: V_DD, V_DDI, V_OFFSET, V_BIAS, and V_RESET. All

V_SSconnections are also required. DMD power-up and power-down sequencing is strictly controlled by the

DLPA2000/2005 devices.

CAUTION

For reliable operation of the DMD, the following power supply sequencing requirements must be

followed. Failure to adhere to the prescribed power-up and power-down procedures may affect

device reliability.

V_DD, V_DDI, V_OFFSET, V_BIAS, and V_RESETpower supplies have to be coordinated during power-up and

power-down operations. Failure to meet any of the below requirements will result in a significant

reduction in the reliability and lifetime of the DMD. Refer to 图9-2. V_SSmust also be connected.

9.1 Power Supply Power-Up Procedure

• During power-up, V_DDand V_DDImust always start and settle before V_OFFSET, V_BIAS, and V_RESETvoltages are

applied to the DMD.

• During power-up, it is a strict requirement that the delta between V_BIASand V_OFFSETmust be within the

specified limit shown in 节6.4. Refer to 图9-2 for power-up delay requirements.

• During power-up, the LPSDR input pins of the DMD shall not be driven high until after V_DDand V_DDIhave

settled at operating voltage.

• During power-up, there is no requirement for the relative timing of V_RESETwith respect to V_OFFSETand V_BIAS

Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the

requirements listed previously and in 图9-1.

9.2 Power Supply Power-Down Procedure

• The power-down sequence is the reverse order of the previous power-up sequence. V_DDand V_DDImust be

supplied until after V_BIAS, V_RESET, and V_OFFSETare discharged to within 4 V of ground.

• During power-down, it is not mandatory to stop driving V_BIASprior to V_OFFSET, but it is a strict requirement that

the delta between V_BIASand V_OFFSETmust be within the specified limit shown in 节6.4 (Refer to Note 2 for 图

9-1).

• During power-down, the LPSDR input pins of the DMD must be less than V_DDI, the specified limit shown in 节

6.4.

• During power-down, there is no requirement for the relative timing of V_RESETwith respect to V_OFFSETand

V_BIAS

• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the

requirements listed previously and in 图9-1.

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9.3 Power Supply Sequencing Requirements

A. Refer to 表9-1 and 图9-2 for critical power-up sequence delay requirements.

B. To prevent excess current, the supply voltage delta |V_BIAS–V_OFFSET| must be less than specified in 节6.4. OEMs may find that the

most reliable way to ensure this is to power V_OFFSETprior to V_BIASduring power-up and to remove V_BIASprior to V_OFFSETduring power-

down. Refer to 表9-1 and 图9-2 for power-up delay requirements.

C. To prevent excess current, the supply voltage delta |V_BIAS–V_RESET| must be less than the specified limit shown in 节6.4.

D. When system power is interrupted, the DLPA2000/2005 initiates hardware power-down that disables V_BIAS, V_RESETand V_OFFSETafter

the micromirror park sequence.

E. Drawing is not to scale and details are omitted for clarity.

图9-1. Power Supply Sequencing Requirements (Power Up and Power Down)

English Data Sheet: DLPS228

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表9-1. Power-Up Sequence Delay Requirement

PARAMETER

MIN

MAX UNIT

t_DELAY

V_OFFSET

V_BIAS

Delay requirement from V_OFFSETpower up to V_BIASpower up

Supply voltage level at beginning of power–up sequence delay (see 图9-2)

Supply voltage level at end of power–up sequence delay (see 图9-2)

12 V

VOFFSET

8 V

VDD ≤ VOFFSET < 6 V

4 V

VSS

0 V

t_DELAY

20 V

16 V

12 V

8 V

VBIAS

VDD ≤ VBIAS < 6 V

4 V

VSS

0 V

Refer to 表9-1 for V_OFFSETand V_BIASsupply voltage levels during power-up sequence delay.

图9-2. Power-Up Sequence Delay Requirement

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10 Layout

10.1 Layout Guidelines

The DMD is connected to a PCB or a flex circuit using an interposer. For additional layout guidelines regarding

length matching, impedance, etc. see the DLPC3421 controller datasheet. For a detailed layout example refer to

the layout design files. Some layout guidelines for routing to the DMD are:

• Match lengths for the LS_WDATA and LS_CLK signals.

• Minimize vias, layer changes, and turns for the HS bus signals. Refer to 图10-1.

• Minimum of two 100-nF (25 V) capacitors - one close to V_BIASpin. Capacitors C4 and C8 in 图10-1.

• Minimum of two 100-nF (25 V) capacitors - one close to each V_RSTpin. Capacitors C3 and C7 in 图10-1.

• Minimum of two 220-nF (25 V) capacitors - one close to each V_OFSpin. Capacitors C5 and C6 in 图10-1.

• Minimum of four 100-nF (6.3 V) capacitors - two close to the VDD/VDDI pins on each side of the DMD.

Capacitors C1, C2, C9 and C10 in Figure 10-1.

10.2 Layout Example

图10-1. Power Supply Connections

English Data Sheet: DLPS228

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11 Device and Documentation Support

11.1 Device Support

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

11.1.2 Device Nomenclature

DLP160CP FQT

Package Type

Device Descriptor

图11-1. Part Number Description

11.1.3 Device Markings

The device marking includes the legible character string GHJJJJK 160CPFQT. GHJJJJK is the lot trace code.

160CPFQT is the abbreviated part number.

图11-2. DMD Marking

Lot Trace Code

GHJJJJK

160CPFQT

Part Marking

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.4 Trademarks

IntelliBright^™is a trademark of Texas Instruments.

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

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11.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

English Data Sheet: DLPS228

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PACKAGE OPTION ADDENDUM

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13-Jul-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

DLP160CPFQT

ACTIVE

CLGA

FQT

180

RoHS & Green

NI/AU

N / A for Pkg Type

0 to 70

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

DWG NO.

2517439

REVISIONS

NOTES UNLESS OTHERWISE SPECIFIED:

REV

DESCRIPTION

ECO 2191771: INITIAL RELEASE

DATE

1/4/2021

BMH

DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY.

ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION

TOLERANCE AND HAS A MAXIMUM ALLOWED VALUE OF 0.6 DEGREES.

BOUNDARY MIRRORS SURROUNDING THE DMD ACTIVE ARRAY.

NOTCH DIMENSIONS ARE DEFINED BY UPPERMOST LAYERS OF CERAMIC,

AS SHOWN IN SECTION A-A.

ENCAPSULANT TO BE CONTAINED WITHIN DIMENSIONS SHOWN IN VIEW C

(SHEET 2). NO ENCAPSULANT IS ALLOWED ON TOP OF THE WINDOW.

ENCAPSULANT NOT TO EXCEED THE HEIGHT OF THE WINDOW.

DATUM B IS DEFINED BY A DIA. 2.5 PIN, WITH A FLAT ON THE SIDE FACING

TOWARD THE CENTER OF THE ACTIVE ARRAY, AS SHOWN IN VIEW B (SHEET 2).

WHILE ONLY THE THREE DATUM A TARGET AREAS A1, A2, AND A3 ARE USED

FOR MEASUREMENT, ALL 4 CORNERS SHOULD BE CONTACTED, INCLUDING E1,

TO SUPPORT MECHANICAL LOADS.

4X (R0.2)

1.1760.05

0.2

0.1

1.235

2.485

0.2

0.1

1.25

(ILLUMINATION

DIRECTION)

0.275

0.075

4.97

2.50.075

90°1°

(2.5)

4X R0.4 0.1

0.2

0.1

0.8

11.59 0.08

0.3

0.1

13.39

(OFF-STATE

DIRECTION)

0.7 0.05

2X ENCAPSULANT

1.003 0.077

0.038A

5 6

(1.783)

3 SURFACES INDICATED

IN VIEW B (SHEET 2)



0.02D

ACTIVE ARRAY

0.780.063

(2.5)

1.4 0.1

(1.4)

0.4 MIN

TYP.

(SHEET 3)

0 MIN TYP.

DATE

DRAWN

UNLESS OTHERWISE SPECIFIED

DIMENSIONS ARE IN MILLIMETERS

TOLERANCES:

TEXAS

1/4/2021

B. HASKETT

ENGINEER

B. HASKETT

QA/CE

INSTRUMENTS

Dallas Texas

1/4/2021

1/8/2021

1/4/2021

1/13/2021

1/11/2021

ANGLES 1

TITLE

ICD, MECHANICAL, DMD,

.16 nHD SERIES 248

(FQT PACKAGE)

2 PLACE DECIMALS 0.25

1 PLACE DECIMALS 0.50

SECTION A-A

NOTCH OFFSETS

C. HART

DIMENSIONAL LIMITS APPLY BEFORE PROCESSES

INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME

Y14.5M-1994

REMOVE ALL BURRS AND SHARP EDGES

PARENTHETICAL INFORMATION FOR REFERENCE ONLY

F. KHAN

THIRD ANGLE

PROJECTION

DWG NO

REV

SIZE

0314DA

USED ON

G.HERMOSILLO

APPROVED

2517439

NEXT ASSY

SCALE

SHEET

APPLICATION

J. GRIMMETT

25:1

INV11-2006a

DWG NO.

2517439

2X (1)

2X 1.176

2X (0.8)

2X 11.59

4X 1.485

1.25

2.5

4X (1)

(1.1)

VIEW B

DATUMS A, B, C, AND E

(FROM SHEET 1)

1.176

11.59

2.585

1.25

5.17

(2.5)

VIEW C

ENCAPSULANT MAXIMUM X/Y DIMENSIONS

(FROM SHEET 1)

2X 0 MIN

VIEW D

DWG NO

REV

SIZE

ENCAPSULANT MAXIMUM HEIGHT

DRAWN

DATE

1/4/2021

TEXAS

2517439

B. HASKETT

INSTRUMENTS

Dallas Texas

SCALE

SHEET

INV11-2006a

DWG NO.

2517439

(3.456)

ACTIVE ARRAY

5.927 0.075

3 4X (0.108)

0.191 0.0635

0.9680.05

1.112 0.075

1.25

(ILLUMINATION

DIRECTION)

(1.944)

ACTIVE

ARRAY

(2.554)

APERTURE

2.363 0.0635

(4.16)

WINDOW

(2.5)

3.1920.05

0.4260.0635

2.464 0.05

3.6830.0635

(4.109)

APERTURE



4.5520.05

(7.016)

WINDOW

VIEW E

WINDOW AND ACTIVE ARRAY

(FROM SHEET 1)

7X (0.52) CIRCULAR TEST PADS

2.15

13 X 0.7424 = 9.6512

BACK SIDE

INDEX MARK

(42°)

TYP.

(42°)

TYP.

(0.15) TYP.

(0.075) TYP.

1.485

4 X 0.7424

= 2.9696

(2.5)

1.25

(0.068) TYP.

(42°)

TYP.



35X SQUARE LGA PADS

0.52±0.05 X 0.52±0.05

0.2ABC

DETAIL G



DETAIL F

0.1A

APERTURE RIGHT EDGE

VIEW H-H

APERTURE LEFT EDGE

(WINDOW OMITTED FOR CLARITY)

SCALE 60 : 1

(WINDOW OMITTED FOR CLARITY)

SCALE 60 : 1

BACK SIDE METALLIZATION

(FROM SHEET 1)

DWG NO

REV

SIZE

DRAWN

DATE

1/4/2021

TEXAS

2517439

B. HASKETT

INSTRUMENTS

Dallas Texas

SCALE

SHEET

INV11-2006a

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