DCV010505P-U/700E4 [TI]
1-OUTPUT 1W DC-DC UNREG PWR SUPPLY MODULE, ROHS COMPLIANT, GULLWING, PLASTIC, DIP-14/7;
| 型号： | DCV010505P-U/700E4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1-OUTPUT 1W DC-DC UNREG PWR SUPPLY MODULE, ROHS COMPLIANT, GULLWING, PLASTIC, DIP-14/7 CD 光电二极管 输出元件 |
| 文件： | 总18页 (文件大小：400K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DCV01 Series
www.ti.com
SBVS014A –AUGUST 2000–REVISED DECEMBER 2013
Miniature, 1-W, 1500-Vrms Isolated
Unregulated DC-DC Converters
1
FEATURES
DESCRIPTION
The DCV01 series is a family of 1-W, 1500-Vrms
23
•
Up To 85% Efficiency
isolated, unregulated dc-dc converters. Requiring a
minimum of external components and including on-
chip device protection, the DCV01 series provides
extra features such as output disable and
synchronization of switching frequencies.
•
Thermal Protection
•
•
•
•
•
Device-to-Device Synchronization
Short-Circuit Protection
EN55022 Class B EMC Performance
UL1950 Recognized Component
JEDEC PDIP-14 and Gull-Wing Packages
The use of a highly integrated package design results
in highly reliable products with a power density of
40 W/in3 (2.4 W/cm3). This combination of features,
high isolation, and small size makes the DCV01
suitable for a wide range of applications.
APPLICATIONS
•
•
•
•
•
•
Industrial Control and Instrumentation
Point-of-Use Power Conversion
Ground Loop Elimination
Data Acquisition
Test Equipment
Secondary Isolation Circuits
SYNCOUT
800kHz
Oscillator
Divide-by-2
VOUT
0V
Reset
Power
Stage
Watchdog/
Start Up
SYNCIN
PSU
Thermal
Shutdown
IBIAS
VS
Power Controller IC
0V
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
Underwriters Laboratories, UL are trademarks of UL LLC.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
DCV01 Series
SBVS014A –AUGUST 2000–REVISED DECEMBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
data sheet, or visit the device product folder at www.ti.com.
SUPPLEMENTAL ORDERING INFORMATION
DCV01 05 05 (D)
( )
Basic Model Number: 1-W Product
Voltage Input:
5-V In
Voltage Output:
5-V Out
Dual Output:
Package Code:
P = PDIP-14
P-U = SOP-14
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
V
5-V input models
7
Input voltage
15-V input models
24-V input models
18
29
V
V
Storage temperature range
–60 to +125
+270
°C
°C
Lead temperature (soldering, 10 s)
2
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DCV01 Series
www.ti.com
SBVS014A –AUGUST 2000–REVISED DECEMBER 2013
ELECTRICAL CHARACTERISTICS
At TA = +25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Power
Ripple
100% full load
0.97
20
W
O/P capacitor = 1-μF, 50% load
Room to cold
mVPP
%/°C
%/°C
0.046
0.016
Voltage vs temperature
Room to hot
INPUT
Voltage range on VS
ISOLATION
–10%
10%
1-s flash test
UL1950(1)
1.5
1.5
kVrms
kVrms
Voltage
LINE
Regulation
1
%/1% of VS
SWITCHING/SYNCHRONIZATION
Oscillator frequency (fOSC
)
Switching frequency = fOSC / 2
VSYNC = +2 V
800
kHz
V
(2)
Sync input low
0
0.4
(2)
Sync input current
75
2
μA
μs
pF
Disable time
Capacitance loading on SYNCIN pin
RELIABILITY
External
3
Demonstrated
TA = +55°C
75
FITS
THERMAL SHUTDOWN
IC temperature at shutdown
Shutdown current
+150
3
°C
mA
TEMPERATURE
Operating range
–40
+85
°C
(1) During UL1950 recognition test only. UL file # E199929.
(2) For more information on synchronization, refer to Application Report SBAA035., External Synchronization of the DCP01/02, DCR01/02,
and DCV01 Series of DC/DC Converters.
ELECTRICAL CHARACTERISTICS PER DEVICE
At TA = +25°C, unless otherwise noted.
INPUT
VOLTAGE
(V)
OUTPUT
VOLTAGE
(V)
LOAD
REGULATION
(%)
NO LOAD
BARRIER
LEAKAGE
CURRENT
(μA)
CURRENT EFFICIENCY CAPACITANCE
(mA)
IQ
(%)
(pF)
CISO
VS
VNOM
10% TO 100%
LOAD(2)
75% LOAD(1)
0% LOAD
100% LOAD VISO = 750 Vrms VISO = 750 Vrms
PRODUCT
DCV010505
DCV010505D
DCV010512
DCV010512D
DCV010515
DCV010515D
DCV011512D
DCV011515D
DCV012405
DCV012415D
MIN
TYP MAX
MIN
TYP
5
MAX
5.25
TYP
23
19
23
19
30
27
11
12
13
12
MAX
31
32
38
37
42
41
39
39
23
35
TYP
20
23
30
40
34
42
19
20
14
17
TYP
78
80
85
82
84
85
78
79
77
76
TYP
3.6
3.8
5.1
4.0
3.8
4.7
4.2
4.2
3.8
5.3
TYP
0.9
0.9
1.2
1.0
0.9
1.1
1.0
1.0
0.9
1.3
4.5
4.5
5
5
5.5
5.5
5.5
5.5
5.5
4.75
±4.25
11.4
±5
±5.75
12.6
4.5
5
12
4.5
5
±11.4
14.25
±12
15
±12.6
15.75
4.5
5
4.5
5
5.5 ±14.25
±15 ±15.75
±12 ±12.6
±15 ±15.75
5.25
±15 ±15.75
13.5
13.5
21.6
21.6
15
15
24
24
16.5
±11.4
16.5 ±14.25
26.4
4.75
5
26.4 ±14.25
(1) 100% load current = 1 W/VNOM typical.
(2) Load regulation = (VOUT at 10% – VOUT at 100%)/VOUT at 75%.
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SBVS014A –AUGUST 2000–REVISED DECEMBER 2013
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PIN CONFIGURATION: SINGLE OUTPUT
NVA AND DUA PACKAGES
PDIP-14 AND SOP-14
(TOP VIEW)
VS
0V
1
2
14 SYNCIN
DCV01
0V
+VOUT
NC
5
6
7
8
SYNCOUT
Table 1. Pin Descriptions (Single Output)
PIN NAME
VS
PIN NO.
DESCRIPTION
1
2
Voltage input
0V
Input side common
Output side common
+Voltage out
0V
5
+VOUT
NC
6
7
Not connected
SYNCOUT
SYNCIN
8
Unrectified transformer output
Synchronization pin
14
PIN CONFIGURATION: DUAL OUTPUT
NVA AND DUA PACKAGES
PDIP-14 AND SOP-14
(TOP VIEW)
VS
0V
1
2
14 SYNCIN
DCV01D
0V
+VOUT
-VOUT
5
6
7
8
SYNCOUT
Table 2. Pin Descriptions (Dual Output)
PIN NAME
VS
PIN NO.
DESCRIPTION
1
2
Voltage input
0V
Input side common
Output side common
+Voltage out
0V
5
+VOUT
–VOUT
SYNCOUT
SYNCIN
6
7
–Voltage out
8
Unrectified transformer output
Synchronization pin
14
4
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DCV01 Series
www.ti.com
SBVS014A –AUGUST 2000–REVISED DECEMBER 2013
TYPICAL CHARACTERISTICS
At TA = +25°C, unless otherwise noted.
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.00
50
45
40
35
30
25
20
15
10
5
1-mF Ceramic
4.7-mF Ceramic
10-mF Ceramic
+VOUT
-VOUT
0
10
20
30
40
50
60
70
80
90 100
10
20
30
40
50
60
70
80
90 100
Load (%)
Load (%)
Figure 1. DCV010505 OUTPUT RIPPLE vs LOAD
(20-MHz BW)
Figure 2. DCV010512D VOUT vs LOAD
85
80
75
70
65
60
55
50
18
17
16
15
14
+VOUT
-VOUT
10
20
30
40
50
Load (%)
Figure 3. DCV010512D EFFICIENCY vs LOAD
60
70
80
90 100
10
20
30
40
50
60
70
80
90 100
Load (%)
Figure 4. DCV010515D VOUT vs LOAD
90
85
80
75
70
65
60
55
50
5.60
5.50
5.40
5.30
5.20
5.10
5.00
4.90
4.80
10
20
30
40
50
Load (%)
Figure 5. DCV010515D EFFICIENCY vs LOAD
60
70
80
90 100
10
20
30
40
50
60
70
80
100
Load (%)
Figure 6. DCV012405 VOUT vs LOAD
Copyright © 2000–2013, Texas Instruments Incorporated
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DCV01 Series
SBVS014A –AUGUST 2000–REVISED DECEMBER 2013
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, unless otherwise noted.
90
60
50
80
70
60
50
40
30
20
10
0
40
30
20
10
0
-10
-20
10
20
30
40
50
60
70
80
90
100
0.15
1
10
30
Load (%)
Frequency (MHz)
Figure 7. DCV012405 EFFICIENCY vs LOAD
Figure 8. DCV010505 CONDUCTED EMISSIONS (125% Load)
60
50
40
30
20
10
0
-10
-20
0.15
1
10
30
Frequency (MHz)
Figure 9. DCV010505 CONDUCTED EMISSIONS (8% Load)
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DCV01 Series
www.ti.com
SBVS014A –AUGUST 2000–REVISED DECEMBER 2013
FUNCTIONAL DESCRIPTION
OVERVIEW
The DCV01 offers up to 1 W of unregulated output power with a typical efficiency of up to 85%. This is achieved
through highly integrated packaging technology and the implementation of a custom power stage and control IC.
The circuit design uses an advanced BiCMOS/DMOS process. Separate primary and secondary transformer
windings give good isolation and low barrier capacitance.
POWER STAGE
This uses a push-pull, center-tapped topology switching at 400 kHz (divide-by-2 from 800-kHz oscillator).
OSCILLATOR AND WATCHDOG
The onboard 800-kHz oscillator generates the switching frequency via a divide-by-2 circuit. The oscillator can be
synchronized to other DCV01 circuits or an external source, and is used to minimize system noise. A watchdog
circuit checks the operation of the oscillator circuit. The oscillator can be stopped by pulling the SYNCIN pin low.
The output pins will be tri-stated. This will occur in 2 μs.
THERMAL SHUTDOWN
The DCV01 is protected by a thermal-shutdown circuit. If the on-chip temperature exceeds 150°C, the device will
shut down. Once the temperature falls below 150°C, normal operation will resume.
SYNCHRONIZATION
In the event that more than one dc-dc converter is needed onboard, beat frequencies and other electrical
interference can be generated. This is due to the small variations in switching frequencies between the dc-dc
converters.
The DCV01 overcomes this by allowing devices to be synchronized to one another. Up to eight devices can be
synchronized by connecting the SYNCIN pins together, taking care to minimize the capacitance of tracking. Stray
capacitance (> 3 pF) will have the effect of reducing the switching frequency, or even stopping the oscillator
circuit.
It should be noted that if synchronized devices are used at start up, all devices will draw maximum current
simultaneously. This can cause the input voltage to dip, and if it dips below the minimum input voltage (4.5 V),
the devices may not start up. A 2.2-μF capacitor should be connected close to the input pins. If more than eight
devices are to be synchronized, it is recommended that the SYNCIN pins are driven by an external device.
Details are contained in Application Report SBAA035, External Synchronization of the DCP01/02 Series of
DC/DC Converters, available for download from www.ti.com.
CONSTRUCTION
The basic construction of the DCV01 is the same as standard ICs. There is no substrate within the molded
package. The DCV01 is constructed using an IC, rectifier diodes, and a wound magnetic toroid on a leadframe.
Since there is no solder within the package, the DCV01 does not require any special printed circuit board (PCB)
assembly processing. This results in an isolated dc-dc converter with inherently high reliability.
Copyright © 2000–2013, Texas Instruments Incorporated
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DCV01 Series
SBVS014A –AUGUST 2000–REVISED DECEMBER 2013
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ADDITIONAL FUNCTIONS
DISABLE/ENABLE
The DCV01 can be disabled or enabled by driving the SYNC pin using an open drain CMOS gate. If the SYNCIN
pin is pulled low, the DCV01 will be disabled. The disable time depends upon the external loading; the internal
disable function is implemented in 2 μs. Removal of the pull down will cause the DCV01 to be enabled.
Capacitive loading on the SYNCIN pin should be minimized in order to prevent a reduction in the oscillator
frequency.
DECOUPLING
Ripple Reduction
The high switching frequency of 400 kHz allows simple filtering. To reduce ripple, it is recommended that at least
a 1-μF ceramic capacitor is used on VOUT. Dual outputs should both be decoupled to pin 5. A 2.2-μF low-ESR
ceramic capacitor on the input of the 5-V input versions, and a 0.47-μF low ESR cap on the 24-V input versions
is recommended.
Connecting the DCV01 in Series
Multiple DCV01 isolated 1W dc-dc converters can be connected in series to provide nonstandard voltage rails.
This is possible by using the floating outputs provided by the galvanic isolation of the DCV01.
Connect the positive VOUT from one DCV01 to the negative VOUT (0 V) of another, as shown in Figure 10. If the
SYNCIN pins are tied together, the self-synchronization feature of the DCV01 will prevent beat frequencies on the
voltage rails. The SYNCIN feature of the DCV01 allows easy series connection without external filtering, thus
minimizing cost. The outputs on the dual-output DCV01 versions can also be connected in series to provide two
times the magnitude of VOUT, as shown in Figure 11. For example, a dual 15-V DCV01 could be connected to
provide a 30-V rail.
VSUPPLY
VOUT1
VS
SYNCIN
DCV
01
0V
VS
0V
VOUT1 + VOUT2
VOUT2
DCV
01
SYNCIN
0V
0V
COM
Figure 10. Connecting the DCV01 in Series
VSUPPLY
+VOUT
VS
+VOUT
-VOUT
0V
DCV
01
-VOUT
0V
COM
Figure 11. Connecting Dual Outputs in Series
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DCV01 Series
www.ti.com
SBVS014A –AUGUST 2000–REVISED DECEMBER 2013
Connecting the DCV01 in Parallel
If the output power from one DCV01 is not sufficient, it is possible to parallel the outputs of multiple DCV01s, as
shown in Figure 12. Again, the SYNCIN feature allows easy synchronization to prevent power-rail beat
frequencies at no additional filtering cost.
VSUPPLY
VOUT
VS
SYNCIN
DCV
01
0V
0V
VS
2 x Power Out
VOUT
DCV
01
SYNCIN
0V
0V
COM
Figure 12. Connecting Multiple DCV01s in Parallel
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DCV01 Series
SBVS014A –AUGUST 2000–REVISED DECEMBER 2013
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PCB LAYOUT
RIPPLE AND NOISE
Careful consideration should be given to the layout of the PCB in order that the best results can be obtained.
The DCV01 is a switching power supply, and as such, can place high peak-current demands on the input supply.
In order to avoid the supply falling momentarily during the fast switching pulses, ground and power planes should
be used to track the power to the input of the DCV01. If this is not possible, then the supplies must be connected
in a star formation with the tracks made as wide as possible.
If the SYNCIN pin is being used, then the tracking between device SYNCIN pins should be short, in order to avoid
stray capacitance. If the SYNCIN pin is not being used, it is advisable to place a guard ring, (connected to input
ground) around this pin to avoid any noise pick up.
The output should be taken from the device using ground and power planes; this will ensure minimum losses.
A good quality low-ESR capacitor placed as close as practicable across the input will reduce reflected ripple and
ensure a smooth start up.
A good quality low-ESR capacitor placed as close as practicable across the rectifier output terminal and output
ground will give the best ripple and noise performance.
THERMAL MANAGEMENT
Due to the high power density of this device, it is advisable to provide ground planes on the input and output.
ISOLATION
Underwriters Laboratories, UL™ defines several classes of isolation that are used in modern power supplies.
Safety Extra Low Voltage (SELV) is defined by UL (UL1950 E199929) as a secondary circuit which is so
designated and protected that under normal and single fault conditions the voltage between any two accessible
parts, or between an accessible part and the equipment earthing terminal for operational isolation does not
exceed steady state 42V peak or 60VDC for more than 1 second.
DCH, DCP, DCR, and DCV Series DC-DC Converters
TI’s DCH, DCP, DCR, and DCV (DCx) series dc-dc converters are specified for operational isolation only.
Operation or Functional Isolation
Operational or functional isolation is defined by the use of a hipot test only. Typically, this isolation is defined as
the use of insulated wire in the construction of the transformer as the primary isolation barrier. The hipot one-
second duration test (dielectric voltage, withstand test) is a production test used to verify that the isolation barrier
is functioning. Products with operational isolation should never be used as an element in a safety-isolation
system.
Basic or Enhanced Isolation
Basic or enhanced isolation is defined by specified creepage and clearance limits between the primary and
secondary circuits of the power supply. Basic isolation is the use of an isolation barrier in addition to the insulated
wire in the construction of the transformer. Input and output circuits must also be physically separated by
specified distances.
Continuous Voltage
For a device that has no specific safety agency approvals (operational isolation), the continuous voltage that can
be applied across the part in normal operation is less than 42.4 V peak, or 60 VDC; that is, both input and output
should normally be maintained within SELV limits. The isolation test voltage represents a measure of immunity to
transient voltages; do not use the device as an element of a safety isolation system when SELV is exceeded. If
the device is expected to function correctly with more than 42.4 V peak or 60 VDC applied continuously across
the isolation barrier, then the circuitry on both sides of the barrier must be regarded as operating at an unsafe
voltage, and further isolation or insulation systems must form a barrier between these circuits and any user-
accessible circuitry according to safety standard requirements.
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DCV01 Series
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SBVS014A –AUGUST 2000–REVISED DECEMBER 2013
Isolation Voltage
Hipot test, flash-tested, withstand voltage, proof voltage, dielectric withstand voltage, and isolation test voltage
are all terms that relate to the same thing: a test voltage applied for a specified time across a component
designed to provide electrical isolation to verify the integrity of that isolation.
TI’s DCx series of dc-dc converters are all 100% production tested at their stated isolation voltage.
For the DCP and DCR series, this voltage is 1.0 kVDC for one second.
For the DCV series, this voltage is 1.5 kVDC for one second.
For the DCH series, this voltage is 3.5 kVDC for one second.
Repeated High-Voltage Isolation Testing
Repeated high-voltage isolation testing of a barrier component can degrade the isolation capability, depending on
materials, construction, and environment. The DCx series of dc-dc converters have toroidal, enameled, wire
isolation transformers with no additional insulation between the primary and secondary windings. While a device
can be expected to withstand several times the stated test voltage, the isolation capability depends on the wire
insulation. Any material, including this enamel (typically polyurethane), is susceptible to eventual chemical
degradation when subject to very-high applied voltages. Therefore, strictly limit the number of high-voltage tests
and repeated high-voltage isolation testing. However, if it is absolutely required, reduce the voltage by 20% from
specified test voltage with a duration limit of one second per test.
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2000) to Revision A
Page
•
•
•
•
•
•
•
•
Changed data sheet format to latest standard look .............................................................................................................. 1
Added note to Sync Input parameters in the Electrical Characteristics ................................................................................ 3
Deleted note 4 ...................................................................................................................................................................... 3
Changed DCV010505D min output voltage from ±4.75 tp ±4.25 ......................................................................................... 3
Changed DCV010505D max output voltage from ±5.25 tp ±5.75 ........................................................................................ 3
Changed Table 1 title text from "Single-Dip" to "Single Output" ........................................................................................... 4
Changed Table 2 title text from "Dual-Dip" to "Dual Output" ................................................................................................ 4
Added Isolation section and subsections. ........................................................................................................................... 10
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
DCV010505DP
DCV010505DP-U
DCV010505P
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
PDIP
SOP
PDIP
SOP
SOP
PDIP
SOP
PDIP
SOP
PDIP
SOP
PDIP
SOP
PDIP
SOP
PDIP
SOP
NVA
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
25
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
N / A for Pkg Type
Level-3-260C-168 HR
N / A for Pkg Type
DCV010505DP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DUA
NVA
DUA
DUA
NVA
DUA
NVA
DUA
NVA
DUA
NVA
DUA
NVA
DUA
NVA
DUA
25
25
25
700
25
25
25
25
25
25
25
25
25
25
25
25
Pb-Free
(RoHS)
DCV010505DP-U
DCV010505P
Pb-Free
(RoHS)
DCV010505P-U
DCV010505P-U/700
DCV010512DP
DCV010512DP-U
DCV010512P
Pb-Free
(RoHS)
Level-3-260C-168 HR
Level-3-260C-168 HR
N / A for Pkg Type
DCV010505P-U
DCV010505P-U
DCV010512DP
DCV10512DPU
DCV010512P
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Level-3-260C-168 HR
N / A for Pkg Type
Pb-Free
(RoHS)
DCV010512P-U
DCV010515DP
DCV010515DP-U
DCV010515P
Pb-Free
(RoHS)
Level-3-260C-168 HR
N / A for Pkg Type
DCV010512P-U
DCV010515DP
DCV010515DP-U
DCV010515P
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Level-3-260C-168 HR
N / A for Pkg Type
Pb-Free
(RoHS)
DCV010515P-U
DCV011512DP
DCV011512DP-U
DCV011515DP
DCV011515DP-U
Pb-Free
(RoHS)
Level-3-260C-168 HR
N / A for Pkg Type
DCV010515P-U
DCV011512DP
DCV011512DP-U
DCV011515DP
DCV011515DP-U
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Level-3-260C-168 HR
N / A for Pkg Type
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Level-3-260C-168 HR
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
DCV011515DP-U/700
DCV012405P
ACTIVE
SOP
PDIP
SOP
DUA
7
7
7
700
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-3-260C-168 HR
DCV011515DP-U
ACTIVE
ACTIVE
NVA
DUA
25
25
Pb-Free
(RoHS)
N / A for Pkg Type
DCV012405P
DCV012405P-U
Pb-Free
(RoHS)
Level-3-260C-168 HR
DCV012405P-U
DCV012405P-U/700
DCV012415DP
OBSOLETE
ACTIVE
SOP
DUA
NVA
7
7
TBD
Call TI
Call TI
DCV012405P-U
DCV012415DP
PDIP
25
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
DCV012415DP-U
ACTIVE
ACTIVE
SOP
SOP
DUA
DUA
7
7
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
DCV012415DP-U
DCV012415DP-U
DCV012415DP-U/700
700
Pb-Free
(RoHS)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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