DAC8742HPBSR [TI]
符合 HART®、FOUNDATION Fieldbus™ 和 PROFIBUS PA 标准且具有 UART/SPI 接口的调制解调器 | PBS | 32 | -55 to 125;型号: | DAC8742HPBSR |
厂家: | TEXAS INSTRUMENTS |
描述: | 符合 HART®、FOUNDATION Fieldbus™ 和 PROFIBUS PA 标准且具有 UART/SPI 接口的调制解调器 | PBS | 32 | -55 to 125 PC 电信 电信集成电路 调制解调器 |
文件: | 总45页 (文件大小:1591K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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DAC8742H
ZHCSJ40 –DECEMBER 2018
DAC8742H HART 和 FOUNDATION 现场总线/PROFIBUS PA 调制解调
器
1 特性
2 应用
1
•
•
•
兼容 HART 的物理层调制解调器
•
•
•
工业过程控制和自动化
PLC 或 DCS I/O 模块
–
–
1200/2200Hz HART FSK 正弦波
现场和传感器发送器
TX 信号振幅的寄存器编程控制
(仅适用于 DAC8741H / DAC8742H)
3 说明
–
集成式 RX 解调器和带通滤波器,具有极少的外
部组件
DAC8742H 是一款 HART®、 FOUNDATION 现场总
线™和 PROFIBUS PA 兼容的低功耗调制解调器,适
用于工业过程控制和工业自动化 数据隔离。
兼容 FOUNDATION 现场总线的 H1 控制器和介质
连接单元 (MAU)
–
基于曼彻斯特编码总线供电 (MBP) 的 31.25
kbit/s 通信
在 HART 模式下,DAC8742H 集成所有必需电路,以
作为一个半双工 HART 物理层调制解调器,在从配置
或主配置中使用最少的外部过滤组件运行。在
FOUNDATION 现场总线模式下,DAC8742H 集成所
有必需电路,以作为兼容 FOUNDATION 现场总线的
半双工 H1 控制器和 MAU 运行。
–
–
集成曼彻斯特编码器和解码器
与 PROFIBUS PA 兼容
低静态电流:最大值 180uA,典型工业工作温度范
围(-40°C 至 85°C)
•
•
集成 1.5V 电压基准
灵活的时钟选项
在 HART、FOUNDATION 现场总线或 PROFIBUS PA
模式下,可通过 UART 接口或 SPI 接口接入的集成式
FIFO 传输来自微控制器的数据流。SPI 接口包括一个
支持菊链的 SDO 引脚、各种中断以及其他扩展 特
性。
–
–
–
内部振荡器
外部晶体振荡器
外部 CMOS 时钟
•
数字接口
–
DAC8742H:UART 和 SPI
器件信息(1)
•
•
•
可靠性:CRC 位错校验、看门狗计时器
宽工作温度范围:-55°C 至 125°C
5mm x 5mm TQFP 封装
器件型号
DAC8742H
封装
TQFP (32)
封装尺寸(标称值)
5mm × 5mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
空白
空白
简化原理图
IOVDD
CLK_CFG0 CLK_CFG1 CLKO
XEN X1 X2
REF_EN
REF
REG_CAP AVDD
Clock
Generator
Precision
Oscillator
Voltage
Reference
DAC
RST
CD / IRQ
Transmit
Modulator
HART
PA/FF
Buffer
MOD_OUT
MOD_INF
MOD_IN
UART_IN / CS
DUPLEX / SDI
UART_OUT / SDO
UART_RTS / SCLK
IF_SEL
MUX
Receive
Carrier
Detect
Bandpass
Filter
Demodulator
DGND
BPFEN
AGND
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBAS940
DAC8742H
ZHCSJ40 –DECEMBER 2018
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 17
7.5 Register Maps......................................................... 21
Application and Implementation ........................ 28
8.1 Application Information............................................ 28
8.2 Typical Application ................................................. 30
Power Supply Recommendations...................... 34
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements................................................ 9
6.7 Typical Characteristics............................................ 10
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
8
9
10 Layout................................................................... 35
10.1 Layout Guidelines ................................................. 35
10.2 Layout Example .................................................... 35
11 器件和文档支持 ..................................................... 37
11.1 文档支持 ............................................................... 37
11.2 接收文档更新通知 ................................................. 37
11.3 社区资源................................................................ 37
11.4 商标....................................................................... 37
11.5 静电放电警告......................................................... 37
11.6 术语表 ................................................................... 37
12 机械、封装和可订购信息....................................... 37
7
4 修订历史记录
日期
修订版本
说明
2018 年 12 月
*
DAC8742H 独立数据表的初始发行版。
2
Copyright © 2018, Texas Instruments Incorporated
DAC8742H
www.ti.com.cn
ZHCSJ40 –DECEMBER 2018
5 Pin Configuration and Functions
PBS Package
32-Pin TQFP
Top View
NC
XEN
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
NC
AVDD
CLKO
MOD_INF
MOD_IN
REF
CLK_CFG0
CLK_CFG1
RST
DAC8742H
MOD_OUT
REG_CAP
NC
CD / IRQ
NC
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Crystal Oscillator Enable. Logic low on this pin enables the crystal oscillator circuit; in this mode
an external crystal is required. Logic high on this pin disables the internal crystal oscillator
circuit; in this mode an external CMOS clock or the internal oscillator are required. No digital
input pin should be left floating.
Digital
Input
XEN
2
Digital
Output
Clock Output. If using the internal oscillator or an external crystal, this pin can be configured as
a clock output.
CLKO
3
4
5
Digital
Input
Clock Configuration Pin. This pin is used to configure the input/output clocking scheme. No
digital input pin should be left floating.
CLK_CFG0
CLK_CFG1
Digital
Input
Clock Configuration Pin. This pin is used to configure the input/output clocking scheme. No
digital input pin should be left floating.
Reset. Logic low on this pin places the DAC8742H into power-down mode and resets the
device. Logic high returns the device to normal operation. No digital input pin should be left
floating.
Digital
Input
RST
6
Copyright © 2018, Texas Instruments Incorporated
3
DAC8742H
ZHCSJ40 –DECEMBER 2018
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
HART
Mode
Carrier detect. A logic high on this pin indicates a valid carrier is
present.
UART
Mode
While not transmitting, a logic high on this pin indicates a valid carrier
is present. While transmitting, a logic high on this pin indicates that the
jabber inhibitor has triggered.
FF / PA
Mode
Digital
Output
CD / IRQ
7
Digital Interrupt. The interrupt can be configured as edge sensitive or level sensitive
SPI Mode with positive or negative polarity, as set by the CONTROL register. Events that
trigger an interrupt are controlled by the Modem IRQ Mask register.
Interface select. A logic high on this pin configures the device for SPI mode. A logic low on this
pin configures the device for UART mode. An internal pull-down resistor is included. No digital
input pin should be left floating.
Digital
Input
IF_SEL
9
UART
UART data input.
Mode
UART_IN /
CS
Digital
Input
10
SPI chip-select. Data bits are clocked into the serial shift register when CS is low.
SPI Mode When CS is high, SDO is in a high-impedance state and data on SDI are ignored.
No digital input pin should be left floating. No digital input pin should be left floating.
Request to send a logic high on this pin enables the demodulator and
HART
Mode
disables the modulator. A logic low on this pin enables the modulator
and disables the demodulator. No digital input pin should be left
floating.
UART
Mode
Digital
Input,
UART_RTS /
SCLK
11
Digital
Output
FF / PA
Mode
This pin reports transmit FIFO threshold information as programmed
by the packet initiation code.
SPI clock. Data can be transferred at rates up to 12.5MHz. Schmitt-Trigger logic
input.
SPI Mode
UART
Mode
Digital input. Logic high enables full-duplex, or internal loop-back, test mode.
Digital
Output
DUPLEX / SDI
12
13
SPI data input. Data is clocked into the 24-bit input shift register on the falling edge
of the serial clock input. Schmitt-Trigger logic input.
SPI Mode
UART
Mode
UART data output.
UART_OUT /
SDO
Digital
Output
SPI Mode SPI data output. Data is valid on the falling edge of SCLK.
Interface supply. Supply voltage for digital input and output circuitry. This voltage sets the logical
thresholds for the digital interface.
IOVDD
GND
14
15
18
Supply
Supply
Digital ground. Ground reference voltage for all digital circuitry of the device.
Analog
Output
REG_CAP
Capacitor for internal regulator.
Modem output. FSK output sinusoid in HART mode or Manchester coded data stream in
FOUNDATION Fieldbus and PROFIBUS PA modes. Requires parallel capacitance of 5-22 nF in
HART mode or 0-100 pF in FOUNDATION Fieldbus and PROFIBUS PA mode for stability.
Analog
Output
MOD_OUT
19
Analog
Input
or Output
When the internal reference is enabled this pin outputs the internal reference voltage. When the
internal reference is disabled, this is the external 2.5V reference input.
REF
20
21
22
Analog
Input
HART FSK input or FOUNDATION Fieldbus and PROFIBUS PA Manchester coded data stream
input. If an external filter is used, do not connect this pin.
MOD_IN
MOD_INF
If using the internal band-pass filter, connect 680 pF to this pin or 120 pF in FOUNDATION
Fieldbus and PROFIBUS PA modes. If using an external filter, connect the output of that filter to
this pin.
Analog
Input
AVDD
GND
23
26
Supply
Supply
Power supply.
Analog ground. Ground reference voltage for power supply input.
Analog
Input
X2
27
Crystal stimulus.
Analog
Input
X1
28
29
30
Crystal/Clock input.
GND
Supply
Digital ground. Ground reference voltage for all digital circuitry of the device.
Digital
Input
Reference enable. Logic high enables the internal 1.5V reference. No digital input pin should be
left floating.
REF_EN
4
Copyright © 2018, Texas Instruments Incorporated
DAC8742H
www.ti.com.cn
ZHCSJ40 –DECEMBER 2018
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
Digital
Input
Filter enable. A logic high enables the internal band-pass filter. No digital input pin should be left
floating.
BPF_EN
31
1, 8, 16,
17,
NC
–
Do not connect these pins.
24, 25, 32
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-10
MAX
UNIT
AVDD to GND
6
6
IOVDD to GND
Input voltage
V
Analog output voltage to GND
AVDD+0.3
IOVDD+0.3
AVDD+0.3
IOVDD+0.3
10
Digital output voltage to GND
Analog output pin to GND
Output voltage
V
Digital output pin to GND
Input Current
Input current to any pin except supply pins
mA
Operating junction temperature, TJ
Junction temperature range (TJ max)
Storage temperature, Tstg
-55
125
150
°C
-60
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±8000
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
AVDD
2.7
5.5
5.5
V
V
IOVDD
1.71
ANALOG INPUTS
External
Reference Input
Voltage
2.375
2.5
2.625
V
DIGITAL INPUTS
External Clock
Source
Frequency
(HART Mode)
3.6864 MHz Clock
1.2288 MHz Clock
3.6469
1.2165
3.6864
1.2288
3.7232
1.2411
MHz
MHz
Copyright © 2018, Texas Instruments Incorporated
5
DAC8742H
ZHCSJ40 –DECEMBER 2018
www.ti.com.cn
Recommended Operating Conditions (continued)
Over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
External Clock
Source
Frequency (FF /
PA Modes)
3.96
4
4.04
MHz
6.4 Thermal Information
DAC8742H
THERMAL METRIC(1)
PBS (TQFP)
32 PIN
79.7
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
19.3
33.2
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
ΨJB
32.9
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
All specifications over -40°C to +125°C ambient operating temperature, 2.7V ≤ AVDD ≤ 5.5V, 1.71V ≤ IOVDD ≤ 5.5V, Internal
Reference, Internal Filter, unless otherwise noted.
PARAMETER
POWER REQUIREMENTS
IOVDD
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.71
2.7
5.5
5.5
V
V
AVDD
AVDD and IOVDD Supply Current (HART Mode)
External Clock, -40°C to 85°C
110
100
160
150
150
220
140
210
180
250
170
240
65
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
External Clock, -55°C to 125°C
Demodulator active
External Clock, -40°C to 85°C, External Reference
External Clock, -55°C to 125°C, External Reference
External Clock, -40°C to 85°C
External Clock, -55°C to 125°C
Modulator active
Crystal Oscillator
External Clock, -40°C to 85°C, External Reference
External Clock, -55°C to 125°C, External Reference
External Crystal, 16pF at XTAL1 and XTAL2
External Crystal, 36pF at XTAL1 and XTAL2
External Reference
40
40
65
Internal Oscillator
SPI Interface
105
180
Additional quiescent current required when interfacing
via SPI
5
µA
AVDD and IOVDD Supply Current (FF/PA Mode)
External Clock, -40°C to 85°C
160
175
175
165
220
330
200
320
250
360
235
350
µA
µA
µA
µA
µA
µA
µA
µA
External Clock, -55°C to 125°C
Decoder active
External Clock, -40°C to 85°C, External Reference
External Clock, -55°C to 125°C, External Reference
External Clock, -40°C to 85°C
External Clock, -55°C to 125°C
Encoder active
External Clock, -40°C to 85°C, External Reference
External Clock, -55°C to 125°C, External Reference
6
Copyright © 2018, Texas Instruments Incorporated
DAC8742H
www.ti.com.cn
ZHCSJ40 –DECEMBER 2018
Electrical Characteristics (continued)
All specifications over -40°C to +125°C ambient operating temperature, 2.7V ≤ AVDD ≤ 5.5V, 1.71V ≤ IOVDD ≤ 5.5V, Internal
Reference, Internal Filter, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
40
MAX
65
UNIT
µA
External Crystal, 16pF at XTAL1 and XTAL2
External Crystal, 36pF at XTAL1 and XTAL2
Crystal Oscillator
40
65
µA
Additional quiescent current required when interfacing
via SPI
SPI Interface
5
µA
AVDD and IOVDD Supply Current (All Modes)
Internal reference disabled, -40°C to 85°C, no active
30
60
µA
µA
clock input
Power-Down Mode
Internal reference disabled, -55°C to 125°C, no active
clock input
182
CLOCK REQUIREMENTS
EXTERNAL CLOCK (HART MODE)
3.6864 MHz Clock
1.2288 MHz Clock
3.6469
1.2165
3.6864
1.2288
3.7232
1.2411
MHz
MHz
External Clock
Source Frequency
EXTERNAL CLOCK (FF/PA MODE)
External Clock
4 MHz Clock
3.96
4
4.04
MHz
MHz
Source Frequency
INTERNAL OSCILLATOR
Frequency
-40°C to 125°C
1.2165
1.2288
1.2411
VOLTAGE REFERENCE
INTERNAL REFERENCE VOLTAGE
Internal Reference
Voltage
1.47
1.5
1.53
V
Load Regulation
1.3
1
V/mA
µF
Capacitive Load
Guaranteed by design
OPTIONAL EXTERNAL REFERENCE VOLTAGE
External Reference
Input Voltage
2.375
2.5
2.625
V
Demodulator
4.5
4.5
4.5
4.5
µA
µA
µA
µA
Modulator
External Reference
Input Current
Internal Oscillator
Power-Down
HART MODEM
MOD_IN INPUT (HART MODE)
External Reference Source, guaranteed by design.
Signal applied at the input to the DC blocking
capacitor.
0
0
1.5
1.5
Vp-p
Vp-p
Input Voltage
Range
Internal Reference Source, guaranteed by design.
Signal applied at the input to the DC blocking
capacitor.
Threshold for successful carrier detection and
demodulation, assuming ideal sinusoidal input FSK
signals with valid preamble using internal filter.
Receiver
Sensitivity
80
100
460
120
mVp-p
MOD_OUT OUTPUT (HART MODE)
AC-coupled (2.2µF), measured at MOD_OUT pin with
160Ω load
Output Voltage
450
-1
480
mVp-p
Mark Frequency
Space Frequency
Frequency Error
Internal Oscillator
1200
2200
Hz
Hz
%
Internal Oscillator
Internal Oscillator, -40°C to 125°C
1
0
Phase Continuity
Error
Guaranteed by design
Degrees
Copyright © 2018, Texas Instruments Incorporated
7
DAC8742H
ZHCSJ40 –DECEMBER 2018
www.ti.com.cn
Electrical Characteristics (continued)
All specifications over -40°C to +125°C ambient operating temperature, 2.7V ≤ AVDD ≤ 5.5V, 1.71V ≤ IOVDD ≤ 5.5V, Internal
Reference, Internal Filter, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Minimum Resistive
Load
160Ω, AC coupled with 2.2µF, guaranteed by design
160
Ω
RTS low, measured at the MOD_OUT pin, 1mA
measurement current
13
Ω
Transmit
Impedance
RTS high, measured at the MOD_OUT pin, ±200nA
measurement current
250
kΩ
FF / PA MODEM
MOD_IN INPUT (FF/PA MODE)
External Reference Source, specified by design.
Signal applied at the input to the DC blocking
capacitor.
0
1
Vp-p
Input Voltage
Range
Internal Reference enabled, specified by design.
Signal applied at the input to the DC blocking
capacitor.
0
1
Vp-p
µs
Receiver Jitter
Tolerance
Edge-to-edge measurement of Manchester Encoded
waveforms
-3.2
3.2
Threshold for successful carrier detection and
Receiver
Sensitivity
decoding, assuming ideal Manchester Encoded input
trapezoidal signals with 6µs rise time, valid preamble
byte(s) and start delimiter byte, using internal filter.
75
mVp-p
MOD_OUT OUTPUT (FF/PA MODE)
Output Voltage
800
mVp-p
mV
Maximum
Amplitude
Difference
Maximum difference in positive and negative
-50
50
amplitude signals
Transmit Bit Rate
31.1875
-0.8
31.25
31.3125
0.8
kbit/s
µs
Measured with respect to ideal crossing of high time
and low time
Transmit Jitter
Output Signal
Distortion
Measured peak to trough distortion for positive and
negative amplitude voltage outputs
-10
10
%
Rise and Fall Time 10% to 90% of peak to peak signal
Slew Rate 10% to 90% of peak to peak signal
8
µs
0.2
V/µs
DIGITAL REQUIREMENTS
DIGITAL INPUTS
VIH, Input High
Voltage
0.7 x
IOVDD
V
V
V
V
VIL, Input Low
Voltage
0.3 x
IOVDD
CLK_CFG0, Input
High Voltage
0.8 x
IOVDD
Guaranteed by design
CLK_CFG0, Input
Mid-Scale Voltage
0.4 x
IOVDD
0.55 x
IOVDD
Guaranteed by design
Guaranteed by design
CLK_CFG0, Input
Low Voltage
0.15 x
IOVDD
Input Current
-1
1
µA
pF
Input Capcitance
DIGITAL OUTPUTS
5
VOH, Output High
Voltage
200µA source/sink
200µA source/sink
IOVDD - 0.5
V
V
VOL, Output Low
Voltage
0.4
8
Copyright © 2018, Texas Instruments Incorporated
DAC8742H
www.ti.com.cn
ZHCSJ40 –DECEMBER 2018
6.6 Timing Requirements
All timing conditions guaranteed by design
PARAMETER
MIN
80
32
32
32
5
NOM
MAX
UNIT
ns
tc
SCLK Cycle Time
tw1
SCLK High Time
ns
tw2
SCLK Low Time
ns
tsu
/CS to SCLK Falling Edge Setup Time
Data Setup Time
ns
tsu1
ns
th1
Data Hold Time
5
ns
td1
SCLK Falling Edge to /CS Rising Edge
32
ns
(1)
1
tw3
Minimum /CS High Time
us
tv
SCLK Rising Edge to SDO Valid
Reset low time
32
ns
trst
100
ns
HART Mode Timing
Carrier start time. Time from RTS falling edge to
transmit carrier reaching its first peak.
tcstart
5
3
Bit-Times
Bit-Times
Carrier stop time. Time from RTS rising edge to
transmit carrier amplitude falling below the receive
amplitude
tcstop
Carrier decay time. Time from RTS riding edge to
carrier amplitude dropping to zero.
tcdecay
tcdeton
tcdetoff1
6
6
3
Bit-Times
Bit-Times
ms
Carrier detect on. Time from valid carrier on receive
path to CD rising edge.
Carrier detect off. Time from valid carrier removed on
receive path to CD falling edge.
Carrier detect on when transitioning from transmit
mode to receive mode in the presence of a constant
valid receive carrier.
tcdetoff2
2.1
25
ms
ms
Crystal oscillator power-up time from enabling the
oscillator via clock configuration pins with 16pF load
capacitors.
tcos1
Crystal oscillator power-up time from enabling the
oscillator via clock configuration pins with 36pF load
capacitors.
tcos2
25
10
30
ms
ms
µs
Reference power-up time from enabling via hardware
pin.
tref
Transition time from power-down mode to normal
operating mode with external clock and external
reference.
tpow
(1) Time between two consecutive CS rising edges must be ≥3.06 µs
tc
1
2
24
tw1
tw2
td1
tsu
th1
tw3
tsu1
MSB
MSB
LSB
LSB
tw
trst
图 1. SPI Timing Diagram
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6.7 Typical Characteristics
0
-5
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-10
-15
-20
-25
-30
-35
-40
-45
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
D002
D003
图 2. HART Mode External Band-Pass Filter Response
图 3. HART Mode Internal Band-Pass Filter Response
0
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-5
-10
-15
-20
-25
-30
-35
-40
-45
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
D004
D005
图 4. FF / PA Mode External Band-Pass Filter Response
图 5. FF / PA Mode Internal Band-Pass Filter Response
1.505
1.53
1.52
1.51
1.50
1.49
1.48
1.47
1.504
1.503
1.502
1.501
1.500
2.7
3.1
3.5
3.9
AVDD (V)
4.3
4.7
5.1
5.5
-55
-35
-15
5
25
45
65
85
105 125
Temperature (oC)
D006
D007
图 6. Internal Reference Voltage versus AVDD
图 7. Internal Reference Voltage versus Temperature
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Typical Characteristics (接下页)
nRTS (2V/div)
nRTS (2V/div)
MOD OUT (0.2V/div)
UART IN (2V/div)
MOD OUT (0.2V/div)
UART IN (2V/div)
0.1 ms/ div
0.1 ms/ div
D008
D009
图 8. HART TX Carrier Start Time
图 9. HART TX Carrier Stop / Decay Time
MOD IN (0.1V/div)
CD (2V/ div)
MOD IN (0.1V/div)
CD (2V/ div)
UART OUT (2V/div)
UART OUT (2V/div)
0.5 ms/ div
1 ms/ div
D010
D011
图 10. HART RX Carrier Detect Off Timing
图 11. HART RX Carrier Detect On Timing
10
9
8
7
6
5
4
3
2
1
0
130
120
110
100
90
Modulator Active
Demodulator Active
Modulator Active
Demodulator Active
80
70
60
50
1.5
2
2.5
3
3.5
IOVDD (V)
4
4.5
5
5.5
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
AVDD (V)
D012
D013
图 12. HART Mode IOVDD Supply Current versus Voltage
图 13. HART Mode AVDD Supply Current versus Voltage
with External Reference
with External Reference
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Typical Characteristics (接下页)
10
165
150
135
120
105
90
Modulator Active
Demodulator Active
Modulator Active
9
Demodulator Active
8
7
6
5
4
3
2
1
0
75
60
45
1.5
2
2.5
3
3.5
IOVDD (V)
4
4.5
5
5.5
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
AVDD (V)
D016
BDP0F17_
图 14. HART Mode IOVDD Supply Current versus Voltage
图 15. HART Mode AVDD Supply Current versus Voltage
with Internal Reference
with Internal Reference
32
28
152
Transmitting data
Receiving data
148
144
140
136
132
128
124
120
Transmitting data
24
Receiving data
20
16
12
8
4
0
1.5
2
2.5
3
3.5
IOVDD (V)
4
4.5
5
5.5
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
AVDD (V)
D014
BDP0F15_
图 16. FF / PA Mode IOVDD Supply Current versus Voltage
图 17. FF / PA Mode AVDD Supply Current versus Voltage
with External Reference
with External Reference
32
28
164
Transmitting data
Receiving data
160
156
152
148
144
140
136
132
Transmitting data
24
Receiving data
20
16
12
8
4
0
1.5
2
2.5
3
3.5
IOVDD (V)
4
4.5
5
5.5
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
AVDD (V)
D018
BDP0F19_
图 18. FF / PA Mode IOVDD Supply Current versus Voltage
图 19. FF / PA Mode AVDD Supply Current versus Voltage
with Internal Reference
with Internal Reference
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Typical Characteristics (接下页)
0.5 ms/ div
0.5 ms/ div
D020
D021
图 20. Typical Manchester Encoded Trapezoid, No Filter
图 21. Typical Manchester Encoded Trapezoid, with
Suggested Filter Response
490
1.2kHz Signal
2.2kHz Signal
485
480
475
470
465
460
455
100 200 300 400 500 600 700 800 900 1000
RLOAD (W)
D025
图 22. MOD_OUT Voltage versus RLOAD
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7 Detailed Description
7.1 Overview
The DAC8742H is a HART© compliant and FOUNDATION Fieldbus® or PROFIBUS PA compatible low power
modem designed for industrial process control and industrial automation applications.
In HART mode, the DAC8742H integrates all of the required circuitry to operate as half-duplex HART physical
layer modems, in either slave or master configurations with minimal external components for filtering. In
FOUNDATION Fieldbus mode, the DAC8742H integrate all of the required circuitry to operate as half-duplex
FOUNDATION Fieldbus compliant H1 Controllers & MAUs.
The HART, FOUNDATION Fieldbus, or PROFIBUS PA, data stream can be transferred from the microcontroller
through either a UART interface or an integrated FIFO accessed by a SPI interface. The SPI interface includes
an SDO pin for daisy-chain support, various interrupts, and other extended features.
7.2 Functional Block Diagram
IOVDD
CLK_CFG0 CLK_CFG1 CLKO
XEN X1 X2
REF_EN
REF
REG_CAP AVDD
Clock
Generator
Precision
Oscillator
Voltage
Reference
DAC
RST
CD / IRQ
Transmit
Modulator
HART
Buffer
MOD_OUT
MOD_INF
MOD_IN
UART_IN / CS
DUPLEX / SDI
UART_OUT / SDO
UART_RTS / SCLK
IF_SEL
MUX
Receive
Demodulator
Carrier
Detect
Bandpass
Filter
PA/FF
DGND
BPFEN
AGND
7.3 Feature Description
7.3.1 HART Modulator
In SPI mode, HART data is loaded into a transmit FIFO via the SPI serial interface. In UART mode, the UART
BAUD rate matches the HART BAUD rate and therefore the FIFO is bypassed. In both cases the input data is
translated into the mark and space, 1200 Hz and 2200 Hz respectively, frequency shift keyed (FSK) analog
signals used in HART communication through an internal HART modulator.
The HART modulator implements a look-up table containing 32 6-bit signed values which represent a single
phase continuous sinusoidal cycle. A counter is implemented that incrementally loads the table values to a
Digital-to-Analog Converter (DAC), at a clock frequency determined by the binary value of the input data, in order
to create the mark and space analog output signals used to represent HART data.
The modem operates in half-duplex mode, unless placed in full-duplex mode, where the modulator and
demodulator are not active simultaneously. The modem arbitrates over which component is active. To request
that the modulator is activated UART devices toggle the RTS pin low, SPI devices toggle the RTS bit in the
MODEM CONTROL register. These mechanics are explained in more detail in the respective sections of Device
Functional Modes.
In HART mode the MOD_OUT pin requires parallel capacitance of 5-22 nF or 0-100 pF in FOUNDATION
Fieldbus and PROFIBUS PA mode for stability.
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Feature Description (接下页)
7.3.2 HART Demodulator
The HART demodulator converts the HART FSK input signals applied at the MOD_IN or MOD_INF pins,
depending on whether an external filter is implemented, to binary data that is loaded into a receive FIFO in SPI
mode. Data in the receive FIFO can then be read by the host controller via SPI serial interface. In UART mode
received data is directly fed through to the UART interface.
When a valid carrier is detected on devices using the UART interfaces, the CD pin will toggle high. For devices
using the SPI interface, the IRQ pin will toggle indicating an alarm condition. The MODEM STATUS register can
then be read to determine the source of the interrupt, which includes a bit for carrier detection in DB1. Hysteresis
is implemented with the carrier detect feature in order to prevent erroneous carrier detection signals. More details
are explained in the respective Device Functional Modes sections.
7.3.3 FOUNDATION FIELDBUS / PROFIBUS PA Manchester Encoder
FOUNDATION FIELDBUS or PROFIBUS PA data is loaded into a transmit FIFO via UART or SPI interfaces
which is translated into the Manchester encoded binary analog signals used in both FOUNDATION FIELDBUS
and PROFIBUS PA bus protocols through an internal Manchester encoder.
The Manchester encoder interacts with the DAC to transmit positive and negative amplitude signals, with respect
to a positive common mode voltage, to create the Manchester encoded analog outputs at 31.25kHz BAUD. A
binary 0 is represented by a low-to-high transition and a binary 1 is represented by a high-to-low transition.
In both UART and SPI interfaced device, the encoder is activated any time there is data available in the transmit
FIFO and the decoder is not receiving data. In order to prevent FIFO buffer overflow, for UART mode the CD pin
acts as an interrupt to indicate when the FIFO level has exceed a programmed threshold in the packet initiation
code. In SPI mode the transmit FIFO threshold programmed in the FIFO LEVEL SET register can trigger an
interrupt on the IRQ pin. Once the IRQ interrupts is triggered, the MODEM STATUS register can then be read to
determine the source of the interrupt, which includes a bit for the FIFO level in DB4. More details are explained
in the respective Device Functional Modes sections.
7.3.4 FOUNDATION FIELDBUS / PROFIBUS PA Manchester Decoder
The FOUNDATION FIELDBUS and PROFIBUS PA decoder converts the Manchester encoded data applied at
the MOD_IN or MOD_INF pins, depending on whether an external filter is implemented, to binary data that is
loaded into a receive FIFO. Data in the receive FIFO can then be read by the host controller via UART or SPI
serial interfaces.
When valid data is provided to the decoder, binary data is read out serially on the UART interface. For SPI
devices, the receive FIFO is loaded until the threshold programmed in FIFO LEVEL SET is met which will trigger
an interrupt on the IRQ pin. The MODEM STATUS register can then be read to determine the source of the
interrupt, which includes a bit for the FIFO level in DB7, indicating that data is ready to be read on the SPI bus.
More details are explained in the respective Device Functional Modes sections.
7.3.5 Internal Reference
An internal reference is included in the DAC8742H. The REF_EN pin is used to enable or disable the internal
reference, when the internal reference is disabled an external reference must be provided at the REF pin. In SPI
mode, the PDVREF bit in the CONTROL register can be used to enable or disable the internal reference via
software. If the REF_EN pin is set high, the register contents of the PDVREF bit is ignored.
INTERFACE
UART
UART
SPI
PDVREF
1 (Default)
1 (Default)
1 (Default)
0
REF_EN
REFERENCE MODE
External Reference
Internal Reference
Internal Reference
Internal Reference
External Reference
External Reference
0
1
1
1
0
0
SPI
SPI
1 (Default)
0
SPI
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7.3.6 Clock Configuration
All of the devices in the DAC8742H family support a variety of clocking options in order to provide system
flexibility and reduce overall current consumption in HART applications. The clocking options include: an internal
oscillator (HART mode only), an external crystal oscillator, or an external CMOS clock. The selection of the
clocking scheme is controlled by the XEN, CLK_CFG1, and CLK_CFG0 pins as described in the table below.
The internal oscillator takes approximately 50 ms to start oscillating from when it is enabled. During this time
period the device is unable to perform modulation or demodulation activities.
表 1. Clock Configuration Table
XEN
CLK_CFG1
CLK_CFG0
CLKO
DESCRIPTION
MODE
3.6864MHz CMOS clock
connected at XTAL1
1
0
0
No Output
1.2288MHz CMOS clock
connected at XTAL1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
No Output
No Output
Internal oscillator enabled
Internal oscillator enabled,
CLKO enabled
1.2288MHz Output
No Output
HART
Crystal oscillator enabled
3.6864MHz crystal oscillator,
CLKO enabled
3.6864MHz Output
3.6864MHz crystal oscillator,
CLKO enabled
0
0
1
1
1
0
0
1
1.8432MHz Output
1.2288MHz Output
No Output
3.6864MHz crystal oscillator,
CLKO enabled
4MHz CMOS clock connected
at XTAL1
0.5
2MHz CMOS clock connected
at XTAL1
FOUNDATION
FIELDBUS &
PROFIBUS PA
1
0
0
1
0
1
0.5
0.5
0.5
No Output
No Output
4MHz crystal oscillator
4MHz crystal oscillator, CLKO
enabled
4MHz Output
7.3.7 Reset and Power-Down
The RST pin functions as both a hardware reset and a power-down. When the pin is brought low a reset is
issued, restoring all device components to their default state. While the pin is kept low, the device is in a power-
down state where the internal reference is disabled, the modulator and demodulator or encoder and decoder are
disabled, serial data output lines are high-impedance, MOD_OUT impedance is set to 70 kΩ, and the clock
output is disabled. If an external crystal oscillator is used, the crystal oscillator circuit remains active to reduce
start-up time when exiting the power-down state. Clock configuration pins remain active in power-down allowing
the crystal oscillator to be disabled if desired.
7.3.8 Full-Duplex Mode
In full-duplex mode the modulator and demodulator (HART mode) or encoder and decoder (FOUNDATION
FIELDBUS or PROFIBUS PA mode) are simultaneously enabled. This allows a self-test feature to verify
functionality of the transmit and receive signal chains to improve system diagnostics.
7.3.9 I/O Selection
The DAC8742H implements both SPI and UART interfaces. Only one interface is active at a time for the
DAC8742H. The interface mode is selected by the IF_SEL pin: a logic high on this pin sets the device to SPI
mode and a logic low sets the device to UART mode. An internal pull-down resistor is included to ensure power-
up in a known state, by default the pull-down sets the interface to UART mode. If changing I/O modes after
power-up, a reset command should be issued on RST.
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7.3.10 Jabber Inhibitor
The DAC8742H implements a Jabber Inhibitor feature in FOUNDATION FIELDBUS or PROFIBUS PA modes
which prevents the encoder from continuously transmitting data on the bus for longer than a programmed
threshold controlled by the UART or SPI interface. In SPI mode this threshold is programmed by the
PAFF_JABBER register, in UART mode this threshold is programmed by the four byte initialization sequence
before each transmission. This is described in further detail in the Device Functional Modes and Register Map
sections.
7.4 Device Functional Modes
7.4.1 UART Interfaced HART
When interfacing the HART modem via the UART interface, the device can be thought of as a simple UART-to-
HART or HART-to-UART direct feedthrough converter. The UART data is transmitted and received at 1200
BAUD, which is matched to the HART FSK input and output signals.
The HART communication protocol is a half-duplex protocol which means that either the modulator or
demodulator is active, and never simultaneously enabled. The device arbitrates over which component of the
modem is active at all times based on activity on the HART bus. Bus activity is interfaced to the host controller
through the CD and RTS pins.
By default when RTS is high the demodulator is active and the modulator is inactive. When a valid carrier is
detected and data is being received by the modem, the CD pin is toggled high and binary UART data is provided
at the output. If a request to send is issued by toggling the RTS pin low while CD is high, the demodulator
remains at priority and any data provided at the UART input is ignored. When CD is low no valid carrier is
present and when RTS is brought low the modulator is activated and UART input data is latched into the
modulator and placed onto the HART bus.
7.4.2 UART Interfaced FOUNDATION FIELDBUS / PROFIBUS PA
FOUNDATION FIELDBUS and PROFIBUS PA are half-duplex communication protocols where only the encoder
or decoder are active at any time and the DAC8742H arbitrates over which path is active. When interfacing the
FOUNDATION FIELDBUS or PROFIBUS PA modem via the UART interface, data placed in the transmit FIFO is
automatically placed on the FF/PA bus until the FIFO is empty any time the device is not receiving data,
assuming correct data format.
When receiving data the decoder will expect a preamble byte(s) and a start delimiter byte. These bytes, as well
as the stop byte, will be stripped from the UART communication and only the first data byte will be transmitted to
start the data packet. The host controller must use a timer to detect the end of the packet. Each byte transmitted
on the UART will be at 57.6 kHz BAUD and byte spacing of 256 us. If a new byte has not been started within 512
us it can be assumed that the incoming packet has ended.
The device expects to see a four byte sequence to initiate transmission: 0xEA followed by 0x80-0x9F, where bits
4:3 of the second byte configure an interrupt threshold for the transmit FIFO level and bits 2:0 set the number of
preamble bytes to be transmitted. The third byte contains the information to configure the Jabber Inhibitor
followed by the final byte of 0xAE. To send inverted Manchester encoded data the first byte, 0xEA, is inverted to
0x15 and the first three bits of the second byte are inverted such that the range of values for the second byte are
from 0x60-0x7F. The functionality of bits 4:3 and 2:0 and the Jabber Inhibitor byte remain the same and the final
byte is inverted to 0x51. The details concerning this four byte sequence are explained in the tables below.
B3
B2
D3
Mode
D7:D0
D7
1
D6
0
D5
0
D4
D2
D1
D0
Non-
inverted
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
D2M_LEVEL
D2M_LEVEL
PRE_BYTES
PRE_BYTES
Inverted
0
1
1
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B1
B0
Mode
D7:D0
D7
1
D6
0
D5
1
D4
0
D3
1
D2
1
D1
1
D0
0
Non-
inverted
JABBER_TIMEOUT
JABBER_TIMEOUT
Inverted
0
1
0
1
0
0
0
1
CONTROL BITS
DESCRIPTION
0
0
1
0
1
Alarm on UART_RTS when transmit FIFO has less than 2 bytes loaded
Alarm on UART_RTS when transmit FIFO has less than 4 bytes loaded
Alarm on UART_RTS when transmit FIFO has less than 6 bytes loaded
Alarm on UART_RTS when transmit FIFO has less than 8 bytes loaded
0
D2M_LEVEL
1
1
PRE_BYTES
Number of preamble bytes is equivalent to the straight binary decimal value in this register plus one
The JABBER_TIMEOUT bits control the timeout period for the Jabber Inhibitor. If a value of 0x0 is programmed
the Jabber Inhibitor is disabled. Otherwise the timer will be programmed in 2.048ms increments such that the
timeout can be calculated as shown below. If the Jabber Inhibitor triggers the CD pin will be taken high. The CD
pin will be returned to logic low when the silence period of 3 seconds has ended.
TimeOut = JABBER_TIMEOUT x 2.048ms
(1)
The encoder will begin transmitting data once the following conditions are met: a valid four-byte transmission
initiation sequence has been sent to the device, the FIFO is not empty, and the device is not receiving data.
Transmission will begin by sending the preamble byte(s) followed by a start delimiter. Then, the encoder will
begin to remove data from the FIFO – this creates at least a five-byte lag of the encoder with respect to the
UART.
During transmission of a packet the UART must take care to ensure that the FIFO does not become empty
before the packet is complete. The encoder transmits at a BAUD rate of 31.25 kHz or 256 µs per byte in the
FIFO so the UART must keep up with this rate. The four-byte sequence that initiates a transmission includes
setting a transmit FIFO threshold in bits 4:3. When the FIFO level is less than or equal to this threshold the
UART_RTS pin will be taken high, this can be leveraged to ensure the FIFO is not prematurely empty. Once the
FIFO is empty a stop delimiter is placed on the bus. Once the FIFO is empty a new packet can be initiated with a
new four-byte transmission initiation sequence.
The device expects UART BAUD rate of 57.6 kHz. This BAUD rate is faster than the 31.25 kHz BAUD rate
specified by FOUNDATION FIELDBUS and PROFIBUS PA, therefore FIFO overflow is possible. In order to
prevent FIFO overflow, the UART_RTS pin FIFO threshold alarm can be leveraged by never adding more data to
the FIFO than it can contain based on the programmed alarm threshold.
7.4.3 SPI Interfaced HART
When interfacing the HART modem via the SPI interface, the device utilizes transmit and receive FIFOs that are
9-bits wide and 16 locations deep to buffer all HART data.
The HART communication protocol is half-duplex protocol which means that either the modulator or demodulator
is active, and never simultaneously enabled. The device arbitrates over which component of the modem is active
at all times based on activity on the HART bus. Bus activity is interfaced to the host controller through the IRQ
pin and MODEM STATUS register.
By default the demodulator is active and the modulator is inactive. When a valid carrier is detected and data is
being received by the modem, the CD bit (bit 1) in the MODEM STATUS register is set high. If the CD bit (bit 1)
in the MODEM IRQ MASK register is set to 0, this will also cause the IRQ pin to toggle as programmed in the
status CONTROL register. The IRQ pin may be programmed to be edge sensitive or level sensitive, the polarity
of the signal is also programmable. When the IRQ pin toggles, the MODEM STATUS register should be read to
determine the source of the interrupt. Receive data can be read from the RECEIVE FIFO by issuing an SPI read
command.
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Alternatively, the CD pin can be ignored by setting the CD bit (bit 1) in the MODEM IRQ MASK register to a 1. In
this mode the IRQ pin will not toggle when the CD bit in the MODEM STATUS register is a 1. Instead, a
RECEIVE FIFO read event can be triggered by the RECEIVE FIFO level threshold. This is achieved by
programming the FIFO LEVEL SET register (bits 7:4) to the desired threshold value from 1-15, if a full FIFO
(level 16 threshold) is desired the M2D FIFO FULL alarm can be used instead. If the M2D FIFO LEVEL bit (bit 7)
in the MODEM IRQ MASK register is set to 0, the IRQ pin will toggle and the MODEM STATUS register should
be read to determine the source of the interrupt. Receive data can then be read from the RECEIVE FIFO by
issuing an SPI read command.
If data is placed in the transmit FIFO while the demodulator is active and the CD bit is high, the data remains in
the FIFO until the modulator is activated. To request that the modulator is activated and the demodulator is
deactivated the RTS bit (bit 0) in the MODEM CONTROL register should be set high. When the modulator is
activated and the demodulator is deactivated the clear to send, or CTS, bit (bit 0) in the MODEM STATUS
register is set high. If the CTS bit (bit 0) in the MODEM IRQ MASK register is set to a 0 this will cause the IRQ
pin to toggle, indicating that transmit FIFO data will begin to be placed on the bus.
The level of the transmit FIFO may be monitored in order to avoid buffer overflow. This can be done either by
watching for a buffer full or buffer threshold event. To monitor by a FIFO level threshold the FIFO LEVEL SET
register (bits 3:0) can be programmed to the desired threshold value from 1-15. If the D2M FIFO LEVEL bit (bit
4) in the MODEM IRQ MASK register is set to a 0, this will cause the IRQ pin to toggle. Similarly an alarm can be
triggered based on the D2M FIFO FULL bit in the MODEM STATUS register.
7.4.4 SPI Interfaced FOUNDATION FIELDBUS / PROFIBUS PA
FOUNDATION FIELDBUS and PROFIBUS PA are half-duplex communication protocols where only the encoder
or decoder are active at any time and the DAC8742H arbitrates over which path is active. When interfacing the
FOUNDATION FIELDBUS or PROFIBUS PA encoder via SPI interface, data is placed in transmit and receive
FIFOs that are each 16-bytes deep to buffer all data.
When receiving data the decoder will expect a preamble byte(s) and a start delimiter byte, followed by the data
bytes for the packet, and concluded with a stop delimiter byte. All of these bytes are placed into the RECEIVE
FIFO where bits 7:0 represent the data and bit 8 is used as a special bit to indicate the start of a packet, with
data 0x014D, the end of a packet, with data 0x0126, or a half-bit slip, with data 0x0100. If a half-bit slip occurs it
is recommended to discard the packet. A timer is not necessary to detect the end of receiving a packet in SPI
mode because the stop delimiter is included in the RECEIVE FIFO data.
In order to prevent RECEIVE FIFO overflow, alarms are available to watch a threshold of the FIFO or when the
FIFO is full. If the FIFO is full it is possible for data to be lost. This is achieved by programming the FIFO LEVEL
SET register (bits 7:4) to the desired threshold value from 1-15, if a full FIFO (level 16 threshold) is desired the
M2D FIFO FULL alarm can be used instead. If the M2D FIFO LEVEL bit (bit 7) in the MODEM IRQ MASK
register is set to 0, the IRQ pin will toggle and the MODEM STATUS register should be read to determine the
source of the interrupt. Receive data can then be read from the RECEIVE FIFO by issuing an SPI read
command.
The encoder will begin to send data by sending the preamble byte(s) followed by a start delimiter when the
TRANSMIT FIFO is not empty and the device is not receiving data. The number of preamble bytes used in the
packet is controlled by the PAFF PREAMBLE bits (bits14:12) in the MODEM CONTROL REGISTER. The
polarity of the Manchester encoded data can also be programmed by the PAFF POLARITY bit (bit 15) in the
MODEM CONTROL REGISTER. After transmitting the preamble byte(s) and start delimiter the encoder will
begin taking data from the TRANSMIT FIFO.
During transmission the SPI controller must take care to ensure that the TRANSMIT FIFO does not become
empty before the packet is complete. When the TRANSMIT FIFO is empty a stop delimiter is placed on the bus.
The level of the transmit FIFO may be monitored in order to avoid buffer overflow. This can be done either by
watching for a buffer full or buffer threshold event. To monitor by a FIFO level threshold the FIFO LEVEL SET
register (bits 3:0) can be programmed to the desired threshold value from 1-15. If the D2M FIFO LEVEL bit (bit
4) in the MODEM IRQ MASK register is set to a 0, this will cause the IRQ pin to toggle. Similarly an alarm can be
triggered based on the D2M FIFO FULL bit in the MODEM STATUS register.
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The Jabber Inhibitor threshold can be programmed by the PAFF_JABBER register (address 0x27). The 8-bit
value programmed in this register can be used to calculate the threshold using the equation below. When the
timeout triggers the JAB_ON bit in the STATUS register will be taken high and transmission will be blocked for
the 3 second timeout period. The JAB_OFF bit will go high when the timeout period has expired. Both JAB_ON
and JAB_OFF bits trigger and IRQ event, meaning the IRQ pin will be triggered for both events.
TimeOut = JABBER_TIMEOUT x 2.048ms
(2)
7.4.5 Interface
7.4.5.1 UART
The behavior of the UART interface changes based on whether the device is operating in HART mode or in
FOUNDATION FIELDBUS and PROFIBUS PA mode.
In HART mode, the device expects 1 start bit, 8 data bits, 1 odd parity bit, and 1 stop bit or an 8O1 UART
character format. The transmit path of the device acts as a direct feedthrough of the UART input to the HART
FSK output, therefore the UART BAUD rate from the host controller must be 1200Hz ±1% as required by the
HART standard. The receive path of the device will also operate at 1200Hz ±1%.
In FOUNDATION FIELDBUS and PROFIBUS PA mode the UART interface expects 1 start bit, 8 data bits, no
parity bit, and 1 stop bit or an 8N1 UART character format. In this mode the UART interfaces transmit and
receive FIFOs so the BAUD rate is not required to match the 31.25 kHz BAUD used by FOUNDATION
FIELDBUS and PROFIBUS PA. In this mode the expected transmit and receive UART BAUD is 57.6 Hz ±2.5%.
7.4.5.1.1 UART Carrier Detect
The behavior of the carrier detect or CD pin changes depending on whether the device is in HART mode or
FOUNDATION FIELDBUS and PROFIBUS PA mode.
In HART mode the pin operates as a carrier detect pin. When a valid carrier is detected and the modem is
receiving data the CD pin is taken high. When the CD pin is high, UART data sent to the device and the request
to send, or RTS, pin will be ignored until the carrier is no longer present.
In FOUNDATION FIELDBUS and PROFIBUS PA the CD pin operates as a carrier detect pin when not in
transmit mode. When the CD pin is high, UART data sent to the device will be ignored until the carrier is no
longer present. When in transmit mode the CD pin functions as an alarm indicator that the jabber inhibitor has
triggered and further UART transmission data will be ignored. In general if the CD pin is high the host controller
should not be sending transmit data to the device.
7.4.5.2 SPI
The SPI interface can operate on SCLK speeds up to 12.5 MHz, but the frame-rate must be greater than 2442
ns in HART mode and 3000 ns in FOUNDATION FIELDBUS and PROFIBUS PA mode. Frames must contain at
least 24-bits without CRC enabled and 32-bits with CRC enabled. The data within the frame is right justified,
meaning that upon the rising edge of CS the right-most, or last, 24-bits or 32-bits will be evaluated as the input
data word. Two modes of SPI are supported by the interface: clock polarity 0 and clock phase 1 or clock polarity
1 and clock phase 0.
The SDO pin will output data on the rising edge of SCLK or the falling edge of CS. SDO will always provide
information from the previous frame, if the previous frame was a read then the output data will be the requested
data. If the previous write was a command or register write, that data will be repeated. This allows a method for
the user to verify what was written to the device. If CRC is enabled and write data is being repeated on SDO, the
CRC provided during the previous frame will be output – not a newly calculated CRC.
The SPI frame structure is shown in the figure below. The frame includes a read/write bit, followed by a 7-bit
address, then 16-bit write data for a write frame or don’t care bits for a read frame. If CRC is enabled, an
additional 8-bits are placed at the end of the frame containing the CRC word.
R/W FRAME
Write Frame
Read Frame
D23
0
D22:16
D15:0
Write Data
X
7-Bit Address
7-Bit Address
1
20
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7.4.5.2.1 SPI Cyclic Redundancy Check
The SPI interface includes an optional CRC mode to enhance the reliability of the interface by blocking
erroneous commands sent to the device due to noise or other errors sources. When writing to or reading from
the device the last 8-bits in the frame contain the CRC word which is calculated based on the polynomial
x8+x2+x+1. If a bad CRC word is included in a write-frame to the device, the frame will be ignored. When reading
from the device, the host controller should check the CRC word to validate the frame.
Read commands with a bad CRC value will output 0x80000000 and, in the case of a receive FIFO read, prevent
data from leaving the FIFO and subsequently being lost.
7.4.5.2.2 SPI Interrupt Request
SPI interfaced devices include an interrupt request, or IRQ, pin to communicate the occurrence of a variety of
events to the host controller. The behavior of the IRQ pin is controlled by the CONTROL register and MODEM
IRQ MASK register.
The CONTROL register allows the host controller to configure the IRQ pin as level sensitive or edge sensitive via
the IRQ LEVEL bit (bit 2). For both level sensitive and edge sensitive modes, the polarity of the IRQ pin can be
set via the IRQ POLARITY bit (bit 3) in the CONTROL register.
The MODEM IRQ MASK register allows the controller to decide which events are able to trigger the IRQ pin to
toggle. If a logic 0 is written to the respective bit, that event is allowed to toggle the IRQ pin. If a logic 1 is written
to the respective bit, the event is masked from the IRQ pin.
When an event occurs the IRQ pin signal, in the case of level-sensitive configurations, is latched and the IRQ pin
voltage stays at logic high until the status has been reset, or cleared, by reading the contents of the
MODEM_STATUS register. In the case of edge-sensitive configurations a pulse is generated any time a new
event is detected.
7.5 Register Maps
Table 2 lists the memory-mapped registers for the DAC8742H. All register offset addresses not listed in Table 2
should be considered as reserved locations and the register contents should not be modified.
Table 2. DAC8742H Registers
Offset
2h
Acronym
Register Name
Section
Go
CONTROL
CONTROL Register
7h
RESET
RESET Register
Go
20h
21h
22h
23h
24h
25h
27h
MODEM_STATUS
MODEM_IRQ_MASK
MODEM_CONTROL
FIFO_D2M
MODEM STATUS Register
MODEM IRQ MASK Register
MODEM CONTROL Register
FIFO D2M Register
Go
Go
Go
Go
FIFO_M2D
FIFO M2D Register
Go
FIFO_LEVEL_SET
PAFF_JABBER
FIFO LEVEL SET Register
PAFF JABBER Register
Go
Go
Complex bit access types are encoded to fit into small table cells. Table 3 shows the codes that are used for
access types in this section.
Table 3. DAC8742H Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
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7.5.1 CONTROL Register (Offset = 2h) [reset = 0x8042]
This register controls the SPI watch-dog timer, internal reference, CRC mode, IRQ pin behavior, and SDO pin
behavior.
CONTROL is shown in Figure 23 and described in Table 4.
Return to Summary Table.
Figure 23. CONTROL Register
15
14
13
12
11
10
9
8
WDTO
R/W
WDT
R/W
RESERVED
R
7
RESERVED
R
6
5
RESERVED
R
4
3
2
1
0
PDVREF
R/W
CRC_EN
R/W
IRQ_POL
R/W
IRQ_LEVEL
R/W
SDO_Z
R/W
SDO_B
R/W
Table 4. CONTROL Register Field Descriptions
Bit
Field
Type
Reset
Description
SPI Watch-dog Timer (based on 3.6864MHz Clock)
15-13
WDTO
R/W
100
D15
0
D14
0
D13
0
Timeout Period
50 ms
100 ms
0
0
1
0
1
0
500 ms
0
1
1
1 second
1
0
0
2 seconds (default)
3 seconds
4 seconds
5 seconds
1
0
1
1
1
0
1
1
1
12
WDT
R/W
0
0 = SPI Watch-dog Timer Disabled (default)
1 = SPI Watch-dog Timer Enabled
11-7
6
RESERVED
PDVREF
R
00000
1
Reserved
R/W
This bit is only functional if the hardware reference enabled is
enabled.
0 = Internal reference is powered down
1 = Internal reference is powered up (default)
5
4
RESERVED
CRC_EN
R
0
0
Reserved
R/W
0 = No CRC (default)
1 = CRC is enabled
3
2
1
0
IRQ_POL
IRQ_LEVEL
SDO_Z
R/W
R/W
R/W
R/W
0
0
1
0
0 = IRQ is active low (default)
1 = IRQ is active high
0 = IRQ creates a pulse for edge sensitivity (default)
1 = IRQ asserts to a level until MODEM STATUS is read
0 = SDO will be driven during writes and read requests
1 = SDO will be HiZ during writes requests (default)
SDO_B
0 = SDO will remain filled from last frame (default)
1 = SDO will clear with the beginning of each frame
22
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7.5.2 RESET Register (Offset = 7h) [reset = 0x0000]
Writing 0x0001 to this register will reset all registers to their default values and the FIFOs will be emptied.
RESET is shown in Figure 24 and described in Table 5.
Return to Summary Table.
Figure 24. RESET Register
15
7
14
6
13
5
12
11
3
10
2
9
1
8
RESERVED
R
4
RESERVED
R
0
RST
R/W
Table 5. RESET Register Field Descriptions
Bit
Field
Type
Reset
Description
15-1
RESERVED
R/W
000000000 Reserved
000000
0
RST
W
0
Writing a 1 to this bit triggers a software reset.
7.5.3 MODEM_STATUS Register (Offset = 20h) [reset = 0x0000]
The modem status register is a read/write register. When an event occurs, the corresponding bit to indicate that
event is set to a logic 1 in this register. The status bits are sticky, meaning they are not cleared unless a 1 is
written to the corresponding bit position, except for carrier detect, or CD, which responds based on the
presences of a carrier, the FIFO level registers, which respond based on the conditions of the FIFOs, and
JAB_OFF and JAB_ON which represent the current status of the jabber inibhior. CTS will assert after RTS is set
and no carrier is present if not operating in full-duplex mode.
MODEM_STATUS is shown in Figure 25 and described in Table 6.
Return to Summary Table.
Figure 25. MODEM_STATUS Register
15
14
13
12
11
10
9
8
RST
R/W
JAB_OFF
R/W
JAB_ON
R/W
GAP
R/W
FRAME
R/W
PARITY
R/W
WDT
R/W
CRC
R/W
7
6
5
FIFO_M2D EMPTY
R/W
4
3
2
FIFO_D2M EMPTY
R/W
1
CD
R
0
CTS
R
FIFO_M2D LEVEL
R/W
FIFO_M2D FULL
R/W
FIFO_D2M LEVEL
R/W
FIFO_D2M FULL
R/W
Table 6. MODEM_STATUS Register Field Descriptions
Bit
15
14
Field
RST
Type
R/W
R/W
Reset
Description
0
0
A reset has occurred
JAB_OFF
This bit goes high when the jabber inhibitor timeout period has
expired
13
12
11
10
9
JAB_ON
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
This bit goes high when the jabber inhibitor has been triggered
A gap error in HART mode
GAP
FRAME
A frame error in HART mode or a 1/2 bit slip in FF/PA mode
A Parity error in HART mode
PARITY
WDT
The watch-dog timer has expired
8
CRC
An incorrect CRC word was provided in a read or write command
The receive FIFO is at the programmed level
The receive FIFO is full
7
FIFO_M2D_LEVEL
FIFO_M2D_FULL
FIFO_M2D_EMPTY
6
5
The receive FIFO is empty
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Table 6. MODEM_STATUS Register Field Descriptions (continued)
Bit
4
Field
Type
R/W
R/W
R/W
R
Reset
Description
FIFO_D2M_LEVEL
FIFO_D2M_FULL
FIFO_D2M_EMPTY
CD
0
0
0
0
0
The transmit FIFO is at the programmed level
The transmit FIFO is full
3
2
The transmit FIFO is empty
1
In HART mode, a valid carrier has been detected
0
CTS
R
In HART mode, the modem is cleared to send data and the
modulator is active
7.5.4 MODEM_IRQ_MASK Register (Offset = 21h) [reset = 0x0024]
This register controls which MODEM STATUS events are allowed to trigger an interrupt on the IRQ pin. A 0 in
the respective bit position allows the interrupt event to toggle the IRQ pin. A 1 in the respective bit position blocks
the interrupt event from toggling the IRQ pin, but the event can still be detected by reading the MODEM STATUS
register.
MODEM_IRQ_MASK is shown in Figure 26 and described in Table 7.
Return to Summary Table.
Figure 26. MODEM_IRQ_MASK Register
15
RESERVED
R
14
13
12
11
10
9
8
JAB_OFF
R/W
JAB_ON
R/W
GAP
R/W
FRAME
R/W
PARITY
R/W
WDT
R/W
CRC
R/W
7
6
5
FIFO_M2D EMPTY
R/W
4
3
2
FIFO_D2M EMPTY
R/W
1
0
FIFO_M2D LEVEL
R/W
FIFO_M2D FULL
R/W
FIFO_D2M LEVEL
R/W
FIFO_D2M FULL
R/W
CD
R/W
CTS
R/W
Table 7. MODEM_IRQ_MASK Register Field Descriptions
Bit
15
14
Field
RESERVED
Type
R/W
R/W
Reset
Description
0
0
Reserved
JAB_OFF
Writing a 1 to this bit blocks the JAB_OFF event from triggering the
IRQ pin
13
12
11
10
9
JAB_ON
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
1
0
0
1
Writing a 1 to this bit blocks the JAB_ON event from triggering the
IRQ pin
GAP
Writing a 1 to this bit blocks the GAP event from triggering the IRQ
pin
FRAME
Writing a 1 to this bit blocks the FRAME event from triggering the
IRQ pin
PARITY
Writing a 1 to this bit blocks the PARITY event from triggering the
IRQ pin
WDT
Writing a 1 to this bit blocks the WDT event from triggering the IRQ
pin
8
CRC
Writing a 1 to this bit blocks the CRC event from triggering the IRQ
pin
7
FIFO_M2D_LEVEL
FIFO_M2D_FULL
FIFO_M2D_EMPTY
FIFO_D2M_LEVEL
FIFO_D2M_FULL
FIFO_D2M_EMPTY
Writing a 1 to this bit blocks the FIFO_M2D_LEVEL event from
triggering the IRQ pin
6
Writing a 1 to this bit blocks the FIFO_M2D_FULL event from
triggering the IRQ pin
5
Writing a 1 to this bit blocks the FIFO_M2D_EMPTY event from
triggering the IRQ pin
4
Writing a 1 to this bit blocks the FIFO_D2M_LEVEL event from
triggering the IRQ pin
3
Writing a 1 to this bit blocks the FIFO_D2M_FULL event from
triggering the IRQ pin
2
Writing a 1 to this bit blocks the FIFO_D2M_EMPTY event from
triggering the IRQ pin
24
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ZHCSJ40 –DECEMBER 2018
Table 7. MODEM_IRQ_MASK Register Field Descriptions (continued)
Bit
1
Field
CD
Type
R/W
R/W
Reset
Description
0
0
Writing a 1 to this bit blocks the CD event from triggering the IRQ pin
0
CTS
Writing a 1 to this bit blocks the CTS event from triggering the IRQ
pin
7.5.5 MODEM_CONTROL Register (Offset = 22h) [reset = 0x0048]
This register controls various modem features including: FF/PA Manchester data polarity, number of FF/PA
preamble bits, analog output amplitude, modem enable, duplex mode, and request to send.
MODEM_CONTROL is shown in Figure 27 and described in Table 8.
Return to Summary Table.
Figure 27. MODEM_CONTROL Register
15
FFPA_POL
R/W
14
6
13
FFPA_PREAMBLE
R/W
12
11
10
RESERVED
R
9
8
TX_AMP
R/W
7
5
4
3
2
1
RESERVED
R
0
TX_AMP
R/W
MOD_EN
R/W
DUP_EN
R/W
RTS
R/W
Table 8. MODEM_CONTROL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
FFPA_POL
R/W
0
Sets the transmitted polarity of the Manchester encoded data
0 = Logical 1 is transmitted as a transition from high-to-low (default)
1 = Logical 1 is transmitted as a transition from low-to-high
14-12
FFPA_PREAMBLE
R/W
0
Number of preamble bytes sent is the value programmed in this
register plus 1
11-9
8-4
RESERVED
TX_AMP
R
0
Reserved
R/W
00100
Unsigned binary value that controls the amplitude (HART mode only)
of the transmitted waveform in 25mVpp steps. Default value 00100
for 500mVpp output amplitude. Amplitude may vary from 400mVpp
to 800mVpp.
3
2
MOD_EN
DUP_EN
R/W
R/W
1
0
0 = Disables TX/RX of the modem
1 = Enables TX/RX of the modem (default)
0 – TX FIFO is not connected to RX FIFO (default)
1 = Connects TX FIFO to RX FIFO
1
0
RESERVED
RTS
R
0
0
Reserved
R/W
0 = No active request to send in HART mode (default)
1 = Active request to send in HART mode
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7.5.6 FIFO_D2M Register (Offset = 23h) [reset = 0x0200]
This register interfaces the FIFO that transmits data from the digital interface to the modem.
FIFO_D2M is shown in Figure 28 and described in Table 9.
Return to Summary Table.
Figure 28. FIFO_D2M Register
15
7
14
6
13
5
12
11
LEVEL_FLAG
R
10
FULL_FLAG
R
9
8
PARITY_BIT
W
FIFO_LEVEL
R
EMPTY_FLAG
R
4
3
2
1
0
DATA
W
Table 9. FIFO_D2M Register Field Descriptions
Bit
Field
Type
R
Reset
Description
Reads back the current level of the FIFO, read only
15-12
11
10
9
FIFO_LEVEL
LEVEL_FLAG
FULL_FLAG
EMPTY_FLAG
PARITY_BIT
DATA
0
0
0
1
0
0
R
Indicates the programmed level has been reached, read only
Indicates the FIFO is full, read only
R
R
Indicates the FIFO is empty, read only
8
W
W
Odd parity for 8-bit data read on bus, write only
Data transmitted from the digital interface to the modem, write only
7-0
7.5.7 FIFO_M2D Register (Offset = 24h) [reset = 0x0200]
This register interfaces the FIFO that receives data from the modem to the digital interface. This register is read
only
FIFO_M2D is shown in Figure 29 and described in Table 10.
Return to Summary Table.
Figure 29. FIFO_M2D Register
15
7
14
6
13
5
12
11
LEVEL_FLAG
R
10
FULL_FLAG
R
9
8
PARITY_BIT
R
FIFO_LEVEL
R
EMPTY_FLAG
R
4
3
2
1
0
DATA
R
Table 10. FIFO_M2D Register Field Descriptions
Bit
Field
Type
R
Reset
Description
Reads back the current level of the FIFO, read only
15-12
11
10
9
FIFO_LEVEL
LEVEL_FLAG
FULL_FLAG
EMPTY_FLAG
PARITY_BIT
DATA
0
0
0
1
0
0
R
Indicates the programmed level has been reached, read only
Indicates the FIFO is full, read only
R
R
Indicates the FIFO is empty, read only
8
R
Odd parity for 8-bit data read on bus, read only
Data transmitted from the modem to the digital interface, read only
7-0
R
26
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7.5.8 FIFO_LEVEL_SET Register (Offset = 25h) [reset = 0x0000]
This register programs the alarm threshold for both transmit and receive FIFOs. Each bit field allows for the FIFO
alarm threshold to be programmed to integer values from 1-15.
FIFO_LEVEL_SET is shown in Figure 30 and described in Table 11.
Return to Summary Table.
Figure 30. FIFO_LEVEL_SET Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
RESERVED
R
4
3
M2D_LEVEL
R/W
D2M_LEVEL
R/W
Table 11. FIFO_LEVEL_SET Register Field Descriptions
Bit
Field
Type
R
Reset
Description
15-8
7-4
RESERVED
M2D_LEVEL
00000000
0000
Reserved
R/W
The binary value in this register sets the modulator FIFO alarm
threshold
3-0
D2M_LEVEL
R/W
0000
The binary value in this register sets the demodulator FIFO alarm
threshold
7.5.9 PAFF_JABBER Register (Offset = 27h) [reset = 0x0000]
This register controls the jabber inhibitor time-out behavior. The time-out can be calculated using the equation
below with PAFF_JABBER in decimal format.
PAFF_JABBER is shown in Figure 31 and described in Table 12.
Return to Summary Table.
Figure 31. PAFF_JABBER Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
RESERVED
R
4
3
PAFF_JABBER
R/W
Table 12. PAFF_JABBER Register Field Descriptions
Bit
Field
Type
R
Reset
Description
15-8
7-0
RESERVED
00000000
00000000
Reserved
PAFF_JABBER
R/W
TimeOut = JABBER_TIMEOUT * 2.048ms
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DAC8742H family of devices integrates modem functionality for several largely used Industrial protocols:
Highway Addressable Remote Transducer (HART), FOUNDATION Fieldbus (FF), and PROFIBUS (PA). The
different modes are set via the CLK_CFGx pins of the device that allow the device to either enter HART or PAFF
mode. In HART mode, a 1200-/2200-Hz HART FSK Signal is modulated and demodulated, while the PAFF mode
communicates via a 31.25 Kbit/s Manchester coded/encoded signal. The small package sizes, wide temperature
range and low quiescent current make this device an ideal candidate for applications in Industrial Process
Control and Automation.
8.1.1 Design Recommendations
Local power supply decoupling is recommended by placing 10-µF capacitors on the IOVDD and AVDD supply
lines, and 0.1-µF capacitors close to the DAC8742H supply pins. Ceramic capacitor types such as C0G or X7R
are recommended for its optimal performance across temperature, and very low dissipation factor. DC bias
characteristics of the capacitors should also be considered when selecting passive components, such as the
voltage rating and equivalent series resistance (ESR).
8.1.2 Selecting the Crystal/Resonator
Both communication modes, HART and PAFF, require different clocking frequencies for correct operation:
HART – 1.2288 MHz or 3.686 MHz, PAFF – 4 MHz. In addition to selecting the communication mode, the
CLK_CFGx and XEN pins also select whether an internal oscillator or external clock source is configured for
device operation. The configuration table is explained in 表 1. Accuracy over the applications temperature range
should be considered when selecting the external crystal or resonator. Furthermore, crystals with a low drift
specification over the desired application temperature range should also be selected when using the DAC8742H
devices in HART, FOUNDATION Fieldbus, and PROFIBUS PA applications as communication timing is critical.
In order to reduce quiescent current consumption, the XTAL nets should be optimized during layout to reduce
any length that may increase net capacitance. This increase in capacitance is directly proportion to current
consumption.
8.1.3 Included Functions and Filter Selection
As a highly integrated device, the DAC8742H not only includes the modulation and demodulation capabilities for
the previously described industrial protocols, but also includes an internal reference, and integrated receive
bandpass filter, with other aforementioned functions. In HART mode, an internal amplifier provides high output
drive capability, and can drive a wide range of purely capacitive loads, ranging from 5 nF to 22 nF. The lower
value specified in the load range is to ensure output stability. Two different filter configurations, external and
internal, are achievable through the BPF_EN digital input -- logic high on this pin enables the internal bandpass
filter. The external filter configuration is shown in 图 32. The example provided displays the DAC8742H device
configured with an external reference and external bandpass filter.
28
版权 © 2018, Texas Instruments Incorporated
DAC8742H
www.ti.com.cn
ZHCSJ40 –DECEMBER 2018
Application Information (接下页)
HART_OUT
4700pF
0.022µF
DAC8740H
14
AGND
MOD_OUT
EXT REF
16
MOD_IN
17
MOD_INF
1
XEN
X1
IOVDD
1.00M
1.50M
21
20
13
HART_IN
150k
300pF
X2
150pF
AGND
REG_CAP
19
12
22
AGND
AGND
DGND
DGND
1µF
25
AGND
PAD
AGND
图 32. HART Mode: DAC8742H Passive Selection For External Bandpass Filter and External Reference
The second configuration, which can reduce costs associated with PCB development and BOM component
counts, additionally aids in the optimization of board space. This optimization gives the user flexibility into
achieving industrial applications with smaller form factor sizes. The internal filter configuration, with correct
MOD_IN, MOD_INF, and MOD_OUT connections, is shown in 图 33.
HART_OUT
4700pF
0.022µF
DAC8740H
14
AGND
MOD_OUT
16
HART_IN
MOD_IN
MOD_INF
17
2200pF
680pF
1
XEN
X1
IOVDD
21
20
13
X2
AGND
REF
REG_CAP
19
12
22
AGND
DGND
DGND
1µF
25
AGND
PAD
AGND
图 33. HART Mode: DAC8742H Passive Selection For Internal Filter
版权 © 2018, Texas Instruments Incorporated
29
DAC8742H
ZHCSJ40 –DECEMBER 2018
www.ti.com.cn
8.2 Typical Application
The application schematic shown in 图 34 is described in the following sections.
C1
C4
0.022 µF
4700pF
IOVDD
AVDD
DAC8740H
C5
0.1 µF
U2
AVDD
R1
1.00M
C6
0.1 µF
18
11
14
AGND
MOD_OUT
AGND
C7
IOVDD
16
17
MOD_IN
MOD_INF
AGND
5
6
7
9
RST
CD
UART_IN
DUPLEX
/RST
2200pF
CD
UART_IN
1
TP5
XEN
X1
IOVDD
C8
680pF
21
10
8
UART_OUT
UART_RTS
UART_OUT
/UART_RTS
AGND
20
13
X2
AGND
TP6
2
3
4
CLKO
CLK_CFG0
CLK_CFG1
5V
REG_CAP
U1
VIN
C9
1µF
19
12
22
AGND
DGND
DGND
1
2
5
AGND
IOVDD
23
24
VOUT
REF_EN
BPF_EN
C2
1µF
C3
10µF
1.5V_REF
15
25
AGND
REF
PAD
3
4
Vref
GND
GND
C10
0.1 µF
DAC8740HRGE
AGND
NC
AGND
R2
100k
AGND
TPS7B6933QDBVRQ1
AGND
AGND
24V
5V
FB1
R3
2.4k
5V
C11
0.1 µF
600 ohm
C12
0.1 µF
U3A
OPA335AIDR
R4
49.9k
AGND
6
AGND
6
U4
VDD
2
Q1
FCX690BTA
R5
R6
14.3k
LM4132AMF-4.1
3
2
R7
AGND
8
3
1
3
1
TP1
11.3k
VOUT
5V
U5
IN
4.096V_non_buffer
5
Vref
U6A
OPA333AID
TP2
10.0
4
3
VREF
VREF
C13
0.012 µF
C14
300pF
C15
1000pF
C16
C17
1µF
C18
0.1 µF
1
C19
4.7 µF
5
6
4
2
7
J1
EN
NC
SCLK
SDI
CS
AGND
DGND
SCLK
SDI
/CS
R8
60.4
5V
2
1
GND
AGND
0.1 µF
2
1
D1
40V
-
+
AGND
CDSOD323-T36SC
R9
1.80k
AGND
AGND
AGND
AGND
D2
ED555/2DS
IOVDD
DAC8830IBDR
R19
1.00M
AGND
R10
10.0
AGND
AGND
C20
1000pF
R11
180
R12
10.0
24V
U7A
5V
R13
200
8
5
1
2
IN
OUT
FB
TP3
R14
107k
FB2
C21
1µF
C22
0.01 µF
C23
10µF
TP4
EN
600 ohm
EP GND
AGND
AGND
R15
32.8k
AGND
TPS7A4101DGNR
Copyright © 2017, Texas Instruments Incorporated
AGND
图 34. 2-Wire Transmitter with DAC8742H HART Modem Design Schematic
30
版权 © 2018, Texas Instruments Incorporated
DAC8742H
www.ti.com.cn
ZHCSJ40 –DECEMBER 2018
8.2.1 Design Requirements
The application presented in 图 34 represents a loop-powered, 2-wire, smart 4-mA to 20-mA transmitter that
commonly resides in factory control and industrial automation sectors. In this application, the DAC8742H enables
a smart interface by providing HART communication, which is responsible for modulating two-way digital
information that encapsulate a wide variety of data, including device/sensor information, calibration data, and
system diagnostic information. This circuit has been successfully HART certification and registered with the
FieldComm Group.
8.2.2 Detailed Design Procedure
8.2.2.1 DAC8742H HART Modem
In this design the DAC8742H internal reference and bandpass filter was chosen to optimize board area,
consequently reducing form factor and cost. X7R, 10% accurate, bypass capacitances of 1-µF and 0.1-µF values
were chosen for the reference and supplies, respectively.
The DAC8742H device interfaces with the MSP430FR5969, or other similar host controller, through a standard
UART interface. The DAC8742H digital pins connected through this interface include UART_RTS, UART_OUT
(TX), UART_IN (RX), and CD.
The remaining portion of the schematic includes other TI devices that aid in the realization of a highly accurate 4-
mA to 20-mA, 2-wire transmitter. This combination of circuitry is ideally suited for remote signal conditioning of a
wide variety of sensors and transducers, including thermocouples, RTDs, thermistors, and strain gauge bridges.
The two-wire transmitter is powered from an external DC power supply that is connected via the two BUS supply
lines. The transmitter communicates by sourcing a 4-mA to 20-mA current through the connected bus, and back
to the central host, which is typically a PLC analog input module. This expressed range of 4 mA to 20 mA is
typically employed to adhere to industry standard, and ensures that the transmitter receives a minimum of 4 mA
for correct powered operation.
Vref
R2
100k
VREF/(R2+R3)
VHART/(R4)
R3
2.4k
R4
49.9k
V+
VDAC/(R5+R6)
R5
R6
14.3k
R7
11.3k
DAC8830
10.0
A1
A2
C13
0.012
µ F
R8
60.4
ILOOP
R9
1.80k
Iq
R10
10.0
1000pF
I1
I2
C20
R11
180
R12
10.0
V-
图 35. Simplified Schematic of the 2-Wire Current Loop
8.2.2.2 2-Wire Current Loop
The A2 operational amplifier employs negative feedback to ensure potentials at both input nodes, V+ and V-, are
equivalent. This establishes the set of KCL equations (1) – assuming no HART communication, VHART = 0 V.
I1 = VDAC/(25.6k) + VREF/(102.4k)
(3)
版权 © 2018, Texas Instruments Incorporated
31
DAC8742H
ZHCSJ40 –DECEMBER 2018
www.ti.com.cn
A2 also drives the base of the NPN BJT, Q1, which enables current to flow from its collector through emitter pins
and through the R8 resistor, while maintaining an equivalent potential drop from its input nodes to the net
represented by TP4. This ensures that the combined voltage drop across R9 and R11 is equivalent to the
combined drop of R10 and R12.
Using this relationship, along with current 公式 3 and 公式 4, IOUT is calculated as follows:
I2 = I1 *(1.80k + 180)/(10 + 10) = I1*(1.980k/20) = I1*99
(4)
(5)
IOUT = I1 + I2 = [VDAC/(25.6k) + VREF/(102.4k)] + I1*99 = [VDAC/(25.6k) + VREF/(102.4k)]*(100)
For a VREF value of 4.096 V, the zero-scale portion of the transfer function, [VREF/(102.4k)]*(100), translates to
4 mA, while the span, [VDAC/(25.6k)]*100, encompasses 16 mA. This final product is a system capable of
sourcing 4 mA to 20 mA, which is dependent on DAC output voltage. The value of R4 is responsible for
converting the 500-mV p-p HART signal into a 1-mA p-p frequency shift keyed (FSK) signal that resides on top of
the 4-mA to 20-mA analog current signal.
8.2.2.3 Regulator
The primary supply for the transmitter is the TPS7A4101 device, which is a 50-V input, 50-mA Single output low-
dropout linear regulator with very low quiescent current, 25 µA. The device supplies a well-regulated voltage rail
(1% accuracy), operating within an extended temperature range of –40°C to 125°C, and also withstands and
maintains regulation during very high and fast voltage transients. In this design the LDO converts the external
supply to a 5-V rail that is used by the DAC8830, LM4132 and OPA333/OPA335. The 200-Ω resistor that
separates the loop supply from the LDO acts as a current limiting resistor at startup and additionally improves the
overall receiver impedance of the design.
Generally, series references are preferred over shunt references because of their lower power consumption; in
this case the LM4132 exhibits a maximum of 60-µA quiescent current. Moreover, the device has an initial
accuracy of 0.05% with a specified temperature coefficient of 10 ppm/°C or less, and is capable of operating with
these metrics at an extended temperature range of –40°C to 125°C.
In order to generate a 3.3-V supply for the DAC8742H, the TPS7B6933-Q1, a low-dropout linear regulator with
low quiescent current, is incorporated into the design. This LDO is capable of operating over a wide temperature
range of –40°C to 125°C, while exhibiting a maximum quiescent value of 25 µA over this temperature range.
8.2.2.4 DAC
After sufficient bypass, this precision reference voltage is applied to the VREF pin of the DAC8830 device. An
accurate reference along with an accurate DAC are largely responsible for the overall accuracy of the current
loop, as any accuracy errors associated with the DAC will propagate through the rest of the signal chain and
decrease the accuracy of the solution. In this case, the DAC8830, a 16-bit voltage-output DAC with excellent
linearity (1 LSB INL), low glitch, low noise, and fast settling was chosen to set the base line performance of the
design.
8.2.2.5 Amplifiers
Next, the voltage output is buffered with the OPA333 CMOS operation amplifier, which features near-zero drift
over time and temperature, low quiescent current (17 µA), and single supply operation with rail-to-rail output that
swings within 50 mV of the supply rail.
As with the OPA333, the OPA335 was chosen due to its excellent DC accuracy specifications. These parameters
include low input bias current, low offset voltage, and high CMRR/PSRR. In addition to these DC specifications,
the OPA335 features an operating bandwidth of up to 2 MHz, which provides ample margin for HART
communication.
8.2.2.6 Diodes
For transient voltage protection, a 40-V bidirectional transient voltage suppressor (TVS) diode is placed across
the BUS lines of the design. Certain criteria should be considered when making this diode selection, such as the
diode’s working voltage, breakdown voltage, leakage current and power rating. In addition to these parameters,
leakage current should also be factored into the design as it will impact the accuracy of the analog current loop.
32
版权 © 2018, Texas Instruments Incorporated
DAC8742H
www.ti.com.cn
ZHCSJ40 –DECEMBER 2018
2-wire polarity protection is also employed by using the DSRHD10 as a diode bridge rectifier. The placement of
this component ensures that the current loop will always correctly operate regardless of the arrangement of input
connections. As with other elements, leakage and biasing voltage should be considered as it will affect system
accuracy and compliance voltage.
8.2.2.7 Passives
Among the passives included in the design, the gain setting resistors should be chosen to exhibit tight tolerances
in order to achieve high accuracy. These resistors -- R4, R5, R6, R9, R11, R10, and R12 -- are primarily
responsible for setting the gain of the current loop, along with primary path of the output current flow. Since the
biased transistor, Q1, is responsible for sourcing most of the output current, components in the path of this
current flow should be chosen with appropriate power ratings. In this case R8 is a 0.25-W resistor.
8.2.3 Application Curves
Five hundred datapoints were taken on five different boards, producing the 4 to 20-mA transfer function below in
图 36. The total unadjusted error (TUE) of the transmitters is displayed in 图 37.
图 36. 4-20mA Transfer Function
图 37. Total Unadjusted Error Graph of Application Circuit
版权 © 2018, Texas Instruments Incorporated
33
DAC8742H
ZHCSJ40 –DECEMBER 2018
www.ti.com.cn
9 Power Supply Recommendations
The DAC8742H can operate with analog supplies from 2.7 V to 5.5 V and digital supplies from 1.71 V to 5.5 V,
enabling interfacing host controller platforms with low voltage digital logic. For applications that are particularly
focused on reducing power dissipation in the modem, it is suggested to use the lowest supply voltage available
for both analog and digital supplies.
34
版权 © 2018, Texas Instruments Incorporated
DAC8742H
www.ti.com.cn
ZHCSJ40 –DECEMBER 2018
10 Layout
10.1 Layout Guidelines
Precision designs require careful layout, the list below provides some insight into good layout practices.
• All Power Supply pins should be bypassed to ground with a low ESR ceramic bypass capacitor. The typical
recommended bypass capacitance is 0.1 to 1 µF ceramic with a X7R or NP0 dielectric.
• Power supply and Reference bypass capacitors should be placed close to terminals to minimize inductance and
optimize performance.
• A high-quality ceramic type NP0 or X7R is recommended for its optimal performance across temperature, and
very low dissipation factor.
• The digital and analog sections should have proper placement with respect to the digital and analog
components. The separation of analog and digital circuitry will allow for better design and practice as it will
ensure less coupling into neighboring blocks, and will minimize the interaction between analog and digital return
currents.
10.2 Layout Example
Bypass
Capacitor
12
6
18
1
24
Bypass
Capacitor
图 38. DAC8742H Basic Layout Example
版权 © 2018, Texas Instruments Incorporated
35
DAC8742H
ZHCSJ40 –DECEMBER 2018
www.ti.com.cn
Layout Example (接下页)
图 39. 2-Wire Transmitter with DAC8742H HART Modem Layout - Top Layer
图 40. 2-Wire Transmitter with DAC8742H HART Modem Layout - Bottom Layer
36
版权 © 2018, Texas Instruments Incorporated
DAC8742H
www.ti.com.cn
ZHCSJ40 –DECEMBER 2018
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档:《DAC8742H 评估模块用户指南》(SLAU700)
11.2 接收文档更新通知
要接收文档更新通知,请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册,即可每周接收产
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
FOUNDATION 现场总线 is a trademark of FieldComm Group.
HART is a registered trademark of FieldComm Group.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
版权 © 2018, Texas Instruments Incorporated
37
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC8742HPBS
ACTIVE
ACTIVE
TQFP
TQFP
PBS
PBS
32
32
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-55 to 125
-55 to 125
8742H
8742H
DAC8742HPBSR
1000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC8742HPBSR
TQFP
PBS
32
1000
330.0
16.4
7.2
7.2
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TQFP PBS 32
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
DAC8742HPBSR
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
DAC8742HPBS
PBS
TQFP
32
250
10 X 25
150
315 135.9 7620 12.2
11.1 11.25
Pack Materials-Page 3
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
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