DAC8718SPAGR [TI]
Octal, 16-Bit, Low-Power, High-Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER; 八路， 16位，低功耗，高电压输出，串行输入数位类比转换器
| 型号： | DAC8718SPAGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Octal, 16-Bit, Low-Power, High-Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总60页 (文件大小：1605K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC8718
www.ti.com
SBAS467A –MAY 2009–REVISED DECEMBER 2009
Octal, 16-Bit, Low-Power, High-Voltage Output, Serial Input
DIGITAL-TO-ANALOG CONVERTER
Check for Samples: DAC8718
1
FEATURES
DESCRIPTION
2345
•
Bipolar Output: ±2V to ±16.5V
Unipolar Output: 0V to +33V
16-Bit Resolution
The DAC8718 is
digital-to-analog converter (DAC). With
a
low-power, octal, 16-bit
5V
a
•
reference, the output can either be a bipolar ±15V
voltage when operating from dual ±15.5V (or higher)
power supplies, or a unipolar 0V to +30V voltage
when operating from a +30.5V (or higher) power
supply. With a 5.5V reference, the output can either
be a bipolar ±16.5V voltage when operating from dual
±17V (or higher) power supplies, or a unipolar 0V to
+33V voltage when operating from a +33.5V (or
higher) power supply. This DAC provides low-power
operation, good linearity, and low glitch over the
specified temperature range of –40°C to +105°C. This
device is trimmed in manufacturing and has very low
zero-code and gain error. In addition, system level
calibration can be performed to achieve ±1 LSB
bipolar zero/full-scale error with bipolar supplies, or
±1 LSB zero code/full-scale error with a unipolar
supply, over the entire signal chain. The output range
can be offset by using the DAC offset register.
•
•
•
•
Low Power: 14.4mW/Ch (Bipolar Supply)
Relative Accuracy: 4 LSB Max
Low Zero/Full-Scale Error
–
–
Before User Calibration: ±10 LSB Max
After User Calibration: ±1 LSB
•
•
•
•
•
•
•
•
•
•
Flexible System Calibration
Low Glitch: 4nV-s
Settling Time: 15μs
Channel Monitor Output
Programmable Gain: x4/x6
Programmable Offset
SPI™: Up to 50MHz, 1.8V/3V/5V Logic
Schmitt Trigger Inputs
The DAC8718 features a standard, high-speed serial
peripheral interface (SPI) that operates at up to
50MHz and is 1.8V, 3V, and 5V logic compatible, to
communicate with a DSP or microprocessor. The
input data of the device are double-buffered. An
asynchronous load input (LDAC) transfers data from
the DAC data register to the DAC latch. The
asynchronous CLR input sets the output of all eight
DACs to AGND. The VMON pin is a monitor output
that connects to the individual analog outputs, the
offset DAC, the reference buffer outputs, and two
external inputs through a multiplexer (mux).
Daisy-Chain with Sleep Mode Enhancement
Packages: QFN-48 (7x7mm), TQFP-64
(10x10mm)
APPLICATIONS
•
•
•
Automatic Test Equipment
PLC and Industrial Process Control
Communications
IOVDD
DGND
DVDD
AVDD
AVSS
REF-A
Analog Monitor
DAC8718
VOUT-0
The DAC8718 is pin-to-pin and function-compatible
with the DAC8218 (14-bit) and the DAC7718 (12-bit).
VOUT-7
AIN-0
AIN-1
Ref Buffer A
Ref Buffer B
OFFSET-B
VMON
Reference
Buffer A
OFFSET
DAC A
WAKEUP
SCLK
CS
Command
Registers
To DAC-0, DAC-1,
DAC-2, DAC-3
(When Correction Engine Disabled)
SDI
OFFSET-A
VOUT-0
SDO
DAC-0
Input Data
Register 0
Correction
Engine
DAC-0
Data
Latch-0
To DAC-0, DAC-1,
DAC-2, DAC-3
LDAC
RST
RSTSEL
LDAC
User Calibration:
Zero Register 0
Gain Regsiter 0
Internal Trimming
Zero/Gain; INL
AGND-A
CLR
To DAC-4, DAC-5, DAC-6, DAC-7
USB/BTC
GPIO-0
GPIO-1
GPIO-2
OFFSET-B
AGND-B
VOUT-7
OFFSET
DAC B
(Same Function Blocks
for All Channels)
Reference
Buffer B
Power-Up/
Power-Down
Control
AIN-0
AIN-1
DGND
DVDD
AVDD
AVSS
REF-B
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
5
DSP is a trademark of Texas Instruments.
SPI, QSPI are trademarks of Motorola Inc.
Microwire is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
DAC8718
SBAS467A –MAY 2009–REVISED DECEMBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
LINEARITY
(LSB)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
PRODUCT
±4
±4
±1
±1
QFN-48
RGZ
PAG
–40°C to +105°C
–40°C to +105°C
DAC8718
DAC8718
DAC8718
TQFP-64
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted).
DAC8718
UNIT
V
AVDD to AVSS
–0.3 to 38
AVDD to AGND
–0.3 to 38
V
AVSS to AGND, DGND
DVDD to DGND
–19 to 0.3
V
–0.3 to 6
V
IOVDD to DGND
–0.3 to min of (6 or DVDD + 0.3)
V
AGND-x to DGND
–0.3 to 0.3
V
Digital input voltage to DGND
SDO to DGND
–0.3 to IOVDD + 0.3
V
–0.3 to IOVDD + 0.3
V
VOUT-x, VMON, AIN-x to AVSS
REF-A, REF-B to AGND
GPIO-n to DGND
–0.3 to AVDD + 0.3
V
–0.3 to DVDD
V
–0.3 to IOVDD + 0.3
V
GPIO-n input current
Maximum current from VMON
Operating temperature range
Storage temperature range
Maximum junction temperature (TJ max)
5
mA
mA
°C
°C
°C
kV
V
3
–40 to +105
–65 to +150
+150
Human body model (HBM)
2.5
ESD ratings
Charged device model (CDM)
Machine model (MM)
1000
200
V
TQFP
QFN
55
°C/W
°C/W
°C/W
°C/W
W
Junction-to-ambient, θJA
Junction-to-case, θJC
27.5
Thermal impedance
Power dissipation
TQFP
QFN
21
10.8
(TJ max – TA) / θJA
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC8718
DAC8718
www.ti.com
SBAS467A –MAY 2009–REVISED DECEMBER 2009
ELECTRICAL CHARACTERISTICS: Dual-Supply
All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V,
gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values(1)
,
unless otherwise noted.
DAC8718
PARAMETER
STATIC PERFORMANCE(2)
Resolution
CONDITIONS
MIN
TYP
MAX
UNIT
16
Bits
LSB
LSB
LSB
LSB
LSB
Linearity error
Measured by line passing through codes 0000h and FFFFh
Measured by line passing through codes 0000h and FFFFh
TA = +25°C, before user calibration, gain = 6, code = 8000h
TA = +25°C, before user calibration, gain = 4, code = 8000h
TA = +25°C, after user calib., gain = 4 or 6, code = 8000h
Gain = 4 or 6, code = 8000h
±4
±1
Differential linearity error
±10
±15
Bipolar zero error
±1
Bipolar zero error TC
Zero-code error
Zero-code error TC
Gain error
±0.5
±2 ppm FSR/°C
TA = +25°C, gain = 6, code = 0000h
±10
±15
LSB
LSB
TA = +25°C, gain = 4, code = 0000h
Gain = 4 or 6, code = 0000h
±0.5
±1
±3 ppm FSR/°C
TA = +25°C, gain = 6
±10
±15
LSB
LSB
TA = +25°C, gain = 4
Gain error TC
Gain = 4 or 6
±3 ppm FSR/°C
TA = +25°C, before user calibration, gain = 6, code = FFFFh
TA = +25°C, before user calibration, gain = 4, code = FFFFh
TA = +25°C, after user calib., gain = 4 or 6, code = FFFFh
Gain = 4 or 6, code = FFFFh
±10
±15
LSB
LSB
LSB
Full-scale error
±1
Full-scale error TC
DC crosstalk(3)
±0.5
±3 ppm FSR/°C
LSB
Measured channel at code = 8000h, full-scale change on any
other channel
0.2
(1) Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the error for symmetrical output. The default value may vary
no more than ±10 LSB from the nominal number listed in Table 7. The Offset DAC pins are not intended to drive an external load, and
must not be connected during dual-supply operation.
(2) Gain = 4 and TC specified by design and characterization.
(3) The DAC outputs are buffered by op amps that share common AVDD and AVSS power supplies. DC crosstalk indicates how much dc
change in one or more channel outputs may occur when the dc load current changes in one channel (because of an update). With
high-impedance loads, the effect is virtually immeasurable. Multiple AVDD and AVSS terminals are provided to minimize dc crosstalk.
Copyright © 2009, Texas Instruments Incorporated
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DAC8718
SBAS467A –MAY 2009–REVISED DECEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS: Dual-Supply (continued)
All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V,
gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values (1)
,
unless otherwise noted.
DAC8718
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG OUTPUT (VOUT-0 to VOUT-7)(4)
VREF = +5V
–15
+15
+4.5
0.5
V
V
Voltage output(5)
VREF = +1.5V
Code = 8000h
–4.5
Output impedance
Short-circuit current(6)
Load current
Ω
±8
±3
mA
mA
See Figure 37
TA = +25°C, device operating for 500 hours, full-scale output
TA = +25°C, device operating for 1000 hours, full-scale output
3.4
4.3
ppm of FSR
ppm of FSR
pF
Output drift vs time
Capacitive load stability
500
To 0.03% of FSR, CL = 200pF, RL= 10kΩ, code from 0000h
to FFFFh and FFFFh to 0000h
10
15
6
μs
μs
μs
To 1 LSB, CL = 200pF, RL = 10kΩ, code from 0000h to
FFFFh and FFFFh to 0000h
Settling time
To 1 LSB, CL = 200pF, RL = 10kΩ, code from 7F00h to
8100h and 8100h to 7F00h
(7)
Slew rate
6
200
60
4
V/μs
μs
Power-on delay(8)
From IOVDD ≥ +1.8V and DVDD ≥ +2.7V to CS low
Power-down recovery time
Digital-to-analog glitch(9)
Glitch impulse peak amplitude
Channel-to-channel isolation(10)
μs
Code from 7FFFh to 8000h and 8000h to 7FFFh
Code from 7FFFh to 8000h and 8000h to 7FFFh
VREF = 4VPP, f = 1kHz
nV-s
mV
5
88
7.5
1
dB
DACs in the same group
nV-s
nV-s
nV-s
nV-s
nV/√Hz
nV/√Hz
μVPP
LSB
DAC-to-DAC crosstalk(11)
DACs among different groups
Digital crosstalk(12)
Digital feedthrough(13)
1
1
TA = +25°C at 10kHz, gain = 6
TA = +25°C at 10kHz, gain = 4
0.1Hz to 10Hz, gain = 6
200
130
20
0.05
Output noise
Power-supply rejection(14)
AVDD = ±15.5V to ±16.5V
(4) Specified by design.
(5) The analog output range of VOUT-0 to VOUT-7 is equal to (6 × VREF – 5 × OUTPUT_OFFSET_DAC) for gain = 6. The maximum value of
the analog output must not be greater than (AVDD – 0.5V), and the minimum value must not be less than (AVSS + 0.5V). All
specifications are for a ±16.5V power supply and a ±15V output, unless otherwise noted.
(6) When the output current is greater than the specification, the current is clamped at the specified maximum value.
(7) Slew rate is measured from 10% to 90% of the transition when the output changes from 0 to full-scale.
(8) Power-on delay is defined as the time from when the supply voltages reach the specified conditions to when CS goes low, for valid
digital communication.
(9) Digital-to-analog glitch is defined as the amount of energy injected into the analog output at the major code transition. It is specified as
the area of the glitch in nV-s. It is measured by toggling the DAC register data between 7FFFh and 8000h in straight binary format.
(10) Channel-to-channel isolation refers to the ratio of the signal amplitude at the output of one DAC channel to the amplitude of the
sinusoidal signal on the reference input of another DAC channel. It is expressed in dB and measured at midscale.
(11) DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one DAC as a result of both the full-scale digital code and
subsequent analog output change at another DAC. It is measured with LDAC tied low and expressed in nV-s.
(12) Digital crosstalk is the glitch impulse transferred to the output of one converter as a result of a full-scale code change in the DAC input
register of another converter. It is measured when the DAC output is not updated, and is expressed in nV-s.
(13) Digital feedthrough is the glitch impulse injected to the output of a DAC as a result of a digital code change in the DAC input register of
the same DAC. It is measured with the full-scale digital code change without updating the DAC output, and is expressed in nV-s.
(14) The output must not be greater than (AVDD – 0.5V) and not less than (AVSS + 0.5V).
4
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Product Folder Link(s): DAC8718
DAC8718
www.ti.com
SBAS467A –MAY 2009–REVISED DECEMBER 2009
ELECTRICAL CHARACTERISTICS: Dual-Supply (continued)
All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V,
gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values (1)
,
unless otherwise noted.
DAC8718
PARAMETER
OFFSET DAC OUTPUT(15)
Voltage output
CONDITIONS
MIN
TYP
MAX
UNIT
(16)
VREF = +5V
TA = +25°C
TA = +25°C
0
5
V
Full-scale error
±4
±2
±6
LSB
LSB
LSB
LSB
Zero-code error
Linearity error
Differential linearity error
±1
ANALOG MONITOR PIN (VMON
Output impedance(17)
Three-state leakage current
AUXILIARY ANALOG INPUT
Input range
)
TA = +25°C
TA = +25°C
2
kΩ
100
nA
AVSS
AVDD
V
Input impedance
2
kΩ
(AIN-x to VMON
)
Input capacitance(15)
Input leakage current
REFERENCE INPUT
4
pF
nA
30
Reference input voltage range(18)
Reference input dc impedance
Reference input capacitance(15)
DIGITAL INPUT(15)
1.0
5.5
V
10
10
MΩ
pF
IOVDD = +4.5V to +5.5V
IOVDD = +2.7V to +3.3V
IOVDD = +1.7V to 2.0V
IOVDD = +4.5V to +5.5V
IOVDD = +2.7V to +3.3V
IOVDD = +1.7V to 2.0V
3.8
2.3
0.3 + IOVDD
V
V
High-level input voltage, VIH
0.3 + IOVDD
1.5
0.3 + IOVDD
V
–0.3
–0.3
–0.3
0.8
0.6
0.3
±1
V
Low-level input voltage, VIL
Input current
V
V
CLR, LDAC, RST, CS, and SDI
USB/BTC, RSTSEL, and GPIO-n
CLR, LDAC, RST, CS, and SDI
USB/BTC and RSTSEL
GPIO-n
μA
μA
pF
pF
pF
±5
5
12
14
Input capacitance
DIGITAL OUTPUT(15)
IOVDD = +2.7V to +5.5V, sourcing 1mA
IOVDD = +1.8V, sourcing 200μA
IOVDD = +2.7V to +5.5V, sinking 1mA
IOVDD = +1.8V, sinking 200μA
1mA sink from IOVDD
IOVDD – 0.4
IOVDD
IOVDD
0.4
V
V
High-level output voltage, VOH
(SDO)
1.6
0
V
Low-level output voltage, VOL
(SDO)
0
0.2
V
GPIO-n output voltage low, VOL
0.15
V
GPIO-n output voltage high, VOH 10kΩ pull-up resistor to IOVDD
0.99 × IOVDD
V
High-impedance leakage current SDO and GPIO-n
±5
5
μA
pF
pF
SDO
High-impedance output
capacitance
GPIO-n
14
(15) Specified by design.
(16) Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the error for symmetrical output. The default value may vary
no more than ±10 LSB from the nominal number listed in Table 7. The Offset DAC pins are not intended to drive an external load, and
must not be connected during dual-supply operation.
(17) 8kΩ when VMON is connected to Reference Buffer A or B, and 4kΩ when VMON is connected to Offset DAC-A or -B.
(18) Reference input voltage ≤ DVDD
.
Copyright © 2009, Texas Instruments Incorporated
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DAC8718
SBAS467A –MAY 2009–REVISED DECEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS: Dual-Supply (continued)
All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V,
gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values (1)
,
unless otherwise noted.
DAC8718
PARAMETER
POWER SUPPLY
CONDITIONS
MIN
TYP
MAX
UNIT
AVDD
AVSS
DVDD
IOVDD
+4.5
–18
+18
–4.5
+5.5
+5.5
6
V
V
+2.7
+1.8
V
(19)
V
Normal operation, midscale code, output unloaded
Power down, output unloaded
4.3
35
mA
μA
mA
μA
μA
μA
μA
μA
mW
AIDD
AISS
DIDD
IOIDD
Normal operation, midscale code, output unloaded
Power down, output unloaded
–4
–2.7
35
Normal operation
78
Power down
36
Normal operation, VIH = IOVDD, VIL = DGND
Power down, VIH = IOVDD, VIL = DGND
Normal operation, ±16.5V supplies, midscale code
5
5
Power dissipation
115
165
TEMPERATURE RANGE
Specified performance
–40
+105
°C
(19) IOVDD ≤ DVDD
.
6
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SBAS467A –MAY 2009–REVISED DECEMBER 2009
ELECTRICAL CHARACTERISTICS: Single-Supply
All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6,
AGND-x = DGND = 0V, data format = straight binary, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted.
DAC8718
PARAMETER
STATIC PERFORMANCE(1)
Resolution
CONDITIONS
MIN
TYP
MAX
UNIT
16
Bits
LSB
LSB
LSB
LSB
LSB
Linearity error
Measured by line passing through codes 0100h and FFFFh
Measured by line passing through codes 0100h and FFFFh
TA = +25°C, before user calibration, gain = 6, code = 0100h
TA = +25°C, before user calibration, gain = 4, code = 0100h
TA = +25°C, after user calib., gain = 4 or 6, code = 0100h
Gain = 4 or 6, code = 0100h
±4
±1
Differential linearity error
±10
±15
Unipolar zero error
±1
Unipolar zero error TC
Gain error
±0.5
±3 ppm FSR/°C
TA = +25°C, gain = 6
±10
±15
LSB
LSB
TA = +25°C, gain = 4
Gain error TC
Gain = 4 or 6
±1
±3 ppm FSR/°C
TA = +25°C, before user calibration, gain = 6, code = FFFFh
TA = +25°C, before user calibration, gain = 4, code = FFFFh
TA = +25°C, after user calib., gain = 4 or 6, code = FFFFh
Gain = 4 or 6, code = FFFFh
±10
±15
LSB
LSB
LSB
Full-scale error
±1
Full-scale error TC
DC crosstalk(2)
±0.5
±3 ppm FSR/°C
LSB
Measured channel at code = 8000h, full-scale change on any
other channel
0.2
ANALOG OUTPUT (VOUT-0 to VOUT-7)(3)
VREF = +5V
0
0
+30
V
Voltage output(4)
VREF = +1.5V
Code = 8000h
+9
V
Output impedance
Short-circuit current(5)
Load current
0.5
Ω
mA
±8
±3
See Figure 84 and Figure 85
mA
TA = +25°C, device operating for 500 hours, full-scale output
TA = +25°C, device operating for 1000 hours, full-scale output
3.4
4.3
ppm of FSR
ppm of FSR
pF
Output drift vs time
Capacitive load stability
500
To 0.03% of FSR, CL = 200pF, RL= 10kΩ, code from 0100h to
FFFFh and FFFFh to 0100h
10
15
6
μs
μs
μs
To 1 LSB, CL = 200pF, RL = 10kΩ, code from 0100h to FFFFh
and FFFFh to 0100h
Settling time
To 1 LSB, CL = 200pF, RL = 10kΩ, code from 7F00h to 8100h
and 8100h to 7F00h
Slew rate(6)
Power-on delay(7)
6
200
90
4
V/μs
μs
From IOVDD ≥ +1.8V and DVDD ≥ +2.7V to CS low
Power-down recovery time
Digital-to-analog glitch(8)
Glitch impulse peak amplitude
Channel-to-channel isolation(9)
μs
Code from 7FFFh to 8000h and 8000h to 7FFFh
Code from 7FFFh to 8000h and 8000h to 7FFFh
VREF = 4VPP, f = 1kHz
nV-s
mV
dB
5
88
(1) Gain = 4 and TC specified by design and characterization.
(2) The DAC outputs are buffered by op amps that share common AVDD and AVSS power supplies. DC crosstalk indicates how much dc
change in one or more channel outputs may occur when the dc load current changes in one channel (because of an update). With
high-impedance loads, the effect is virtually immeasurable. Multiple AVDD and AVSS terminals are provided to minimize dc crosstalk.
(3) Specified by design.
(4) The analog output range of VOUT-0 to VOUT-7 is equal to (6 × VREF) for gain = 6. The maximum value of the analog output must not be
greater than (AVDD – 0.5V). All specifications are for a +32V power supply and a 0V to +30V output, unless otherwise noted.
(5) When the output current is greater than the specification, the current is clamped at the specified maximum value.
(6) Slew rate is measured from 10% to 90% of the transition when the output changes from 0 to full-scale.
(7) Power-on delay is defined as the time from when the supply voltages reach the specified conditions to when CS goes low, for valid
digital communication.
(8) Digital-to-analog glitch is defined as the amount of energy injected into the analog output at the major code transition. It is specified as
the area of the glitch in nV-s. It is measured by toggling the DAC register data between 7FFFh and 8000h in straight binary format.
(9) Channel-to-channel isolation refers to the ratio of the signal amplitude at the output of one DAC channel to the amplitude of the
sinusoidal signal on the reference input of another DAC channel. It is expressed in dB and measured at midscale.
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ELECTRICAL CHARACTERISTICS: Single-Supply (continued)
All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6,
AGND-x = DGND = 0V, data format = straight binary, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted.
DAC8718
PARAMETER
CONDITIONS
DACs in the same group
MIN
TYP
10
MAX
UNIT
nV-s
DAC-to-DAC crosstalk(10)
DACs among different groups
1
nV-s
Digital crosstalk(11)
1
nV-s
Digital feedthrough(12)
1
nV-s
TA = +25°C at 10kHz, gain = 6
TA = +25°C at 10kHz, gain = 4
0.1Hz to 10Hz, gain = 6
200
130
20
nV/√Hz
nV/√Hz
μVPP
Output noise
Power-supply rejection(13)
ANALOG MONITOR PIN (VMON
Output impedance(14)
Three-state leakage current
AUXILIARY ANALOG INPUT
Input range
AVDD = +33V to +36V
0.05
LSB
)
TA = +25°C
TA = +25°C
2
kΩ
100
nA
AVSS
AVDD
V
Input impedance
2
kΩ
(AIN-x to VMON
)
Input capacitance(15)
Input leakage current
REFERENCE INPUT
4
pF
nA
30
Reference input voltage
range(16)
1.0
5.5
V
Reference input dc impedance
Reference input capacitance(15)
DIGITAL INPUT(15)
10
10
MΩ
pF
IOVDD = +4.5V to +5.5V
IOVDD = +2.7V to +3.3V
IOVDD = +1.7V to 2.0V
IOVDD = +4.5V to +5.5V
IOVDD = +2.7V to +3.3V
IOVDD = +1.7V to 2.0V
CLR, LDAC, RST, CS, and SDI
USB/BTC, RSTSEL, and GPIO-n
CLR, LDAC, RST, CS, and SDI
USB/BTC and RSTSEL
GPIO-n
3.8
2.3
0.3 + IOVDD
V
V
High-level input voltage, VIH
0.3 + IOVDD
1.5
0.3 + IOVDD
V
–0.3
–0.3
–0.3
0.8
0.6
0.3
±1
V
Low-level input voltage, VIL
Input current
V
V
μA
μA
pF
pF
pF
±5
5
12
14
Input capacitance
(10) DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one DAC as a result of both the full-scale digital code and
subsequent analog output change at another DAC. It is measured with LDAC tied low and expressed in nV-s.
(11) Digital crosstalk is the glitch impulse transferred to the output of one converter as a result of a full-scale code change in the DAC input
register of another converter. It is measured when the DAC output is not updated, and is expressed in nV-s.
(12) Digital feedthrough is the glitch impulse injected to the output of a DAC as a result of a digital code change in the DAC input register of
the same DAC. It is measured with the full-scale digital code change without updating the DAC output, and is expressed in nV-s.
(13) The analog output must not be greater than (AVDD – 0.5V).
(14) 8kΩ when VMON is connected to Reference Buffer A or B, and 4kΩ when VMON is connected to Offset DAC-A or -B.
(15) Specified by design.
(16) Reference input voltage ≤ DVDD
.
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ELECTRICAL CHARACTERISTICS: Single-Supply (continued)
All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6,
AGND-x = DGND = 0V, data format = straight binary, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted.
DAC8718
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL OUTPUT(17)
IOVDD = +2.7V to +5.5V, sourcing 1mA
IOVDD = +1.8V, sourcing 200μA
IOVDD = +2.7V to +5.5V, sinking 1mA
IOVDD = +1.8V, sinking 200μA
IOVDD – 0.4
IOVDD
IOVDD
0.4
V
V
High-level output voltage, VOH
(SDO)
1.6
0
V
Low-level output voltage, VOL
(SDO)
0
0.2
V
GPIO-n output voltage low, VOL 1mA sink from IOVDD
GPIO-n output voltage high, VOH 10kΩ pull-up resistor to IOVDD
High-impedance leakage current SDO and GPIO-n
0.15
V
0.99 × IOVDD
V
±5
5
μA
pF
pF
SDO
High-impedance output
capacitance
GPIO-n
14
POWER SUPPLY
AVDD
+9
+2.7
+1.8
+36
+5.5
+5.5
7
V
V
DVDD
(18)
IOVDD
V
Normal operation, midscale code, output unloaded
4.5
35
70
36
5
mA
µA
μA
μA
μA
μA
mW
AIDD
DIDD
IOIDD
Power down, output unloaded
Normal operation
Power down
Normal operation, VIH = IOVDD, VIL = DGND
Power down, VIH = IOVDD, VIL = DGND
Normal operation
5
Power dissipation
140
225
TEMPERATURE RANGE
Specified performance
–40
+105
°C
(17) Specified by design.
(18) IOVDD ≤ DVDD
.
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FUNCTIONAL BLOCK DIAGRAM
IOVDD
DGND
DVDD
AVDD
AVSS
REF-A
Analog Monitor
DAC8718
VOUT-0
VOUT-7
AIN-0
AIN-1
VMON
Reference
Buffer A
OFFSET
DAC A
WAKEUP
SCLK
CS
Ref Buffer A
Ref Buffer B
OFFSET-B
Command
Registers
To DAC-0, DAC-1,
DAC-2, DAC-3
(When Correction Engine Disabled)
SDI
OFFSET-A
VOUT-0
SDO
DAC-0
Input Data
Register 0
Correction
Engine
DAC-0
Data
Latch-0
To DAC-0, DAC-1,
DAC-2, DAC-3
LDAC
RST
RSTSEL
LDAC
User Calibration:
Zero Register 0
Gain Regsiter 0
Internal Trimming
Zero/Gain; INL
AGND-A
CLR
To DAC-4, DAC-5, DAC-6, DAC-7
USB/BTC
GPIO-0
GPIO-1
GPIO-2
OFFSET-B
AGND-B
VOUT-7
OFFSET
DAC B
(Same Function Blocks
for All Channels)
Reference
Buffer B
Power-Up/
Power-Down
Control
AIN-0
AIN-1
DGND
DVDD
AVDD
AVSS
REF-B
Figure 1. Functional Block Diagram
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PIN CONFIGURATIONS
PAG PACKAGE
TQFP-64
(TOP VIEW)
RGZ PACKAGE
QFN-48
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVDD
NC
1
2
3
4
5
6
7
8
9
48 AVDD
47 NC
36
35
34
33
32
31
30
29
28
27
26
25
AVDD
1
2
AVDD
AIN-0
AIN-0
46 AIN-1
45 VOUT-4
44 REF-B
43 VOUT-5
42 VOUT-6
41 AGND-B
40 AGND-B
39 OFFSET-B
38 VOUT-7
37 AVSS
36 NC
AIN-1
VOUT-3
REF-A
VOUT-2
VOUT-1
AGND-A
AGND-A
3
VOUT-4
REF-B
VOUT-5
VOUT-6
AGND-B
AGND-B
OFFSET-B
VOUT-7
AVSS
VOUT-3
REF-A
4
5
VOUT-2
VOUT-1
AGND-A
AGND-A
OFFSET-A
VOUT-0
AVSS
6
DAC8718
DAC8718
7
OFFSET-A 10
VOUT-0 11
AVSS 12
NC 13
8
9
10
11
12
VMON 14
NC 15
35 NC
34 NC
NC
VMON
NC 16
33 NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
(1) The thermal pad is internally connected to
the substrate. This pad can be connected
to AVSS or left floating. Keep the thermal
pad separate from the digital ground, if
possible.
PIN DESCRIPTIONS
PIN NO.
PIN
NAME
QFN-48
TQFP-64
I/O
I
DESCRIPTION
AVDD
AIN-0
1
2
3
4
5
6
7
8
1
3
4
5
6
7
8
9
Positive analog power supply
I
Auxiliary analog input 0, directly routed to the analog mux
VOUT-3
REF-A
VOUT-2
VOUT-1
AGND-A
AGND-A
O
I
DAC-3 output
Group A(1) reference input
O
O
I
DAC-2 output
DAC-1 output
Group A analog ground and the ground of REF-A. This pin must be tied to AGND-B and DGND.
Group A analog ground and the ground of REF-A. This pin must be tied to AGND-B and DGND.
I
OFFSET DAC-A analog output. Must be connected to AGND-A during single power-supply
operation (AVSS = 0V). This pin is not intended to drive an external load.
OFFSET-A
9
10
O
VOUT-0
AVSS
10
11
11
12
O
I
DAC-0 output
Negative analog power supply
Analog monitor output. This pin is either in Hi-Z status, connected to one of the eight DAC outputs,
reference buffer outputs, offset DAC outputs, or one of the auxiliary analog inputs, depending on
the content of the Monitor Register. See the Monitor Register, Table 12, for details.
VMON
GPIO-2
CLR
12
13
14
15
14
19
20
21
O
I/O
I
General-purpose digital input/output 2. This pin is a bidirectional digital input/output, open-drain and
requires an external pull-up resistor. See the GPIO Pins section for details.
Clear input, level triggered. When the CLR pin is logic '0', all VOUT-X pins connect to AGND-x
through switches and internal low-impedance. When the CLR pin is logic '1', all VOUT-X pins
connect to the amplifier outputs.
Reset input (active low). Logic low on this pin resets the DAC registers and DACs to the values
defined by the RSTSEL pin. CS must be logic high when RST is active.
RST
I
(1) Group A consists of DAC-0, DAC-1, DAC-2, and DAC-3. Group B consists of DAC-4, DAC-5, DAC-6, and DAC-7.
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PIN DESCRIPTIONS (continued)
PIN NO.
PIN
NAME
QFN-48
17
TQFP-64
I/O
DESCRIPTION
DVDD
DGND
DGND
24
25
28
I
I
I
Digital power supply
Digital ground
20
22
Digital ground
General-purpose digital input/output 1. This pin is a bidirectional digital input/output, open-drain and
requires an external resistor. See the GPIO Pins section for details.
GPIO-1
GPIO-0
23
24
29
30
I/O
I/O
General-purpose digital input/output 0. This pin is a bidirectional digital input/output, open-drain and
requires an external resistor. See the GPIO Pins section for details.
AVSS
26
27
37
38
I
Negative analog power supply
DAC-7 output
VOUT-7
O
OFFSET DAC-B analog output. Must be connected to AGND-B during single-supply operation
(AVSS = 0V).
OFFSET-B
28
39
O
AGND-B
AGND-B
VOUT-6
VOUT-5
REF-B
VOUT-4
AIN-1
29
30
31
32
33
34
35
36
40
41
42
43
44
45
46
48
I
I
Group B(1) analog ground and the ground of REF-B. This pin must be tied to AGND-A and DGND.
Group B analog ground and the ground of REF-B. This pin must be tied to AGND-A and DGND.
O
O
I
DAC-6 output
DAC-5 output
Group B reference input
DAC-4 output
O
I
Auxiliary analog input 1, directly routed to the analog mux
Positive analog power supply
AVDD
I
Data format selection of Input DAC data and Offset DAC data. Data are in straight binary format
when connected to DGND or in twos complement format when connected to IOVDD. The command
data are always in straight binary format. Refer to Input Data Format section for details.
USB/BTC
RSTSEL
37
38
50
51
I
I
Output reset selection. Selects the output voltage on the VOUT pin after power-on or hardware reset.
Refer to the Power-On Reset section for details.
DGND
IOVDD
DVDD
40
41
42
43
54
55
56
57
I
I
I
I
Digital ground
Interface power
Digital power supply
SPI bus serial clock input
SCLK
SPI bus chip select input (active low). Data are not clocked into SDI unless CS is low. When CS is
high, SDO is in a high-impedance state and the SCLK and SDI signals are blocked from the device.
CS
44
45
58
59
I
I
SDI
SPI bus serial data input
SPI bus serial data output.
When the DSDO bit = '0', the SDO pin works as an output in normal operation.
When the DSDO bit = '1', SDO is always in a Hi-Z state, regardless of the CS pin status. Refer to
the Timing Diagrams section for details.
SDO
46
61
O
Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent and the
contents of the DAC Data Register are transferred to it. The DAC output changes to the
corresponding level simultaneously when the DAC latch is updated. See the Updating the DAC
Outputs section for details. If asynchronous mode is desired, LDAC must be permanently tied low
before power is applied to the device. If synchronous mode is desired, LDAC must be logic high
during power-on.
LDAC
WAKEUP
NC
47
48
62
63
I
I
Wake-up input (active low). Restores the SPI from sleep to normal operation. See the Daisy-Chain
Operation section for details.
2, 13,
15-18, 22,
23, 26, 27,
31-36, 47,
49, 52, 53,
60, 64
16, 18, 19,
21, 25, 39
—
Not connected
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TIMING DIAGRAMS
Case 1: Standalone mode: Update without LDAC pin; LDAC pin tied to logic low.
t8
t4
CS
Input Data Register and
DAC Latch Updated
When Correction Completes(1)
t7
t1
SCLK
t2
t3
t5
t6
BIT 22
BIT 23 (MSB)
BIT 1
BIT 0
SDI
Low
LDAC
NOTE: (1) If the correction engine is off, the DAC latch is reloaded immediately after the DAC Data Register is updated.
Case 2: Standalone mode: Update with LDAC pin.
t8
t4
CS
Input Data Register Updated,
but DAC Latch is Not Updated
t7
t1
SCLK
t2
t3
t5
t6
BIT 22
BIT 23 (MSB)
BIT 1
BIT 0
SDI
t9
DAC Latch Updated(2)
t10
High
LDAC
NOTE: (2) The DAC latch is updated when LDAC goes low, as long as the timing requirement of t9 is satisfied.
Bit 23 = MSB
= Don’t Care
Bit 0 = LSB
Figure 2. SPI Timing for Standalone Mode
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TIMING DIAGRAMS (continued)
Case 3: Daisy-Chain Mode: Update without LDAC pin; LDAC pin tied to logic low.
t8
t4
CS
SCLK
SDI
Input Data Register and
DAC Latch Updated
When Correction Completes(1)
t7
t1
t2
t3
t5
t6
BIT 23 (N)
BIT 22 (N)
BIT 0 (N)
BIT 23 (N+1)
BIT 0 (N+1)
t12
t13
t11
Hi-Z
Hi-Z
BIT 23 (N)
BIT 0 (N)
SDO
Low
LDAC
NOTE: (1) If the correction engine is off, the DAC latch is reloaded immediately after the DAC Data Register is updated.
Case 4: Daisy-Chain Mode: Update with LDAC pin.
t8
t4
CS
SCLK
SDI
Input Data Register Updated,
but DAC Latch is Not Updated
t7
t1
t2
t3
t5
t6
BIT 23 (N)
BIT 22 (N)
BIT 0 (N)
BIT 23 (N+1)
BIT 0 (N+1)
BIT 0 (N)
t12
t13
t11
Hi-Z
High
Hi-Z
BIT 23 (N)
SDO
t9
DAC Latch Updated(2)
t10
LDAC
NOTE: (2) The DAC latch is updated when LDAC goes low. The proper data are loaded if the t9 timing requirement is satisfied.
Otherwise, invalid data are loaded.
Case 5: Daisy-Chain Mode: Sleeping.
CS
SCLK
First Word
Last Word
DB23
DB0
DB23
DB0
SDI
t14
Hi-Z
Hi-Z
Hi-Z
DB23
DB0
DB23
DB0
SDO
Bit 23 = MSB
Bit 0 = LSB
= Don’t Care
Figure 3. SPI Timing for Daisy-Chain Mode
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TIMING DIAGRAMS (continued)
Case 6: Readback for Standalone mode.
t8
t4
t7
CS
SCLK
SDI
Internal Register Updated
t1
t2
t3
t5
t6
BIT 23 (= 1)
BIT 22
BIT 0
BIT 23 (= 1)
BIT 22
BIT 1
BIT 0
t13
NOP Command (write ‘1’ to NOP bit)
Input Word Specifies Register to be Read
t11
Hi-Z
Low
Hi-Z
Hi-Z
SDO
BIT 23
BIT 22
BIT 1
BIT 0
Data from the Selected Register
LDAC
Bit 23 = MSB
Bit 0 = LSB
= Don’t Care
Figure 4. SPI Timing for Readback Operation in Standalone Mode
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TIMING CHARACTERISTICS: IOVDD = +5V(1)(2)(3)(4)
At –40°C to +105°C, DVDD = +5V, and IOVDD = +5V, unless otherwise noted.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fSCLK
t1
Clock frequency
50
SCLK cycle time
20
10
7
t2
SCLK high time
ns
t3
SCLK low time
ns
t4
CS falling edge to SCLK falling edge setup time
SDI setup time before falling edge of SCLK
SDI hold time after falling edge of SCLK
SCLK falling edge to CS rising edge
CS high time
8
ns
t5
5
ns
t6
5
ns
t7
5
ns
t8
10
5
ns
t9
CS rising edge to LDAC falling edge
LDAC pulse duration
ns
t10
t11
t12
t13
t14
10
3
ns
Delay from SCLK rising edge to SDO valid
Delay from CS rising edge to SDO Hi-Z
Delay from CS falling edge to SDO valid
SDI to SDO delay during sleep mode
8
5
6
5
ns
ns
ns
2
ns
(1) Specified by design. Not production tested.
(2) Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
(3) All input signals are specified with tR = tF = 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2.
(4) SDO loaded with 10Ω series resistance and 10pF load capacitance for SDO timing specifications, with tR = tF ≤ 5ns.
BLANKSPACE
TIMING CHARACTERISTICS: IOVDD = +3V(1)(2)(3)(4)
At –40°C to +105°C, DVDD = +3V/+5V, and IOVDD = +3V, unless otherwise noted.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fSCLK
t1
Clock frequency
SCLK cycle time
SCLK high time
SCLK low time
25
40
19
7
t2
ns
t3
ns
t4
CS falling edge to SCLK falling edge setup time
SDI setup time before falling edge of SCLK
SDI hold time after falling edge of SCLK
SCLK falling edge to CS rising edge
CS high time
15
5
ns
t5
ns
t6
5
ns
t7
10
19
5
ns
t8
ns
t9
CS rising edge to LDAC falling edge
LDAC pulse duration
ns
t10
t11
t12
t13
t14
10
3
ns
Delay from SCLK rising edge to SDO valid
Delay from CS rising edge to SDO Hi-Z
Delay from CS falling edge to SDO valid
SDI to SDO delay during sleep mode
15
7
ns
ns
10
10
ns
2
ns
(1) Specified by design. Not production tested.
(2) Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
(3) All input signals are specified with tR = tF = 3ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2.
(4) SDO loaded with 10Ω series resistance and 10pF load capacitance for SDO timing specifications, with tR = tF ≤ 5ns.
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TIMING CHARACTERISTICS: IOVDD = +1.8V(1)(2)(3)(4)
At –40°C to +105°C, DVDD = +3V/+5V, and IOVDD = +1.8V, unless otherwise noted.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fSCLK
t1
Clock frequency
16.6
SCLK cycle time
60
28
7
t2
SCLK high time
ns
t3
SCLK low time
ns
t4
CS falling edge to SCLK falling edge setup time
SDI setup time before falling edge of SCLK
SDI hold time after falling edge of SCLK
SCLK falling edge to CS rising edge
CS high time
28
10
5
ns
t5
ns
t6
ns
t7
10
28
5
ns
t8
ns
t9
CS rising edge to LDAC falling edge
LDAC pulse duration
ns
t10
t11
t12
t13
t14
10
3
ns
Delay from SCLK rising edge to SDO valid
Delay from CS rising edge to SDO Hi-Z
Delay from CS falling edge to SDO valid
SDI to SDO delay during sleep mode
25
15
23
25
ns
ns
ns
2
ns
(1) Specified by design. Not production tested.
(2) Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
(3) All input signals are specified with tR = tF = 6ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2.
(4) SDO loaded with 10Ω series resistance and 10pF load capacitance for SDO timing specifications, with tR = tF ≤ 15ns.
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SBAS467A –MAY 2009–REVISED DECEMBER 2009
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TYPICAL CHARACTERISTICS: Bipolar
At TA = 25°C, AVDD = 16.5V, AVSS = –16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (All 8 Channels)
vs DIGITAL INPUT CODE (All 8 Channels)
4
3
1.0
0.8
All Eight Channels Shown
All Eight Channels Shown
0.6
2
0.4
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-4
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 5.
Figure 6.
LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
4
3
1.0
0.8
Typical Channel Shown
Gain = 4
Typical Channel Shown
Gain = 4
0.6
2
0.4
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-4
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 7.
Figure 8.
18
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SBAS467A –MAY 2009–REVISED DECEMBER 2009
TYPICAL CHARACTERISTICS: Bipolar (continued)
At TA = 25°C, AVDD = 16.5V, AVSS = –16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
4
3
1.0
0.8
Typical Channel Shown
Typical Channel Shown
0.6
2
0.4
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-4
0
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 9.
Figure 10.
LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
1.0
0.8
4
3
Typical Channel Shown
Typical Channel Shown
0.6
2
0.4
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-4
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 11.
Figure 12.
LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
4
3
1.0
0.8
Typical Channel Shown
Typical Channel Shown
0.6
2
0.4
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-4
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS: Bipolar (continued)
At TA = 25°C, AVDD = 16.5V, AVSS = –16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted.
LINEARITY ERROR
vs TEMPERATURE
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
1.0
0.8
4
3
0.6
INL Max
2
DNL Max
DNL Min
0.4
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
INL Min
-1
-2
-3
-4
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Figure 15.
Figure 16.
LINEARITY ERROR
vs TEMPERATURE
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
1.0
0.8
4
3
Gain = 4
Gain = 4
0.6
DNL Max
DNL Min
INL Max
2
0.4
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-4
INL Min
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Figure 17.
Figure 18.
LINEARITY ERROR
vs REFERENCE VOLTAGE
DIFFERENTIAL LINEARITY ERROR
vs REFERENCE VOLTAGE
4
3
1.0
0.8
AVDD = +18V
AVSS = -18V
AVDD = +18V
AVSS = -18V
0.6
2
DNL Max
DNL Min
INL Max
INL Min
0.4
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-4
1.0
1.5
2.0
2.5
3.0
3.5 4.0
4.5
5.0
5.5
1.0
1.5
2.0
2.5
3.0
3.5 4.0
4.5
5.0
5.5
VREF (V)
VREF (V)
Figure 19.
Figure 20.
20
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SBAS467A –MAY 2009–REVISED DECEMBER 2009
TYPICAL CHARACTERISTICS: Bipolar (continued)
At TA = 25°C, AVDD = 16.5V, AVSS = –16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted.
LINEARITY ERROR
vs AVDD AND AVSS
DIFFERENTIAL LINEARITY ERROR
vs AVDD AND AVSS
4
3
1.0
0.8
DVDD = IOVDD = 4.5V
VREF = 2.048V
Gain = 4
DVDD = IOVDD = 4.5V
VREF = 2.048V
Gain = 4
0.6
DNL Max
DNL Min
2
INL Max
INL Min
0.4
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-4
4.5
4.5
1.0
6.0
6.0
1.5
7.5
9.0 10.5 12.0 13.5 15.0 16.5 18.0
4.5
6.0
7.5
9.0 10.5 12.0 13.5 15.0 16.5 18.0
AVDD = -AVSS (V)
AVDD = -AVSS (V)
Figure 21.
Figure 22.
BIPOLAR ZERO ERROR
vs AVDD AND AVSS
BIPOLAR GAIN ERROR
vs AVDD AND AVSS
5
4
5
4
DVDD = IOVDD = 4.5V
VREF = 2.048V
Gain = 4
DVDD = IOVDD = 4.5V
VREF = 2.048V
Gain = 4
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
Ch0
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
Ch0
Ch4
Ch5
Ch6
Ch7
Ch1
Ch2
Ch3
7.5
9.0 10.5 12.0 13.5 15.0 16.5 18.0
4.5
6.0
7.5
9.0 10.5 12.0 13.5 15.0 16.5 18.0
AVDD = -AVSS (V)
AVDD = -AVSS (V)
Figure 23.
Figure 24.
BIPOLAR ZERO ERROR
vs REFERENCE VOLTAGE
BIPOLAR ZERO ERROR
vs REFERENCE VOLTAGE
5
4
5
4
AVDD = +18V
AVSS = -18V
AVDD = +18V
AVSS = -18V
3
3
Gain = 4
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
Ch0
Ch4
Ch5
Ch6
Ch7
Ch0
Ch4
Ch5
Ch6
Ch7
Ch1
Ch2
Ch3
Ch1
Ch2
Ch3
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VREF (V)
VREF (V)
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS: Bipolar (continued)
At TA = 25°C, AVDD = 16.5V, AVSS = –16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted.
BIPOLAR GAIN ERROR
BIPOLAR GAIN ERROR
vs REFERENCE VOLTAGE
vs REFERENCE VOLTAGE
5
4
5
4
AVDD = +18V
AVSS = -18V
AVDD = +18V
AVSS = -18V
3
3
Gain = 4
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
Ch0
Ch4
Ch5
Ch6
Ch7
Ch0
Ch4
Ch5
Ch6
Ch7
Ch1
Ch2
Ch3
Ch1
Ch2
Ch3
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VREF (V)
VREF (V)
Figure 27.
Figure 28.
BIPOLAR ZERO ERROR
vs TEMPERATURE
BIPOLAR ZERO ERROR
vs TEMPERATURE
5
4
5
4
Gain = 4
Ch0
Ch4
Ch5
Ch6
Ch7
Ch0
Ch4
Ch5
Ch6
Ch7
Ch1
Ch2
Ch3
Ch1
Ch2
Ch3
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Figure 29.
Figure 30.
BIPOLAR GAIN ERROR
vs TEMPERATURE
BIPOLAR GAIN ERROR
vs TEMPERATURE
5
4
5
4
Gain = 4
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
Ch0
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
Ch0
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Figure 31.
Figure 32.
22
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SBAS467A –MAY 2009–REVISED DECEMBER 2009
TYPICAL CHARACTERISTICS: Bipolar (continued)
At TA = 25°C, AVDD = 16.5V, AVSS = –16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted.
ANALOG POWER-SUPPLY CURRENT
vs TEMPERATURE
ANALOG POWER-SUPPLY CURRENT
vs REFERENCE VOLTAGE
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
All DACs Loaded with Midscale Code
AVDD = +18V
AVSS = -18V
IAVDD
IAVDD
-IAVSS
-IAVSS
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
1.0
1.5
2.0
2.5
3.0
3.5 4.0
4.5
5.0
5.5
Temperature (°C)
VREF (V)
Figure 33.
Figure 34.
ANALOG POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE
DIGITAL POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
250
200
150
100
50
8
One Digital Input Swept, All Others at GND or IOVDD
All DACs Loaded with Same Code
7
6
5
4
3
2
1
0
Sweep From
5.5V to 0V
Sweep From
0V to 5.5V
IAVDD
-IAVSS
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Logic Input Voltage (V)
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 35.
Figure 36.
DELTA OUTPUT VOLTAGE
vs SOURCE AND SINK CURRENTS
DAC OUTPUT NOISE DENSITY
vs FREQUENCY
6
2000
1800
1600
1400
1200
1000
800
DAC Loaded with Midscale Code
FFFFh
C000h
8000h
4000h
0000h
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
600
Gain = 6
400
Gain = 4
200
0
-15 -12 -9
-6
-3
0
3
6
9
12
15
1
10
100
1k
10k
100k
Current Output IOUT (mA)
Frequency (Hz)
Figure 37.
Figure 38.
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TYPICAL CHARACTERISTICS: Bipolar (continued)
At TA = 25°C, AVDD = 16.5V, AVSS = –16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted.
SETTLING TIME
SETTLING TIME
–15V TO +15V TRANSITION
+15V TO –15V TRANSITION
From Code: FFFFh
To Code: 0000h
Load: 10kW || 240pF
Large-Signal VOUT
Small-Signal Error
5V/div
5V/div
Small-Signal Error
1 LSB/div
1 LSB/div
From Code: 0000h
To Code: FFFFh
Large-Signal VOUT
5V/div
5V/div
Load: 10kW || 240pF
Trigger Pulse: LDAC
Trigger Pulse: LDAC
Time (10ms/div)
Time (10ms/div)
Figure 39.
Figure 40.
SETTLING TIME
SETTLING TIME
1/4 TO 3/4 FULL-SCALE TRANSITION
3/4 TO 1/4 FULL-SCALE TRANSITION
From Code: C000h
To Code: 4000h
Load: 10kW || 240pF
Large-Signal VOUT
Small-Signal Error
5V/div
Small-Signal Error
Large-Signal VOUT
1 LSB/div
1 LSB/div
5V/div
5V/div
From Code: 4000h
To Code: C000h
Load: 10kW || 240pF
5V/div
Trigger Pulse: LDAC
Trigger Pulse: LDAC
Time (10ms/div)
Time (10ms/div)
Figure 41.
Figure 42.
GLITCH ENERGY
GLITCH ENERGY
1 LSB STEP, RISING EDGE
1 LSB STEP, FALLING EDGE
Trigger Pulse 5V/div
Trigger Pulse 5V/div
From Code: 8000h
To Code: 7FFFh
Channel 0 as Example
Load: 10kW || 200pF
Glitch Impulse
From Code: 7FFFh
To Code: 8000h
Channel 0 as Example
Load: 10kW || 200pF
Glitch Impulse
Time (2ms/div)
Time (2ms/div)
Figure 43.
Figure 44.
24
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SBAS467A –MAY 2009–REVISED DECEMBER 2009
TYPICAL CHARACTERISTICS: Bipolar (continued)
At TA = 25°C, AVDD = 16.5V, AVSS = –16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted.
BIPOLAR ZERO ERROR
HISTOGRAM
BIPOLAR ZERO ERROR
HISTOGRAM
40
35
30
25
20
15
10
5
60
55
50
45
40
35
30
25
20
15
10
5
Gain = 4
0
0
Bipolar Zero Error (LSB)
Bipolar Zero Error (LSB)
Figure 45.
Figure 46.
BIPOLAR GAIN ERROR
HISTOGRAM
BIPOLAR GAIN ERROR
HISTOGRAM
25
20
15
10
5
25
20
15
10
5
Gain = 4
0
0
Bipolar Gain Error (LSB)
Bipolar Gain Error (LSB)
Figure 47.
Figure 48.
NEGATIVE ANALOG POWER SUPPLY
HISTOGRAM
POSITIVE ANALOG POWER SUPPLY
HISTOGRAM
45
40
35
30
25
20
15
10
5
30
25
20
15
10
5
0
0
AIDD (mA)
AISS (mA)
Figure 49.
Figure 50.
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TYPICAL CHARACTERISTICS: Bipolar (continued)
At TA = 25°C, AVDD = 16.5V, AVSS = –16.5V, VREF = IOVDD = DVDD = 5V, gain = 6, data format=USB, unless otherwise noted.
DAC OUTPUT NOISE
0.1Hz TO 10Hz
DAC OUTPUT NOISE
0.1Hz TO 10Hz
DAC Code = 8000h
DAC Code = 8000h
No Load
Gain = 6
Channel 0 as Example
No Load
Gain = 4
Channel 0 as Example
Time (2ms/div)
Time (2ms/div)
Figure 51.
Figure 52.
26
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SBAS467A –MAY 2009–REVISED DECEMBER 2009
TYPICAL CHARACTERISTICS: Unipolar
At TA = 25°C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (All 8 Channels)
vs DIGITAL INPUT CODE (All 8 Channels)
4
3
1.0
0.8
All Eight Channels Shown
All Eight Channels Shown
0.6
2
0.4
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-4
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 53.
Figure 54.
LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
4
3
1.0
0.8
Gain = 4
Gain = 4
0.6
2
0.4
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-4
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 55.
Figure 56.
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TYPICAL CHARACTERISTICS: Unipolar (continued)
At TA = 25°C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
4
3
1.0
0.8
Typical Channel Shown
Typical Channel Shown
0.6
2
0.4
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-4
0
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 57.
Figure 58.
LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
1.0
0.8
4
3
Typical Channel Shown
Typical Channel Shown
0.6
2
0.4
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-4
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 59.
Figure 60.
LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
4
3
1.0
0.8
Typical Channel Shown
Typical Channel Shown
0.6
2
0.4
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-4
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 61.
Figure 62.
28
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SBAS467A –MAY 2009–REVISED DECEMBER 2009
TYPICAL CHARACTERISTICS: Unipolar (continued)
At TA = 25°C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted.
LINEARITY ERROR
vs TEMPERATURE
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
1.0
0.8
4
3
0.6
INL Max
2
DNL Max
0.4
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-4
DNL Min
INL Min
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Figure 63.
Figure 64.
LINEARITY ERROR
vs TEMPERATURE
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
4
3
1.0
0.8
Gain = 4
Gain = 4
0.6
2
DNL Max
DNL Min
INL Max
0.4
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-4
INL Min
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Figure 65.
Figure 66.
LINEARITY ERROR
vs REFERENCE VOLTAGE
DIFFERENTIAL LINEARITY ERROR
vs REFERENCE VOLTAGE
1.0
0.8
4
3
AVDD = +36V
AVDD = +36V
0.6
DNL Max
DNL Min
2
0.4
INL Max
INL Min
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-4
1.0
1.5
2.0
2.5
3.0
3.5 4.0
4.5
5.0
5.5
1.0
1.5
2.0
2.5
3.0
3.5 4.0
4.5
5.0
5.5
VREF (V)
VREF (V)
Figure 67.
Figure 68.
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TYPICAL CHARACTERISTICS: Unipolar (continued)
At TA = 25°C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted.
LINEARITY ERROR
vs ANALOG SUPPLY VOLTAGE
DIFFERENTIAL LINEARITY ERROR
vs ANALOG SUPPLY VOLTAGE
4
3
1.0
0.8
DNL Max
0.6
2
0.4
INL Max
INL Min
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-4
DNL Min
9
12
15
18
21
24
27
30
33
36
9
12
15
18
21
24
27
30
33
36
AVDD (V)
AVDD (V)
Figure 69.
Figure 70.
ZERO-SCALE ERROR
vs ANALOG SUPPLY VOLTAGE
UNIPOLAR GAIN ERROR
vs ANALOG SUPPLY VOLTAGE
5
4
5
4
DVDD = IOVDD = 4.5V
VREF = 2.048V
Gain = 4
All DACS Loaded with 0100h
VREF = 2.048V
Gain = 4
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
Ch0
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
Ch0
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
9
12
15
18
21
24
27
30
33
36
9
12
15
18
21
24
27
30
33
36
+AVDD (V)
+AVDD (V)
Figure 71.
Figure 72.
ZERO-SCALE ERROR
ZERO-SCALE ERROR
vs REFERENCE VOLTAGE
vs REFERENCE VOLTAGE
5
4
5
4
All DACS Loaded with 0100h
AVDD = +36V
All DACS Loaded with 0100h
AVDD = +36V
Gain = 4
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
Ch0
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
Ch0
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VREF (V)
VREF (V)
Figure 73.
Figure 74.
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TYPICAL CHARACTERISTICS: Unipolar (continued)
At TA = 25°C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted.
UNIPOLAR GAIN ERROR
vs REFERENCE VOLTAGE
UNIPOLAR GAIN ERROR
vs REFERENCE VOLTAGE
5
4
5
4
AVDD = +36V
AVDD = +36V
Gain = 4
Ch0
Ch4
Ch5
Ch6
Ch7
Ch0
Ch4
Ch5
Ch6
Ch7
Ch1
Ch2
Ch3
Ch1
Ch2
Ch3
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VREF (V)
VREF (V)
Figure 75.
Figure 76.
ZERO-SCALE ERROR
vs TEMPERATURE
ZERO-SCALE ERROR
vs TEMPERATURE
5
4
5
4
All DACS Loaded with 0100h
All DACS Loaded with 0100h
Gain = 4
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
Ch0
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
Ch0
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Figure 77.
Figure 78.
UNIPOLAR GAIN ERROR
vs TEMPERATURE
UNIPOLAR GAIN ERROR
vs TEMPERATURE
5
4
5
4
Gain = 4
Ch0
Ch4
Ch5
Ch6
Ch7
Ch0
Ch4
Ch5
Ch6
Ch7
Ch1
Ch2
Ch3
Ch1
Ch2
Ch3
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Figure 79.
Figure 80.
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TYPICAL CHARACTERISTICS: Unipolar (continued)
At TA = 25°C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted.
ANALOG POWER-SUPPLY CURRENT
vs TEMPERATURE
ANALOG POWER-SUPPLY CURRENT
vs REFERENCE VOLTAGE
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
All DACs Loaded with Midscale Code
AVDD = +36V
IAVDD
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Temperature (°C)
VREF (V)
Figure 81.
Figure 82.
ANALOG POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE
8
7
6
5
4
3
2
1
0
All DACs Loaded with Same Code
IAVDD
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 83.
OUTPUT VOLTAGE
vs SOURCE CURRENT CAPABILITY
OUTPUT VOLTAGE
vs SINK CURRENT CAPABILITY
30.5
30.0
29.5
29.0
28.5
28.0
27.5
2.5
2.0
1.5
1.0
0.5
0
FFFFh
FF00h
FE00h
FC00h
F800h
0000h
0100h
0200h
0400h
0800h
0
3
6
9
12
15
-15
-12
-9
-6
-3
0
ISOURCE (mA)
ISINK (mA)
Figure 84.
Figure 85.
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TYPICAL CHARACTERISTICS: Unipolar (continued)
At TA = 25°C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted.
SETTLING TIME
SETTLING TIME
0V TO 30V TRANSITION
30V TO 0V TRANSITION
Large-Signal VOUT
From Code: FFFFh
5V/div
To Code: 0100h
Load: 10kW || 240pF
Small-Signal Error
Small-Signal Error
Large-Signal VOUT
1 LSB/div
1 LSB/div
5V/div
From Code: 0100h
To Code: FFFFh
5V/div
5V/div
Load: 10kW || 240pF
Trigger Pulse: LDAC
Trigger Pulse: LDAC
Time (10ms/div)
Time (10ms/div)
Figure 86.
Figure 87.
SETTLING TIME
SETTLING TIME
1/4 TO 3/4 TRANSITION
3/4 TO 1/4 TRANSITION
From Code: C000h
To Code: 4000h
Load: 10kW || 240pF
Large-Signal VOUT
5V/div
Small-Signal Error
Small-Signal Error
Large-Signal VOUT
1 LSB/div
1 LSB/div
5V/div
5V/div
From Code: 4000h
To Code: C000h
Load: 10kW || 240pF
5V/div
Trigger Pulse: LDAC
Time (10ms/div)
Trigger Pulse: LDAC
Time (10ms/div)
Figure 88.
Figure 89.
GLITCH ENERGY
GLITCH ENERGY
1 LSB STEP, RISING EDGE
1 LSB STEP, FALLING EDGE
Trigger Pulse 5V/div
Trigger Pulse 5V/div
From Code: 8000h
To Code: 7FFFh
Channel 0 as Example
Load: 10kW || 200pF
Glitch Impulse
Glitch Impulse
From Code: 7FFFh
To Code: 8000h
Channel 0 as Example
Load: 10kW || 200pF
Time (2ms/div)
Time (2ms/div)
Figure 90.
Figure 91.
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TYPICAL CHARACTERISTICS: Unipolar (continued)
At TA = 25°C, AVDD = 32V, AVSS = 0V, VREF = 5V, IOVDD = DVDD = 5V, gain=6, and data format=USB, unless otherwise noted.
ZERO-SCALE ERROR
HISTOGRAM
ZERO-SCALE ERROR
HISTOGRAM
45
40
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
Code = 0100h
Code = 0100h
Gain = 4
0
0
Zero-Scale Error (LSB)
Zero-Scale Error (LSB)
Figure 92.
Figure 93.
UNIPOLAR GAIN ERROR
HISTOGRAM
UNIPOLAR GAIN ERROR
HISTOGRAM
25
20
15
10
5
25
20
15
10
5
Gain = 4
0
0
Unipolar Gain Error (LSB)
Unipolar Gain Error (LSB)
Figure 94.
Figure 95.
ANALOG POWER-SUPPLY CURRENT
HISTOGRAM
30
25
20
15
10
5
0
AIDD (mA)
Figure 96.
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THEORY OF OPERATION
GENERAL DESCRIPTION
The DAC8718 contains eight DAC channels and eight output amplifiers in a single package. Each channel
consists of a resistor-string DAC followed by an output buffer amplifier. The resistor-string section is simply a
string of resistors, each with a value of R, from REF-x to AGND, as shown in Figure 97. This type of architecture
provides DAC monotonicity. The 16-bit binary digital code loaded to the DAC latch determines at which node on
the string the voltage is tapped off before being fed into the output amplifier. The output amplifier multiplies the
DAC output voltage by a gain of six or four. Using a gain of 6 and power supplies allowing for at least 0.5V
headroom, the output span is 9V with a 1.5V reference, 18V with a 3V reference, and 30V with a 5V reference.
REF-x
R
R
To Output
Amplifier
R
R
R
Figure 97. Resistor String
CHANNEL GROUPS
The eight DAC channels and two Offset DACs are arranged into two groups (A and B) with four channels and
one Offset DAC per group. Group A consists of DAC-0, DAC-1, DAC-2, DAC-3, and Offset DAC-A. Group B
consists of DAC-4, DAC-5, DAC-6, DAC-7, and Offset DAC-B. Group A derives its reference voltage from
REF-A, and Group B derives its reference voltage from REF-B.
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USER-CALIBRATION FOR ZERO-CODE ERROR AND GAIN ERROR
The DAC8718 implements a digital user-calibration function that allows for trimming gain and zero errors on the
entire signal chain. This function can eliminate the need for external adjustment circuits. Each DAC channel has
a Zero Register and Gain Register. Using the correction engine, the data from the Input Data Register are
operated on by a digital adder and multiplier controlled by the contents of the Zero and Gain registers,
respectively. The calibrated DAC data are then stored in the DAC Data Register where they are finally
transferred into the DAC latch and set the DAC output. Each time the data are written to the Input Data Register
(or to the Gain or Zero registers), the data in the Input Data Register are corrected, and the results automatically
transferred to the DAC Data Register.
The range of the gain adjustment coefficient is 0.5 to 1.5. The range of the zero adjustment is –32768 LSB to
+32767 LSB, or ±50% of full scale.
There is only one correction engine in the DAC8718, which is shared among all channels.
If the user-calibration function is not needed, the correction engine can be turned off. Setting the SCE bit in the
Configuration Register to '0' turns off the correction engine. Setting SCE to '1' enables the correction engine.
When SCE = '0', the data are directly transferred to the DAC Data Register. In this case, writing to the Gain
Register or Zero Register updates the Gain and Zero registers but does not start a math engine calculation.
Reading these registers returns the written values.
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ANALOG OUTPUTS (VOUT-0 to VOUT-7, with reference to the ground of REF-x)
When the correction engine is off (SCE = '0'):
INPUT_CODE
65536
OFFSETDAC_CODE
65536
VOUT
=
VREF ´ Gain ´
- VREF ´ (Gain - 1) ´
(1)
(2)
SPACE
When the correction engine is on (SCE = '1'):
DAC_DATA_CODE
OFFSETDAC_CODE
VOUT
=
VREF ´ Gain ´
- VREF ´ (Gain - 1) ´
65536
65536
SPACE
Where:
INPUT_CODE ´ (USER_GAIN + 215)
DAC_DATA_CODE =
+ USER_ZERO
216
Gain = the DAC gain defined by the GAIN bit in the Configuration Register.
INPUT_CODE = data written into the Input Data Register (SCE = '1') or the DAC Data Register (SCE = '0').
OFFSETDAC_CODE = the data written into the Offset DAC Register.
USER_GAIN = the code of the Gain Register.
USER_ZERO = the code of the Zero Register.
For single-supply operation, the OFFSET-A pin must be connected to the AGND-A pin and the OFFSET-B pin
must be connected to the AGND-B pin through low-impedance connections (see the Layout section for details).
Offset DAC-A and Offset DAC-B are in a power-down state.
For dual-supply operation, the OFFSET-A and OFFSET-B default codes for a gain of 6 are 39322 with a ±10
LSB variation, depending on the linearity of the Offset DACs. The default code for a gain of 4 is 43691 with a ±10
LSB variation. The default codes of OFFSET-A and OFFSET-B are independently factory trimmed for both gains
of 6 and 4.
The power-on default value of the Gain Register is 32768, and the default value of the Zero Register is '0'. The
DAC input registers are set to a default value of 0000h.
Note that the maximum output voltage must not be greater than (AVDD – 0.5V) and the minimum output voltage
must not be less than (AVSS + 0.5V); otherwise, the output may be saturated.
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INPUT DATA FORMAT
The USB/BTC pin defines the input data format and the Offset DAC format. When this pin is connected to
DGND, the Input DAC data and Offset DAC data are straight binary, as shown in Table 1 and Table 3. When this
pin is connected to IOVDD, the Input DAC data and Offset DAC data are in twos complement format, as shown in
Table 2 and Table 4.
Table 1. Bipolar Output vs Straight Binary Code Using Dual Power Supplies with Gain = 6
USB CODE
FFFFh
••• •••
NOMINAL OUTPUT
+3 × VREF × (32767/32768)
••• •••
DESCRIPTION
+Full-Scale – 1 LSB
••• •••
8001h
8000h
7FFFh
••• •••
+3 × VREF × (1/32768)
0
+1 LSB
Zero
–3 × VREF × (1/32768)
••• •••
–1 LSB
••• •••
0000h
–3 × VREF × (32768/32768)
–Full-Scale
Table 2. Bipolar Output vs Twos Complement Code Using Dual Power Supplies with Gain = 6
BTC CODE
7FFFh
••• •••
NOMINAL OUTPUT
+3 × VREF × (32767/32768)
••• •••
DESCRIPTION
+Full-Scale – 1 LSB
••• •••
0001h
0000h
FFFFh
••• •••
+3 × VREF × (1/32768)
0
+1 LSB
Zero
–3 × VREF × (1/32768)
••• •••
–1 LSB
••• •••
8000h
–3 × VREF × (32768/32768)
–Full-Scale
Table 3. Unipolar Output vs Straight Binary Code Using Single Power Supply with Gain = 6
USB CODE
FFFFh
••• •••
NOMINAL OUTPUT
+6 × VREF × (65535/65536)
••• •••
DESCRIPTION
+Full-Scale – 1 LSB
••• •••
8001h
8000h
7FFFh
••• •••
+6 × VREF × (32769/65536)
+6 × VREF × (32768/65536)
+6 × VREF × (32767/65536)
••• •••
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
••• •••
0000h
0
0
Table 4. Unipolar Output vs Twos Complement Code Using Single Power Supply with Gain = 6
BTC CODE
7FFFh
••• •••
NOMINAL OUTPUT
+6 × VREF × (65535/65536)
••• •••
DESCRIPTION
+Full-Scale – 1 LSB
••• •••
0001h
0000h
FFFFh
••• •••
+6 × VREF × (32769/65536)
+6 × VREF × (32768/65536)
+6 × VREF × (32767/65536)
••• •••
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
••• •••
8000h
0
0
The data written to the Gain Register are always in straight binary, data to the Zero Register are in twos
complement, and data to all other control registers are as specified in the definitions, regardless of the USB/BTC
pin status.
In reading operation, the read-back data are in the same format as written.
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OFFSET DACS
There are two 16-bit Offset DACs: one for Group A, and one for Group B. The Offset DACs allow the entire
output curve of the associated DAC groups to be shifted by introducing a programmable offset. This offset allows
for asymmetric bipolar operation of the DACs or unipolar operation with bipolar supplies. Thus, subject to the
limitations of headroom, it is possible to set the output range of Group A and/or Group B to be unipolar positive,
unipolar negative, symmetrical bipolar, or asymmetrical bipolar, as shown in Table 5 and Table 6. Increasing the
digital input codes for the offset DAC shifts the outputs of the associated channels in the negative direction. The
default codes for the Offset DACs in the DAC8718 are factory trimmed to provide optimal offset and gain
performance for the default output range and span of symmetric bipolar operation. When the output range is
adjusted by changing the value of the Offset DAC, an extra offset is introduced as a result of the linearity and
offset errors of the Offset DAC. Therefore, the actual shift in the output span may vary slightly from the ideal
calculations. For optimal offset and gain performance in the default symmetric bipolar operation, the Offset DAC
input codes should not be changed from the default power-on values. The maximum allowable offset depends on
the reference and the power supply. If INPUT_CODE from Equation 1 or DAC_DATA_CODE from Equation 2 is
set to 0, then these equations simplify to Equation 3:
OFFSETDAC_CODE
VOUT = -VREF ´ (Gain - 1) ´
65536
(3)
This equation shows the transfer function of the Offset DAC to the output of the DAC channels. In any case, the
analog output must not go beyond the specified range shown in the Analog Outputs section. After power-on or
reset, the Offset DAC is set to the value defined by the selected data format and the selected analog output
voltage. If the DAC gain setting is changed, the offset DAC code is reset to the default value corresponding to
the new DAC gain setting. Refer to the Power-On Reset and Hardware Reset sections for details.
For single-supply operation (AVSS = 0V), the Offset DAC is turned off, and the output amplifier is in a Hi-Z state.
The OFFSET-x pin must be connected to the AGND-x pin through a low-impedance connection (see the Layout
section for details). For dual-supply operation, this pin provides the output of the Offset DAC. The OFFSET-x pin
is not intended to drive an external load. See Figure 98 for the internal Offset DAC and output amplifier
configuration.
Table 5. Example of Offset DAC Codes and Output Ranges with Gain = 6 and VREF = 5V
OFFSET DAC
CODE
OFFSET DAC
VOLTAGE
DAC CHANNELS MFS(1)
VOLTAGE
DAC CHANNELS PFS(1)
VOLTAGE
999Ah(2)
3.0V
0V
–15V
0V
+15V – 1 LSB
+30V – 1 LSB
+5V – 1 LSB
+20V – 1 LSB
+10V – 1 LSB
0000h
FFFFh
6666h
~5.0V
~2.0V
~4.0V
–25V
–10V
–20V
CCCDh
(1) MFS = minus full-scale; PFS = plus full-scale.
(2) This is the default code for symmetric bipolar operation; actual codes may vary ±10 LSB. Codes are in straight binary format.
Table 6. Example of Offset DAC Codes and Output Ranges with Gain = 4 and VREF = 5V
OFFSET DAC
CODE
OFFSET DAC
VOLTAGE
DAC CHANNELS MFS(1)
VOLTAGE
DAC CHANNELS PFS(1)
VOLTAGE
AAABh(2)
~3.33333V
0V
–10V
0V
+10V – 1 LSB
+20V – 1 LSB
+5V – 1 LSB
0000h
FFFFh
5555h
~5.0V
–15V
–5V
~1.666V
2.5V
+15V – 1 LSB
+12.5V – 1 LSB
+7.5V – 1 LSB
8000h
–7.5V
–12.5V
D555h
~4.1666V
(1) MFS = minus full-scale; PFS = plus full-scale.
(2) This is the default code for symmetric bipolar operation; actual codes may vary ±10 LSB. Codes are in straight binary format.
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VOUT = GAIN x V1 - (GAIN - 1) x VOFF
V1
DAC
Channel
VOUT
AGND-x
VOFF
Offset
DAC
OFFSET
Figure 98. Output Amplifier and Offset DAC
OUTPUT AMPLIFIERS
The output amplifiers can swing to 0.5V below the positive supply and 0.5V above the negative supply. This
condition limits how much the output can be offset for a given reference voltage. The maximum range of the
output for ±17V power and a +5.5V reference is –16.5V to +16.5V for gain = 6.
Each output amplifier is implemented with individual over-current protection. The amplifier is clamped at 8mA,
even if the output current goes over 8mA.
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GENERAL-PURPOSE INPUT/OUTPUT PINS (GPIO-0 to GPIO-2)
The GPIO pins are general-purpose, bidirectional, digital input/outputs, as shown in Figure 99. When a GPIO pin
acts as an output, the pin status is determined by the corresponding GPIO bit in the GPIO Register. The pin
output is high-impedance when the GPIO bit is set to '1', and is logic low when the GPIO bit is cleared to '0'.
Note that a pull-up resistor to IOVDD is required when using a GPIO pin as an output. When a GPIO pin acts as
an input, the digital value on the pin is acquired by reading the corresponding GPIO bit. After power-on reset, or
any forced hardware or software reset, the GPIO bits are set to '1', and the GPIO pins are in a high-impedance
state. If not used, the GPIO pins must be tied to either DGND or to IOVDD through a pull-up resistor. Leaving the
GPIO pins floating can cause high IOVDD supply currents.
+V
GPIO-n
Enable
Bit GPIO-n (when writing)
Bit GPIO-n (when reading)
Figure 99. GPIO-n Pin
ANALOG OUTPUT PIN (CLR)
The CLR pin is an active low input that should be high for normal operation. When this pin is in logic '0', all VOUT
outputs connect to AGND-x through internal 15kΩ resistors and are cleared to 0V, and the output buffer is in a
Hi-Z state. While CLR is low, all LDAC pulses are ignored. When CLR is taken high again while the LDAC is
high, the DAC outputs remain cleared until LDAC is taken low. However, if LDAC is tied low, taking CLR back to
high sets the DAC output to the level defined by the value of the DAC latch. The contents of the Zero Registers,
Gain Registers, Input Data Registers, DAC Data Registers, and DAC latches are not affected by taking CLR low.
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POWER-ON RESET
The DAC8718 contains a power-on reset circuit that controls the output during power-on and power down. This
feature is useful in applications where the known state of the DAC output during power-on is important. The
Offset DAC Registers, DAC Data Registers, and DAC latches are loaded with the value defined by the RSTSEL
pin, as shown in Table 7. The Gain Registers and Zero Registers are loaded with default values. The Input Data
Register is reset to 0000h, independent of the RSTSEL state.
Table 7. Bipolar Output Reset Values for Dual Power-Supply Operation
VALUE OF DAC
DATA REGISTER
AND DAC LATCH
VALUE OF OFFSET
DAC REGISTER
FOR GAIN = 6(1)
RSTSEL PIN
DGND
USB/BTC PIN
DGND
INPUT FORMAT
Straight Binary
VOUT
–Full-Scale
0 V
0000h
8000h
8000h
0000h
999Ah
999Ah
199Ah
199Ah
IOVDD
DGND
Straight Binary
DGND
IOVDD
Twos Complement
Twos Complement
–Full-Scale
0 V
IOVDD
IOVDD
(1) Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the error for symmetrical output. The default value may vary
no more than ±10 LSB from the nominal number listed in this table.
In single-supply operation, the Offset DAC is turned off and the output is unipolar. The power-on reset is defined
as shown in Table 8.
Table 8. Unipolar Output Reset Values for Single Power-Supply Operation
VALUE OF DAC DATA
REGISTER AND DAC
RSTSEL PIN
DGND
USB/BTC PIN
DGND
INPUT FORMAT
Straight Binary
LATCH
0000h
8000h
8000h
0000h
VOUT
0 V
IOVDD
DGND
Straight Binary
Midscale
0 V
DGND
IOVDD
Twos Complement
Twos Complement
IOVDD
IOVDD
Midscale
HARDWARE RESET
When the RST pin is low, the device is in hardware reset. All the analog outputs (VOUT-0 to VOUT-7), the DAC
registers, and the DAC latches are set to the reset values defined by the RSTSEL pin as shown in Table 7 and
Table 8. In addition, the Gain and Zero Registers are loaded with default values, communication is disabled, and
the signals on CS and SDI are ignored (note that SDO is in a high-impedance state). The Input Data Register is
reset to 0000h, independent of the RSTSEL state. On the rising edge of RST, the analog outputs (VOUT-0 to
VOUT-7) maintain the reset value as defined by the RSTSEL pin until a new value is programmed. After RST
goes high, the serial interface returns to normal operation. CS must be set to a logic high whenever RST is used.
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UPDATING THE DAC OUTPUTS
Depending on the status of both CS and LDAC, and after data have been transferred into the DAC Data
registers, the DAC outputs can be updated either in asynchronous mode or synchronous mode. This update
mode is established at power-on. If asynchronous mode is desired, the LDAC pin must be permanently tied low
before power is applied to the device. If synchronous mode is desired, LDAC must be logic high before and
during power-on.
The DAC8718 updates a DAC latch only if it has been accessed since the last time LDAC was brought low or if
the LD bit is set to '1', thereby eliminating any unnecessary glitch. Any DAC channels that were not accessed are
not loaded again. When the DAC latch is updated, the corresponding output changes to the new level
immediately.
Asynchronous Mode
In this mode, the LDAC pin is set low at power-up. This action places the DAC8718 into Asynchronous mode,
and the LD bit and LDAC signal are ignored. When the correction engine is off (SCE bit = '0'), the DAC Data
Registers and DAC latches are updated immediately when CS goes high. When the correction engine is on (SCE
bit = '1'), each DAC latch is updated individually when the correction engine updates the corresponding DAC
Data Register.
Synchronous Mode
To use this mode, set LDAC high before CS goes low, and then take LDAC low or set the LD bit to '1' after CS
goes high. If LDAC goes low or if the LD bit is set to '1' when SCE = '0', all DAC latches are updated
simultaneously. If LDAC goes low or if the LD bit is set to '1' when SCE = '1', all DAC latches are updated
simultaneously after the correction engine has updated the corresponding DAC register.
In this mode, when LDAC stays high, the DAC latch is not updated; therefore, the DAC output does not change.
The DAC latch is updated by taking LDAC low (or by setting the LD bit in the Configuration Register to '1') any
time after the delay of t9 from the rising edge of CS. If the timing requirement of t9 is not satisfied, invalid data are
loaded. Refer to the Timing Diagrams and the Configuration Register (Table 11) for details.
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MONITOR OUTPUT PIN (VMON
)
The VMON pin is the channel monitor output. It can be either high-impedance or monitor any one of the DAC
outputs, auxiliary analog inputs, offset DAC outputs, or reference buffer outputs. The channel monitor function
consists of an analog multiplexer addressed via the serial interface, allowing any channel output, reference buffer
output, auxiliary analog inputs, or offset DAC output to be routed to the VMON pin for monitoring using an external
ADC. The monitor function is controlled by the Monitor Register, which allows the monitor output to be enabled
or disabled. When disabled, the monitor output is high-impedance; therefore, several monitor outputs may be
connected in parallel with only one enabled at a time.
Note that the multiplexer is implemented as a series of analog switches. Care should be taken to ensure the
maximum current from the VMON pin must not be greater than the given specification because this could
conceivably cause a large amount of current to flow from the input of the multiplexer (that is, from VOUT-X) to the
output of the multiplexer (VMON). Refer to the Monitor Register section and Table 12 for more details.
ANALOG INPUT PINS (AIN-0 and AIN-1)
Pins AIN-0 and AIN-1 are two analog inputs that directly connect to the analog mux of the analog monitor output.
When AIN-0 or AIN-1 is accessed, it is routed via the mux to the VMON pin. Thus, one external ADC channel can
monitor eight DACs plus two extra external analog signals, AIN-0 and AIN-1.
POWER-DOWN MODE
The DAC8718 is implemented with a power-down function to reduce power consumption. Either the entire device
or each individual group can be put into power-down mode. If the proper power-down bit (PD-x) in the
Configuration Register is set to '1', the individual group is put into power down mode. During power-down mode,
the analog outputs (VOUT-0 to VOUT-7) connect to AGND-X through an internal 15kΩ resistor, and the output
buffer is in Hi-Z status. When the entire device is in power-down, the bus interface remains active in order to
continue communication and receive commands from the host controller, but all other circuits are powered down.
The host controller can wake the device from power-down mode and return to normal operation by clearing the
PD-x bit; it takes 200μs or less for recovery to complete.
POWER-ON RESET SEQUENCING
The DAC8718 permanently latches the status of some of the digital pins at power-on. These digital levels should
be well-defined before or while the digital supply voltages are applied. Therefore, it is advised to have a pull up
resistor to IOVDD for the digital initialization pins (LDAC, CLR, RST, CS, and RSTSEL) to ensure that these levels
are set correctly while the digital supplies are raised.
For proper power-on initialization of the device, IOVDD and the digital pins must be applied before or at the same
time as DVDD. If possible, it is preferred that IOVDD and DVDD can be connected together in order to simplify the
supply sequencing requirements. Pull-up resistors should go to either supply. AVDD should be applied after the
digital supplies (IOVDD and DVDD) and digital initialization pins (LDAC, CLR, RST, CS, and RSTSEL). AVSS can
be applied at the same time as or after AVDD. The REF-x pins must be applied last.
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SERIAL INTERFACE
The DAC8718 is controlled over a versatile, three-wire serial interface that operates at clock rates of up to
50MHz and is compatible with SPI, QSPI™, Microwire™, and DSP™ standards.
SPI Shift Register
The SPI Shift Register is 24 bits wide. Data are loaded into the device MSB first as a 24-bit word under the
control of the serial clock input, SCLK. The SPI Shift Register consists of a read/write bit, five register address
bits, 16 data bits, and two reserve bits for future devices, as shown in Table 9. The falling edge of CS starts the
communication cycle. The data are latched into the SPI Shift Register on the falling edge of SCLK while CS is
low. When CS is high, the SCLK and SDI signals are blocked and the SDO pin is in a high-impedance state. The
contents of the SPI shifter register are decoded and transferred to the proper internal registers on the rising edge
of CS. The timing for this operation is shown in the Timing Diagrams section.
The serial interface works with both a continuous and non-continuous serial clock. A continuous SCLK source
can only be used if CS is held low for the correct number of clock cycles. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used and CS must be taken high after the final clock in
order to latch the data.
The serial interface requires CS to be logic high during the power-on sequencing; therefore, it is advised to have
a pullup resistor to IOVDD on the CS pin. Refer to the Power-On Reset Sequencing section for further details.
Stand-Alone Operation
The serial clock can be a continuous or a gated clock. The first falling edge of CS starts the operation cycle.
Exactly 24 falling clock edges must be applied before CS is brought back high again. If CS is brought high before
the 24th falling SCLK edge, then the data written are not transferred into the internal registers. If more than 24
falling SCLK edges are applied before CS is brought high, then the last 24 bits are used. The device internal
registers are updated from the Shift Register on the rising edge of CS. In order for another serial transfer to take
place, CS must be brought low again.
When the data have been transferred into the chosen register of the addressed DAC, all DAC latches and analog
outputs can be updated by taking LDAC low.
Daisy-Chain Operation
For systems that contain more than one device, the SDO pin can be used to daisy-chain multiple devices
together. Daisy-chain operation can be useful in system diagnostics and in reducing the number of serial
interface lines. Note that before daisy-chain operation can begin, the SDO pin must be enabled by setting the
SDO disable bit (DSDO) in the Configuration Register to '0'; this bit is cleared by default.
The DAC8718 provides two modes for daisy-chain operation: normal and sleep. The SLEEP bit in the SPI Mode
register determines which mode is used.
In Normal mode (SLEEP bit = '0'), the data clocked into the SDI pin are transferred into the Shift Register. The
first falling edge of CS starts the operating cycle. SCLK is continuously applied to the SPI Shift Register when CS
is low. If more than 24 clock pulses are applied, the data ripple out of the Shift Register and appear on the SDO
line. These data are clocked out on the rising edge of SCLK and are valid on the falling edge. By connecting the
SDO pin of the first device to the SDI input of the next device in the chain, a multiple-device interface is
constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles
must equal 24 × N, where N is the total number of DAC8718s in the chain. When the serial transfer to all devices
is complete, CS is taken high. This action latches the data from the SPI Shift Registers to the device internal
registers for each device in the daisy-chain, and prevents any further data from being clocked in. The serial clock
can be a continuous or a gated clock. Note that a continuous SCLK source can only be used if CS is held low for
the correct number of clock cycles. For gated clock mode, a burst clock containing the exact number of clock
cycles must be used and CS must be taken high after the final clock in order to latch the data.
In Sleep mode (SLEEP bit = '1'), the data clocked into SDI are routed to the SDO pin directly; the Shift Register
is bypassed. The first falling edge of CS starts the operating cycle. When SCLK is continuously applied with CS
low, the data clocked into the SDI pin appear on the SDO pin almost immediately (with approximately a 5 ns
delay; see the Timing Diagrams section); there is no 24 clock delay, as there is in normal operting mode. While
in Sleep mode, no data bits are clocked into the Shift Register, and the device does not receive any new data or
commands. Putting the device into Sleep mode eliminates the 24 clock delay from SDI to SDO caused by the
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Shift Register, thus greatly speeding up the data transfer. For example, consider three DAC8718s (A, B, and C)
in a daisy-chain configuration. The data from the SPI controller are transferred first to A, then to B, and finally to
C. In normal daisy-chain operation, a total of 72 clocks are needed to transfer one word to C. However, if A and
B are placed into Sleep mode, the first 24 data bits are directly transferred to C (through A and B); therefore, only
24 clocks are needed.
To wake the device up from sleep mode and return to normal operation, either one of following methods can be
used:
1. Pull the WAKEUP pin low, which forces the SLEEP bit to '0' and returns the device to normal operating
mode.
2. Use the W2 bit and the CS pin.
When the W2 bit = '1', if CS is applied with no more than one falling edge of SCLK, then the rising edge of CS
wakes the device from sleep mode back to normal operation. However, the device will not wake-up if more than
one falling edge of SCLK exists while CS is low.
Read-Back Operation
The READ command is used to start read-back operation. However, before read-back operation can be initiated,
the SDO pin must be enabled by setting the DSDO bit in the Configuration Register to '0'; this bit is cleared by
default. Read-back operation is then started by executing a READ command (R/W bit = '1', see Table 9). Bits A4
to A0 in the READ command select the register to be read. The remaining data in the command are don’t care
bits. During the next SPI operation, the data appearing on the SDO output are from the previously addressed
register. For a read of a single register, a NOP command can be used to clock out the data from the selected
register on SDO. Multiple registers can be read if multiple READ commands are issued. The readback diagram
in Figure 100 shows the read-back sequence.
Single Reading
CS
SCLK
R/W = ‘1’
R/W = ‘0’
DB23
DB0
DB0
DB23
DB0
DB0
SDI
READ Command Specifies
Register to be Read
NOP Command
(write ‘1’ to NOP bit)
DB23
DB23
SDO
Undefined
Data from
Selected Register
Multiple Readings
CS
SCLK
SDI
R/W = ‘1’
R/W = ‘1’
R/W = ‘1’
R/W = ‘0’
DB23
DB0
DB23
DB0
DB0
DB23
DB0
DB23
DB0
DB23
DB23
DB0
Command
Command to Read
Register A
Command to Read
Register B
Command to Read
Register C
NOP Command
(write ‘1’ to NOP bit)
DB23
DB0
DB23
DB23
DB0
DB23
DB0
DB0
Undefined
SDO
Undefined
Data from
Register A
Data from
Register B
Data from
Register C
Bit 23 = MSB
Bit 0 = LSB
= Don’t Care
Figure 100. Read-Back Operation
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SPI SHIFT REGISTER
The SPI Shift Register is 24 bits wide, as shown in Table 9. The register mapping is shown in Table 10; X = don't
care—writing to it has no effect, reading it returns '0'.
Table 9. Shift Register Format
MSB
DB23
R/W
DB22
X
DB21
X
DB20
A4
DB19
A3
DB18
A2
DB17
A1
DB16
A0
DB15:DB0
DATA
R/W
Indicates a read from or a write to the addressed register.
R/W = '0' sets a write operation and the data are written to the specified register.
R/W = '1' sets a read-back operation. Bits A4 to A0 select the register to be read. The remaining bits
are don’t care bits. During the next SPI operation, the data appearing on SDO pin are from the
previously addressed register.
A4:A0
DATA
Address bits that specify which register is accessed.
16 data bits
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REGISTER
Table 10. Register Map
ADDRESS BITS
DATA BITS
A4 A3 A2 A1 A0
D15
A/B
D14
LD
D13
RST
D12
D11
D10
D9
X
D8
D7
D6
D5
D4
D3:D0
X(1)
Configuration
Register
0
0
0
0
0
PD-A PD-B SCE
GAIN-A GAIN-B DSDO NOP
W2
0
0
0
0
0
0
0
1
1
0
Analog Monitor Select
X(1)
Monitor Register
GPIO Register
GPIO-2 GPIO-1 GPIO-0
X(1)
Offset DAC-A
Data
0
0
0
0
0
1
1
0
1
0
OS15:OS0(2)
Offset DAC-B
Data
OS15:OS0(2)
Reserved(3)
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Reserved
SPI MODE
SLEEP
Reserved(3)
DB15:DB0
DB15:DB0
DB15:DB0
DB15:DB0
DB15:DB0
DB15:DB0
DB15:DB0
DB15:DB0
DB15:DB0
Broadcast
DAC-0
DAC-1
DAC-2
DAC-3
DAC-4
DAC-5
DAC-6
DAC-7
Z15:Z0, default = 0 (0000h), twos complement
G15:G0, default = 32768 (8000h), straight binary
Z15:Z0, default = 0 (0000h), twos complement
G15:G0, default = 32768 (8000h), straight binary
Z15:Z0, default = 0 (0000h), twos complement
G15:G0, default = 32768 (8000h), straight binary
Z15:Z0, default = 0 (0000h), twos complement
G15:G0, default = 32768 (8000h), straight binary
Z15:Z0, default = 0 (0000h), twos complement
G15:G0, default = 32768 (8000h), straight binary
Z15:Z0, default = 0 (0000h), twos complement
G15:G0, default = 32768 (8000h), straight binary
Z15:Z0, default = 0 (0000h), twos complement
G15:G0, default = 32768 (8000h), straight binary
Z15:Z0, default = 0 (0000h), twos complement
G15:G0, default = 32768 (8000h), straight binary
Zero Register-0
Gain Register-0
Zero Register-1
Gain Register-1
Zero Register-2
Gain Register-2
Zero Register-3
Gain Register-3
Zero Register-4
Gain Register-4
Zero Register-5
Gain Register-5
Zero Register-6
Gain Register-6
Zero Register-7
Gain Register-7
(1) X = don't care—writing to this bit has no effect; reading the bit returns '0'.
(2) Table 7 lists the default values for a dual power supply. Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the
error for symmetrical output. The default value may vary no more than ±10 LSB from the nominal number listed in Table 7. For a single
power supply, the Offset DACs are turned off.
(3) Writing to a reserved bit has no effect; reading the bit returns '0'.
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INTERNAL REGISTERS
The DAC8718 internal registers consist of the Configuration Register, the Monitor Register, the DAC Input Data
Registers, the Zero Registers, the DAC Data Registers, and the Gain Registers, and are described in the
following section.
The Configuration Register specifies which actions are performed by the device. Table 11 shows the details.
Table 11. Configuration Register (Default = 8000h)
DEFAULT
BIT
NAME
VALUE
DESCRIPTION
A/B bit.
When A/B = '0', reading DAC-x returns the value in the Input Data Register.
D15
A/B
1
When A/B = '1', reading DAC-x returns the value in the DAC Data Register.
When the correction engine is enabled, the data returned from the Input Data Register is the original data written to the
bus, and the value in the DAC Data Register is the corrected data.
Synchronously update DACs bit.
When LDAC is tied high, setting LD = '1' at any time after the write operation and the correction process complete
synchronously updates all DAC latches with the content of the corresponding DAC Data Register, and sets VOUT to a new
level. The DAC8718 updates the DAC latch only if it has been accessed since the last time LDAC was brought low or the
LD bit was set to '1', thereby eliminating unnecessary glitch. Any DACs that were not accessed are not reloaded. After
updating, the bit returns to '0'. When the correction engine is turned off, bit LD can be set to '1' any time after the writing
operation is complete; the DAC latch is immediately updated when bit LD is set. When the LDAC pin is tied low, this bit is
ignored.
D14
LD
0
Software reset bit.
D13
D12
RST
0
0
Set the RST bit to '1' to reset the device; functions the same as a hardware reset. After reset completes, the RST bit
returns to '0'.
Power-down bit for Group A (DAC-0, DAC-1, DAC-2, and DAC-3).
Setting the PD-A bit to '1' places Group A (DAC-0, DAC-1, DAC-2, and DAC-3) into power-down operation. All output
buffers are in Hi-Z and all analog outputs (VOUT-X) connect to AGND-A through an internal 15-kΩ resistor. The interface is
still active.
PD-A
Setting the PD-A bit to '0' returns group A to normal operation.
Power-down bit for Group B (DAC-4, DAC-5, DAC-6, and DAC-7).
Setting the PD-B bit to '1' places Group B (DAC-4, DAC-5, DAC-6, and DAC-7) into power-down operation. All output
buffers are in Hi-Z and all analog outputs (VOUT-X) connect to AGND-B through an internal 15-kΩ resistor. The interface is
still active.
D11
D10
PD-B
SCE
0
0
Setting the PD-B bit to '0' returns group B to normal operation.
System-calibration enable bit.
Set the SCE bit to '1' to enable the correction engine. When the engine is enabled, the input data are adjusted by the
correction engine according to the contents of the corresponding Gain Register and Zero Register. The results are
transferred to the corresponding DAC Data Register, and finally loaded into the DAC latch, which sets the VOUT-x pin
output level.
Set the SCE bit to '0' to turn off the correction engine. When the engine is turned off, the input data are transferred to the
corresponding DAC Data Register immediately, and then loaded into the DAC latch, which sets the output voltage. Refer
to the User Calibration for Zero-Code Error and Gain Error section for details.
D9
D8
—
0
0
Reserved. Writing to this bit has no effect; reading this bit returns '0'.
Gain bit for Group A (DAC-0, DAC-1, DAC-2, and DAC-3). Updating this bit to a new value automatically resets the Offset
DAC-A Register to the factory-trimmed value for the new gain setting.
Set the GAIN-A bit to '0' for an output span = 6 × REF-A.
GAIN-A
Set the GAIN-A bit to '1' for an output span = 4 × REF-A.
Gain bit for Group B (DAC-4, DAC-5, DAC-6, and DAC-7). Updating this bit to a new value automatically resets the Offset
DAC-B Register to the factory-trimmed value for the new gain setting.
Set the GAIN-B bit to '0' for an output span = 6 × REF-B.
D7
D6
D5
GAIN-B
DSDO
NOP
0
0
0
Set the GAIN-B bit to '1' for an output span = 4 × REF-B.
Disable SDO bit.
Set the DSDO bit to '0' to enable the SDO pin (default). The SDO pin works as a normal SPI output.
Set the DSDO bit to '1' to disable the SDO pin. The SDO pin is always in a Hi-Z state no matter what the status of the CS
pin is.
No operation bit.
During a write operation, setting the NOP bit to '1' has no effect (the bit returns to '0' when the write operation completes).
Setting the NOP bit to '0', returns the device to normal operation.
During a read operation, the bit always returns “0”
Second wake-up operation bit.
If the WAKEUP pin is high, an alternative method to wake-up the device from sleep in SPI is by using the CS pin. When
W2 = '1', the rising edge of CS restores the device from sleep mode to normal operation, if no more than one falling edge
of SCLK exists while CS is low. However, the device will not wake up if more than one falling edge of SCLK exists. Setting
the W2 bit to '0' disables this function, and the rising edge of CS does not wake up the device.
If the WAKEUP is low, this bit is ignored and the device is always in normal mode.
D4
W2
—
0
0
D3:D0
Reserved. Writing to these bits has no effect; reading these bits returns '0'.
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Monitor Register (default = 0000h).
The Monitor Register selects one of the DAC outputs, auxiliary analog inputs, reference buffer outputs, or offset
DAC outputs to be monitored through the VMON pin. When bits [D15:D4] = '0', the monitor is disabled and VMON is
in a Hi-Z state.
Note that if any value is written other than those specified in Table 12, the Monitor Register stores the invalid
value; however, the VMON pin is forced into a Hi-Z state.
Table 12. Monitor Register (Default = 0000h)
D15 D14 D13 D12 D11 D10
D9
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
D8
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
D7
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
D6
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
D5
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
D4
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
D3:D0
X(1)
VMON CONNECTS TO
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Reference buffer B output
X
Reference buffer A output
X
Offset DAC B output
X
Offset DAC A output
X
AIN-0
X
AIN-1
X
DAC-0
X
DAC-1
X
DAC-2
X
DAC-4
X
DAC-4
X
DAC-5
X
DAC-6
DAC-7
X
X
Monitor function disabled, Hi-Z (default)
(1) X = don't care.
BLANKSPACE
GPIO Register (default = E000h).
The GPIO Register determines the status of each GPIO pin.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
GPIO-2 GPIO-1 GPIO-0
X
X
X
X
X
X
X
X
X
X
X
X
X
GPIO-2:0 For write operations, the GPIO-n pin operates as an output. Writing a '1' to the GPIO-n bit sets the
GPIO-n pin to high impedance, and writing a '0' sets the GPIO-n pin to logic low. An external
pull-up resistor is required when using the GPIO-n pin as an output.
For read operations, the GPIO-n pin operates as an input. Read the GPIO-n bit to receive the
status of the corresponding GPIO-n pin. Reading a '0' indicates that the GPIO-n pin is low, and
reading a '1' indicates that the GPIO-n pin is high.
After power-on reset, or any forced hardware or software reset, all GPIO-n bits are set to '1', and
the GPIO pins are in a high impedance state.
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Offset DAC-A/B Registers (default = 999Ah for dual supplies or 0000h for single supplies).
The Offset DAC-A and Offset DAC-B registers contain, by default, the factory-trimmed Offset DAC code
providing optimal offset and span for symmetric bipolar operation when dual supplies are detected, and contain
code 0000h when a single supply is detected.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OS15
OS14
OS13
OS12 OS11 OS10
OS9
OS8
OS7
OS6
OS5
OS4
OS3
OS2
OS1
OS0
OS15:0
For dual-supply operation, the default code for a gain of 6 is 999Ah with a ±10 LSB variation,
depending on the linearity of each Offset DAC. The default code for a gain of 4 is AAABh with a
±10 LSB variation. The default codes of Offset DAC-A and Offset DAC-B registers are
independently factory trimmed for both gains of 6 and 4.
When single-supply operation is present, writing to these registers is ignored and reading returns
0000h. When dual-supply operation is present, updating the GAIN-A (GAIN-B) bit on the
configuration register automatically reloads the factory-trimmed code into the Offset DAC-A (Offset
DAC-B) register for the new GAIN-A (GAIN-B) setting. See the Offset DACs for further details.
BLANKSPACE
SPI MODE Register (default = 0000h).
The SPI Mode Register is used to put the device into SPI sleep mode.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SLEEP
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SLEEP
Set the SLEEP bit to '1' to put the device into SPI sleep mode.
When the SLEEP bit = '0', the SPI is in normal mode. The bit is cleared ('0') after a hardware reset
(through the RST pin) or if the WAKEUP pin is low.
For normal SPI operation, the data entering the SDI pin is transferred into the Shift Register.
However, for SPI sleep mode, the Shift Register is bypassed. The data entering into the SDI pin
are directly transferred to the SDO pin instead of the Shift Register.
BLANKSPACE
Broadcast Register.
The DAC8718 broadcast register can be used to update all eight DAC register channels simultaneously using
data bits D15:D0. This write-only register uses address A4:A0 = 07h, and is only available when the SCE bit = '0'
(default). If the SCE bit = '1', this register is ignored. Reading this register always returns 0000h.
BLANKSPACE
Input Data Register for DAC-n, where n = 0 to 7 (default = 0000h).
This register stores the DAC data written to the device when the SCE bit = '1' and is controlled by the correction
engine. When the SCE bit = '0' (default), the DAC Data Register stores the DAC data written to the device. When
the data are loaded into the corresponding DAC latch, the DAC output changes to the new level defined by the
DAC latch. The default value after power-on or reset is 0000h.
Table 13. DAC-n(1) Input Data Register
MSB
D15
LSB
D0
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
DB15(2) DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
(1) n = 0, 1, 2, 3, 4, 5, 6, or 7.
(2) DB15:DB0 are the DAC data bits.
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Zero Register n, where n = 0 to 7 (default = 0000h).
The Zero Register stores the user-calibration data that are used to eliminate the offset error. The data are 16 bits
wide, 1 LSB/step, and the total adjustment is –32768 LSB to +32767 LSB, or ±50% of full-scale range. The Zero
Register uses a twos complement data format.
Table 14. Zero Register
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Z15
Z14
Z13
Z12
Z11
Z10
Z9
Z8
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
Z15:Z0—OFFSET BITS
7FFFh
ZERO ADJUSTMENT
+32767 LSB
+32766 LSB
••• ••• •••
7FFEh
••• ••• •••
0001h
+1 LSB
0000h
0 LSB (default)
–1 LSB
FFFFh
••• ••• •••
8001h
••• ••• •••
–32767 LSB
–32768 LSB
8000h
BLANKSPACE
Gain Register n, where n = 0 to 7 (default = 8000h).
The Gain Register stores the user-calibration data that are used to eliminate the gain error. The data are 16 bits
wide, 0.0015% FSR/step, and the total adjustment range 0.5 to 1.5. The Gain Register uses a straight binary
data format.
Table 15. Gain Register
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
G15
G14
G13
G12
G11
G10
G9
G8
G7
G6
G5
G4
G3
G2
G1
G0
G15:G0—GAIN-CODE BITS
GAIN ADJUSTMENT COEFFICIENT
FFFFh
FFFEh
••• ••• •••
8001h
1.499985
1.499969
••• ••• •••
1.000015
1 (default)
0.999985
••• ••• •••
0.500015
0.5
8000h
7FFFh
••• ••• •••
0001h
0000h
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SBAS467A –MAY 2009–REVISED DECEMBER 2009
APPLICATION INFORMATION
BASIC OPERATION
The DAC8718 is a highly-integrated device with high-performance reference buffers and output buffers, greatly
reducing the printed circuit board (PCB) area and production cost. On-chip reference buffers eliminate the need
for a negative external reference. Figure 101 shows a basic application for the DAC8718.
1mF
10kW
1mF
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVDD
AVDD
1
2
3
4
5
6
7
8
9
AVDD
AVDD 48
NC 47
10mF
10mF
NC
AIN-0
AIN-1
AIN-0
AIN-1 46
VOUT-4 45
REF-B 44
VOUT-5 43
VOUT-6 42
AGND-B 41
AGND-B 40
OFFSET-B 39
VOUT-7 38
AVSS 37
VOUT-3
REF-A
VOUT-2
VOUT-1
VOUT-4
REF-B
VOUT-5
VOUT-6
VOUT-3
REF-A
VOUT-2
VOUT-1
AGND-A
AGND-A
DAC8718
OFFSET-A
VOUT-0
OFFSET-B
VOUT-7
10 OFFSET-A
11 VOUT-0
12 AVSS
13 NC
10mF
AVSS
10mF
AVSS
NC 36
VMON
14 VMON
15 NC
NC 35
NC 34
16 NC
NC 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1mF
10kW
10kW
10kW
NOTES: AVDD = +15V, AVSS = -15V, DVDD = +5V, IOVDD = +1.8V to +5V, REF-A = +5V, and REF-B = +2.5V.
NOTES: The OFFSET-A and OFFSET-B pins must be connected to the AGND pin when used in unipolar operation.
Figure 101. Basic Application Example
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PRECISION VOLTAGE REFERENCE SELECTION
To achieve the optimum performance from the DAC8718 over the full operating temperature range, a precision
voltage reference must be used. Careful consideration should be given to the selection of a precision voltage
reference. The DAC8718 has two reference inputs, REF-A and REF-B. The voltages applied to the reference
inputs are used to provide a buffered positive reference for the DAC cores. Therefore, any error in the voltage
reference is reflected in the outputs of the device. There are four possible sources of error to consider when
choosing a voltage reference for high-accuracy applications: initial accuracy, temperature coefficient of the output
voltage, long-term drift, and output voltage noise. Initial accuracy error on the output voltage of an external
reference can lead to a full-scale error in the DAC. Therefore, to minimize these errors, a reference with low
initial accuracy error specification is preferred. Long-term drift is a measure of how much the reference output
voltage drifts over time. A reference with a tight, long-term drift specification ensures that the overall solution
remains relatively stable over its entire lifetime. The temperature coefficient of a reference output voltage affects
the output drift when the temperature changes. Choose a reference with a tight temperature coefficient
specification to reduce the dependence of the DAC output voltage on ambient conditions. In high-accuracy
applications, which have a relatively low noise budget, the reference output voltage noise also must be
considered. Choosing a reference with as low an output noise voltage as practical for the required system
resolution is important. Precision voltage references such as TI's REF50xx (2V to 5V) and REF32xx (1.25V to
4V) provide a low-drift, high-accuracy reference voltage.
POWER-SUPPLY NOISE
The DAC8718 must have ample supply bypassing of 1μF to 10μF in parallel with 0.1μF on each supply, located
as close to the package as possible; ideally, immediately next to the device. The 1μF to 10μF capacitors must be
the tantalum-bead type. The 0.1μF capacitor must have low effective series resistance (ESR) and low effective
series inductance (ESI), such as common ceramic types, which provide a low-impedance path to ground at high
frequencies to handle transient currents because of internal logic switching. The power-supply lines must be as
large a trace as possible to provide low-impedance paths and reduce the effects of glitches on the power-supply
line. Apart from these considerations, the wideband noise on the AVDD, AVSS, DVDD and IOVDD supplies should
be filtered before feeding to the DAC to obtain the best possible noise performance.
LAYOUT
Precision analog circuits require careful layout, adequate bypassing, and a clean, well-regulated power supply to
obtain the best possible dc and ac performance. Careful consideration of the power-supply and ground-return
layout helps to meet the rated performance. DGND is the return path for digital currents and AGND is the power
ground for the DAC. For the best ac performance, care should be taken to connect DGND and AGND with very
low resistance back to the supply ground. The PCB must be designed so that the analog and digital sections are
separated and confined to certain areas of the board. If multiple devices require an AGND-to-DGND connection,
the connection is to be made at one point only. The star ground point is established as close as possible to the
device.
The power-supply traces must be as large as possible to provide low impedance paths and reduce the effects of
glitches on the power-supply line. Fast switching signals must never be run near the reference inputs. It is
essential to minimize noise on the reference inputs because it couples through to the DAC output. Avoid
crossover of digital and analog signals. Traces on opposite sides of the board must run at right angles to each
other. This configuration reduces the effects of feedthrough on the board. A microstrip technique may be
considered, but is not always possible with a double-sided board. In this technique, the component side of the
board is dedicated to the ground plane, and signal traces are placed on the solder-side.
Each DAC group has a ground pin, AGND-x, which is the ground of the output from the DACs in the group. It
must be connected directly to the corresponding reference ground in low-impedance paths to get the best
performance. AGND-A must be connected with REFGND-A and AGND-B must be connected with REFGND-B.
AGND-A and AGND-B must be tied together and connected to the analog power ground and DGND.
During single-supply operation, the OFFSET-x pins must be connected to AGND-x with a low-impedance path
because these pins carry DAC-code-dependent current. Any resistance from OFFSET-x to AGND-x causes a
voltage drop by this code-dependent current. Therefore, it is very important to minimize routing resistance to
AGND-x or to any ground plane that AGND-x is connected to.
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PACKAGE OPTION ADDENDUM
www.ti.com
5-May-2010
PACKAGING INFORMATION
Orderable Device
DAC8718SPAG
DAC8718SPAGR
DAC8718SRGZR
DAC8718SRGZT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TQFP
PAG
64
64
48
48
160 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
TQFP
VQFN
VQFN
PAG
RGZ
RGZ
1500 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
M
0,08
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
11,80
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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TI
DAC8718_14
Octal, 16-Bit, Low-Power, High-Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER
TI
DAC8728
Octal, 16-Bit, Low-Power, High-Voltage Output, Parallel Input DIGITAL-TO-ANALOG CONVERTER
TI
DAC8728SPAG
Octal, 16-Bit, Low-Power, High-Voltage Output, Parallel Input DIGITAL-TO-ANALOG CONVERTER
TI
DAC8728SPAGR
Octal, 16-Bit, Low-Power, High-Voltage Output, Parallel Input DIGITAL-TO-ANALOG CONVERTER
TI
DAC8728SRTQR
Octal, 16-Bit, Low-Power, High-Voltage Output, Parallel Input DIGITAL-TO-ANALOG CONVERTER
TI
DAC8728SRTQT
Octal, 16-Bit, Low-Power, High-Voltage Output, Parallel Input DIGITAL-TO-ANALOG CONVERTER
TI
DAC8728_14
Octal, 16-Bit, Low-Power, High-Voltage Output, Parallel Input DIGITAL-TO-ANALOG CONVERTER
TI
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