DAC8555IPW [TI]
16 位、四通道、超低毛刺脉冲、电压输出数模转换器 | PW | 16 | -40 to 105;
| 型号： | DAC8555IPW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16 位、四通道、超低毛刺脉冲、电压输出数模转换器 | PW | 16 | -40 to 105 脉冲 转换器 数模转换器 |
| 文件： | 总32页 (文件大小：1012K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DAC8555
SLAS475B–NOVEMBER 2005–REVISED OCTOBER 2006
16-BIT, QUAD CHANNEL, ULTRA-LOW GLITCH, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
•
•
•
Relative Accuracy: 4LSB
The DAC8555 is a 16-bit, quad channel, voltage
output digital-to-analog converter (DAC) offering
low-power operation and flexible serial host
interface. It offers monotonicity, good linearity, and
exceptionally low glitch. Each on-chip precision
output amplifier allows rail-to-rail output swing to be
achieved over the supply range of 2.7V to 5.5V. The
device supports a standard 3-wire serial interface
capable of operating with input data clock
frequencies up to 50MHz for IOVDD = 5V.
Glitch Energy: 0.15nV-s
a
MicroPower Operation:
150µA per Channel at 2.7V
•
•
•
•
•
•
Power-On Reset to Zero-Scale or Midscale
Power Supply: +2.7V to +5.5V
16-Bit Monotonic Over Temperature
Settling Time: 10µs to ±0.003% FSR
Ultra-Low AC Crosstalk: –100dB Typ
The DAC8555 requires an external reference voltage
to set the output range of each DAC channel. Also
incorporated into the device is a power-on reset
circuit, which can be programmed to ensure that the
DAC outputs power up at zero-scale or midscale and
remain there until a valid write takes place. The
device also has the capability to function in both
binary and 2's complement mode. The DAC8555
Low-Power SPI™-Compatible Serial Interface
with Schmitt-Triggered Inputs: Up to 50MHz
•
On-Chip Output Buffer Amplifier with
Rail-to-Rail Operation
•
•
Double Buffered Input Architecture
Simultaneous or Sequential Output Update
and Power-Down
provides
a
per channel power-down feature,
accessed over the serial interface, that reduces the
current consumption to 175nA per channel at 5V.
•
•
Binary and 2's Complement Capability
Asynchronous Clear to Zero-Scale and
Midscale
The low-power consumption of this device in normal
operation makes it ideally suited to portable battery-
•
•
1.8V to 5.5V Logic Compatibility
Available in a TSSOP-16 Package
operated
equipment
and
other
low-power
applications. The power consumption is 5mW at 5V,
reducing to 4µW in power-down mode.
APPLICATIONS
The DAC8555 is available in a TSSOP-16 package
with a specified operating temperature range of
–40°C to +105°C.
•
•
•
•
•
•
Portable Instrumentation
Closed-Loop Servo-Control
Process Control
Data Acquisition Systems
Programmable Attenuation
PC Peripherals
FUNCTIONAL BLOCK DIAGRAM
AV
DD
IOV
DD
V
H
REF
Data
Buffer A
DAC
Register A
V
V
V
V
A
B
C
D
DAC A
DAC D
OUT
OUT
OUT
Data
Buffer D
DAC
Register D
OUT
18
SYNC
SCLK
Buffer
Control
Register
Control
24-Bit
Serial-to-Parallel
Shift Register
Power-Down
Control Logic
8
D
Resistor
Network
IN
RST RSTSEL
LDAC
ENABLE
V
L
REF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
DAC8555
www.ti.com
SLAS475B–NOVEMBER 2005–REVISED OCTOBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGING/ORDERING INFORMATION(1)
MAXIMUM
RELATIVE
MAXIMUM
DIFFERENTIAL
SPECIFIED
TEMPERATURE
RANGE
ACCURACY NONLINEARITY PACKAGE-
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
(LSB)
(LSB)
LEAD
DAC8555IPW
Tube, 90
DAC8555
±12
±1
TSSOP-16
PW
–40°C to +105°C
D8555
DAC8555IPWR Tape and Reel, 2000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
UNIT
AVDD, IOVDD to GND
–0.3V to 6V
–0.3V to +AVDD + 0.3V
–0.3V to +AVDD + 0.3V
–40°C to +105°C
–65°C to +150°C
+150°C
Digital input voltage to GND
VO(A) to VO(D) to GND
Operating temperature range
Storage temperature range
Junction temperature range (TJ max)
Power dissipation
(TJ max – TA)/θJA
118°C/W
θJA Thermal impedance
θJC Thermal impedance
29°C/W
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted).
PARAMETER
STATIC PERFORMANCE(1)
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
16
Bits
LSB
LSB
mV
Relative accuracy
Differential nonlinearity
Zero-scale error
Measured by line passing through codes 485 and 64741
16-bit Monotonic
±4
±0.25
±2
±12
±1
Measured by line passing through codes 485 and 64741
±12
Zero-scale error drift
Full-scale error
±5
µV/°C
±0.3
±0.05
±0.5 % of FSR
±0.15 % of FSR
Measured by line passing through codes 485 and 64741,
(AVDD = 5V, VREF = 4.99V) and (AVDD = 2.7V, VREF = 2.69V)
Gain error
ppm of
FSR/°C
Gain temperature coefficient
±1
PSRR Power-Supply Rejection Ratio RL = 2kΩ, CL = 200pF
OUTPUT CHARACTERISTICS(2)
0.75
mV/V
Output voltage range
0
VREF
H
V
To ±0.003% FSR, 0200h to FD00h, RL = 2kΩ,
0pF < CL < 200pF
8
10
µs
Output voltage settling time
RL = 2kΩ, CL = 500pF
12
1.8
µs
V/µs
pF
Slew rate
RL = ∞
470
Capacitive load stability
RL = 2kΩ
1000
pF
(1) Linearity calculated using a reduced code range of 485 to 64741; output unloaded.
(2) Ensured by design and characterization; not production tested.
2
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SLAS475B–NOVEMBER 2005–REVISED OCTOBER 2006
ELECTRICAL CHARACTERISTICS (continued)
VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted).
PARAMETER
Code change glitch impulse
Digital feedthrough
TEST CONDITIONS
1LSB change around major carry
MIN
TYP
0.15
0.15
MAX
UNIT
nV-s
Full-scale swing on adjacent channel. AVDD = 5V,
VREF = 4.096V
DC crosstalk
0.25
LSB
AC crosstalk
1kHz sine wave
–100
1
dB
DC output impedance
At mid-point input
Ω
AVDD = 5V
50
20
2.5
5
Short-circuit current
Power-up time
mA
AVDD = 3V
Coming out of power-down mode, AVDD = 5V
Coming out of power-down mode, AVDD = 3V
µs
AC PERFORMANCE
SNR
95
–85
87
THD
BW = 20kHz, AVDD = 5V, fOUT = 1kHz,
1st 19 harmonics removed for SNR calculation
dB
SFDR
SINAD
84
REFERENCE INPUT
VREFH Voltage
VREFL Voltage
VREFL < VREFH, AVDD– (VREFH + VREFL) /2 > 1.2V
VREFL < VREFH, AVDD– (VREFH + VREFL) /2 > 1.2V
VREFL = GND, VREFH = AVDD = 5V
0
0
AVDD
AVDD/2
250
V
V
180
120
31
µA
µA
kΩ
Reference input current
VREFL = GND, VREFH = AVDD = 3V
200
Reference input impedance
VREFL < VREFH
LOGIC INPUTS(3)
2.7V ≤ IOVDD ≤ 5.5V
1.8V ≤ IOVDD ≤ 2.7V
2.7 ≤ IOVDD ≤ 5.5V
1.8 ≤ IOVDD < 2.7V
0.3 × IOVDD
0.1 × IOVDD
VIL
VIH
Logic input LOW voltage
V
0.7 × IOVDD
Logic input HIGH voltage
V
0.95 × IOVDD
Pin capacitance
3
pF
POWER REQUIREMENTS
AVDD
2.7
1.8
5.5
5.5
V
IOVDD
IDD (normal mode)
IOIDD
Input code = 32768, no load, reference current not included
VIH = IOVDD and VIL = GND
10
0.65
0.6
20
0.95
0.9
µA
AVDD = 3.6V to 5.5V
AVDD = 2.7V to 3.6V
IDD (all power-down modes)
AVDD = 3.6V to 5.5V
AVDD = 2.7V to 3.6V
POWER EFFICIENCY
IOUT/IDD
mA
VIH = IOVDD and VIL = GND
IL = 2mA, AVDD = 5V
0.7
0.4
2
2
µA
89
%
TEMPERATURE RANGE
Specified performance
–40
+105
°C
(3) Ensured by design and characterization; not production tested.
3
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SLAS475B–NOVEMBER 2005–REVISED OCTOBER 2006
PIN CONFIGURATION
VOUT
VOUT
VREF
AVDD
VREF
GND
A
1
2
3
4
5
6
7
8
16 LDAC
B
15 ENABLE
H
RSTSEL
RST
14
13
12
11
10
9
DAC8555
L
IOVDD
DIN
VOUT
C
D
SCLK
SYNC
VOUT
PIN DESCRIPTIONS
PIN
1
NAME
DESCRIPTION
VOUT
VOUT
A
B
Analog output voltage from DAC A.
Analog output voltage from DAC B.
Positive reference voltage input.
Power supply input, 2.7V to 5.5V.
Negative reference voltage input.
2
3
VREFH
AVDD
4
5
VREF
L
6
GND
Ground reference point for all circuitry on the device.
Analog output voltage DAC C.
7
VOUT
VOUT
C
8
D
Analog output voltage DAC D.
Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When
SYNC goes LOW, it enables the input shift register and data is transferred in on the falling edges of the
following clocks. The DAC is updated following the 24th clock (unless SYNC is taken HIGH before this edge,
in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the
DAC8555). Schmitt-Trigger logic input.
9
SYNC
10
11
12
13
SCLK
DIN
Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic input.
Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock
input. Schmitt-Trigger logic input.
IOVDD
RST
Digital input-output power supply
Asynchronous reset. Active low. If RST is low, all DAC channels reset either to zero-scale (RSTSEL = 0) or
to midscale (RSTSEL = 1).
14
15
16
RSTSEL
ENABLE
LDAC
Reset select. If RSTSEL is low, input coding is binary; if high = 2's complement.
Active LOW, ENABLE LOW connects the SPI interface to the serial port.
Load DACs, rising edge triggered loads all DAC registers.
4
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SLAS475B–NOVEMBER 2005–REVISED OCTOBER 2006
SERIAL WRITE OPERATION
t9
t1
SCLK
1
24
t8
t2
t3
t7
t4
SYNC
t6
t5
DB23
DB0
DIN
DB23
t10
RST
TIMING REQUIREMENTS(1)(2)
AVDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 5.5V
IOVDD = AVDD = 2.7V to 3.5V
IOVDD = AVDD = 3.6V to 5.5V
40
ns
20
(3)
t1
t2
t3
t4
t5
t6
t7
SCLK cycle time
SCLK HIGH time
SCLK LOW time
20
ns
10
20
ns
10
0
SYNC falling edge to SCLK rising edge setup time
Data setup time
ns
0
5
ns
5
4.5
Data hold time
ns
4.5
0
24th SCLK falling edge to SYNC rising edge
ns
0
40
ns
20
t8
t9
Minimum SYNC HIGH time
24th SCLK falling edge to SYNC falling edge
Miniumum RST low time
130
40
ns
t10
ns
20
(1) All input signals are specified with tR = tF = 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See Serial Write Operation timing diagram.
(3) Maximum SCLK frequency is 50MHz at IOVDD = AVDD = 3.6V to 5.5V and 25 MHz at IOVDD = AVDD = 2.7V to 3.6V.
5
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SLAS475B–NOVEMBER 2005–REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS: VDD = 5V
At TA = +25°C, unless otherwise noted.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
8
6
8
6
VDD = 5V, VREF = 4.99V
VDD = 5V, VREF = 4.99V
Channel A
Channel B
4
4
2
2
0
0
-2
-4
-6
-8
-2
-4
-6
-8
1.0
0.5
1.0
0.5
0
0
-0.5
-1.0
-0.5
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 1.
Figure 2.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
8
6
8
6
VDD = 5V, VREF = 4.99V
VDD = 5V, VREF = 4.99V
Channel C
Channel D
4
4
2
2
0
0
-2
-4
-6
-8
-2
-4
-6
-8
1.0
0.5
1.0
0.5
0
0
-0.5
-1.0
-0.5
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 3.
Figure 4.
ZERO-SCALE ERROR
vs TEMPERATURE
FULL-SCALE ERROR
vs TEMPERATURE
0
5.0
2.5
VDD = 5V
AVDD = 5V, VREF = 4.99V
VREF = 4.99V
CH C
-5
-10
-15
-20
-25
CH A
CH B
0
CH C
CH D
CH A
-2.5
-5.0
CH D
CH B
-40
0
40
80
120
-40
0
40
80
120
Temperature (°C)
Temperature (°C)
Figure 5.
Figure 6.
6
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SLAS475B–NOVEMBER 2005–REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS: VDD = 5V (continued)
At TA = +25°C, unless otherwise noted.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
SOURCE CURRENT CAPABILITY (ALL CHANNELS)
6.0
2000
1600
1200
800
400
0
TA = +25°C, SYNC Input (All other inputs = GND)
CH A Powered Up (All other channels in powerdown)
Reference Current Included
5.6
5.2
4.8
IOVDD = AVDD = VREF = 5V
4.4
4.0
AVDD = 5.5V
VREF = AVDD - 10mV
DAC Loaded with FFFFh
0
2
4
6
8
10
0
1
2
3
4
5
ISOURCE (mA)
VLOGIC (V)
Figure 7.
Figure 8.
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
POWER SPECTRAL DENSITY
-40
-50
-60
-70
-80
-90
-100
AVDD = 5V
AVDD = VREF = 5V
-10
-30
VREF = 4.096V
fCLK = 1MSPS
fOUT = 1kHz
THD = 79dB
SNR = 96dB
-1dB FSR Digital Input
fS = 1MSPS
Measurement Bandwidth = 20kHz
-50
-70
THD
-90
-110
-130
2nd Harmonic
1
3rd Harmonic
0
5k
10k
15k
20k
0
2
3
4
5
Frequency (Hz)
fOUT (kHz)
Figure 9.
Figure 10.
FULL-SCALE SETTLING TIME: 5V RISING EDGE
FULL-SCALE SETTLING TIME: 5V FALLING EDGE
Trigger Pulse: 5V/div
Trigger Pulse: 5V/div
AVDD = 5V,
AVDD = 5V,
VREF = 4.096V,
From Code: FFFF
To Code: 0000
VREF = 4.096V,
From Code: 0000
To Code: FFFF
Falling
Edge
1V/div
Rising
Edge
1V/div
Zoomed Rising Edge
1mV/div
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
Figure 11.
Figure 12.
7
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SLAS475B–NOVEMBER 2005–REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS: VDD = 5V (continued)
At TA = +25°C, unless otherwise noted.
HALF-SCALE SETTLING TIME: 5V RISING EDGE
HALF-SCALE SETTLING TIME: 5V FALLING EDGE
Trigger Pulse: 5V/div
Trigger Pulse: 5V/div
AVDD = 5V,
VREF = 4.096V,
From Code: CFFF
To Code: 4000
AVDD = 5V,
VREF = 4.096V,
From Code: 4000
To Code: CFFF
Falling
Edge
1V/div
Rising
Edge
1V/div
Zoomed Rising Edge
1mV/div
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
Figure 13.
Figure 14.
GLITCH ENERGY: 5V, 1LSB STEP, RISING EDGE
GLITCH ENERGY: 5V, 1LSB STEP, FALLING EDGE
AVDD = 5V,
AVDD = 5V,
VREF = 4.096V,
From Code: 7FFF
To Code: 8000
Glitch: 0.08nV-s
VREF = 4.096V,
From Code: 8000
To Code: 7FFF
Glitch: 0.16nV-s
Measured Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 15.
Figure 16.
GLITCH ENERGY: 5V, 16LSB STEP, RISING EDGE
GLITCH ENERGY: 5V, 16LSB STEP, FALLING EDGE
AVDD = 5V,
VREF = 4.096V,
From Code: 8010
To Code: 8000
Glitch: 0.08nV-s
AVDD = 5V,
VREF = 4.096V,
From Code: 8000
To Code: 8010
Glitch: 0.04nV-s
Time (400ns/div)
Time (400ns/div)
Figure 17.
Figure 18.
8
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TYPICAL CHARACTERISTICS: VDD = 5V (continued)
At TA = +25°C, unless otherwise noted.
GLITCH ENERGY: 5V, 256LSB STEP, RISING EDGE
GLITCH ENERGY: 5V, 256LSB STEP, FALLING EDGE
AVDD = 5V,
VREF = 4.096V,
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
AVDD = 5V,
VREF = 4.096V,
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 19.
Figure 20.
SIGNAL-TO-NOISE RATIO
vs OUTPUT FREQUENCY
OUTPUT NOISE DENSITY
350
98
AVDD = VREF = 5V
-1dB FSR Digital Inputs
AVDD = 5V
VREF = 4.096V
Code = 7FFF
No Load
96
fS = 1MSPS
Measurement Bandwidth = 20kHz
94
300
250
200
150
100
92
90
88
86
84
100
1k
10k
100k
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Frequency (Hz)
fOUT (kHz)
Figure 21.
Figure 22.
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TYPICAL CHARACTERISTICS: VDD = 2.7V
At TA = +25°C, unless otherwise noted.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
8
6
8
6
VDD = 2.7V, VREF = 2.69V
VDD = 2.7V, VREF = 2.69V
Channel A
Channel B
4
4
2
2
0
0
-2
-4
-6
-8
-2
-4
-6
-8
1.0
0.5
1.0
0.5
0
0
-0.5
-1.0
-0.5
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 23.
Figure 24.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
8
6
8
6
VDD = 2.7V, VREF = 2.69V
VDD = 2.7V, VREF = 2.69V
Channel C
Channel D
4
4
2
2
0
0
-2
-4
-6
-8
-2
-4
-6
-8
1.0
0.5
1.0
0.5
0
0
-0.5
-1.0
-0.5
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 25.
Figure 26.
ZERO-SCALE ERROR
vs TEMPERATURE
FULL-SCALE ERROR
vs TEMPERATURE
0
5.0
2.5
VDD = 2.7V
AVDD = 2.7V, VREF = 2.69V
VREF = 2.69V
-5
-10
-15
-20
-25
CH C
CH C
CH A
CH A
CH B
CH D
0
CH B
CH D
-2.5
-5.0
-40
0
40
80
120
-40
0
40
80
120
Temperature (°C)
Temperature (°C)
Figure 27.
Figure 28.
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TYPICAL CHARACTERISTICS: VDD = 2.7V (continued)
At TA = +25°C, unless otherwise noted.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
SOURCE CURRENT CAPABILITY (ALL CHANNELS)
3.0
800
600
400
200
0
TA = +25°C, SYNC Input (All other inputs = GND)
CH A Powered Up (All other channels in powerdown)
Reference Current Included
2.7
2.4
2.1
IOVDD = AVDD = VREF = 2.7V
1.8
1.5
AVDD = 2.7V
VREF = AVDD - 10mV
DAC Loaded with FFFFh
0
2
4
6
8
10
0
0.5
1.0
1.5
2.0
2.5 2.7
ISOURCE (mA)
VLOGIC (V)
Figure 29.
Figure 30.
FULL-SCALE SETTLING TIME: 2.7V RISING EDGE
FULL-SCALE SETTLING TIME: 2.7V FALLING EDGE
Trigger Pulse: 2.7V/div
Trigger Pulse: 2.7V/div
Rising
Edge
0.5V/div
AVDD = 2.7V,
VREF = 2.5V,
From Code: 0000
To Code: FFFF
AVDD = 2.7V,
VREF = 2.5V,
From Code: FFFF
To Code: 0000
Zoomed Falling Edge
1mV/div
Falling
Edge
0.5V/div
Zoomed Rising Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
Figure 31.
Figure 32.
HALF-SCALE SETTLING TIME: 2.7V RISING EDGE
HALF-SCALE SETTLING TIME: 2.7V FALLING EDGE
Trigger Pulse: 2.7V/div
Trigger Pulse: 2.7V/div
AVDD = 2.7V,
VREF = 2.5V,
From Code: CFFF
To Code: 4000
AVDD = 2.7V,
VREF = 2.5V,
From Code: 4000
To Code: CFFF
Rising
Edge
Falling
Edge
Zoomed Rising Edge
0.5V/div
Zoomed Falling Edge
0.5V/div
1mV/div
1mV/div
Time (2ms/div)
Time (2ms/div)
Figure 33.
Figure 34.
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TYPICAL CHARACTERISTICS: VDD = 2.7V (continued)
At TA = +25°C, unless otherwise noted.
GLITCH ENERGY: 2.7V, 1LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7V, 1LSB STEP, FALLING EDGE
AVDD = 2.7V,
VREF = 2.5V,
AVDD = 2.7V,
VREF = 2.5V,
From Code: 7FFF
To Code: 8000
Glitch: 0.08nV-s
From Code: 8000
To Code: 7FFF
Glitch: 0.16nV-s
Measured Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 35.
Figure 36.
GLITCH ENERGY: 2.7V, 16LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7V, 16LSB STEP, FALLING EDGE
AVDD = 2.7V,
VREF = 2.5V,
From Code: 8010
To Code: 8000
Glitch: 0.12nV-s
AVDD = 2.7V,
VREF = 2.5V,
From Code: 8000
To Code: 8010
Glitch: 0.04nV-s
Time (400ns/div)
Time (400ns/div)
Figure 37.
Figure 38.
GLITCH ENERGY: 2.7V, 256LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7V, 256LSB STEP, FALLING EDGE
AVDD = 2.7V,
VREF = 2.5V,
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
AVDD = 2.7V,
VREF = 2.5V,
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 39.
Figure 40.
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TYPICAL CHARACTERISTICS: VDD = 5V and 2.7V
At TA = +25°C, unless otherwise noted.
SUPPLY CURRENT
vs DIGITAL INPUT CODE
SINK CURRENT CAPABILITY (ALL CHANNELS)
1200
1000
800
600
400
200
0
0.150
VREF = AVDD - 10mV
DAC Loaded with 0000h
Reference Current Included
AVDD = VREF = 5V
0.125
0.100
0.075
0.050
0.025
0
VDD = 2.7V
VDD = 5.5V
AVDD = VREF = 2.7V
0
8192 16384 24576 32768 40960 49152 57344 65535
Digital Input Code
0
2
4
6
8
10
ISINK (mA)
Figure 41.
Figure 42.
SUPPLY CURRENT
vs FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs SUPPLY VOLTAGE
1200
1000
800
600
400
200
0
900
850
800
750
700
650
600
VREF = AVDD, All DACs Powered,
Reference Current Included, No Load
Reference Current Included
AVDD = VREF = 5V
AVDD = VREF = 2.7V
-40
0
40
80
120
2.7
3.05
3.4
3.75
4.1
4.45
4.8
5.15
5.5
Temperature (°C)
AVDD (V)
Figure 43.
Figure 44.
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THEORY OF OPERATION
VREF
H
DAC SECTION
The architecture of each channel of the DAC8555
consists of a resistor-string DAC followed by an
output buffer amplifier. Figure 45 shows a simplified
block diagram of the DAC architecture.
RDIVIDER
VREF
2
VREF
H
50kW
50kW
R
R
62kW
VOUT
REF(+)
Resistor String
REF(-)
To Output Amplifier
(2x Gain)
DAC
Register
VREFL
Figure 45. DAC8555 Architecture
The input coding for each device can be 2's
complement or unipolar straight binary, so the ideal
output voltage is given by:
R
R
D
IN
L ) ǒVREF
LǓ
REF
V
X + 2 V
H * V
OUT
REF
65536
where DIN = decimal equivalent of the binary code
that is loaded to the DAC register; it can range from
0 to 65535.
RESISTOR STRING
VREFL
The resistor string section is shown in Figure 46. It is
simply a divide-by-2 resistor followed by a string of
resistors. The code loaded into the DAC register
determines at which node on the string the voltage is
tapped off. This voltage is then applied to the output
amplifier by closing one of the switches connecting
the string to the amplifier.
Figure 46. Resistor String
The write sequence begins by bringing the SYNC
line LOW. Data from the DIN line are clocked into the
24-bit shift register on each falling edge of SCLK.
The serial clock frequency can be as high as 50MHz,
making the DAC8555 compatible with high-speed
DSPs. On the 24th falling edge of the serial clock,
the last data bit is clocked into the shift register and
the shift register gets locked. Further clocking does
not change the shift register data. Once 24 bits are
locked into the shift register, the eight MSBs are
used as control bits and the 16 LSBs are used as
data. After receiving the 24th falling clock edge, the
DAC8555 decodes the eight control bits and 16 data
bits to perform the required function, without waiting
for a SYNC rising edge. A new SPI sequence starts
at the next falling edge of SYNC. A rising edge of
SYNC before the 24-bit sequence is complete resets
the SPI interface; no data transfer occurs.
OUTPUT AMPLIFIER
Each output buffer amplifier is capable of generating
rail-to-rail voltages on its output that approaches an
output range of 0V to AVDD (gain and offset errors
must be taken into account). Each buffer is capable
of driving a load of 2kΩ in parallel with 1000pF to
GND. The source and sink capabilities of the output
amplifier can be seen in the Typical Characteristics.
SERIAL INTERFACE
The DAC8555 uses a 3-wire serial interface (SYNC,
SCLK, and DIN), which is compatible with SPI,
QSPI™, and Microwire™ interface standards, as well
as most DSPs. See the Serial Write Operation timing
diagram for an example of a typical write sequence.
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After the 24th falling edge of SCLK is received, the
SYNC line may be kept LOW or brought HIGH. In
either case, the minimum delay time from the 24th
falling SCLK edge to the next falling SYNC edge
must be met in order to properly begin the next
cycle.
To assure the lowest power consumption of the
device, care should be taken that the levels are as
close to each rail as possible. (Refer to the Typical
Characteristics section for Figure 41, the Supply
Current vs Logic Input Voltage transfer characteristic
curve.)
ASYNCHRONOUS CLEAR
The DAC8555 output is asynchronously set to
zero-scale voltage or midscale voltage (depending
on RSTSEL) immediately after the RST pin is
brought low. The RST signal resets all internal
registers, and therefore, behaves like the Power-On
Reset. The RST pin must be brought back to high
before a write sequence is started.
If the RSTSEL pin is high, RST signal going low
resets all outputs to midscale. If the RSTSEL pin is
low, RST signal going low resets all outputs to
zero-scale. RSTSEL should be set at power up.
IOVDD AND VOLTAGE TRANSLATORS
INPUT SHIFT REGISTER
The IOVDD pin powers the the digital input structures
of the DAC8555. For single-supply operation, it can
be tied to AVDD. For dual-supply operation, the
IOVDD pin provides interface flexibility with various
CMOS logic families and should be connected to the
logic supply of the system. Analog circuits and
internal logic of the DAC8555 use AVDD as the
supply voltage. The external logic high inputs get
translated to AVDD by level shifters. These level
shifters use the IOVDD voltage as a reference to shift
the incoming logic HIGH levels to AVDD. IOVDD is
ensured to operate from 2.7V to 5.5V regardless of
the AVDD voltage, which ensures compatibility with
various logic families. Although specified down to
2.7V, IOVDD will operate at as low as 1.8V with
degraded timing and temperature performance. For
lowest power consumption, logic VIH levels should be
as close as possible to IOVDD, and logic VIL levels
should be as close as possible to GND voltages.
The input shift register (SR) of the DAC8555 is 24
bits wide, as shown in Figure 47, and is made up of
eight control bits (DB23–DB16) and 16 data bits
(DB15–DB0). DB23 and DB22 should always be '0'.
LD1 (DB21) and LD0 (DB20) control the updating of
each analog output with the specified 16-bit data
value or power-down command. Bit DB19 is a don't
care bit that does not affect the operation of the
DAC8555, and can be '1' or '0'. The DAC channel
select bits (DB18, DB17) control the destination of
the data (or power-down command) from DAC A
through DAC D. The final control bit, PD0 (DB16),
selects the power-down mode of the DAC8555
channels.
DB23
DB12
0
0
LD1
D9
LD0
D8
X
DAC Select 1
D6
DAC Select 0
D5
PD0
D4
D15
D3
D14
D2
D13
D1
D12
DB0
D0
DB11
D11
D10
D7
Figure 47. DAC8555 Data Input Register Format
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The DAC8555 also supports a number of different
load commands. The load commands can be
summarized as follows:
DB16 is a power-down flag. If this flag is set, then
DB15 and DB14 select one of the four power-down
modes of the device as described in Table 1. If DB16
= 1, DB15 and DB14 no longer represent the two
MSBs of data, but represent a power-down condition
described in Table 1. Similar to data, power-down
conditions can be stored at the temporary registers
of each DAC. It is possible to update DACs
simultaneously either with data, power-down, or a
combination of both.
DB21 = 0 and DB20 = 0: Single-channel store.
The temporary register (data buffer) corresponding to
a DAC selected by DB18 and DB17 is updated with
the contents of SR data (or power-down).
DB21 = 0 and DB20 = 1: Single-channel update.
The temporary register and DAC register
corresponding to a DAC selected by DB18 and DB17
are updated with the contents of SR data (or
power-down).
Refer to Table 2 for more information.
Table 1. DAC8555 Power-Down Modes
DB21 = 1 and DB20 = 0: Simultaneous update. A
channel selected by DB18 and DB17 gets updated
with the SR data, and simultaneously, all the other
channels get updated with previous stored data (or
power-down) from temporary registers.
PD0
PD1
PD2
(DB16) (DB15) (DB14)
OPERATING MODE
Output high impedance
1
1
1
1
0
0
1
1
0
1
0
1
Output typically 1kΩ to GND
Output typically 100kΩ to GND
Output high impedance
DB21 = 1 and DB20 = 1: Broadcast update. If
DB18 = 0, then SR data gets ignored, all channels
get updated with previously stored data (or
power-down). If DB18 = 1, then SR data (or
power-down) updates all channels.
Power-down/data selection is as follows:
Table 2. Control Matrix
DB23
0
DB22
0
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13-DB0
Don't
Care
LD 1
LD 0
DAC Sel 1
DAC Sel 0
PD0
MSB
MSB-1
MSB-2...LSB
DESCRIPTION
Write to buffer A with data
Write to buffer B with data
Write to buffer C with data
Write to buffer D with data
0
0
0
0
0
0
0
0
X
X
X
X
0
0
1
1
0
1
0
1
0
0
0
0
Data
Data
Data
Data
Write to buffer (selected by DB17 and DB18) with
power-down command
0
0
0
0
1
1
X
X
X
(00, 01, 10, or 11)
1
0
1
See Table 1
0
0
Write to buffer with data and load DAC (selected by
DB17 and DB18)
(00, 01, 10, or 11)
(00, 01, 10, or 11)
Data
Data
Write to buffer with power-down command and load
DAC (selected by DB17 and DB18)
See Table 1
See Table 1
Write to buffer with data (selected by DB17 and DB18)
and then load all DACs simultaneously from their
corresponding buffers.
1
1
0
0
X
X
(00, 01, 10, or 11)
0
1
Write to buffer with power-down command (selected by
DB17 and DB18) and then load all DACs
(00, 01, 10, or 11)
0
simultaneously from their corresponding buffers.
Broadcast Modes
0
Simultaneously update all channels of DAC8555 with
data stored in each channels temporary register.
X
X
X
X
X
X
1
1
1
1
1
1
X
X
X
X
X
0
1
X
1
1
X
X
Data
Write to all channels and load all DACs with SR data
Write to all channels and load all DACs with
power-down command in SR.
See Table 1
0
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SYNC INTERRUPT
POWER-ON RESET TO
ZERO-SCALE/MIDSCALE
In a normal write sequence, the SYNC line is kept
LOW for at least 24 falling edges of SCLK and the
addressed DAC register is updated on the 24th
falling edge. However, if SYNC is brought HIGH
before the 24th falling edge, it acts as an interrupt to
the write sequence; the shift register is reset and the
write sequence is discarded. Neither an update of
the data buffer contents, DAC register contents, nor
The DAC8555 contains a power-on reset circuit that
controls the output voltage during power-up.
Depending on RSTSEL signal, on power-up, the
DAC registers are reset and the output voltages are
set to zero-scale (RSTSEL
= 0) or midscale
(RSTSEL = 1); they remain that way until a valid
write sequence and load command are made to the
respective DAC channel. The power-on reset is
useful in applications where it is important to know
the state of the output of each DAC while the device
is in the process of powering up.
a
change in the operating mode occurs (see
Figure 48).
24th Falling Edge
24th Falling Edge
SCLK
SYNC
1
2
1
2
Invalid Write-Sync Interrupt:
SYNC HIGH Before 24th Falling Edge
Valid Write-Buffer/DAC Update:
SYNC HIGH After 24th Falling Edge
DIN
DB23 DB22
DB1 DB0
DB23 DB22
DB0
Figure 48. Interrupt and Valid SYNC Timing
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POWER-DOWN MODES
Individual channels can be separately powered
down, reducing the total power consumption. When
all channels are powered down, the DAC8555 power
consumption drops below 2µA. There is no power-up
command. When a channel is updated with data, it
automatically exits power-down. All channels exit
power-down simultaneously after a broadcast data
update. The time to exit power-down is
approximately 5µs. See Table 1 and Table 2 for
power-down operation details.
The DAC8555 uses four modes of operation. These
modes are accessed by setting three bits (PD2, PD1,
and PD0) in the shift register and performing a Load
action to the DACs. The DAC8555 offers a very
flexible power-down interface based on channel
register operation. A channel consists of a single
16-bit DAC with power-down circuitry, a temporary
storage register (TR), and a DAC register (DR). TR
and DR are both 18 bits wide. Two MSBs represent
a power-down condition and 16 LSBs represent data
for TR and DR. By adding bits 17 and 18 to TR and
DR, a power-down condition can be temporarily
stored and used as data. Internal circuits ensure that
DB15 and DB14 are transferred to TR17 and TR16
(DR17 and DR16), when DB16 = '1'.
Resistor
Amplifier
VOUTX
String
DAC
Power-Down
Circuitry
Resistor
Network
The DAC8555 treats the power-down condition as
data; all the operational modes are still valid for
power-down. It is possible to broadcast
a
power-down condition to all the DAC8555s in a
system, or it is possible to simultaneously
power-down a channel while updating data on other
channels.
Figure 49. Output Stage During Power-Down
(High-Impedance)
DB16, DB15, and DB14 = '100' (or '111') represent a
power-down condition with Hi-Z output impedance
for
a
selected channel. '101' represents
a
power-down condition with 1kΩ output impedance
and '110' represents a power-down condition with
100kΩ output impedance.
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OPERATION EXAMPLES
Example 1: Write to Data Buffer A Through Buffer D; Load DAC A Through DAC D Simultaneously
•
•
•
•
1st — Write to data buffer A:
DB23
0
DB22
0
LD1
0
LD0
0
DC
X
DAC Sel 1
0
DAC Sel 0
0
PD0
0
DB15
D15
—
—
DB1
D1
DB0
D0
2nd — Write to data buffer B:
DB23
0
DB22
0
LD1
0
LD0
0
DC
X
DAC Sel 1
0
DAC Sel 0
1
PD0
0
DB15
D15
—
—
DB1
D1
DB0
D0
3rd — Write to data buffer C:
DB23
0
DB22
0
LD1
0
LD0
0
DC
X
DAC Sel 1
1
DAC Sel 0
0
PD0
0
DB15
D15
—
—
DB1
D1
DB0
D0
4th — Write to data buffer D and simultaneously update all DACs:
DB23
0
DB22
0
LD1
1
LD0
0
DC
X
DAC Sel 1
1
DAC Sel 0
1
PD0
0
DB15
D15
—
—
DB1
D1
DB0
D0
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon
completion of the 4th write sequence. (The DAC voltages update simultaneously after the 24th SCLK falling
edge of the 4th write cycle).
Example 2: Load New Data to DAC A Through DAC D Sequentially
•
•
•
•
1st — Write to data buffer A and load DAC A: DAC A output settles to specified value upon completion:
DB23
0
DB22
0
LD1
0
LD0
1
DC
X
DAC Sel 1
0
DAC Sel 0
0
PD0
0
DB15
D15
—
—
DB1
D1
DB0
D0
2nd — Write to data buffer B and load DAC B: DAC B output settles to specified value upon completion:
DB23
0
DB22
0
LD1
0
LD0
1
DC
X
DAC Sel 1
0
DAC Sel 0
1
PD0
0
DB15
D15
—
—
DB1
D1
DB0
D0
3rd — Write to data buffer C and load DAC C: DAC C output settles to specified value upon completion:
DB23
0
DB22
0
LD1
0
LD0
1
DC
X
DAC Sel 1
1
DAC Sel 0
0
PD0
0
DB15
D15
—
—
DB1
D1
DB0
D0
4th — Write to data buffer D and load DAC D: DAC D output settles to specified value upon completion:
DB23
0
DB22
0
LD1
0
LD0
1
DC
X
DAC Sel 1
1
DAC Sel 0
1
PD0
0
DB15
D15
—
—
DB1
D1
DB0
D0
After completion of each write cycle, DAC analog output settles to the voltage specified.
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Example 3: Power Down DAC A and DAC B to 1kΩ and Power Down DAC C and DAC D to 100kΩ
Simultaneously
•
•
•
•
Write power-down command to data buffer A: DAC A to 1kΩ.
DB23
0
DB22
0
LD1
0
LD0
0
DC
X
DAC Sel 1
0
DAC Sel 0
0
PD0
1
DB15
0
DB14
1
DB13
X
—
—
Write power-down command to data buffer B: DAC B to 1kΩ.
DB23
0
DB22
0
LD1
0
LD0
0
DC
X
DAC Sel 1
0
DAC Sel 0
1
PD0
1
DB15
0
DB14
1
DB13
X
—
—
Write power-down command to data buffer C: DAC C to 1kΩ.
DB23
0
DB22
0
LD1
0
LD0
0
DC
X
DAC Sel 1
1
DAC Sel 0
0
PD0
1
DB15
1
DB14
0
DB13
X
—
—
Write power-down command to data buffer D: DAC D to 100kΩ and simultaneously update all DACs.
DB23
0
DB22
0
LD1
1
LD0
0
DC
X
DAC Sel 1
1
DAC Sel 0
1
PD0
1
DB15
1
DB14
0
DB13
X
—
—
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously power down to each respective
specified mode upon completion of the 4th write sequence.
Example 4: Power Down DAC A Through DAC D to High-Impedance Sequentially:
•
•
•
•
Write power-down command to data buffer A and load DAC A: DAC A output = Hi-Z:
DB23
0
DB22
0
LD1
0
LD0
1
DC
X
DAC Sel 1
0
DAC Sel 0
0
PD0
1
DB15
1
DB14
1
DB13
X
—
—
Write power-down command to data buffer B and load DAC B: DAC B output = Hi-Z:
DB23
0
DB22
0
LD1
0
LD0
1
DC
X
DAC Sel 1
0
DAC Sel 0
1
PD0
1
DB15
1
DB14
1
DB13
x
—
—
Write power-down command to data buffer C and load DAC C: DAC C output = Hi-Z:
DB23
0
DB22
0
LD1
0
LD0
1
DC
X
DAC Sel 1
1
DAC Sel 0
0
PD0
1
DB15
1
DB14
1
DB13
X
—
—
Write power-down command to data buffer D and load DAC D: DAC D output = Hi-Z:
DB23
0
DB22
0
LD1
0
LD0
1
DC
X
DAC Sel 1
1
DAC Sel 0
1
PD0
1
DB15
1
DB14
1
DB13
X
—
—
The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power down to high-impedance upon
completion of the 1st, 2nd, 3rd, and 4th write sequences, respectively.
20
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SLAS475B–NOVEMBER 2005–REVISED OCTOBER 2006
LDAC FUNCTIONALITY
channels must be loaded with desired data before
LDAC is triggered. After
a low-to-high LDAC
The DAC8555 offers both a software and hardware
simultaneous update function. The DAC8555
double-buffered architecture has been designed so
that new data can be entered for each DAC without
disturbing the analog outputs. The software
simultaneous update capability is controlled by the
load 1 (LD1) and load 0 (LD0) control bits. By setting
load 1 = 1 all of the DAC registers will be updated on
the falling edge of the 24th clock signal. When the
new data has been entered into the device, all of the
DAC outputs can be updated simultaneously and
synchronously with the clock.
transition, all DACs are simultaneously updated with
the contents of the corresponding data buffers. If the
contents of a data buffer are not changed by the
serial interface, the corresponding DAC output will
remain unchanged after the LDAC trigger.
ENABLE PIN
For normal operation, the enable pin must be tied to
a logic low. If the enable pin is tied high, the
DAC8555 stops listening to the serial port. This
feature can be useful for applications that share the
same serial port.
DAC8555 data updates are synchronized with the
falling edge of the 24th SCLK cycle, which follows a
falling edge of SYNC. For such synchronous
updates, the LDAC pin is not required and it must be
connected to GND permanently. The LDAC pin is
used as a positive edge triggered timing signal for
asynchronous DAC updates. Data buffers of all
21
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SLAS475B–NOVEMBER 2005–REVISED OCTOBER 2006
DAC8555 to 68HC11 Interface
MICROPROCESSOR INTERFACING
Figure 52 shows a serial interface between the
DAC8555 and the 68HC11 microcontroller. SCK of
the 68HC11 drives the SCLK of the DAC8555, while
the MOSI output drives the serial data line of the
DAC. The SYNC signal is derived from a port line
(PC7), similar to the 8051 diagram.
DAC8555 to 8051 Interface
See Figure 50 for a serial interface between the
DAC8555 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8555, while RXD
drives the serial data line of the device. The SYNC
signal is derived from a bit-programmable pin on the
port of the 8051. In this case, port line P3.3 is used.
When data are to be transmitted to the DAC8555,
P3.3 is taken LOW. The 8051 transmits data in 8-bit
bytes; thus, only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is
left LOW after the first eight bits are transmitted, then
a second and third write cycle are initiated to
transmit the remaining data. P3.3 is taken HIGH
following the completion of the third write cycle. The
8051 outputs the serial data in a format that presents
the LSB first, while the DAC8555 requires data with
the MSB as the first bit received. The 8051 transmit
routine must therefore take this into account, and
mirror the data as needed.
68HC11(1)
DAC8555
PC7
SCK
SYNC
SCLK
DIN
MOSI
(1) Additional pins omitted for clarity.
Figure 52. DAC8555 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCLK. When data are
being transmitted to the DAC, the SYNC line is held
LOW (PC7). Serial data from the 68HC11 are
transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. (Data are
transmitted MSB first.) In order to load data to the
DAC8555, PC7 is left LOW after the first eight bits
are transferred, then a second and third serial write
operation are performed to the DAC. PC7 is taken
HIGH at the end of this procedure.
80C51/80L51(1)
DAC8555
P3.3
TXD
RXD
SYNC
SCLK
DIN
(1) Additional pins omitted for clarity.
Figure 50. DAC8555 to 80C51/80L51 Interface
DAC8555 to Microwire Interface
DAC8555 to TMS320 DSP Interface
Figure 53 shows the connections between the
DAC8555 and a TMS320 Digital Signal Processor
(DSP).
A single DSP can control up to four
Figure 51 shows an interface between the DAC8555
and any Microwire-compatible device. Serial data are
shifted out on the falling edge of the serial clock and
is clocked into the DAC8555 on the rising edge of
the SK signal.
DAC8555s without any interface logic.
DAC8555
Positive Supply
AVDD
0.1mF
10mF
TMS320 DSP
MicrowireTM
DAC8555
SYNC
SCLK
DIN
CS
FSX
DX
SYNC
DIN
Output A
Output D
VOUT
VOUT
VREF
A
SK
SO
D
H
SCLK
CLKX
Reference
Input
(1) Additional pins omitted for clarity.
0.1mF
1mF to 10mF
VREFL
Microwire is a registered trademark of National Semiconductor.
GND
Figure 51. DAC8555 to Microwire Interface
Figure 53. DAC8555 to TMS320 DSP
22
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SLAS475B–NOVEMBER 2005–REVISED OCTOBER 2006
APPLICATION INFORMATION
In addition, the DAC8555 can achieve typical AC
performance of 95dB signal-to-noise ratio (SNR) and
–85dB total harmonic distortion (THD), making the
DAC8555 a solid choice for applications requiring
high SNR at output frequencies at or below 10kHz.
CURRENT CONSUMPTION
The DAC8555 typically consumes 208µA at AVDD
=
5V and 180µA at AVDD = 3V for each active channel,
including reference current consumption. Additional
current consumption can occur at the digital inputs if
VIH << IOVDD. For most efficient power operation,
CMOS logic levels are recommended at the digital
inputs to the DAC.
OUTPUT VOLTAGE STABILITY
The DAC8555 exhibits excellent temperature stability
of 5ppm/°C typical output voltage drift over the
specified temperature range of the device. This
stability enables the output voltage of each channel
to stay within a ±25µV window for a ±1°C ambient
temperature change.
In power-down mode, typical current consumption is
175nA per channel. A delay time of 10ms to 20ms
after a power-down command is issued to the DAC
is typically sufficient for the power-down current to
drop below 10µA.
Good
power-supply
rejection
ratio
(PSRR)
performance reduces supply noise present on AVDD
from appearing at the outputs to well below 10µV-s.
Combined with good dc noise performance and true
16-bit differential linearity, the DAC8555 becomes a
perfect choice for closed-loop control applications.
DRIVING RESISTIVE AND CAPACITIVE
LOADS
The DAC8555 output stage is capable of driving
loads of up to 1000pF while remaining stable. Within
the offset and gain error margins, the DAC8555 can
operate rail-to-rail when driving a capacitive load.
Resistive loads of 2kΩ can be driven by the
DAC8555 while achieving good load regulation.
When the outputs of the DAC are driven to the
positive rail under resistive loading, the PMOS
transistor of each Class-AB output stage can enter
into the linear region. When this scenario occurs, the
added IR voltage drop deteriorates the linearity
performance of the DAC. This deterioration only
occurs within approximately the top 100mV of the
DAC output voltage characteristic. Under resistive
loading conditions, good linearity is preserved as
long as the output voltage is at least 100mV below
the AVDD voltage.
SETTLING TIME AND OUTPUT GLITCH
PERFORMANCE
The DAC8555 settles to ±0.003% of its full-scale
range within 10µs, driving a 200pF 2kΩ load. For
good settling performance, the outputs should not
approach the top and bottom rails. Small signal
settling time is under 1µs, enabling data update rates
exceeding 1MSPS for small code changes.
Many applications are sensitive to undesired
transient signals such as glitch. The DAC8555 has a
proprietary, ultra-low glitch architecture addressing
such applications. Code-to-code glitches rarely
exceed 1mV and they last under 0.3µs. Typical glitch
energy is an outstanding 0.15nV-s. Theoretical
worst-case glitch should occur during a 256LSB step,
but it is so low, it cannot be detected.
CROSSTALK AND AC PERFORMANCE
The DAC8555 architecture uses separate resistor
strings for each DAC channel in order to achieve
ultra-low crosstalk performance. DC crosstalk seen
at one channel during a full-scale change on the
neighboring channel is typically less than 0.5LSBs.
The AC crosstalk measured (for a full-scale, 1kHz
sine wave output generated at one channel, and
measured at the remaining output channel) is
typically under –100dB.
DIFFERENTIAL AND INTEGRAL
NONLINEARITY
The DAC8555 uses precision thin film resistors to
achieve monotonicity and good linearity. Typical
linearity error is ±4LSBs, with a ±0.3mV error for a
5V range. Differential linearity is typically ±0.25LSBs,
with a ±19µV error for a consecutive code change.
23
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SLAS475B–NOVEMBER 2005–REVISED OCTOBER 2006
USING THE REF02 AS A POWER SUPPLY
FOR THE DAC8555
BIPOLAR OPERATION USING THE DAC8555
The DAC8555 has been designed for single-supply
operation, but a bipolar output range is also possible
using the circuit in Figure 55. The circuit shown will
give an output voltage range of ±VREF. Rail-to-rail
operation at the amplifier output is achievable using
an amplifier such as the OPA703, as shown in
Figure 55.
Due to the extremely low supply current required by
the DAC8555, a possible configuration is to use a
REF02 +5V precision voltage reference to supply the
required voltage to the DAC8555 supply input as well
as the reference input, as shown in Figure 54. This is
especially useful if the power supply is quite noisy or
if the system supply voltages are at some value
other than 5V. The REF02 will output a steady
supply voltage for the DAC8555. If the REF02 is
used, the current it needs to supply to the DAC8555
is 0.85mA typical for AVDD = 5V. When a DAC output
is loaded, the REF02 also needs to supply the
current to the load. The total typical current required
(with a 5kΩ load on a given DAC output) is:
The output voltage for any input code can be
calculated as follows:
R1 ) R2
ǒ Ǔ
R1
R2
ǒ Ǔ
R1
D
65536
ǒ Ǔ
VOUTX +
ƪ
VREF
* VREF
ƫ
where D represents the input code in decimal
(0–65535).
With VREF = 5V, R1 = R2 = 10kΩ.
10 D
0.85mA + (5V/5kΩ) = 1.85mA
X + ǒ Ǔ*5V
VOUT
65536
+15V
Using this example, an output voltage range of ±5V
with 0000h corresponding to a –5V output and
+5V
FFFFh corresponding to
a 5V output can be
REF02
achieved. Similarly, using VREF = 2.5V, a ±2.5V
output voltage range can be achieved.
AIDD + IREF
R2
10kW
+5V
AVDD, VREF
SYNC
Three-Wire
VOUT = 0V to 5V
+6V
Serial
SCLK
DIN
DAC8555
R1
10kW
Interface
±5V
OPA703
AVDD, VREF
DAC8555
VOUTX
10mF
0.1mF
-6V
Figure 54. REF02 as a Power Supply to the
DAC8555
(Other pins omitted for clarity.)
Figure 55. Bipolar Operation With the DAC8555
24
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SLAS475B–NOVEMBER 2005–REVISED OCTOBER 2006
LAYOUT
As with the GND connection, AVDD should be
connected to a positive power-supply plane or trace
that is separate from the connection for digital logic
until they are connected at the power-entry point. In
addition, a 1µF to 10µF capacitor in parallel with a
0.1µF bypass capacitor is strongly recommended. In
some situations, additional bypassing may be
required, such as a 100µF electrolytic capacitor or
A
precision analog component requires careful
layout, adequate bypassing, and clean,
well-regulated power supplies.
The DAC8555 offers single-supply operation, and it
will often be used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal
processors. The more digital logic present in the
design and the higher the switching speed, the more
difficult it is to keep digital noise from appearing at
the output.
even
a Pi filter made up of inductors and
capacitors—all designed to essentially low-pass filter
the supply, removing the high-frequency noise.
Up to four DAC8555 devices can be used on a single
SPI bus without any glue logic to create a high
channel count solution. Special attention is required
to avoid digital signal integrity problems when using
multiple DAC8555s on the same SPI bus. Signal
integrity of SYNC, SCLK, and DIN lines will not be an
issue as long as the rise times of these digital signals
are longer than six times the propagation delay
between any two DAC8555 devices. Propagation
speed is approximately six inches/ns on standard
printed circuit boards (PCBs). Therefore, if the digital
signal rise time is 1ns, the distance between any two
DAC8555s has to be further apart on the PCB, and
the signal rise times should be reduced by placing
series resistors at the drivers for SYNC, SCLK, and
DIN lines. If the largest distance between any two
DAC8555s must be six inches, the rise time should
be reduced to 6ns with an RC network formed by the
series resistor at the digital driver and the total trace
and input capacitance on the PCB.
Due to the single ground pin of the DAC8555, all
return currents, including digital and analog return
currents for the DAC, must flow through a single
point. Ideally, GND would be connected directly to an
analog ground plane. This plane would be separate
from the ground connection for the digital
components until they were connected at the
power-entry point of the system.
The power applied to AVDD should be well-regulated
and low-noise. Switching power supplies and DC/DC
converters often have high-frequency glitches or
spikes riding on the output voltage. In addition, digital
components can create similar high-frequency
spikes. This noise can easily couple into the DAC
output voltage through various paths between the
power connections and analog output.
25
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC8555IPW
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
16
16
90
90
RoHS & Green
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 105
-40 to 105
D8555
D8555
DAC8555IPWG4
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DAC8555IPW
PW
PW
TSSOP
TSSOP
16
16
90
90
530
530
10.2
10.2
3600
3600
3.5
3.5
DAC8555IPWG4
Pack Materials-Page 1
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2022, Texas Instruments Incorporated
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