DAC8541_技术文档

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SLAS353 − DECEMBER 2001

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FEATURES

DESCRIPTION

D

Micropower Operation: 250 µA at 5 V AV

Power-On Reset to Min-Scale

16-Bit Monotonic

DD

The DAC8541 is a low-power, single channel, 16-bit,

voltage output DAC. Its on-chip precision output

amplifier allows rail-to-rail voltage swing to be achieved

at the output. The DAC8541 utilizes a 16-bit parallel

interface and features additional powerdown function

pins as well as hardware-enabled, asynchronous DAC

updating and reset capability.

Settling Time: 10 µs to 0.003% FSR

16-Bit Parallel Interface

On-Chip Output Buffer Amplifier With

Rail-to-Rail Operation

The DAC8541 requires an external reference voltage to

set the output range of the DAC. The device

incorporates a power-on-reset circuit that ensures that

the DAC output powers up at min-scale and remains

there until a valid write takes place to the device. In

addition, the DAC8541 contains a power-down feature,

accessed via two hardware pins, that when enabled

reduces the current consumption of the device to

200 nA at 5 V.

Hardware Reset to Min-Scale or Mid-Scale

Double-Buffered Architecture

Asynchronous LDAC Control

Data Readback Support

1.8 V Compatible Digital Interface:

− DV

= 1.8 V−5.5 V

DD

D

Wide Analog Supply Range:

− AV = 2.7 V−5.5 V

DD

The low power consumption of this device in normal

operation makes it ideally suited for use in portable

battery operated equipment applications. The power

32-Lead 5 mm × 5 mm TQFP Package

APPLICATIONS

consumption is 1.2 mW at AV = 5 V reducing to 1 µW

DD

in power-down mode.

D

Process Control

The DAC8541 is available in a 32-lead TQFP package

with an operating temperature range of −40°C to 85°C.

Data Acquisition Systems

Closed-Loop Servo Control

PC Peripherals

Portable Instrumentation

AV

DD

DV

V H

REF

DD

DAC8541

V

Sense

OUT

I/O

Input

Register

DAC

Register

DAC

Data I/O

CS

R/W

BTC/USB

Buffer

16

Power

Down

Control

Logic

Control

Logic

Resistor

Network

AGND DGND

RSTSEL RST LDAC

PD0 PD1

V L

REF

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2001, Texas Instruments Incorporated

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1

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ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ

SLAS353 − DECEMBER 2001

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

AVAILABLE OPTIONS

PACKAGE

DRAWING NUMBER

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA

PRODUCT

PACKAGE

T

A

DAC8541Y/250

DAC8541Y/2K

DAC8541

32-TQFP

PBS

−40°C to 85°C

E41Y

Tape and Reel

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

AV

DV

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V

DD

Digital input voltage to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DV

+ 0.3 V

DD

V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AV

OUT

Operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

Junction temperature, T max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

J

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

electrical characteristics, DV

pF to AGND; all specifications –40°C to 85°C (unless otherwise noted)

= 1.8 V to 5.5 V; AV

= 2.7 V to 5.5 V; R = 2 kΩ to AGND; C = 200

DD

DD L L

PARAMETER

STATIC PERFORMANCE (see Note 1)

Resolution

TEST CONDITIONS

MIN

TYP

MAX

UNIT

16

Bits

Relative accuracy

0.098 %FSR

Differential nonlinearity

Zero code error

16-Bit monotonic

1

LSB

mV

All zeroes loaded to DAC register

All ones loaded to DAC register

5

20

Full-scale error

–0.15

–0.8 %FSR

0.8 %FSR

µV/°C

Gain error

Zero code error drift

20

5

ppm of

FSR/°C

Gain temperature coefficient

OUTPUT CHARACTERISTICS (see Note 2)

Output voltage range

2×V L

REF

V H

REF

10

V

µs

R

= 2 kΩ; 0 pF < C < 200 pF

8

12

L

Output voltage settling time (full scale)

Slew rate

R

= 2 kΩ; C = 500 pF

L

1

V/µs

pF

R

= ∞

470

1000

20

L

Capacitive load stability

= 2 kΩ

Digital-to-analog glitch impulse

Digital feedthrough

1 LSB change around major carry (see Note 3)

nV−s

Ω

0.5

1

DC output impedance

AV

= 5 V

= 3 V

50

DD

Short circuit current

Power-up time

mA

20

Coming out of power-down mode, AV

= 5 V

= 3 V

2.5

5

DD

µs

DD

NOTES: 1. Linearity calculated using a reduced code range of 485 to 64714. Output unloaded.

2. Assured by design and characterization, not production tested.

3. Specification for code changes at each N x 4096 code boundary.

2

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SLAS353 − DECEMBER 2001

electrical characteristics, DV

= 1.8 V to 5.5 V; AV

= 2.7 V to 5.5 V; R = 2 kΩ to AGND;

DD

DD L

C = 200 pF to AGND; all specifications –40°C to 85°C (unless otherwise noted) (continued)

L

PARAMETER

REFERENCE INPUT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

AV

= V

H = 5 V,

V

L = AGND

50

35

75

60

DD

REF

Reference current

µA

H = 3.6 V,

REF

V

L = AGND

REF

DD

V

H input range

L input range

V

H>V

L

0

AV

V

REF

DD

−100 AGND

100

mV

kΩ

REF

Reference input impedance

LOGIC INPUTS (see Note 2)

Input current

1

µA

V

L, input low voltage

H, input high voltage

DV

= 1.8 V to 5.5 V

0.3×DV

IN

DD

0.7×DV

V

IN

DD

1.8

2.7

Pin input capacitance

3

pF

POWER REQUIREMENTS

DV

5.5

1.0

5.5

V

µA

V

DD

DAC active and excluding load current,

= DV and V = DGND

DI

0.2

DD

V

IH

DD IL

AV

DD

AI

(normal operation)

DD

DAC active and excluding load current,

AV

= 3.6 V to 5.5 V

= 2.7 V to 3.6 V

250

240

400

390

DD

V

IH

= DV

and V = DGND

DD

IL

µA

AV

AI

(all power-down modes)

AV

= 3.6 V to 5.5 V

= 2.7 V to 3.6 V

0.2

1

DD

V

IH

= DV

and V = DGND

IL

DD

0.05

DD

POWER EFFICIENCY

/AI

I

= 2 mA, AV

DD

= +5 V

89%

OUT DD

(LOAD)

NOTE 2; Assured by design and characterization, not production tested.

3

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SLAS353 − DECEMBER 2001

PBS PACKAGE

(TOP VIEW)

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

DB15

DB14

DB13

DB12

DB11

DB10

DB9

V

OUT

Sense

AGND

V

L

DAC8541

REF

H

AV

DD

DV

DD

DB8

DGND

9 10 11 12 13 14 15 16

Terminal Functions

TERMINAL

I/O

I/O Data input/output, (pin 1-MSB: pin 16-LSB)

DESCRIPTION

NAME

DB15−DB0

DGND

NO.

1−16

17

I

Digital ground

DV

18

Digital supply input, 1.8 V to 5.5 V

Analog power supply input, 2.7 V to 5.5 V

DD

AV

19

DD

V

REF

H

20

Positive reference voltage input (referenced to AGND)

V

REF

L

21

Negative reference voltage input (referenced to AGND), nominally V

L = AGND

REF

AGND

22

23

24

25

26

27

28

I

Analog ground

V

Sense

Analog output sense. The feedback terminal of the output amplifier.

OUT

O

I

Analog output voltage from DAC. The output amplifier has rail-to-rail operation.

Powerdown control bit 0

OUT

PD0

PD1

I

Powerdown control bit 1

BTC/USB

RSTSEL

I

Data input format: binary twos complement or unipolar straight binary

I

Reset V

on active RST to min-scale (RSTSEL = 0) or mid-scale (RSTSEL = 1)

reset to min-scale or mid-scale, rising edge (Does not reset input register data.)

OUT

RST

LDAC

R/W

CS

29

30

31

32

I

V

OUT

Asynchronous load command, rising edge

Read/Write control input

Chip select, active low

4

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SLAS353 − DECEMBER 2001

timing characteristics, DV

= 1.8 V to 5.5 V; AV

= 2.7 V to 5.5 V; R = 2 kΩ to AGND;

DD

DD L

C = 200 pF to AGND; all specifications –40°C to 85°C (unless otherwise noted)

L

MIN

TYP

MAX

UNIT

ns

µs

t

Pulse width: CS low for valid write

Setup time: R/W low before CS falling (see Note 4)

Setup time: data in valid before CS falling

Hold time: R/W low after CS rising (see Note 4)

Hold time: data in valid after CS rising

Pulse width: CS low for valid read

Setup time: R/W high before CS falling

Delay time: data out valid after CS falling

Hold time: R/W high after CS rising

Hold time: data out valid after CS rising

Setup time: LDAC rising after CS falling (see Note 4)

Delay time: CS low after LDAC rising

Pulse width: LDAC low

20

0

w1

su1

su2

h1

0

10

15

40

30

h2

w2

su3

d1

60

80

20

10

5

h3

h4

10

50

40

80

0

su4

d2

w3

w4

w5

su5

h5

Pulse width: LDAC high

Pulse width: CS high (see Note 4)

Setup time: RSTSEL valid before RST rising

Hold time: RSTSEL valid after RST rising

Pulse width: RST low

20

40

w6

w7

S

Pulse width: RST high

V

OUT

Settling time (settling time for a full scale code change)

10

NOTE 4: Simplified operation: CS and W/R can be tied low if the DAC8541 is the only device on the bus and Read operation is not needed. In

this case, LDAC is still required to update the output of the DAC and t is from Data In Valid to LDAC Rising.

su(4)

t

w2

w1

w5

CS

t

su1

su2

h1

su3

h3

h4

R/W

t

h2

t

d1

Data I/O

DB0−DB15

Data In Valid

t

Data Out Valid

t

su4

d2

LDAC

t

w4

w3

V

OUT

0.003% of FSR Error Bands

t

s

Figure 1. Data Read/Write Timing

5

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SLAS353 − DECEMBER 2001

t

su5

RSTSEL

t

h5

t

w6

RST

t

w7

t

s

+FS

V

(RSTSEL = Low)

OUT

Min-Scale

−FS

+FS

Mid-Scale

(RSTSEL = High)

−FS

OUT

Figure 2. Reset Timing

TYPICAL CHARACTERISTICS

This condition applies to all typical characteristics: V

otherwise noted)

H = AV , V

L = AGND, T = 25°C (unless

REF

DD REF A

LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR

vs

DIGITAL INPUT CODE

64

48

32

16

AV

DD

= 2.7 V, T = 85°C

A

0

−16

−32

−48

−64

2

1.5

1

0.5

0

−0.5

−1

−1.5

−2

0

8192

16384

24576

32768

40960

49152

57344

65535

Digital Input Code

Figure 3

6

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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ

SLAS353 − DECEMBER 2001

TYPICAL CHARACTERISTICS

LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR

vs

DIGITAL INPUT CODE

64

48

32

AV

DD

= 2.7 V, T = 25°C

A

16

0

−16

−32

−48

−64

2

1.5

1

0.5

0

−0.5

−1

−1.5

−2

0

8192

16384

24576

32768

40960

49152

57344

65535

Digital Input Code

Figure 4

7

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TYPICAL CHARACTERISTICS

LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR

vs

DIGITAL INPUT CODE

64

48

32

16

AV

DD

= 2.7 V, T = −40°C

A

0

−16

−32

−48

−64

2

1.5

1

0.5

0

−0.5

−1

−1.5

−2

0

8192

16384

24576

32768

40960

49152

57344

65535

Digital Input Code

Figure 5

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SLAS353 − DECEMBER 2001

TYPICAL CHARACTERISTICS

FULL-SCALE ERROR

ZERO-SCALE ERROR

vs

FREE-AIR TEMPERATURE

vs

FREE-AIR TEMPERATURE

20

15

20

15

10

5

To Avoid Clipping of The Output Signal

AV

= V

REF

= 5 V

DD

During The Test, V

REF

= AV

−10mV

DD

10

5

AV = 2.7 V

DD

AV

= V

REF

= 2.7 V

DD

0

−5

AV

= 5 V

DD

0

−5

−10

−15

−20

−15

−20

−40

−15

10

35

60

85

−40

−15

10

35

60

85

T

A

− Free-Air Temperature − °C

T

A

− Free-Air Temperature − °C

Figure 6

Figure 7

OUTPUT VOLTAGE

vs

OUTPUT VOLTAGE

vs

DRIVE CURRENT CAPABILITY

3

AV

= V = 2.7 V

REF

DD

5

2.5

DAC Loaded With FFFFh

4

3

2

1

0

2

1.5

AV

= V = 5 V

REF

DD

1

0.5

0

DAC Loaded With 0000h

5

DAC Loaded With 0000h

0

5

10

15

10

15

0

I

− Drive Current Capability − mA

I

(SOURCE/SINK)

− Drive Current Capability − mA

(SOURCE/SINK)

Figure 8

Figure 9

ANALOG SUPPLY CURRENT

vs

ANALOG SUPPLY VOLTAGE

AI

DD

HISTOGRAM

2500

2000

1500

1000

300

280

260

240

220

200

AV

T

A

= 5 V

DD

= 25°C

500

0

100

150

200

AI

250

− µA

300

350

400

2.7

3.1

AV

3.5

3.9

4.3

4.7

5.1 5.5

DD

− Analog Supply Voltage − V

DD

Figure 10

Figure 11

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SLAS353 − DECEMBER 2001

TYPICAL CHARACTERISTICS

ANALOG SUPPLY CURRENT

vs

DIGITAL INPUT CODE

AI

HISTOGRAM

DD

400

2500

2000

1500

1000

AV

T

A

= 2.7 V

= 25°C

Excluding Reference and Load Current.

DD

350

300

250

AV

= DV = 5 V

DD

200

150

AV

= DV = 2.7 V

DD

100

50

500

0

16384

32768

49152

65535

100

150

200

AI

250

− µA

300

350

400

Digital Input Code

DD

Figure 12

Figure 13

ANALOG SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

POWER-DOWN CURRENT

vs

SUPPLY VOLTAGE

350

50

45

40

35

30

Excluding Reference and Load Current.

300

250

AV

= DV

= 5 V

DD

T

A

= 85°C

T

= −40°C

= 25°C

A

200

150

100

50

AV

= DV = 2.7 V

DD

25

20

15

T

A

10

5

0

2.7

0

−40

−15

10

35

60

85

3.4

4.1

4.8

5.5

T

A

− Free-Air Temperature − °C

AV

− Supply Voltage − V

DD

Figure 14

Figure 15

DIGITAL SUPPLY CURRENT

vs

LOGIC INPUT VOLTAGE

POWER-ON RESET TO 0 V

500

400

300

200

DI

Values are Shown for Logic

Loaded With 2 kΩ to AGND

DD

Level Change on one Digital Input.

AV

(2 V/div)

DD

DV

= 5 V

DD

V

(1 V/div)

OUT

100

0

DV

= 2.7 V

DD

0

1

2

3

4

5

0

100 200 300400 500 600 700 800 9001000

V

− Logic Input Voltage − V

LOGIC

t − Time − µs

Figure 16

Figure 17

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TYPICAL CHARACTERISTICS

EXITING POWER-DOWN

MAJOR CARRY CODE CHANGE GLITCH

AV = V

DD REF

= 2.7 V

Digital Code = 8000h

Scope Trigger (5 V/div)

V

(2 V/div)

OUT

AV = DV = V

DD DD REF

= 2.7 V

Code 8000 to 7FFF

H

Glitch Occurs Every N × 4096 Code

Boundary.

0

2

4

6

8

10 12 14 16 18 20

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

t − Time − µs

Figure 18

Figure 19

FULL-SCALE SETTLING TIME

MAJOR CARRY CODE CHANGE GLITCH

AV = 2.7 V

DD

Large-Signal Output (1 V/div)

Small-Signal Error (1 mV/div)

Full-Scale Code Change:

0000 to FFFF

H

Output Loaded With

2 kΩ and 200 pF to AGND

AV = DV = V

DD DD REF

= 5 V

Code 8000 to 7FFF

H

Glitch Occurs Every N × 4096 Code

Boundary.

Scope Trigger (5 V/div)

0

2

4

6

8

10 12 14 16 18 20

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

t − Time − µs

Figure 20

Figure 21

FULL-SCALE SETTLING TIME

HALF-SCALE SETTLING TIME

AV = 2.7 V

DD

AV = 2.7 V

DD

Large-Signal Output (1 V/div)

Full-Scale Code Change:

Half-Scale Code Change:

4000 to C000

H

Output Loaded With

FFFF to 0000

H

2 kΩ and 200 pF to AGND

Output Loaded With

2 kΩ and 200 pF to AGND

Large-Signal Output (1 V/div)

Small-Signal Error (1 mV/div)

Scope Trigger (5 V/div)

0

2

4

6

8

10 12 14 16 18 20

0

2

4

6

8

10 12 14 16 18 20

t − Time − µs

Figure 22

Figure 23

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TYPICAL CHARACTERISTICS

FULL-SCALE SETTLING TIME

HALF-SCALE SETTLING TIME

AV = 5 V

DD

AV = 2.7 V

DD

Large-Signal Output (2 V/div)

Half-Scale Code Change:

C000 to 4000

H

Output Loaded With

2 kΩ and 200 pF to AGND

Small-Signal Error (1 mV/div)

Large-Signal Output (1 V/div)

Small-Signal Error (1 mV/div)

Full-Scale Code Change:

0000 to FFFF

H

Output Loaded With

2 kΩ and 200 pF to AGND

Scope Trigger (5 V/div)

0

2

4

6

8

10 12 14 16 18 20

0

2

4

6

8

10 12 14 16 18 20

t − Time − µs

Figure 24

Figure 25

FULL-SCALE SETTLING TIME

HALF-SCALE SETTLING TIME

AV = 5 V

DD

AV = 5 V

DD

Large-Signal Output (2 V/div)

Half-Scale Code Change:

Full-Scale Code Change:

FFFF to 0000

4000 to C000

H

Output Loaded With

H

Output Loaded With

2 kΩ and 200 pF to AGND

Large-Signal Output (1 V/div)

Small-Signal Error (1 mV/div)

Scope Trigger (5 V/div)

0

2

4

6

8

10 12 14 16 18 20

0

2

4

6

8

10 12 14 16 18 20

t − Time − µs

Figure 26

Figure 27

HALF-SCALE SETTLING TIME

AV = 5 V

DD

Half-Scale Code Change:

C000 to 4000

H

Output Loaded With

2 kΩ and 200 pF to AGND

Small-Signal Error (1 mV/div)

Large-Signal Output (1 V/div)

Scope Trigger (5 V/div)

0

2

4

6

8

10 12 14 16 18 20

t − Time − µs

Figure 28

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THEORY OF OPERATION

D/A section

The architecture of the DAC8541 consists of a string DAC followed by an output buffer amplifier. Figure 29

shows a generalized block diagram of the DAC architecture.

V H = External Reference Voltage

REF

V

Sense

OUT

REF+

Resistor

String

−

OUT

+

DAC Register

REF−

V L = AGND

REF

Figure 29. Generalized DAC Architecture

The input coding to the DAC8541 is set by the BTC/USB input to the device. When this input is high, the input

code is binary 2s complement. If the input is low, the format is unipolar straight binary, in which case the ideal

output voltage is given by:

D

65536

V

+ V

H

OUT

REF

Where D = the decimal equivalent of the binary code that is loaded to the DAC register, which can range from

0 to 65535 and V L = AGND.

REF

V H

REF

R

DIVIDE

V H

REF

2

R

To Output Amplifier

(2x Gain)

R

V

REF

L

Figure 30. Typical Resistor String

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THEORY OF OPERATION

resistor string

The resistor string section is shown in Figure 30. It is simply a string of resistors, each of which has a value of

R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off. This

voltage is then presented to the output amplifier by closing one of the switches connecting the string to the

amplifier. The negative tap of the resistor string, V

in order to make minor adjustments to the offset seen at the V

voltage reference inputs section.)

L, can be tied to AGND or a small voltage can be applied

REF

pin. (This is discussed in more detail in the

OUT

output amplifier

The output buffer amplifier is capable of generating near rail-to-rail voltages on its output, which gives an output

range of 0 V to AV (offset and gain errors affect the absolute V range). It is also capable of driving a load

DD

OUT

of 2 kΩ in parallel with 1000 pF to AGND while remaining stable. The source and sink capabilities of the output

amplifier can be seen in the typical curves. The slew rate of the DAC8541 is typically 1 V/µs with a typical

full-scale settling time of 8 µs.

For additional functionality, the inverting input of the output amplifier is brought out via the V

Sense pin. This

OUT

allows for better accuracy in critical applications by tying the V

Sense and V

together directly at the load.

OUT

Other signal conditioning circuitry may also be connected between these points for specific applications.

parallel interface

The DAC8541 provides a 16-bit parallel interface and supports both writing to and reading from the DAC input

register. (See the timing characteristics section for detailed information for a typical write or read command.)

In addition to the data, CS, and R/W inputs, the DAC8541’s interface also provides powerdown, LDAC, data

format, and reset/reset-select control. Tables 1 and 2 show the control signal actions and data format,

respectively. These features are discussed in more detail in the remaining sections.

Table 1. DAC8541 CONTROL SIGNAL SUMMARY

CS

H

↓

R/W

X

BTC/USB LDAC RST RSTSEL PD1 PD0

ACTION

†

X

↑

X

L

X

L

Device data I/O is disabled on the bus.

L

H,L

Write initiated, present input data to the bus.

↓

H

Read initiated, data from input register is presented to data bus.

Input data is latched when writing to the device.

↑

X

Data from input register is transferred to DAC register and V

updated.

OUT is

X

L

H

X

↑

X

L

X

L

X

L

Input/output data format is unipolar straight binary.

Input/output data format is binary 2s complement.

DAC register and V

OUT

reset to min-scale. (If DAC is powered down

during reset, DAC register resets and V

upon power up.)

will settle to min-scale

OUT

X

↑

H

L

DAC register and V reset to mid-scale. (If DAC is powered down

OUT

during reset, DAC register resets and V

upon power up.)

will settle to mid-scale

OUT

X

L

H

L

Powerdown device, V

impedance equals 1 kΩ to AGND

impedance equals 100 kΩ to AGND

impedance equals high impedance

OUT

H

†

Only disables 16-bit data I/O interface. Other control lines remain active.

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THEORY OF OPERATION

data format

Table 2 details the input data format of the DAC8541. Two data I/O formats are available to the host interface.

These two formats are binary 2s complement (BTC) and unipolar straight binary (USB). The BTC/USB input

pin controls the format used by the DAC. The data format selected by the BTC/USB input is used for data written

into the device as well as data that is read back from the DAC8541. (Refer to Table 1 and Figure 1 for additional

information for performing read and write operations.)

Table 2. DAC8541 Data Format

BTC/USB = 0

BTC/USB = 1

UNIPOLAR STRAIGHT BINARY

BINARY 2s COMPLEMENT

DIGITAL INPUT

0x0000h

ANALOG OUTPUT

Min-scale

DIGITAL INPUT

ANALOG OUTPUT

Min-scale

0x8000h

0x8001h

0x0001h

Min-scale + 1 LSB

S

0x8000h

0x8001h

Mid-scale

0x0000h

0x0001h

Mid-scale

Mid-scale + 1 LSB

S

0xFFFFh

Full Scale

0x7FFFh

Full Scale

LDAC function

The DAC8541 is designed using a double-buffered architecture. A write command transfers data from the data

input pins into the input register. The data is held in the input register until a rising edge is detected on the LDAC

input. This rising edge signal transfers the data from the input register to the DAC register. Upon issuance of

the rising LDAC edge, the output of the DAC8541 begins settling to the newly written data value presented to

the DAC register.(Data in the input register is not changed when an LDAC command is given.)

RST and RSTSEL

The RST and RSTSEL inputs control the reset of the DAC register and consequently, the DAC output. The reset

command is edge triggered by a low-to-high transition on the RST pin. Once a rising edge on RST is detected,

the DAC output may settle to the mid-scale or min-scale code depending on the state of the RSTSEL input. A

logic high value on RSTSEL causes the DAC output to reset to mid-scale and a logic low value resets the DAC

to min-scale. Application of a valid reset signal to the DAC does not overwrite existing data in the input register.

power-on reset

The DAC8541 contains a power-on reset circuit that controls the output voltage during power up. On power up,

the DAC register (and DAC output) is set to min-scale (plus a small offset error produced by the output buffer).

It remains at min-scale until a valid write sequence is made to the DAC changing the DAC register data. This

is useful in applications where it is important to know the state of the output of the DAC while the system is in

the process of powering up. DGND must be applied to all digital inputs until the digital and analog supplies are

applied to the DAC8541. Logic voltages applied to the input pins when power is not applied to DV

may power the device through the ESD input structures causing undesired operation.

and AV

,

DD

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THEORY OF OPERATION

power-down modes

The DAC8541 utilizes four modes of operation. These modes are programmable via two inputs (PD1 and PD0)

to the device. Table 3 shows how the state of these pins correspond to the mode of operation of the DAC8541.

Table 3. Modes of Operation for the DAC8541

PD1

PD0

OPERATING MODE

0

Normal operation

POWER-DOWN MODES

0

1

0

1

1 kΩ to AGND

100 kΩ to AGND

High impedance

When both pins are set to 0, the device works normally with its typical power consumption of 250 µA at

AV = 5 V. However, for the three power-down modes, the supply current falls to 200 nA at AV = 5 V (50 nA

DD

at AV

= 3 V). Not only does the supply current fall, but the V

terminal is internally switched from the output

DD

OUT

of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the

device is known while in power-down mode. There are three different options: The output is connected internally

to AGND through a 1-kΩ resistor, it is connected to AGND through a 100-kΩ resistor, or it is left open-circuited

(high impedance). The output stage is illustrated in Figure 31.

V Sense

OUT

Amplifier

_

V

OUT

+

DAC

Powerdown

Circuitry

Resistor

Network

Figure 31. Output Stage During Power Down (High-Impedance)

All analog circuitry is shut down when a power-down mode is activated. However, the contents of the DAC

register are unaffected when in power-down. This allows the DAC’s output voltage to return to the previous level

when power-up resumes. The delay time required to exit power-down is typically 2.5 µs for AV

= 5 V and 5

DD

µs for AV

= 3 V. (See the typical curves section for additional information.)

DD

voltage reference inputs

Two voltage inputs provide the reference set points for the DAC architecture. These are V

Hand V

L. For

REF

typical rail-to-rail operation, V

is given by:

H should be equivalent to AV and V

L tied to AGND. The output voltage

REF

DD

REF

V

+ V

H * 2 V

L

OUT

REF

The use of the V

a small voltage to the V

L input allows minor adjustments to be made to the offset of the DAC output by applying

REF

L input. The acceptable range is between −100 mV and 100 mV with respect to

REF

AGND. A low output impedance source is needed, so that the accuracy of the DAC over its operating range is

not affected.

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THEORY OF OPERATION

analog and digital supplies

The DAC8541 utilizes two separate supplies for operation. The analog supply (AV ) powers the output buffer

DD

and DAC while the digital supply (DV ) sets the I/O voltage thresholds. Refer to the device specification table

DD

for additional information. AV

can operate from 2.7 V to 5.5 V while DV

can independently function from

DD

1.8 V to 5.5 V. The control and data I/O thresholds are determined by DV

and are given in the electrical

DD

characteristics section.

APPLICATION INFORMATION

host processor interfacing

DAC8541 to MSP430 microcontroller

Figure 32 shows a typical parallel interface connection between the DAC8541 and a MSP430 microcontroller.

The setup for the interface shown uses ports 4 and 5 of the MSP430 to send or receive the 16-bit data while

bits 0−7 of port 2 provides the control signals for the DAC. When data is to be transmitted to the DAC8541, the

data is made available to the DAC via P4 and P5 and P2.1 is taken low. The MSP430 then toggles P2.0 from

high-to-low and back to high, transferring the 16-bit data to the DAC. This data is loaded into the DAC register

by applying a rising edge to P2.4. The remaining five I/O signals of P2 shown in the figure control the reset,

power-down, and data format functions of the DAC. Depending on the specific requirements of a given

application, these pins may be tied to DGND or DV , enabling the desired mode of operation.

DD

DAC8541

MSP430F149

P4[0:7]

8 Bits

16 Bits

D[15:0]

AV

DD

0.1 µF

10 µF

P5[0:7]

P2:0

CS

R/W

P2:1

P2:2

P2:3

DV

DD

RST

RSTSEL

LDAC

PD0

P2:4

P2:5

V SENSE

OUT

V

OUT

PD1

P2:6

P2:7

BTC/USB

V

REF

H

V

REF

V

L

REF

DGND

0.1 µF

1 to 10 µF

AGND

(Other Connections Omitted for Clarity)

Figure 32. DAC8541 to MSP430 Microcontroller

DAC8541 to TMS320C5402 DSP

Figure 33 shows the connections between the DAC8541 and the TMS320C5402 digital signal processor. Data

is provided via the parallel data bus of the DSP while the DAC’s CS control input is derived from the decoded

I/O strobe signal. The IOSTRB in addition to the R/W and XF(I/O) signals control the data transmission to and

from the DAC as well as the LDAC control. With additional decoding, multiple DAC8541’s can be connected

to the same parallel data bus of the DSP.

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APPLICATION INFORMATION

DAC8541

TMS320C5402

16 Bits

D[15:0]

A[23:0]

D[15:0]

CS

AV

DD

0.1 µF

10 µF

Address

Decoder

IOSTRB

EN

DV

DD

R/W

LDAC

XF(I/O)

V SENSE

OUT

V

OUT

V

OUT

V H

REF

V

REF

V

L

REF

DGND

0.1 µF

1 to 10 µF

AGND

(Other Connections Omitted for Clarity)

Figure 33. DAC8541 to TMS320 DSP

bipolar operation using the DAC8541

The DAC8541 has been designed for single-supply operation but a bipolar output range is also possible using

the circuit shown in Figure 34. The circuit allows the DAC8541 to achieve an analog output range of 5 V.

Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the output amplifier.

Setting BTC/USB = 1, sets the DAC into binary 2s complement I/O format for the bipolar V

When operated with BTC/USB set high, the output voltage for any input code can be calculated as follows:

configuration.

OUT

D

R1 ) R2

R2

R1

ǒ Ǔ ǒ

Ǔ_* V

ǒ Ǔ

₊ƪ_VREF

ƫ

V

H

OUT

REF

65536

R1

where D represents the input code in decimal, unipolar straight binary (0–65535) and V

L = AGND.

REF

With V

H = 5 V, R = R = 10 kΩ:

1 2

REF

10 D

₊ǒ

Ǔ_{* 5 V}

V

OUT

65536

This is an output voltage range of 5 V with 8000h corresponding to a –5 V output and 7FFFh corresponding

to a 5 V output. Bipolar zero is given by 0000h applied to the DAC.

R2 = 10 kΩ

5 V

R1 = 10 kΩ

5 V

−

5 V

+

V

H

L

V

REF

OUT

OPA703

DAC8541

V

Sense

−5 V

OUT

0.1 µF

10 µF

REF

(Other Pins Omitted for Clarity)

Figure 34. Bipolar Operation With the DAC8541

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APPLICATION INFORMATION

layout

A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power

supplies. The following measures should be taken to assure optimum performance of the DAC8541.

The DAC8541 offers dual-supply operation, as it can often be used in close proximity with digital logic,

microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design

and the higher the switching speed, the more important it becomes to separate the analog and digital ground

and supply planes at the DAC.

Because the DAC8541 has both analog and digital ground pins, return currents can be better controlled and

have less effect on the DAC’s output error. Ideally, AGND would be connected directly to an analog ground plane

and DGND to the digital ground plane. The analog ground plane would be separate from the ground connection

for the digital components until they were connected at the power entry point of the system.

The power applied to AV

and V

H (this also applies to V

L if not tied to AGND) should be well-regulated

DD

REF

and low-noise. Switching power supplies and dc/dc converters often have high-frequency glitches or spikes

riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their

internal logic switches states. This noise can easily couple into the DAC output voltage through various paths

between the power connections and analog output.

As with the AGND connection, AV should be connected to a 5-V power supply plane or trace that is separate

DD

from the connection for digital logic until they are connected at the power entry point. In addition, the 1-µF to

10-µF and 0.1-µF bypass capacitors are strongly recommended. In some situations, additional bypassing may

be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all

designed to essentially lowpass filter the AV

supply, removing the high frequency noise.

DD

19

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MECHANICAL DATA

PBS (S-PQFP-G32)

PLASTIC QUAD FLATPACK

0,23

M

0,50

0,08

0,17

17

24

25

32

16

9

0,13 NOM

1

8

3,50 TYP

Gage Plane

5,05

SQ

4,95

0,25

7,10

SQ

0,10 MIN

6,90

0°−ā7°

0,70

0,40

1,05

0,95

Seating Plane

0,08

1,20 MAX

4087735/A 11/95

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

20

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型号：	DAC8541
厂家：	TEXAS INSTRUMENTS
描述：	16-BIT SINGLE CHANNEL, PARALLEL INPUT DIGITAL-TO-ANALOG CONVERTER WITH RAIL VOLTAGE OUTPUT 16位单通道，并行输入数字 - 模拟与轨电压输出转换器转换器输出元件输入元件
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