DAC8411IDCKRG4_技术文档

DAC8311

DAC8411

www.ti.com ................................................................................................................................................................................................ SBAS439–AUGUST 2008

1.8V to 5.5V, 80µA, 14- and 16-Bit, Low-Power, Single-Channel,

DIGITAL-TO-ANALOG CONVERTERS in SC70 Package

1

FEATURES

DESCRIPTION

234

•

Relative Accuracy:

The DAC8311 (14-bit) and DAC8411 (16-bit) are

low-power,

digital-to-analog converters (DAC). They provide

excellent linearity and minimize undesired

code-to-code transient voltages while offering an

easy upgrade path within a pin-compatible family. All

devices use a versatile, 3-wire serial interface that

operates at clock rates of up to 50MHz and is

single-channel,

voltage

output

–

1 LSB INL (DAC8311: 14-bit)

4 LSB INL (DAC8411: 16-bit)

•

microPower Operation: 80µA at 1.8V

Power-Down: 0.5µA at 5V, 0.1µA at 1.8V

Wide Power Supply: +1.8V to +5.5V

Power-On Reset to Zero Scale

compatible

with

standard

SPI™,

QSPI™,

Straight Binary Data Format

MICROWIRE™, and digital signal processor (DSP)

interfaces.

Low Power Serial Interface with

Schmitt-Triggered Inputs: Up to 50MHz

All devices use an external power supply as a

reference voltage to set the output range. The

devices incorporate a power-on reset (POR) circuit

that ensures the DAC output powers up at 0V and

remains there until a valid write to the device occurs.

The DAC8311 and DAC8411 contain a power-down

feature, accessed over the serial interface, that

reduces current consumption of the device to 0.1µA

at 1.8V in power down mode. The low power

consumption of this part in normal operation makes it

•

On-Chip Output Buffer Amplifier, Rail-to-Rail

Operation

•

SYNC Interrupt Facility

Extended Temperature Range –40°C to +125°C

Pin-Compatible Family in a Tiny, 6-Pin SC70

Package

APPLICATIONS

ideally

suited

for

portable,

battery-operated

•

Portable, Battery-Powered instruments

Process Control

Digital Gain and Offset Adjustment

Programmable Voltage and Current Sources

equipment. The power consumption is 0.55mW at 5V,

reducing to 2.5µW in power-down mode.

These devices are pin-compatible with the DAC5311,

DAC6311, and DAC7311, offering an easy upgrade

path from 8-, 10-, and 12-bit resolution to 14- and

16-bit. All devices are available in a small, 6-pin,

SC70 package. This package offers

a flexible,

16-BIT

14-BIT

12-BIT

10-BIT

8-BIT

pin-compatible, and functionally-compatible drop-in

solution within the family over an extended

temperature range of –40°C to +125°C.

Pin and

Function

Compatible

DAC8411 DAC8311 DAC7311 DAC6311 DAC5311

AV_DDGND

Power-On

Reset

REF(+)

DAC

Register

Output

Buffer

V_OUT

14-/16-Bit DAC

Power-Down

Control Logic

Input Control

Logic

Resistor

Network

D_IN

SYNC SCLK

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

4

SPI, QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corporation.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DAC8311

DAC8411

SBAS439–AUGUST 2008 ................................................................................................................................................................................................ www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION⁽¹⁾

MAXIMUM

RELATIVE

ACCURACY

(LSB)

MAXIMUM

DIFFERENTIAL

NONLINEARITY

(LSB)

SPECIFIED

TEMPERATURE

RANGE

PACKAGE-

LEAD

PACKAGE

DESIGNATOR

PACKAGE

MARKING

PRODUCT

DAC8411

DAC8311

±8

±4

±2

±1

SC70-6

DCK

–40°C to 125°C

D84

D83

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

PARAMETER

VALUE

–0.3 to +6

UNIT

V

AV_DDto GND

Digital input voltage to GND

AV_OUTto GND

–0.3 to +AV_DD+0.3

–40 to +125

–65 to +150

+150

V

Operating temperature range

Storage temperature range

Junction temperature (T_Jmax)

Power dissipation

°C

(T_Jmax – T_A)/θ_JA

250

θ_JAthermal impedance

°C/W

(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods may affect device reliability.

2

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ELECTRICAL CHARACTERISTICS

At AV_DD= +1.8V to +5.5V, R_L= 2kΩ to GND, and C_L= 200 pF to GND, unless otherwise noted.

DAC8411, DAC8311

PARAMETER

STATIC PERFORMANCE⁽¹⁾

Resolution

TEST CONDITIONS

MIN

TYP

MAX

UNIT

16

Bits

3.6V to 5V

±4

±8

Measured by the line passing

through codes 485 and 64714

Relative accuracy

DAC8411

LSB

1.8V to 3.6V

±12

Differential

nonlinearity

±0.5

±2

±4

LSB

Bits

LSB

Resolution

14

Measured by the line passing through codes 120 and

16200

Relative accuracy

DAC8311

±1

Differential

nonlinearity

±0.125

±1

±4

LSB

Offset error

Measured by the line passing through two codes⁽²⁾

±0.05

3

mV

µV/°C

mV

Offset error drift

Zero code error

Full-scale error

Gain error

All zeros loaded to the DAC register

All ones loaded to DAC register

0.2

0.04

0.05

±0.5

±1.5

0.2 % of FSR

±0.15 % of FSR

AV_DD= +5V

ppm of

FSR/°C

Gain temperature coefficient

AV_DD= +1.8V

OUTPUT CHARACTERISTICS⁽³⁾

Output voltage range

0

AV_DD

10

V

µs

R_L= 2kΩ, C_L= 200 pF, AV_DD= 5V, 1/4 scale to 3/4 scale

R_L= 2MΩ, C_L= 470pF

6

12

Output voltage settling time

Slew rate

µs

0.7

470

1000

0.5

17

V/µs

pF

R_L= ∞

Capacitive load stability

R_L= 2kΩ

pF

Code change glitch impulse

Digital feedthrough

1LSB change around major carry

nV-s

mV

Ω

Power-on glitch impulse

DC output impedance

R_L= 2kΩ, C_L= 200pF, AV_DD= 5V

0.5

50

AV_DD= +5V

mA

µs

Short-circuit current

AV_DD= +3V

20

Power-up time

AC PERFORMANCE

SNR

Coming out of power-down mode

50

88

–66

66

dB

T_A= +25°C, BW = 20kHz, 16-bit level, AV_DD= 5V,

f_OUT= 1kHz, 1st 19 harmonics removed for SNR

calculation

THD

SFDR

dB

SINAD

66

dB

T_A= +25°C, at zero-scale input, f_OUT= 1kHz, AV_DD= 5V

T_A= +25°C, at mid-code input, f_OUT= 1kHz, AV_DD= 5V

T_A= +25°C, at mid-code input, 0.1Hz to 10Hz, AV_DD= 5V

17

nV/√Hz

µV_pp

DAC output noise density⁽⁴⁾

DAC output noise⁽⁵⁾

110

3

(1) Linearity calculated using a reduced code range of 485 to 64714 for 16-bit, and 120 to 16200 for 14-bit, output unloaded.

(2) Straight line passing through codes 485 and 64714 for 16-bit, and 120 and 16200 for 14-bit, output unloaded.

(3) Specified by design and characterization, not production tested.

(4) For more details, see Figure 31.

(5) For more details, see Figure 32.

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ELECTRICAL CHARACTERISTICS (continued)

At AV_DD= +1.8V to +5.5V, R_L= 2kΩ to GND, and C_L= 200 pF to GND, unless otherwise noted.

DAC8411, DAC8311

PARAMETER

LOGIC INPUTS⁽⁶⁾

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input current

±1

0.8

0.5

µA

V

AV_DD= +5V

AV_DD= +1.8V

AV_DD= +5V

AV_DD= +1.8V

V_INL, input low voltage

V

1.8

1.1

V

V_INH, input high voltage

V

Pin capacitance

POWER REQUIREMENTS

AV_DD

1.5

3

pF

1.8

5.5

160

150

140

3.5

V

AV_DD= 3.6V to 5.5V

AV_DD= 2.7V to 3.6V

AV_DD= 1.8V to 2.7V

AV_DD= 3.6V to 5.5V

AV_DD= 2.7V to 3.6V

AV_DD= 1.8V to 2.7V

AV_DD= 3.6V to 5.5V

AV_DD= 2.7V to 3.6V

AV_DD= 1.8V to 2.7V

AV_DD= 3.6V to 5.5V

AV_DD= 2.7V to 3.6V

AV_DD= 1.8V to 2.7V

110

95

V_INH = AV_DDand V_INL =

GND, at mid-scale code⁽⁷⁾

Normal mode

µA

80

I_DD

0.5

V_INH = AV_DDand V_INL =

GND, at mid-scale code

All power-down mode

0.4

3.0

µA

mW

µW

°C

0.1

2.0

0.55

0.25

0.14

2.50

1.08

0.72

0.88

0.54

0.38

19.2

10.8

8.1

V_INH = AV_DDand V_INL =

GND, at mid-scale code

Normal mode

Power

dissipation

V_INH = AV_DDand V_INL =

GND, at mid-scale code

All power-down mode

TEMPERATURE RANGE

Specified performance

–40

+125

(6) Specified by design and characterization, not production tested.

(7) For more details, see Figure 12, Figure 53, and Figure 83.

4

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PIN CONFIGURATION

DCK PACKAGE

SC70-6

(TOP VIEW)

SYNC

SCLK

D_IN

1

2

3

6

5

4

V_OUT

GND

AV_DD/V_REF

Table 1. PIN DESCRIPTION

NAME

DESCRIPTION

Level-triggered control input (active low). This is the frame sychronization signal for the input data. When

SYNC goes low, it enables the input shift register and data are transferred in on the falling edges of the

following clocks. The DAC is updated following the 24th (DAC8411) or 16th (DAC8311) clock cycle,

unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt

and the write sequence is ignored by the DAC8x11. Refer to the DAC8311 and DAC8411 SYNC Interrupt

sections for more details.

1

SYNC

2

3

SCLK

D_IN

Serial Clock Input. Data can be transferred at rates up to 50MHz.

Serial Data Input. Data is clocked into the 24-bit (DAC8411) or 16-bit (DAC8311) input shift register on

the falling edge of the serial clock input.

4

5

6

AV_DD/V_REF

GND

Power Supply Input, +1.8V to 5.5V.

Ground reference point for all circuitry on the part.

Analog output voltage from DAC. The output amplifier has rail-to-rail operation.

V_OUT

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SERIAL WRITE OPERATION: 14-Bit (DAC8311)

t₉

t₁

SCLK

1

16

t₈

t₂

t₃

t₇

t₄

SYNC

t₁₀

t₆

t₅

DB15

D_IN

DB0

DB15

TIMING REQUIREMENTS⁽¹⁾⁽²⁾

All specifications at –40°C to +125°C, and AV_DD= +1.8V to +5.5V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

MIN TYP MAX UNIT

50

ns

20

(3)

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

t₉

SCLK cycle time

SCLK high time

SCLK low time

25

ns

10

25

ns

10

0

SYNC to SCLK rising edge setup time

Data setup time

ns

0

5

ns

5

4.5

Data hold time

ns

4.5

0

SCLK falling edge to SYNC rising edge

Minimum SYNC high time

ns

0

50

ns

20

100

16th SCLK falling edge to SYNC falling edge

ns

100

15

ns

15

SYNC rising edge to 16th SCLK falling edge

(for successful SYNC interrupt)

t₁₀

(1) All input signals are specified with t_R= t_F= 3ns (10% to 90% of AV_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

(2) See 14-Bit Serial Write Operation timing diagram.

(3) Maximum SCLK frequency is 50MHz at AV_DD= 3.6V to 5.5V and 20MHz at AV_DD= 1.8V to 3.6V.

6

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SERIAL WRITE OPERATION: 16-Bit (DAC8411)

t₉

t₁

SCLK

1

24

t₈

t₂

t₃

t₇

t₄

SYNC

t₁₀

t₆

t₅

DB23

D_IN

DB0

DB23

TIMING REQUIREMENTS⁽¹⁾⁽²⁾

All specifications at –40°C to +125°C, and AV_DD= +1.8V to +5.5V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

AV_DD= 1.8V to 3.6V

AV_DD= 3.6V to 5.5V

MIN TYP MAX UNIT

50

ns

20

(3)

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

t₉

SCLK cycle time

SCLK high time

SCLK low time

25

ns

10

25

ns

10

0

SYNC to SCLK rising edge setup time

Data setup time

ns

0

5

ns

5

4.5

Data hold time

ns

4.5

0

SCLK falling edge to SYNC rising edge

Minimum SYNC high time

ns

0

50

ns

20

100

24th SCLK falling edge to SYNC falling edge

ns

100

15

ns

15

SYNC rising edge to 24th SCLK falling edge

(for successful SYNC interrupt)

t₁₀

(1) All input signals are specified with t_R= t_F= 3ns (10% to 90% of AV_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

(2) See 16-Bit Serial Write Operation timing diagram.

(3) Maximum SCLK frequency is 50MHz at AV_DD= 3.6V to 5.5V and 20MHz at AV_DD= 1.8V to 3.6V.

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TYPICAL CHARACTERISTICS: AV_DD= +5V

At T_A= +25°C, AV_DD= +5V, and DAC loaded with mid-scale code, unless otherwise noted.

DAC8411 16-BIT LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C)

DAC8311 14-BIT LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C)

6

2

AV_DD= 5V

4

2

1

0

-2

-4

-6

-1

-2

1.0

0.5

0.2

0.1

0

-0.5

-1.0

-0.1

-0.2

0

8192 16384 24576 32768 40960 49152 57344 65536

0

2048

4096 6144 8192 10240 12288 14336 16384

Digital Input Code

Figure 1.

Figure 2.

DAC8411 16-BIT LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C)

DAC8311 14-BIT LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C)

6

2

AV_DD= 5V

4

2

1

0

-2

-4

-6

-1

-2

1.0

0.5

0.2

0.1

0

-0.5

-1.0

-0.1

-0.2

0

8192 16384 24576 32768 40960 49152 57344 65536

0

2048

4096 6144 8192 10240 12288 14336 16384

Digital Input Code

Figure 3.

Figure 4.

DAC8411 16-BIT LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C)

DAC8311 14-BIT LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C)

6

2

AV_DD= 5V

4

1

0

2

0

-2

-1

-4

-6

-2

0.2

0.1

0

1.0

0.5

0

-0.5

-1.0

-0.1

-0.2

0

8192 16384 24576 32768 40960 49152 57344 65536

0

2048

4096 6144 8192 10240 12288 14336 16384

Digital Input Code

Figure 5.

Figure 6.

8

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TYPICAL CHARACTERISTICS: AV_DD= +5V (continued)

At T_A= +25°C, AV_DD= +5V, and DAC loaded with mid-scale code, unless otherwise noted.

ZERO-CODE ERROR

vs TEMPERATURE

SOURCE CURRENT

AT POSITIVE RAIL

0.4

0.3

0.2

0.1

0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

AV_DD= 5V

DAC Loaded with FFFFh

-40 -25 -10

5

20 35 50 65 80 95 110 125

0

2

4

6

8

10

Temperature (°C)

I_SOURCE(mA)

Figure 7.

Figure 8.

OFFSET ERROR

vs TEMPERATURE

SINK CURRENT

AT NEGATIVE RAIL

0.6

0.4

0.6

0.4

0.2

0

AV_DD= 5V

DAC Loaded with 0000h

AV_DD= 5V

0.2

0

-0.2

-0.4

-0.6

-40 -25 -10

5

20 35 50 65 80 95 110 125

0

2

4

6

8

10

Temperature (°C)

I_SINK(mA)

Figure 9.

Figure 10.

FULL-SCALE ERROR

vs TEMPERATURE

POWER-SUPPLY CURRENT

vs DIGITAL INPUT CODE

0.06

0.04

0.02

0

120

AV_DD= 5.5V

AV_DD= 5V

100

80

-0.02

-0.04

-0.06

60

-40 -25 -10

5

20 35 50 65 80 95 110 125

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Temperature (°C)

Figure 11.

Figure 12.

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TYPICAL CHARACTERISTICS: AV_DD= +5V (continued)

At T_A= +25°C, AV_DD= +5V, and DAC loaded with mid-scale code, unless otherwise noted.

POWER-SUPPLY CURRENT

vs TEMPERATURE

POWER-DOWN CURRENT

vs TEMPERATURE

140

130

120

110

100

1.6

1.2

0.8

0.4

0

AV_DD= 5V

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 13.

Figure 14.

POWER-SUPPLY CURRENT

vs LOGIC INPUT VOLTAGE

POWER-SUPPLY CURRENT

HISTOGRAM

50

45

40

35

30

25

20

15

10

5

2000

1500

1000

500

0

AV_DD= 5.5V

SYNC Input (all other digital inputs = GND)

Sweep from

0V to 5.5V

Sweep from

5.5V to 0V

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

V_LOGIC(V)

I_DD(mA)

Figure 15.

Figure 16.

TOTAL HARMONIC DISTORTION

vs OUTPUT FREQUENCY

SIGNAL-TO-NOISE RATIO

vs OUTPUT FREQUENCY

-40

-50

-60

-70

-80

-90

-100

94

92

90

88

86

84

AV_DD= 5V,

AV_DD= 5V, f_S= 225kSPS,

THD

f_S= 225kSPS,

-1dB FSR Digital Input,

Measurement Bandwidth = 20kHz

2nd Harmonic

3rd Harmonic

0

1

2

3

4

5

0

1

2

3

4

5

f_OUT(kHz)

Figure 17.

Figure 18.

10

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TYPICAL CHARACTERISTICS: AV_DD= +5V (continued)

At T_A= +25°C, AV_DD= +5V, and DAC loaded with mid-scale code, unless otherwise noted.

CLOCK FEEDTHROUGH

5V, 2MHz, MIDSCALE

POWER SPECTRAL DENSITY

0

20

AV_DD= 5V,

f_OUT= 1kHz, f_S= 225kSPS,

Measurement Bandwidth = 20kHz

-40

-60

-80

-100

-120

-140

AV_DD= 5V

Clock Feedthrough Impulse ~0.5nV-s

Time (500ns/div)

0

5

10

15

20

Frequency (kHz)

Figure 19.

Figure 20.

GLITCH ENERGY

5V, 16-BIT, 1LSB STEP, RISING EDGE

GLITCH ENERGY

5V, 16-BIT, 1LSB STEP, FALLING EDGE

AV_DD= 5V

From Code: 7FFFh

To Code: 8000h

AV_DD= 5V

From Code: 8000h

To Code: 7FFFh

Clock

Feedthrough

~0.5nV-s

Clock

Feedthrough

~0.5nV-s

Glitch Impulse

< 0.5nV-s

Glitch Impulse

< 0.5nV-s

Time (5ms/div)

Figure 21.

Figure 22.

GLITCH ENERGY

5V, 14-BIT, 1LSB STEP, RISING EDGE

GLITCH ENERGY

5V, 14-BIT, 1LSB STEP, FALLING EDGE

AV_DD= 5V

From Code: 2001h

To Code: 2000h

Glitch Impulse

< 0.5nV-s

Clock

Feedthrough

~0.5nV-s

Clock

Feedthrough

~0.5nV-s

AV_DD= 5V

From Code: 2000h

To Code: 2001h

Glitch Impulse

< 0.5nV-s

Time (5ms/div)

Figure 23.

Figure 24.

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TYPICAL CHARACTERISTICS: AV_DD= +5V (continued)

At T_A= +25°C, AV_DD= +5V, and DAC loaded with mid-scale code, unless otherwise noted.

FULL-SCALE SETTLING TIME

5V RISING EDGE

FULL-SCALE SETTLING TIME

5V FALLING EDGE

AV_DD= 5V

From Code: 0000h

To Code: FFFFh

AV_DD= 5V

From Code: FFFFh

To Code: 0000h

Rising Edge

1V/div

Zoomed Rising Edge

100mV/div

Falling Edge

1V/div

Zoomed Falling Edge

100mV/div

Trigger Pulse 5V/div

Time (2ms/div)

Figure 25.

Figure 26.

HALF-SCALE SETTLING TIME

5V RISING EDGE

HALF-SCALE SETTLING TIME

5V FALLING EDGE

AV_DD= 5V

From Code: C000h

To Code: 4000h

Falling

Edge

1V/div

Rising

Edge

1V/div

Zoomed Falling Edge

100mV/div

Zoomed Rising Edge

100mV/div

AV_DD= 5V

From Code: 4000h

To Code: C000h

Trigger

Pulse

5V/div

Trigger

Pulse

5V/div

Time (2ms/div)

Figure 27.

Figure 28.

POWER-ON RESET TO 0V

POWER-ON GLITCH

POWER-OFF GLITCH

AV_DD= 5V

DAC = Zero Scale

Load = 200pF || 10kW

AV_DD= 5V

DAC = Zero Scale

Load = 200pF || 10kW

17mV

Time (5ms/div)

Time (10ms/div)

Figure 29.

Figure 30.

12

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TYPICAL CHARACTERISTICS: AV_DD= +5V (continued)

At T_A= +25°C, AV_DD= +5V, and DAC loaded with mid-scale code, unless otherwise noted.

DAC OUTPUT NOISE DENSITY

vs FREQUENCY

DAC OUTPUT NOISE

0.1Hz TO 10Hz BANDWIDTH

300

250

200

150

100

50

AV_DD= 5V,

DAC = Midscale, No Load

AV_DD= 5V

Midscale

3mV_PP

Zero Scale

Full Scale

0

Time (2s/div)

10

100

1k

10k

100k

Frequency (Hz)

Figure 31.

Figure 32.

POWER-SUPPLY CURRENT

vs POWER-SUPPLY VOLTAGE

POWER-DOWN CURRENT

vs POWER-SUPPLY VOLTAGE

120

110

100

90

0.4

0.3

0.2

0.1

0

AV_DD= 1.8V to 5.5V

80

70

1.800

2.725

3.650

4.575

5.500

1.800

2.725

3.650

4.575

5.500

AV_DD(V)

Figure 33.

Figure 34.

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TYPICAL CHARACTERISTICS: AV_DD= +3.6V

At T_A= 25°C, and AV_DD= +3.6V, unless otherwise noted.

POWER-SUPPLY CURRENT

vs DIGITAL INPUT CODE

POWER-SUPPLY CURRENT

vs TEMPERATURE

100

90

80

70

60

50

140

130

120

110

100

90

AV_DD= 3.6V

80

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 35.

Figure 36.

POWER-SUPPLY CURRENT

vs LOGIC INPUT VOLTAGE

POWER-DOWN CURRENT

vs TEMPERATURE

1.2

0.8

0.4

0

1200

900

600

300

0

SYNC Input (all other digital inputs = GND)

AV_DD= 3.6V

Sweep from

0V to 3.6V

Sweep from

3.6V to 0V

-40 -25 -10

5

20 35 50 65 80 95 110 125

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Temperature (°C)

V_LOGIC(V)

Figure 37.

Figure 38.

SOURCE CURRENT

AT POSITIVE RAIL

SINK CURRENT

AT NEGATIVE RAIL

3.7

3.5

3.3

3.1

2.9

2.7

2.5

0.6

0.4

0.2

0

AV_DD= 3.6V

DAC Loaded with 0000h

AV_DD= 3.6V

DAC Loaded with FFFFh

0

2

4

6

8

10

0

2

4

6

8

10

I_SOURCE(mA)

I_SINK(mA)

Figure 39.

Figure 40.

14

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TYPICAL CHARACTERISTICS: AV_DD= +3.6V (continued)

At T_A= 25°C, and AV_DD= +3.6V, unless otherwise noted.

POWER-SUPPLY CURRENT

HISTOGRAM

50

AV_DD= 3.6V

45

40

35

30

25

20

15

10

5

0

I_DD(mA)

Figure 41.

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TYPICAL CHARACTERISTICS: AV_DD= +2.7V

At T_A= 25°C, and AV_DD= +2.7V, unless otherwise noted.

DAC8411 16-BIT LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C)

DAC8311 14-BIT LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C)

6

2

AV_DD= 2.7V

4

2

1

0

-2

-4

-6

-1

-2

1.0

0.5

0.2

0.1

0

-0.5

-1.0

-0.1

-0.2

0

8192 16384 24576 32768 40960 49152 57344 65536

0

2048

4096 6144 8192 10240 12288 14336 16384

Digital Input Code

Figure 42.

Figure 43.

DAC8411 16-BIT LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C)

DAC8311 14-BIT LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C)

6

2

AV_DD= 2.7V

4

2

1

0

-2

-4

-6

-1

-2

1.0

0.5

0.2

0.1

0

-0.5

-1.0

-0.1

-0.2

0

8192 16384 24576 32768 40960 49152 57344 65536

0

2048

4096 6144 8192 10240 12288 14336 16384

Digital Input Code

Figure 44.

Figure 45.

DAC8411 16-BIT LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C)

DAC8311 14-BIT LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C)

6

2

AV_DD= 2.7V

4

1

0

2

0

-2

-1

-4

-6

-2

0.2

0.1

0

1.0

0.5

0

-0.5

-1.0

-0.1

-0.2

0

8192 16384 24576 32768 40960 49152 57344 65536

0

2048

4096 6144 8192 10240 12288 14336 16384

Digital Input Code

Figure 46.

Figure 47.

16

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TYPICAL CHARACTERISTICS: AV_DD= +2.7V (continued)

At T_A= 25°C, and AV_DD= +2.7V, unless otherwise noted.

ZERO-CODE ERROR

vs TEMPERATURE

SOURCE CURRENT

AT POSITIVE RAIL

0.4

0.3

0.2

0.1

0

2.8

2.6

2.4

2.2

2.0

AV_DD= 2.7V

DAC Loaded with FFFFh

-40 -25 -10

5

20 35 50 65 80 95 110 125

0

2

4

6

8

10

Temperature (°C)

I_SOURCE(mA)

Figure 48.

Figure 49.

OFFSET ERROR

vs TEMPERATURE

SINK CURRENT

AT NEGATIVE RAIL

0.6

0.4

0.6

0.4

0.2

0

AV_DD= 2.7V

DAC Loaded with 0000h

0.2

0

-0.2

-0.4

-0.6

-40 -25 -10

5

20 35 50 65 80 95 110 125

0

2

4

6

8

10

Temperature (°C)

I_SINK(mA)

Figure 50.

Figure 51.

FULL-SCALE ERROR

vs TEMPERATURE

POWER-SUPPLY CURRENT

vs DIGITAL INPUT CODE

0.06

0.04

0.02

0

100

AV_DD= 2.7V

90

80

70

60

50

-0.02

-0.04

-0.06

-40 -25 -10

5

20 35 50 65 80 95 110 125

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Temperature (°C)

Figure 52.

Figure 53.

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TYPICAL CHARACTERISTICS: AV_DD= +2.7V (continued)

At T_A= 25°C, and AV_DD= +2.7V, unless otherwise noted.

POWER-SUPPLY CURRENT

vs TEMPERATURE

POWER-DOWN CURRENT

vs TEMPERATURE

120

110

100

90

1.0

0.8

0.6

0.4

0.2

0

AV_DD= 2.7V

80

70

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 54.

Figure 55.

POWER-SUPPLY CURRENT

vs LOGIC INPUT VOLTAGE

POWER-SUPPLY CURRENT

HISTOGRAM

50

45

40

35

30

25

20

15

10

5

800

600

400

200

0

AV_DD= 2.7V

SYNC Input (all other digital inputs = GND)

Sweep from

0V to 2.7V

Sweep from

2.7V to 0V

0

0.5

1.0

1.5

2.0

2.5

3.0

V_LOGIC(V)

I_DD(mA)

Figure 56.

Figure 57.

TOTAL HARMONIC DISTORTION

vs OUTPUT FREQUENCY

SIGNAL-TO-NOISE RATIO

vs OUTPUT FREQUENCY

-20

-40

88

86

84

82

80

AV_DD= 2.7V, f_S= 225kSPS,

-1dB FSR Digital Input,

Measurement Bandwidth = 20kHz

THD

-60

2nd Harmonic

-80

3rd Harmonic

-100

0

1

2

3

4

5

0

1

2

3

4

5

f_OUT(kHz)

Figure 58.

Figure 59.

18

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TYPICAL CHARACTERISTICS: AV_DD= +2.7V (continued)

At T_A= 25°C, and AV_DD= +2.7V, unless otherwise noted.

CLOCK FEEDTHROUGH

2.7V, 20MHz, MIDSCALE

POWER SPECTRAL DENSITY

0

20

AV_DD= 2.7V,

f_OUT= 1kHz, f_S= 225kSPS,

Measurement Bandwidth = 20kHz

-40

-60

-80

-100

-120

-140

AV_DD= 2.7V

Clock Feedthrough Impulse ~0.4nV-s

Time (5ms/div)

0

5

10

15

20

Frequency (kHz)

Figure 60.

Figure 61.

GLITCH ENERGY

2.7V, 16-BIT, 1LSB STEP, RISING EDGE

GLITCH ENERGY

2.7V, 16-BIT, 1LSB STEP, FALLING EDGE

AV_DD= 2.7V

From Code: 8000h

To Code: 7FFFh

AV_DD= 2.7V

From Code: 7FFFh

To Code: 8000h

Glitch Impulse

< 0.3nV-s

Glitch Impulse

< 0.3nV-s

Clock

Feedthrough

~0.4nV-s

Clock

Feedthrough

~0.4nV-s

Time (5ms/div)

Figure 62.

Figure 63.

GLITCH ENERGY

2.7V, 14-BIT, 1LSB STEP, RISING EDGE

GLITCH ENERGY

2.7V, 14-BIT, 1LSB STEP, FALLING EDGE

AV_DD= 2.7V

From Code: 2001h

To Code: 2000h

AV_DD= 2.7V

From Code: 2000h

To Code: 2001h

Glitch Impulse

< 0.3nV-s

Clock

Feedthrough

~0.4nV-s

Clock

Feedthrough

~0.4nV-s

Glitch Impulse

< 0.3nV-s

Time (5ms/div)

Figure 64.

Figure 65.

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TYPICAL CHARACTERISTICS: AV_DD= +2.7V (continued)

At T_A= 25°C, and AV_DD= +2.7V, unless otherwise noted.

FULL-SCALE SETTLING TIME

2.7V RISING EDGE

FULL-SCALE SETTLING TIME

2.7V FALLING EDGE

AV_DD= 2.7V

From Code: 0000h

To Code: FFFFh

AV_DD= 2.7V

From Code: FFFFh

To Code: 0000h

Falling Edge

1V/div

Rising Edge

1V/div

Zoomed Rising Edge

100mV/div

Zoomed Falling Edge

100mV/div

Trigger

Pulse

2.7V/div

Trigger Pulse 2.7V/div

Time (2ms/div)

Figure 66.

Figure 67.

HALF-SCALE SETTLING TIME

2.7V RISING EDGE

HALF-SCALE SETTLING TIME

2.7V FALLING EDGE

AV_DD= 2.7V

From Code: 4000h

To Code: C000h

AV_DD= 2.7V

From Code: C000h

To Code: 4000h

Falling

Edge

1V/div

Rising

Edge

1V/div

Zoomed Rising Edge

100mV/div

Trigger

Pulse

2.7V/div

Trigger

Zoomed Falling Edge

100mV/div

Pulse

2.7V/div

Time (2ms/div)

Figure 68.

Figure 69.

POWER-ON RESET TO 0V

POWER-ON GLITCH

POWER-OFF GLITCH

AV_DD= 2.7V

DAC = Zero Scale

Load = 200pF || 10kW

AV_DD= 2.7V

DAC = Zero Scale

Load = 200pF || 10kW

17mV

Time (5ms/div)

Time (10ms/div)

Figure 70.

Figure 71.

20

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TYPICAL CHARACTERISTICS: AV_DD= +1.8V

At T_A= 25°C, and AV_DD= +1.8V, unless otherwise noted.

DAC8411 16-BIT LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(–40°C)

DAC8311 14-BIT LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C)

6

4

2

AV_DD= 1.8V

1

0

2

0

-2

-4

-6

-1

-2

1.0

0.5

0.2

0.1

0

-0.5

-1.0

-0.1

-0.2

0

8192 16384 24576 32768 40960 49152 57344 65536

0

2048

4096 6144 8192 10240 12288 14336 16384

Digital Input Code

Figure 72.

Figure 73.

DAC8411 16-BIT LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C)

DAC8311 14-BIT LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C)

6

2

AV_DD= 1.8V

4

2

1

0

-2

-4

-6

-1

-2

1.0

0.5

0.2

0.1

0

-0.5

-1.0

-0.1

-0.2

0

8192 16384 24576 32768 40960 49152 57344 65536

0

2048

4096 6144 8192 10240 12288 14336 16384

Digital Input Code

Figure 74.

Figure 75.

DAC8411 16-BIT LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C)

DAC8311 14-BIT LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C)

6

2

AV_DD= 1.8V

4

1

0

2

0

-2

-1

-4

-6

-2

0.2

0.1

0

1.0

0.5

0

-0.5

-1.0

-0.1

-0.2

0

8192 16384 24576 32768 40960 49152 57344 65536

0

2048

4096 6144 8192 10240 12288 14336 16384

Digital Input Code

Figure 76.

Figure 77.

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TYPICAL CHARACTERISTICS: AV_DD= +1.8V (continued)

At T_A= 25°C, and AV_DD= +1.8V, unless otherwise noted.

ZERO-CODE ERROR

vsTEMPERATURE

SOURCE CURRENT

AT POSITIVE RAIL

1.2

1.0

0.8

0.6

0.4

0.2

0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

AV_DD= 1.8V

DAC Loaded with FFFFh

-40 -25 -10

5

20 35 50 65 80 95 110 125

0

2

4

6

8

Temperature (°C)

I_SOURCE(mA)

Figure 78.

Figure 79.

OFFSET ERROR

vs TEMPERATURE

SINK CURRENT

AT NEGATIVE RAIL

0.6

0.4

0.6

0.4

0.2

0

AV_DD= 1.8V

DAC Loaded with 0000h

AV_DD= 1.8V

0.2

0

-0.2

-0.4

-0.6

-40 -25 -10

5

20 35 50 65 80 95 110 125

0

2

4

6

8

Temperature (°C)

I_SINK(mA)

Figure 80.

Figure 81.

FULL-SCALE ERROR

vs TEMPERATURE

POWER-SUPPLY CURRENT

vs DIGITAL INPUT CODE

0.06

0.04

0.02

0

100

AV_DD= 1.8V

90

80

70

60

50

-0.02

-0.04

-0.06

-40 -25 -10

5

20 35 50 65 80 95 110 125

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Temperature (°C)

Figure 82.

Figure 83.

22

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TYPICAL CHARACTERISTICS: AV_DD= +1.8V (continued)

At T_A= 25°C, and AV_DD= +1.8V, unless otherwise noted.

POWER-SUPPLY CURRENT

vs TEMPERATURE

POWER-DOWN CURRENT

vs TEMPERATURE

110

100

90

0.8

0.6

0.4

0.2

0

AV_DD= 1.8V

80

70

60

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 84.

Figure 85.

POWER-SUPPLY CURRENT

vs LOGIC INPUT VOLTAGE

POWER-SUPPLY CURRENT

HISTOGRAM

50

45

40

35

30

25

20

15

10

5

200

150

100

50

AV_DD= 1.8V

SYNC Input (all other digital inputs = GND)

Sweep from

0V to 1.8V

Sweep from

1.8V to 0V

0

0.5

1.0

1.5

2.0

V_LOGIC(V)

I_DD(mA)

Figure 86.

Figure 87.

TOTAL HARMONIC DISTORTION

vs OUTPUT FREQUENCY

SIGNAL-TO-NOISE RATIO

vs OUTPUT FREQUENCY

-20

-40

86

84

82

80

78

76

AV_DD= 1.8V, f_S= 225kSPS,

-1dB FSR Digital Input,

THD

Measurement Bandwidth = 20kHz

-60

-80

2nd Harmonic

-100

-120

3rd Harmonic

0

1

2

3

4

5

0

1

2

3

4

5

f_OUT(kHz)

Figure 88.

Figure 89.

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TYPICAL CHARACTERISTICS: AV_DD= +1.8V (continued)

At T_A= 25°C, and AV_DD= +1.8V, unless otherwise noted.

CLOCK FEEDTHROUGH

1.8V, 20MHz, MIDSCALE

POWER SPECTRAL DENSITY

0

20

AV_DD= 1.8V,

f_OUT= 1kHz, f_S= 225kSPS,

Measurement Bandwidth = 20kHz

-40

-60

-80

-100

-120

-140

AV_DD= 1.8V

Clock Feedthrough Impulse ~0.34nV-s

Time (5ms/div)

0

5

10

15

20

Frequency (kHz)

Figure 90.

Figure 91.

GLITCH ENERGY

1.8V, 16-BIT, 1LSB STEP, RISING EDGE

GLITCH ENERGY

1.8V, 16-BIT, 1LSB STEP, FALLING EDGE

AV_DD= 1.8V

From Code: 8000h

To Code: 7FFFh

AV_DD= 1.8V

From Code: 7FFFh

To Code: 8000h

Clock

Feedthrough

~0.3nV-s

Glitch Impulse

< 0.2nV-s

Clock

Feedthrough

~0.3nV-s

Glitch Impulse

< 0.2nV-s

Time (5ms/div)

Figure 92.

Figure 93.

GLITCH ENERGY

1.8V, 14-BIT, 1LSB STEP, RISING EDGE

GLITCH ENERGY

1.8V, 14-BIT, 1LSB STEP, FALLING EDGE

AV_DD= 1.8V

From Code: 2001h

To Code: 2000h

Glitch Impulse

< 0.2nV-s

Clock

Feedthrough

~0.3nV-s

Glitch Impulse

< 0.2nV-s

Clock

Feedthrough

~0.3nV-s

AV_DD= 1.8V

From Code: 2000h

To Code: 2001h

Time (5ms/div)

Figure 94.

Figure 95.

24

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TYPICAL CHARACTERISTICS: AV_DD= +1.8V (continued)

At T_A= 25°C, and AV_DD= +1.8V, unless otherwise noted.

FULL-SCALE SETTLING TIME

1.8V RISING EDGE

FULL-SCALE SETTLING TIME

1.8V FALLING EDGE

AV_DD= 1.8V

From Code: 0000h

To Code: FFFFh

AV_DD= 1.8V

From Code: FFFFh

To Code: 0000h

Falling Edge

1V/div

Zoomed Rising Edge

100mV/div

Rising Edge

1V/div

Zoomed Falling Edge

100mV/div

Trigger

Pulse

1.8V/div

Trigger Pulse 1.8V/div

Time (2ms/div)

Figure 96.

Figure 97.

HALF-SCALE SETTLING TIME

1.8V RISING EDGE

HALF-SCALE SETTLING TIME

1.8V FALLING EDGE

AV_DD= 1.8V

From Code: 4000h

To Code: C000h

AV_DD= 1.8V

From Code: C000h

To Code: 4000h

Falling

Edge

1V/div

Rising

Edge

1V/div

Zoomed Falling Edge

100mV/div

Zoomed Rising Edge

100mV/div

Trigger

Pulse

1.8V/div

Trigger Pulse 1.8V/div

Time (2ms/div)

Figure 98.

Figure 99.

POWER-ON RESET TO 0V

POWER-ON GLITCH

POWER-OFF GLITCH

AV_DD= 1.8V

DAC = Zero Scale

Load = 200pF || 10kW

AV_DD= 1.8V

DAC = Zero Scale

Load = 200pF || 10kW

4mV

Time (5ms/div)

Figure 100.

Time (10ms/div)

Figure 101.

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THEORY OF OPERATION

DAC SECTION

V_REF

The DAC8311 and DAC8411 are fabricated using TI's

proprietary HPA07 process technology. The

architecture consists of a string DAC followed by an

output buffer amplifier. Because there is no reference

input pin, the power supply (AV_DD) acts as the

reference. Figure 102 shows a block diagram of the

DAC architecture.

R_DIVIDER

V_REF

2

R

AV_DD

To Output

Amplifier

R

REF (+)

DAC Register

Resistor String

V_OUT

Output

Amplifier

GND

Figure 102. DAC8x11 Architecture

R

The input coding to the DAC8311 and DAC8411 is

straight binary, so the ideal output voltage is given by:

D

V

+ AV

n

OUT

DD

2

Where:

n = resolution in bits; either 14 (DAC8311) or 16

(DAC8411).

D = decimal equivalent of the binary code that is

loaded to the DAC register; it ranges from 0 to

16,383 for the 14-bit DAC8311, or 0 to 65,535 for

the 16-bit DAC8411.

Figure 103. Resistor String

OUTPUT AMPLIFIER

RESISTOR STRING

The output buffer amplifier is capable of generating

rail-to-rail voltages on its output which gives an output

range of 0V to AV_DD. It is capable of driving a load of

2kΩ in parallel with 1000pF to GND. The source and

sink capabilities of the output amplifier can be seen in

the Typical Characteristics section for each device.

The slew rate is 0.7V/µs with a half-scale settling time

of typically 6µs with the output unloaded.

The resistor string section is shown in Figure 103. It

is simply a string of resistors, each of value R. The

code loaded into the DAC register determines at

which node on the string the voltage is tapped off to

be fed into the output amplifier by closing one of the

switches connecting the string to the amplifier. It is

tested monotonic because it is a string of resistors.

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SERIAL INTERFACE (for 14-Bit DAC8311)

At this point, the SYNC line may be kept low or

brought high. In either case, it must be brought high

for a minimum of 20ns before the next write

sequence so that a falling edge of SYNC can initiate

the next write sequence. As previously mentioned, it

must be brought high again before the next write

sequence.

The DAC8311 has a 3-wire serial interface (SYNC,

SCLK, and DIN) compatible with SPI, QSPI, and

Microwire interface standards, as well as most DSPs.

See the 14-bit Serial Write Operation timing diagram

for an example of a typical write sequence.

DAC8311 Input Shift Register

DAC8311 SYNC Interrupt

The input shift register is 16 bits wide, as shown in

Table 2. The first two bits (PD0 and PD1) are

reserved control bits that set the desired mode of

operation (normal mode or any one of three

power-down modes) as indicated in Table 4.

In a normal write sequence, the SYNC line is kept

low for at least 16 falling edges of SCLK and the DAC

is updated on the 16th falling edge. However,

bringing SYNC high before the 16th falling edge acts

as an interrupt to the write sequence. The shift

register is reset and the write sequence is seen as

invalid. Neither an update of the DAC register

contents or a change in the operating mode occurs,

as shown in Figure 104.

The write sequence begins by bringing the SYNC line

low. Data from the DIN line are clocked into the 16-bit

shift register on each falling edge of SCLK. The serial

clock frequency can be as high as 50MHz, making

the DAC8311 compatible with high-speed DSPs. On

the 16th falling edge of the serial clock, the last data

bit is clocked in and the programmed function is

executed.

Table 2. DAC8311 Data Input Register

DB15 DB14

PD1 PD0

DB0

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

CLK

SYNC

D_IN

DB15

DB0

DB15

DB0

Invalid Write Sequence:

SYNC HIGH before 16th Falling Edge

Valid Write Sequence:

Output Updates on 16th Falling Edge

Figure 104. DAC8311 SYNC Interrupt Facility

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SERIAL INTERFACE (for 16-Bit DAC8411)

At this point, the SYNC line may be kept low or

brought high. In either case, it must be brought high

for a minimum of 20ns before the next write

sequence so that a falling edge of SYNC can initiate

the next write sequence. As previously mentioned, it

must be brought high again before the next write

sequence.

The DAC8411 has a 3-wire serial interface (SYNC,

SCLK, and DIN) compatible with SPI, QSPI, and

Microwire interface standards, as well as most DSPs.

See the 16-bit Serial Write Operation timing diagram

for an example of a typical write sequence.

The SYNC line may be brought high after the 18th bit

is clocked in because the last six bits are don't care.

DAC8411 Input Shift Register

The input shift register is 24 bits wide, as shown in

Table 3. The first two bits are reserved control bits

(PD0 and PD1) that set the desired mode of

operation (normal mode or any one of three

power-down modes) as indicated in Table 4. The last

six bits are don't care.

DAC8411 SYNC Interrupt

In a normal write sequence, the SYNC line is kept

low for 24 falling edges of SCLK and the DAC is

updated on the 18th falling edge, ignoring the last six

don't care bits. However, bringing SYNC high before

the 18th falling edge acts as an interrupt to the write

sequence. The shift register is reset and the write

sequence is seen as invalid. Neither an update of the

DAC register contents or a change in the operating

mode occurs, as shown in Figure 105.

The write sequence begins by bringing the SYNC line

low. Data from the DIN line are clocked into the 24-bit

shift register on each falling edge of SCLK. The serial

clock frequency can be as high as 50MHz, making

the DAC8411 compatible with high-speed DSPs. On

the 18th falling edge of the serial clock, the last data

bit is clocked in and the programmed function is

executed. The last six bits are don't care.

Table 3. DAC8411 Data Input Register

DB23

PD1

DB7 DB6 DB5

DB0

X

PD0 D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

X

18th Falling Edge

18th/24th Falling Edge

18

24

18

24

CLK

SYNC

D_IN

DB23

DB6 DB5

DB0

DB23

DB6 DB5

DB0

Invalid/Interrupted Write Sequence:

Output/Mode Does Not Update on the 18th Falling Edge

Valid Write Sequence:

Output/Mode Updates on the 18th or 24th Falling Edge

Figure 105. DAC8411 SYNC Interrupt Facility

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POWER-ON RESET TO ZERO-SCALE

power-down mode. There are three different options.

The output is connected internally to GND either

through a 1kΩ resistor or a 100kΩ resistor, or is left

open-circuited (High-Z). See Figure 106 for the output

stage.

The DAC8x11 contains a power-on reset circuit that

controls the output voltage during power-up. On

power-up, the DAC register is filled with zeros and

the output voltage is 0V. The DAC register remains

that way until a valid write sequence is made to the

DAC. This design is useful in applications where it is

important to know the state of the output of the DAC

while it is in the process of powering up.

Amplifier

Resistor

V_OUT

String DAC

The occuring power-on glitch impulse is only a few

mV (typically, 17mV; see Figure 29, Figure 70, or

Figure 100).

Power-down

Resistor

Circuitry

Network

POWER-DOWN MODES

The DAC8x11 contains four separate modes of

operation. These modes are programmable by setting

two bits (PD1 and PD0) in the control register.

Table 4 shows how the state of the bits corresponds

to the mode of operation of the device.

Figure 106. Output Stage During Power-Down

All linear circuitry is shut down when the power-down

mode is activated. However, the contents of the DAC

register are unaffected when in power-down. The

time to exit power-down is typically 50µs for AV_DD

5V and AV_DD= 3V. See the Typical Characteristics

section for each device for more information.

Table 4. Modes of Operation for the DAC8x11

=

PD1

PD0

OPERATING MODE

Normal Operation

0

Power-Down Modes

Output 1kΩ to GND

Output 100kΩ to GND

High-Z

DAC NOISE PERFORMANCE

0

1

0

1

Typical noise performance for the DAC8x11 is shown

in Figure 31 and Figure 32. Output noise spectral

density at the V_OUTpin versus frequency is depicted

in Figure 31 for full-scale, midscale, and zero-scale

input codes. The typical noise density for midscale

code is 110nV/√Hz at 1kHz and at 1MHz.

When both bits are set to 0, the device works

normally with a standard power consumption of

typically 80µA at 1.8V. However, for the three

power-down modes, the typical supply current falls to

0.5µA at 5V, 0.4µA at 3V, and 0.1µA at 1.8V. Not

only does the supply current fall, but the output stage

is also internally switched from the output of the

amplifier to a resistor network of known values. The

advantage of this architecture is that the output

impedance of the part is known while the part is in

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APPLICATION INFORMATION

USING THE REF5050 AS A POWER SUPPLY

FOR THE DAC8x11

BIPOLAR OPERATION USING THE DAC8x11

The DAC8x11 has been designed for single-supply

operation but a bipolar output range is also possible

using the circuit in Figure 108. The circuit shown

gives an output voltage range of ±5V. Rail-to-rail

operation at the amplifier output is achievable using

an OPA211, OPA340, or OPA703 as the output

amplifier. For a full list of available operational

amplifiers from TI, see TI web site at www.ti.com

As a result of the extremely low supply current

required by the DAC8x11, an alternative option is to

use a REF5050 +5V precision voltage reference to

supply the required voltage to the part, as shown in

Figure 107. This option is especially useful if the

power supply is too noisy or if the system supply

voltages are at some value other than 5V. The

REF5050 outputs a steady supply voltage for the

DAC8x11. If the REF5050 is used, the current

needed to supply DAC8x11 is typically 110µA at 5V,

with no load on the output of the DAC. When the

DAC output is loaded, the REF5050 also needs to

supply the current to the load. The total current

required (with a 5kΩ load on the DAC output) is:

The output voltage for any input code can be

calculated as follows:

R ) R

R

2

R

1

D

2

1

2

ǒ Ǔ

ǒ Ǔ_* AVǒ Ǔ

V

+

AV

ƪ

ƫ

n

O

DD

R

1

(1)

110µA + (5V/5kΩ) = 1.11mA

Where:

The load regulation of the REF5050 is typically

0.002%/mA, resulting in an error of 90µV for the

1.11mA current drawn from it. This value corresponds

to a 1.1LSB error at 16bit (DAC8411).

n = resolution in bits; either 14 (DAC8311) or 16

(DAC8411).

D = the input code in decimal; either 0 to 16,383

(DAC8311) or 0 to 65,535 (DAC8411).

With AV_DD= 5V, R₁= R₂= 10kΩ:

10 D

+5.5V

₊ǒ Ǔ_*5V

V

n

O

+5V

2

(2)

REF5050

1mF

This is an output voltage range of ±5V with 0000h

(16-bit level) corresponding to a –5V output and

FFFFh (16-bit level) corresponding to a +5V output.

110mA

SYNC

V_OUT= 0V to 5V

Three-Wire

Serial

R₂

+5V

SCLK

D_IN

DAC8x11

10kW

Interface

+5.5V

R₁

10kW

OPA211

±5V

V_OUT

Figure 107. REF5050 as Power Supply to

DAC8x11

AV_DD

DAC8x11

5.5V

10mF

0.1mF

Three-Wire

Serial

For other power-supply voltages, alternative

references such as the REF3030 (3V), REF3033

(3.3V), or REF3220 (2.048V) are recommended. For

a full list of available voltage references from TI, see

TI web site at www.ti.com.

Interface

Figure 108. Bipolar Operation with the DAC8x11

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MICROPROCESSOR INTERFACING

DAC8x11⁽¹⁾

Microwire

SYNC

CS

DAC8x11 to 8051 Interface

SCLK

SK

SO

Figure 109 shows a serial interface between the

DAC8x11 and a typical 8051-type microcontroller.

The setup for the interface is as follows: TXD of the

8051 drives SCLK of the DAC8x11, while RXD drives

the serial data line of the part. The SYNC signal is

derived from a bit programmable pin on the port. In

this case, port line P3.3 is used. When data are to be

transmitted to the DAC8x11, P3.3 is taken low. The

8051 transmits data only in 8-bit bytes; thus, only

eight falling clock edges occur in the transmit cycle.

To load data to the DAC, P3.3 remains low after the

first eight bits are transmitted, and a second write

cycle is initiated to transmit the second byte of data.

P3.3 is taken high following the completion of this

cycle. The 8051 outputs the serial data in a format

which has the LSB first. The DAC8x11 requires its

data with the MSB as the first bit received. Therefore,

the 8051 transmit routine must take this requirement

into account, and mirror the data as needed.

D_IN

NOTE: (1) Additional pins omitted for clarity.

Figure 110. DAC8x11 to Microwire Interface

DAC8x11 to 68HC11 Interface

Figure 111 shows a serial interface between the

DAC8x11 and the 68HC11 microcontroller. SCK of

the 68HC11 drives the SCLK of the DAC8x11, while

the MOSI output drives the serial data line of the

DAC. The SYNC signal is derived from a port line

(PC7), similar to what was done for the 8051.

DAC8x11⁽¹⁾

SYNC

68HC11⁽¹⁾

PC7

SCK

SCLK

D_IN

MOSI

80C51/80L51⁽¹⁾

P3.3

DAC8x11⁽¹⁾

SYNC

NOTE: (1) Additional pins omitted for clarity.

TXD

RXD

SCLK

D_IN

Figure 111. DAC8x11 to 68HC11 Interface

NOTE: (1) Additional pins omitted for clarity.

The 68HC11 should be configured so that its CPOL

bit is a '0' and its CPHA bit is a '1'. This configuration

causes data appearing on the MOSI output to be

valid on the falling edge of SCK. When data are

being transmitted to the DAC, the SYNC line is taken

low (PC7). Serial data from the 68HC11 are

transmitted in 8-bit bytes with only eight falling clock

edges occurring in the transmit cycle. Data are

transmitted MSB first. In order to load data to the

DAC8x11, PC7 is held low after the first eight bits are

transferred, and a second serial write operation is

performed to the DAC; PC7 is taken high at the end

of this procedure.

Figure 109. DAC8x11 to 80C51/80L51 Interfaces

DAC8x11 to Microwire Interface

Figure 110 shows an interface between the DAC8x11

and any Microwire-compatible device. Serial data are

shifted out on the falling edge of the serial clock and

are clocked into the DAC8x11 on the rising edge of

the SK signal.

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LAYOUT

A precision analog component requires careful layout,

adequate bypassing, and clean, well-regulated power

supplies.

The power applied to AV_DDshould be well-regulated

and low-noise. Switching power supplies and dc/dc

converters often have high-frequency glitches or

spikes riding on the output voltage. In addition, digital

components can create similar high-frequency spikes

as the internal logic switches state. This noise can

easily couple into the DAC output voltage through

various paths between the power connections and

analog output. This condition is particularly true for

the DAC8x11, as the power supply is also the

reference voltage for the DAC.

The DAC8x11 offers single-supply operation; it will

often be used in close proximity with digital logic,

microcontrollers, microprocessors, and digital signal

processors. The more digital logic present in the

design and the higher the switching speed, the more

difficult it will be to achieve good performance from

the converter.

Because of the single ground pin of the DAC8x11, all

return currents, including digital and analog return

currents, must flow through the GND pin. Ideally,

GND would be connected directly to an analog

ground plane. This plane would be separate from the

ground connection for the digital components until

they were connected at the power entry point of the

system.

As with the GND connection, AV_DDshould be

connected to a +5V power supply plane or trace that

is separate from the connection for digital logic until

they are connected at the power entry point. In

addition, the 1µF to 10µF and 0.1µF bypass

capacitors are strongly recommended. In some

situations, additional bypassing may be required,

such as a 100µF electrolytic capacitor or even a Pi

filter made up of inductors and capacitors—all

designed to essentially low-pass filter the +5V supply,

removing the high-frequency noise.

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PARAMETER DEFINITIONS

With the increased complexity of many different

specifications listed in product data sheets, this

Full-Scale Error

section summarizes selected specifications related to

digital-to-analog converters.

Full-scale error is defined as the deviation of the real

full-scale output voltage from the ideal output voltage

while the DAC register is loaded with the full-scale

STATIC PERFORMANCE

code (0xFFFF). Ideally, the output should be V_DD– 1

LSB. The full-scale error is expressed in percent of

full-scale range (%FSR).

Static performance parameters are specifications

such as differential nonlinearity (DNL) or integral

nonlinearity (INL). These are dc specifications and

provide information on the accuracy of the DAC. They

are most important in applications where the signal

changes slowly and accuracy is required.

Offset Error

Offset error is defined as the difference between

actual output voltage and the ideal output voltage in

the linear region of the transfer function. This

difference is calculated by using a straight line

defined by two codes (for example, for 16-bit

resolution, codes 485 and 64714). Since the offset

error is defined by a straight line, it can have a

negative or positve value. Offset error is measured in

mV.

Resolution

Generally, the DAC resolution can be expressed in

different forms. Specifications such as IEC 60748-4

recognize the numerical, analog, and relative

resolution. The numerical resolution is defined as the

number of digits in the chosen numbering system

necessary to express the total number of steps of the

transfer characteristic, where a step represents both

a digital input code and the corresponding discrete

analogue output value. The most commonly-used

definition of resolution provided in data sheets is the

numerical resolution expressed in bits.

Zero-Code Error

Zero-code error is defined as the DAC output voltage,

when all '0's are loaded into the DAC register.

Zero-scale error is a measure of the difference

between actual output voltage and ideal output

voltage (0V). It is expressed in mV. It is primarily

caused by offsets in the output amplifier.

Least Significant Bit (LSB)

The least significant bit (LSB) is defined as the

smallest value in a binary coded system. The value of

the LSB can be calculated by dividing the full-scale

output voltage by 2ⁿ, where n is the resolution of the

converter.

Gain Error

Gain error is defined as the deviation in the slope of

the real DAC transfer characteristic from the ideal

transfer function. Gain error is expressed as a

percentage of full-scale range (%FSR).

Most Significant Bit (MSB)

Full-Scale Error Drift

The most significant bit (MSB) is defined as the

largest value in a binary coded system. The value of

the MSB can be calculated by dividing the full-scale

output voltage by 2. Its value is one-half of full-scale.

Full-scale error drift is defined as the change in

full-scale error with

Full-scale error drift is expressed in units of

%FSR/°C.

a change in temperature.

Relative Accuracy or Integral Nonlinearity (INL)

Offset Error Drift

Relative accuracy or integral nonlinearity (INL) is

defined as the maximum deviation between the real

transfer function and a straight line passing through

the endpoints of the ideal DAC transfer function. INL

is measured in LSBs.

Offset error drift is defined as the change in offset

error with a change in temperature. Offset error drift

is expressed in µV/°C.

Zero-Code Error Drift

Differential Nonlinearity (DNL)

Zero-code error drift is defined as the change in

Differential nonlinearity (DNL) is defined as the

maximum deviation of the real LSB step from the

ideal 1LSB step. Ideally, any two adjacent digital

codes correspond to output analog voltages that are

exactly one LSB apart. If the DNL is within ±1LSB,

the DAC is said to be monotonic.

zero-code error with

Zero-code error drift is expressed in µV/°C.

a change in temperature.

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Gain Temperature Coefficient

Digital Feedthrough

The gain temperature coefficient is defined as the

change in gain error with changes in temperature.

The gain temperature coefficient is expressed in ppm

of FSR/°C.

Digital feedthrough is defined as impulse seen at the

output of the DAC from the digital inputs of the DAC.

It is measured when the DAC output is not updated. It

is specified in nV-s, and measured with a full-scale

code change on the data bus; that is, from all '0's to

all '1's and vice versa.

Power-Supply Rejection Ratio (PSRR)

Power-supply rejection ratio (PSRR) is defined as the

ratio of change in output voltage to a change in

supply voltage for a full-scale output of the DAC. The

PSRR of a device indicates how the output of the

DAC is affected by changes in the supply voltage.

PSRR is measured in decibels (dB).

Channel-to-Channel DC Crosstalk

Channel-to-channel dc crosstalk is defined as the dc

change in the output level of one DAC channel in

response to a change in the output of another DAC

channel. It is measured with a full-scale output

change on one DAC channel while monitoring

another DAC channel remains at midscale. It is

expressed in LSB.

Monotonicity

Monotonicity is defined as a slope whose sign does

not change. If a DAC is monotonic, the output

changes in the same direction or remains at least

constant for each step increase (or decrease) in the

input code.

Channel-to-Channel AC Crosstalk

AC crosstalk in a multi-channel DAC is defined as the

amount of ac interference experienced on the output

of a channel at a frequency (f) (and its harmonics),

when the output of an adjacent channel changes its

value at the rate of frequency (f). It is measured with

one channel output oscillating with a sine wave of

1kHz frequency, while monitoring the amplitude of

1kHz harmonics on an adjacent DAC channel output

(kept at zero scale). It is expressed in dB.

DYNAMIC PERFORMANCE

Dynamic performance parameters are specifications

such as settling time or slew rate, which are important

in applications where the signal rapidly changes

and/or high frequency signals are present.

Slew Rate

Signal-to-Noise Ratio (SNR)

The output slew rate (SR) of an amplifier or other

electronic circuit is defined as the maximum rate of

change of the output voltage for all possible input

signals.

Signal-to-noise ratio (SNR) is defined as the ratio of

the root mean-squared (RMS) value of the output

signal divided by the RMS values of the sum of all

other spectral components below one-half the output

frequency, not including harmonics or dc. SNR is

measured in dB.

DV

(t)

OUT

SR = max

Dt

(3)

Total Harmonic Distortion (THD)

Where ΔV_OUT(t) is the output produced by the

amplifier as a function of time t.

Total harmonic distortion + noise is defined as the

ratio of the RMS values of the harmonics and noise

to the value of the fundamental frequency. It is

Output Voltage Settling Time

expressed in

frequency amplitude at sampling rate f_S.

a percentage of the fundamental

Settling time is the total time (including slew time) for

the DAC output to settle within an error band around

its final value after a change in input. Settling times

are specified to within ±0.003% (or whatever value is

specified) of full-scale range (FSR).

Spurious-Free Dynamic Range (SFDR)

Spurious-free dynamic range (SFDR) is the usable

dynamic range of a DAC before spurious noise

interferes or distorts the fundamental signal. SFDR is

the measure of the difference in amplitude between

the fundamental and the largest harmonically or

non-harmonically related spur from dc to the full

Nyquist bandwidth (half the DAC sampling rate, or

f_S/2). A spur is any frequency bin on a spectrum

analyzer, or from a Fourier transform, of the analog

output of the DAC. SFDR is specified in decibels

relative to the carrier (dBc).

Code Change/Digital-to-Analog Glitch Energy

Digital-to-analog glitch impulse is the impulse injected

into the analog output when the input code in the

DAC register changes state. It is normally specified

as the area of the glitch in nanovolts-second (nV-s),

and is measured when the digital input code is

changed by 1LSB at the major carry transition.

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Signal-to-Noise plus Distortion (SINAD)

DAC Output Noise

SINAD includes all the harmonic and outstanding

spurious components in the definition of output noise

power in addition to quantizing any internal random

noise power. SINAD is expressed in dB at a specified

input frequency and sampling rate, f_S.

DAC output noise is defined as any voltage deviation

of DAC output from the desired value (within a

particular frequency band). It is measured with a DAC

channel kept at midscale while filtering the output

voltage within

a band of 0.1Hz to 10Hz and

measuring its amplitude peaks. It is expressed in

terms of peak-to-peak voltage (V_pp).

DAC Output Noise Density

Output

noise

density

is

defined

as

Full-Scale Range (FSR)

internally-generated random noise. Random noise is

characterized as a spectral density (nV/√Hz). It is

measured by loading the DAC to midscale and

measuring noise at the output.

Full-scale range (FSR) is the difference between the

maximum and minimum analog output values that the

DAC is specified to provide; typically, the maximum

and minimum values are also specified. For an n-bit

DAC, these values are usually given as the values

matching with code 0 and 2ⁿ– 1.

Submit Documentation Feedback

35

Product Folder Link(s): DAC8311 DAC8411

PACKAGE OPTION ADDENDUM

www.ti.com

13-Nov-2008

PACKAGING INFORMATION

Orderable Device

DAC8311IDCKR

DAC8311IDCKRG4

DAC8311IDCKT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SC70

DCK

6

3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SC70

DCK

3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

DAC8311IDCKTG4

DAC8411IDCKR

DAC8411IDCKRG4

DAC8411IDCKT

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

DAC8411IDCKTG4

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

6-Nov-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

DAC8311IDCKR

DAC8311IDCKT

DAC8411IDCKR

DAC8411IDCKT

SC70

DCK

6

3000

250

177.8

9.7

2.3

2.52

1.2

4.0

8.0

Q3

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

6-Nov-2008

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DAC8311IDCKR

DAC8311IDCKT

DAC8411IDCKR

DAC8411IDCKT

SC70

DCK

6

3000

250

184.0

50.0

3000

250

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

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amplifier.ti.com

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www.ti.com/clocks

interface.ti.com

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www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DAC8411IDCKRG4
厂家：	TEXAS INSTRUMENTS
描述：	1.8V to 5.5V, 80mA, 14- and 16-Bit, Low-Power, Single-Channel,DIGITAL-TO-ANALOG CONVERTERS in SC70 Package 1.8V至5.5V ， 80毫安， 14位和16位，低功耗，单通道， DIGITAL- TO- ANALOG ，SC70封装转换器转换器数模转换器光电二极管
文件：	总40页 (文件大小：2245K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC8411IDCKRG4 [TI]

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