DAC82001 [TI]
单通道 16 位低干扰噪声、无缓冲电压输出数模转换器 (DAC);型号: | DAC82001 |
厂家: | TEXAS INSTRUMENTS |
描述: | 单通道 16 位低干扰噪声、无缓冲电压输出数模转换器 (DAC) 转换器 数模转换器 |
文件: | 总31页 (文件大小:2345K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DAC82001
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
DAC82001 16 位、低毛刺脉冲、单通道电压输出、非缓冲DAC
1 特性
3 说明
• 16 位性能:1-LSB DNL 和2-LSB INL
• 低毛刺脉冲能量:0.5nV-s
• 快速稳定:1µs
16 位 DAC82001 是一款具有非缓冲电压输出的高精
度、低功耗、单通道数模转换器(DAC)。
DAC82001 由 3.3V 和 5V 电源供电,并提供 1‑LSB
DNL 和 2‑LSB INL 的线性度。高精度与微型封装相结
合,使得该器件成为增益和偏移校准、电压设定点生成
和电源控制等应用的理想选择。DAC82001 包含一个
上电复位 (POR) 电路。POR 电路可确保 DAC 输出根
据 RSTSEL 引脚的状态在零刻度或中间刻度上电,并
保持在该刻度,直到将有效代码写入器件。所有内部寄
存器都会在RESET 引脚被拉低后异步复位。
• 宽电源:2.7V 至5.5V
• 宽基准范围:2.0 V 至VDD
• 低功耗:250µA(5.0 V 时)
• 3 线制串行外设接口(SPI),频率高达50MHz
• 复位至零标度或中标度
• 1.62V VIH (VDD = 5.5V)
• 温度范围:–40°C 至+85°C
• 封装:微型10 引脚WSON
DAC82001 使用一个以高达50MHz 的时钟速率运行的
多功能3 线制串行外设接口(SPI)。
2 应用
• 示波器(DSO)
• 电池测试
• 半导体测试
• 超声波扫描仪
• 直流电源、交流电源、电子负载
封装信息
封装(1)
封装尺寸(标称值)
器件型号
DAC82001
DRX(WSON,10) 2.50mm × 2.50mm
(1) 如需了解所有可用封装,请参阅数据表末尾的封装选项附录。
VDD
VREF
0 V to +VREF
Single-Ended
Op
Amp
Input
DAC82001
REF
Output
SYNC
SCLK
Buffer
Op
Amp
DAC
Buffer
DAC
Register
Differential
Output
DAC
VOUT
SDIN
Single-
Ended to
RESET
Differential
Conversion
RSTSEL
Power On Reset
AGND
用于生成时间增益补偿(TGC) 控制的DAC82001
功能方框图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBASAK3
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
Table of Contents
7.4 Device Functional Modes..........................................14
7.5 Programming............................................................ 15
7.6 Register Maps...........................................................16
8 Application and Implementation..................................18
8.1 Application Information............................................. 18
8.2 Typical Applications.................................................. 18
8.3 Power Supply Recommendations.............................22
8.4 Layout....................................................................... 22
9 Device and Documentation Support............................23
9.1 Documentation Support............................................ 23
9.2 接收文档更新通知..................................................... 23
9.3 支持资源....................................................................23
9.4 Trademarks...............................................................23
9.5 Electrostatic Discharge Caution................................23
9.6 术语表....................................................................... 23
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements..................................................7
6.7 Timing Diagram ..........................................................7
6.8 Typical Characteristics................................................8
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................12
7.3 Feature Description...................................................13
Information.................................................................... 23
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision * (September 2022) to Revision A (November 2022)
Page
• 将器件状态从“预告信息(预发布)”更改为“量产数据(正在供货)”.........................................................1
Copyright © 2023 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
5 Pin Configuration and Functions
VDD
VOUT
1
2
3
4
5
10
9
VREF
NC
RSTSEL
AGND
8
SDIN
SYNC
SCLK
7
RESET
6
Not to scale
图5-1. DRX (10-Pin WSON) Package, Top View
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
AGND
NC
NO.
4
Ground
Ground reference point for all circuitry on the device.
Do not connect
9
—
Asynchronous reset. Active low. If RESET is low, all DAC channels reset either to zero-scale
(RSTSEL = AGND) or to midscale (RSTSEL = VDD).
RESET
5
3
Input
Input
Reset select pin.
DAC powers up to zero scale if RSTSEL = AGND.
RSTSEL
DAC powers up to midscale if RSTSEL = VDD
.
SCLK
SDIN
6
8
Input
Input
Serial interface clock of SPI.
Serial interface data input of SPI. Data are clocked into the input shift register on each falling edge
of the SCLK pin.
Serial data enable of SPI. Active low. This input is the frame-synchronization signal for the serial
data. When the signal goes low, the serial interface input shift register is enabled.
SYNC
7
Input
VDD
1
2
Power
Output
Input
Analog supply voltage (2.7 V to 5.5 V)
Analog output voltage from DAC
VOUT
VREF
10
This pin is the external reference input to the device.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–10
–40
–65
MAX
UNIT
VDD to AGND
6
VDD + 0.3
VDD + 0.3
VDD + 0.3
10
VS
Input voltage
VREF to AGND
V
Digital inputs to AGND
Output voltage, VOUT to AGND
Input current into any digital pin
Junction temperature
V
mA
°C
°C
TJ
150
Tstg
Storage temperature
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
±1500
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
MAX
UNIT
POWER SUPPLY
VS
Positive supply voltage to ground, VDD to AGND
5.5
V
DIGITAL INPUTS
VIH
Input high voltage
Input low voltage
1.62
V
V
VIL
0.45
VDD
85
REFERENCE INPUT
VREF
Reference voltage to ground, VREF to AGND
Operating temperature
2.0
V
TEMPERATURE
TA
°C
–40
6.4 Thermal Information
DAC82001
DRX (WSON)
10 PINS
99.7
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
49.9
35.9
1.7
ΨJT
Copyright © 2023 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
DAC82001
THERMAL METRIC(1)
DRX (WSON)
10 PINS
35.7
UNIT
Junction-to-board characterization parameter
°C/W
ΨJB
(1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
all minimum and maximum values at TA = –40°C to +85°C and all typical values at TA = 25°C, 2.7 V ≤VDD ≤5.5 V,
2.0 V ≤VREF ≤5.5 V , AGND = 0 V, and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE
Resolution
16
–2
Bits
LSB
LSB
INL
Integral nonlinearity
Differential nonlinearity
Total unadjusted error
Zero code error
±0.6
±0.5
0.04
0.5
2
1
DNL
TUE
–1
0.06 %FSR
–0.06
–2.6
2.6
LSB
Zero code error temperature
coefficient
±0.02
ppm/°C
Gain error
4
20
LSB
–20
Gain error temperature coefficient
±0.1
ppm/°C
OUTPUT CHARACTERISTICS
VO
ZO
Output voltage
0
VREF
V
Output impedance
6.25
5
kΩ
DAC at midscale; VDD = 5 V ±10%,
VREF = 2.5 V
PSRR DC Power supply rejection ratio (dc)
μV/V
DYNAMIC PERFORMANCE
ts
Output voltage settling time
Output noise
To 1/2 LSB of FS, CL = 10 pF
1
0.1
10
µs
DAC at midcode, 0.1 Hz to 10 Hz
DAC at midcode, measured at 10 kHz
μVPP
nV/√Hz
Output noise density
1-kHz sinusoid at DAC output (unbuffered,
full scale), DAC updated at 200 kSPS with
40-kHz low-pass filter, include up to 7th
harmonics
SFDR
THD
Spurious free dynamic range
Total harmonic distortion
dB
–96
1-kHz sinusoid at DAC output (unbuffered,
full scale), DAC updated at 200 kSPS with
40-kHz low-pass filter, include up to 7th
harmonics
dB
dB
–91
–72
DAC at midscale, VREF = 2.5 V,
VDD = 5 V ±200 mV at 10 kHz
PSRR AC Power supply rejection ratio (ac)
Code change glitch impulse
Digital feedthrough
±1 LSB around major carry
0.5
0.5
0.8
nV-s
nV-s
V
Power on glitch magnitude
VOLTAGE REFERENCE INPUT
Reference input voltage
CLOAD = 10 pF
2.0
5
VDD
V
ZREF
CREF
Reference input impedance
Reference input capacitance
kΩ
pF
75
DIGITAL INPUTS
Hysteresis voltage
0.4
V
Input current
5
µA
–5
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
6.5 Electrical Characteristics (continued)
all minimum and maximum values at TA = –40°C to +85°C and all typical values at TA = 25°C, 2.7 V ≤VDD ≤5.5 V,
2.0 V ≤VREF ≤5.5 V , AGND = 0 V, and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pin capacitance
Per pin
10
pF
POWER
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
250
250
350
350
IDD
Power-supply current
Power
µA
750
1050
1750
µW
1250
Copyright © 2023 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
6.6 Timing Requirements
all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤VDD ≤5.5 V,
VIH = 1.62 V, VIL = 0.15 V, 2.0 V ≤VREF ≤5.5 V, and TA = –40°C to +85°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
MHz
ns
fSCLK
SCLK frequency
50
tSCLKHIGH
tSCLKLOW
tSDIS
SCLK high time
9
9
SCLK low time
ns
SDIN setup
5
ns
tSDIH
SDIN hold
10
13
10
160
15
1
ns
tSYNCS
SYNC falling edge to SCLK falling edge setup
SCLK falling edge to SYNC rising edge
SYNC high time
ns
tSYNCH
ns
tSYNCHIGH
tSYNCIGNORE
tDACWAIT
ns
SCLK falling edge to SYNC ignore
Sequential DAC update wait time
ns
µs
6.7 Timing Diagram
tSYNCHIGH
tSYNCH
tSYNCS
SYNC
SCLK
tSYNCIGNORE
tSCLKLOW
tSCLKHIGH
SDIN
Bit 23
Bit 1
Bit 0
tSDIH
tSDIS
图6-1. Timing Diagram
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
6.8 Typical Characteristics
at TA = 25°C, channel output shown, and DAC outputs unloaded (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
85 C
25 C
-40 C
85 C
25 C
-40 C
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
0
8192 16384 24576 32768 40960 49152 57344 65535
DAC Code
0
8192 16384 24576 32768 40960 49152 57344 65535
DAC Code
VDD = 5.5 V, VREF = 5.0 V
VDD = 2.7 V, VREF = 2.5 V
图6-2. Integral Linearity Error vs Digital Input Code
图6-3. Integrated Linearity Error vs Digital Input Code
0.5
0.4
0.3
0.2
0.1
0
0.4
-40 C
25 C
85 C
-40 C
25 C
85 C
0.3
0.2
0.1
0
2
1
8
6
4
2
0
2
4
6
8
1
2
.
1
8
6
4
2
0
2
4
6
.
0
8
.
1
.
.
.
.
-
.
.
-
1.
0.
0.
0.
0.
-
0
0
0
0
1
0.
0.
0.
0.
-
0
0
0
-
-
-
-
-
-
-
Maximum/Minimum Integral Nonlinearity Error (LSB)
VDD = 2.7 V, VREF = 2.5 V
Maximum/Minimum Integral Nonlinearity Error (LSB)
VDD = 5.5 V, VREF = 5.0 V
图6-5. Integrated Linearity Error Histogram
图6-4. Integral Linearity Error Histogram
0.4
0.3
0.2
0.1
0
85 C
25 C
-40 C
-0.1
-0.2
-0.3
-0.4
0
8192 16384 24576 32768 40960 49152 57344 65535
DAC Code
VDD = 5.5 V, VREF = 5.0 V
VDD = 2.7 V, VREF = 2.5 V
图6-6. Differential Linearity Error vs Digital Input Code
图6-7. Differential Linearity Error vs Digital Input Code
Copyright © 2023 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
6.8 Typical Characteristics (continued)
at TA = 25°C, channel output shown, and DAC outputs unloaded (unless otherwise noted)
5
0
-40 C
25 C
85 C
-5
-10
-15
-20
-25
-30
0
8192 16384 24576 32768 40960 49152 57344 65535
DAC Code
VDD = 5.5 V, VREF = 5.0 V
VDD = 2.7 V, VREF = 2.5 V
图6-8. Total Unadjusted Error vs Digital Input Code
图6-9. Total Unadjusted Error vs Digital Input Code
1.5
-8
VREF = 2.5 V
VREF = 5.0 V
1.4
1.3
1.2
1.1
1
-9
-10
-11
VDD = 2.7 V
VDD = 5.5 V
-12
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (C)
Temperature (C)
图6-10. Zero-Code Error vs Temperature
图6-11. Gain Error vs Temperature
280
270
260
250
240
230
220
10
8
VDD = 5.5 V
VDD = 2.7 V
6
4
2
VDD = 5.5 V
VDD = 2.7 V
0
-40
-40
-15
10
35
60
85
-15
10
35
60
85
Temperature (C)
Temperature (C)
图6-12. Supply Current vs Temperature
图6-13. Power-down Current vs Temperature
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
6.8 Typical Characteristics (continued)
at TA = 25°C, channel output shown, and DAC outputs unloaded (unless otherwise noted)
SYNC
DAC (20 mV/div)
Time (100 ns/div)
VDD = 5.5 V, VREF = 5.0 V,
VDD = 5.5 V, VREF = 5.0 V,
DAC code transition from midscale to midscale - 1 LSB
DAC code transition from midscale –1 to midscale LSB
图6-15. Glitch Impulse, Falling Edge, 1-LSB Step
图6-14. Glitch Impulse, Rising Edge, 1-LSB Step
SYNC
DAC ( 0.5 V/div)
Time (100 ns/div)
VDD = 2.7 V, VREF = 2.5 V
VDD = 2.7 V, VREF = 2.5 V
图6-16. Full-Scale Settling Time, Rising Edge
图6-17. Full-Scale Settling Time, Falling Edge
6
VDD (1 V/div)
VREF (1 V/div)
DAC Output (50mV/div)
VDD (V)
VREF (V)
DAC Output
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-0.5
0
1
2
3
4
5
6
7
8
9
10
Time (ms)
Time (1 ms/div)
VDD = 5.5 V, VREF = 5.0 V
图6-18. Power-On Glitch
VDD = 5.5 V, VREF = 5.0 V
图6-19. Power-Off Glitch
Copyright © 2023 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
6.8 Typical Characteristics (continued)
at TA = 25°C, channel output shown, and DAC outputs unloaded (unless otherwise noted)
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
1
10
100
1000
10000 100000 1000000
Frequency (Hz)
VDD = 5.5 V, VREF = 5.0 V
VDD = 5.5 V, DAC code at midscale
图6-20. Power-Supply Rejection Ratio (PSRR)
图6-21. Output Noise Density vs Frequency
700
600
500
400
300
200
100
0
SCLK (2.7 V/div)
VOUT (200 V/div)
VREF = 2.5 V
VREF = 5.0 V
0
8192 16384 24576 32768 40960 49152 57344 65535
DAC Code (LSB)
Time (100 ns/div)
VDD = 2.7 V, VREF = 2.5 V
图6-22. Reference Current vs Digital Input Code
图6-23. Clock Feedthrough
6
5
SYNC (2.7 V/div)
VOUT (150 V/div)
RESET
DAC Output
4
3
2
1
0
-1
Time (200 ns/div)
Time (50 ns/div)
VDD = 5.5 V, VREF = 5.0 V
VDD = 2.7 V, VREF = 2.5 V
图6-25. RESET Response
图6-24. Control Feedthrough
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
7 Detailed Description
7.1 Overview
The DAC82001 device is a single-channel, unbuffered voltage output, 16‑bit digital-to-analog converter (DAC)
operating from a single 3.3-V to 5-V power supply. This converter provides 1-LSB DNL and 2-LSB INL linearity.
With a 10-pF load, the output of the DAC82001 settles to ½ LSB of full scale at 1 µs. The glitch impulse of 1-LSB
code change around major carry is 0.5 nV-s.
The device incorporates a power-on-reset circuit to make sure that the DAC output powers up at zero scale or
midscale, depending on status of the RSTSEL pin, and remains at that scale until a valid code is written to the
device. All internal registers are asynchronously reset after the RESET pin is pulled low. Similar to the power-on-
reset, the RESET signal sets the DAC output to zero scale or midscale based on the status of the RSTSEL pin.
The digital interface of the DAC82001 uses a 3-wire serial peripheral interface (SPI) that operates at clock rates
of up to 50 MHz.
7.2 Functional Block Diagram
VDD
VREF
SYNC
SCLK
DAC
DAC
DAC
VOUT
Buffer
Register
SDIN
RESET
RSTSEL
Power On Reset
AGND
Copyright © 2023 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
7.3 Feature Description
7.3.1 Digital-to-Analog Converter (DAC) Architecture
The output channel in the DAC82001 device consists of a segmented R-2R architecture. 图 7-1 shows a block
diagram of the DAC architecture. The four MSBs of the 16-bit data word are decoded to drive 15 switches, E1 to
E15. Each of these switches connects one of 15 matched resistors to either AGND or VREF. The remaining 12
bits of the data word drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder network.
R
R
VOUT
2R
2R
2R
S1
2R
2R
E1
2R
E2
2R
S0
S11
E15
VREF
GND
4 MSBs Decoded into
15 Equal Segments
12-Bit R-2R Ladder
图7-1. DAC82001 DAC Block Diagram
7.3.1.1 DAC Transfer Function
The input data writes to the individual DAC data registers in straight binary format. After a power-on or a reset
event, all DAC registers are set to zero code (RSTSEL = AGND) or midscale code (RSTSEL = VDD). The DAC
transfer function is shown by 方程式1.
DAC_DATA
V
=
× V
(1)
OUT
REF
N
2
where:
• N = 16 (resolution in bits)
• DAC_DATA = decimal equivalent of the binary code that is loaded to the DAC register (address 8h),
DAC_DATA ranges from 0 to 2N –1
• VREF = DAC external reference voltage. VREF ranges from 2.0 V to VDD
7.3.1.2 DAC Register Structure
Data written to the DAC data registers are initially stored in the DAC buffer registers. The update mode of the
DAC output is determined by the status of the DAC_SYNC_EN bit (address 2h).
In asynchronous mode (default, DAC_SYNC_EN = 0), a write to the DAC buffer register results in an immediate
update of the DAC active register. The DAC output (VOUT pin) updates on the rising edge of SYNC.
In synchronous mode (DAC_SYNC_EN = 1), writing to the DAC buffer register does not automatically update
the DAC active register. Instead, the update occurs only after a software LDAC trigger event. A software LDAC
trigger generates through the LDAC bit in the TRIGGER register (address 5h).
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
7.3.2 Power-On Reset (POR)
The DAC82001 device includes a power-on reset function that controls the output voltage at power up. After the
VDD supply has been established, a POR event is issued. The POR causes all registers to initialize to default
values, and communication with the device is valid only after a 250-µs, power-on-reset delay. The default value
for all DACs is zero code if RSTSEL = AGND, and midscale code if RSTSEL = VDD. The DAC channel remains
at the power-up voltage until a valid command is written to the channel.
When the device powers up, a POR circuit sets the device to the default mode. 图 7-2 shows that the POR
circuit requires specific VDD levels to make sure that the internal capacitors discharge and reset the device at
power up. To make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms. When VDD drops to
less than 2.2 V but remains greater than 0.7 V (shown as the undefined region in 图7-2), the device may or may
not reset under all specified temperature and power-supply conditions; in this case, initiate a POR. When VDD
remains greater than 2.2 V, a POR does not occur.
VDD (V)
5.50
Specified supply
voltage range
No power-on reset
2.70
2.20
Undefined
0.70
Power-on reset
0.00
图7-2. Threshold Levels for the VDD POR Circuit
7.3.3 Hardware Reset
The DAC output is asynchronously set to zero code if RSTSEL = AGND, and midscale code if RSTSEL = VDD
,
immediately after the RESET pin is brought low. The RESET signal resets all internal registers, meaning all
registers initialize to default values. Bring the RESET pin back to high before a write sequence starts. Similar to
the POR delay, communication with the device is valid only after a 250‑µs delay. The default value for the DAC
channel remains at the reset voltage until a valid command is written to the channel. The RSTSEL pin can be
reconfigured without a power cycle. The DAC output always reflects the current RSTSEL status when the
RESET pin is pulled low.
7.3.4 Software Reset
A device software reset event is initiated by writing the reserved code 0x1010 to the SOFT-RESET bits in the
TRIGGER register (address 5h). A software reset initiates a POR event.
7.4 Device Functional Modes
The DAC82001 has one mode of operation: normal.
In normal mode, the DAC82001 is fully operational. The device translates digital input or reset input to
corresponding analog output.
Copyright © 2023 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
7.5 Programming
7.5.1 Serial Peripheral Interface (SPI)
The DAC82001 is controlled through a 3-wire serial peripheral interface (SPI) using SYNC, SCLK, and SDIN.
The serial interface operates at up to 50 MHz. The input shift register is 24-bits wide.
表7-1 shows the SPI frame format.
表7-1. SPI Frame Format
BIT
23
22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DESC
W
Register Address - Command Byte 16-Bit MSB-Aligned DAC Data
Serial clock SCLK is a continuous or a gated clock. The first falling edge of SYNC starts the operation cycle.
When SYNC is high, the SCLK and SDIN signals are blocked. The device internal registers are updated from the
shift register on the rising edge of SYNC.
7.5.1.1 SYNC Interrupt
For SPI operation, the SYNC line stays low for at least 24 falling edges of SCLK, and the addressed DAC
register updates on the SYNC rising edge. However, if the SYNC line is brought high before the 24th SCLK
falling edge, this event acts as an interrupt to the write sequence. The shift register resets and the write
sequence is discarded. As 图 7-3 shows, the data buffer contents and the DAC register contents do not update,
and the operating mode does not change.
SCLK
1
2
24
SYNC
SDIN
DB23
DB0
Invalid or interrupted write sequence
2
SCLK
1
24
SYNC
SDIN
DB23
DB0
Valid write sequence
图7-3. SYNC Interrupt
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
7.6 Register Maps
7.6.1 Registers
表7-2. DAC82001 Registers
Offset
0h
Register Description
Section
No Operation
Synchronization
Trigger
NOOP Register
SYNC Register
TRIGGER Register
DAC Register
2h
5h
8h
DAC
7.6.1.1 NOOP Register (offset = 0h) [reset = 0000h]
图7-4. NOOP Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOOP
W-0h
表7-3. NOOP Register Field Descriptions
Bit
15-0
Field
NOOP
Type
Reset
Description
W
0h
No operation command
Copyright © 2023 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
7.6.1.2 SYNC Register (offset = 2h) [reset = 0000h]
图7-5. SYNC Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
DAC-SYNC-
EN
W-0h
W-0h
表7-4. SYNC Register Field Descriptions
Bit
Field
RESERVED
DAC-SYNC-EN
Type
Reset
Description
15-1
0
W
0h
These bits are reserved.
W
0h
When set to 1, the DAC output is set to update in response to an
LDAC trigger (synchronous mode).
When cleared to 0, the DAC output is set to update immediately
(asynchronous mode), default.
7.6.1.3 TRIGGER Register (offset = 5h) [reset = 0000h]
图7-6. TRIGGER Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
W-0h
LDAC
W-0h
SOFT-RESET [3:0]
W-0h
表7-5. TRIGGER Register Field Descriptions
Bit
Field
Type
Reset
Description
15-5
4
RESERVED
LDAC
W
0h
These bits are reserved.
W
0h
Set this bit to 1 to synchronously load the DAC that is set to
synchronous mode in the SYNC register. This bit self-resets.
3-0
SOFT-RESET [3:0]
W
0h
When set to reserved code 1010, this bit resets the device to the
default state. This bit self-resets.
7.6.1.4 DAC Register (offset = 8h) [reset = 0000h when RSTSEL is logic low, or reset = 8000h when
RSTSEL is logic high]
图7-7. DAC Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAC-DATA [15:0]
W-0000h when RSTSEL is logic low or 8000h when RSTSEL is logic high
表7-6. DAC Data Register Field Descriptions (8h)
Bit
15-0
Field
DAC-DATA [15:0]
Type
Reset
Description
W
0000h when
RSTSEL is
logic low
Data are MSB aligned in straight binary format.
or
8000h when
RSTSEL is
logic high
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
Generating accurate, stable, programmable dc voltages is a key requirement in most precision end equipment.
The DAC82001 serves a wide range of end equipment, such as battery testers, communications equipment,
factory automation and control, test and measurement. The DAC82001 tiny package, high resolution, fast
settling, and simple interface makes this device an excellent choice for applications such as offset and gain
control, arbitrary waveform generation (AWG), closed-loop control, and bipolar analog outputs. A wide variety of
operational amplifiers can be used as output buffers for the DAC82002, allowing the user to choose components
that best fit their design.
8.2 Typical Applications
8.2.1 Arbitrary Waveform Generator
Arbitrary waveform generation (AWG) circuits are common in test and measurement equipment. These circuits
are used to generate ac waveforms for test applications. The key performance parameters in test and
measurement circuits are total harmonic distortion and noise (THD+N), signal-to-noise ratio (SNR), and the
update rate. 图8-1 shows a basic example of an AWG circuit using the DAC82001.
VDD
VREF
100 nF
47 pF
5 V
–
+
VOUT
DAC82001
OPA328
图8-1. Arbitrary Waveform Generator
8.2.1.1 Design Requirements
• DAC output range: 0 V to 2.5 V
• THD+N at 1 kHz: < –91 dB
• Update rate: 200 kHz
8.2.1.2 Detailed Design Procedure
图 8-1 shows a simplified circuit diagram of an arbitrary waveform generator. The DAC82001 specifies a THD+N
of –91 dB at 1 kHz. The OPA328 provides a great balance between fast settling, bandwidth, and voltage and
current noise. The buffer must have a negative voltage supply rail or an output offset to make sure the DAC
output is not clipped. Attach two decoupling capacitors as close as possible to the VREF pin. Use 100 nF for the
first capacitor to provide very good noise performance for the system. Use 47 pF for the second capacitor to
allow for a good dynamic response performance that improves any code-to-code glitch. The REF5025 is a low-
noise, very low-drift, precise voltage reference that generates a 2.5-V reference for this application.
Copyright © 2023 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
8.2.1.3 Application Curves
图 8-2 shows the THD+N plot vs frequency of the buffer output using a 20-Hz to 20-kHz sine wave sweep with a
DAC code range of 0x81FF ± 0x7E00 to prevent voltage clipping. A 40-kHz low-pass filter is also used in the
measurement tool.
-65
-70
-75
-80
-85
-90
-95
20
100
1k
Frequency (Hz)
10k 20k
20-Hz to 20-kHz sine wave sweep with a code range of 0x81FF ± 0x7E00
40-kHz low-pass filter
图8-2. THD+N vs Frequency
图 8-3 shows the FFT of the buffer output using a 1-kHz sine wave with a code range of 0x81FF ± 0x7E00 to
prevent voltage clipping. 32768 bins, 8 averages, and a 40-kHz low-pass filter are also used in the measurement
tool.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
10
100
1000
10000
40000
Frequency (Hz)
1-kHz sine wave with a code range of 0x81FF ± 0x7E00
32768 bins, 8 averages, 40-kHz low-pass filter
图8-3. FFT Amplitude vs Frequency
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
8.2.2 Bipolar Analog Output Configuration
Programmable logic circuits (PLCs) have analog output modules that typically output ±10 V. This bipolar analog
output circuit converts the unipolar DAC output to a bipolar ±10-V output. The key performance parameters of
these circuits are noise and slew rate. The circuit can also be used to force voltage in semiconductor test
applications. 图8-4 shows the example configuration using the DAC82001.
VDD VREF
15 V
OPA210
DAC82001
+
VOP
VOUT
–
–15 V
8.25 k
VREF
33.2 k
100 pF
11 k
图8-4. Bipolar Analog Output Circuit
8.2.2.1 Design Requirements
• DAC output range: 0 V to 2.5 V
• PLC analog output range: –10 V to +10 V
• Noise: < 3 µV/√Hz
• Slew rate: > 1 V/µs
8.2.2.2 Detailed Design Procedure
The OPA210 output buffer provides a balance between fast settling, bandwidth, voltage and current noise, and
wide voltage rails. The buffer uses ±15-V voltage rails to make sure there is no voltage clipping. The REF5025 is
a low-noise, very low-drift, precise voltage reference and is used to generate a stable 2.5-V reference for this
application. To further reduce noise, use a 100-pF capacitor between the non-inverting input pin and the output
of the OPA210.
8.2.2.3 Application Curves
图 8-5 shows the noise on the buffer output vs frequency using a 100-Hz to 1-MHz frequency sweep with a
grounded reference to isolate the noise in the circuit.
Copyright © 2023 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
2000
1800
1600
1400
1200
1000
800
600
400
200
0
100
1k
10k
Frequency (Hz)
100k
1M
图8-5. Noise vs Frequency
图 8-6 shows the output of the circuit rising from –10 V to +10 V, with the DAC starting at code 0x0000 and
ending at code 0xFFFF. The measured slew rate is 2.5 V/µs. The REF5025 is used as a 2.5-V reference.
12
DAC SYNC
DAC OUT
BUFFER OUT
10
8
6
4
2
0
-2
-4
-6
-8
-10
-12
-5
-3
-1
1
3
5
7
9
11
13
15
Time (µs)
DAC at code 0x0000 rising to code 0xFFFF
图8-6. Bipolar Output Rising Slew Rate
图 8-7 shows the output of the circuit falling from +10 V to –10 V, with the DAC starting at code 0xFFFF and
ending at code 0x0000. This measured slew rate is 2.5 V/µs. The REF5025 is used as a 2.5-V reference.
12
DAC SYNC
DAC OUT
BUFFER OUT
10
8
6
4
2
0
-2
-4
-6
-8
-10
-12
-5
-3
-1
1
3
5
7
9
11
13
15
Time (µs)
DAC at code 0xFFFF falling to code 0x0000
图8-7. Bipolar Output Falling Slew Rate
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
8.3 Power Supply Recommendations
The DAC82001 operates within the specified VDD supply range of 2.7 V to 5.5 V. The DAC82001 does not
require specific supply sequencing, but VREF must be less than VDD, as noted in the Absolute Maximum Ratings.
The VDD supply must be well-regulated and low-noise. Switching power supplies and DC/DC converters often
have high-frequency glitches or spikes riding on the output voltage. Digital components also create similar high-
frequency spikes. This noise can easily couple into the DAC output voltage through various paths between the
power connections and analog output. To further minimize noise from the power supply, include a 1-μF to 10-
μF capacitor and 0.1-μF bypass capacitor.
8.4 Layout
8.4.1 Layout Guidelines
A precision analog component requires careful layout. The following list provides some insight into good layout
practices.
• Bypass the VDD to ground with a low ESR ceramic bypass capacitor. The typical recommended bypass
capacitance is 0.1-µF to 0.22-µF ceramic capacitor, with a X7R or NP0 dielectric.
• Bypass VREF to ground with low ESR ceramic bypass capacitors.
• Place power supplies and REF bypass capacitors close to the pins to minimize inductance and optimize
performance.
• The output pin, VOUT, has relatively high impedance and is susceptible to high parasitic capacitance. Use
short and direct traces when routing VOUT.
8.4.2 Layout Example
GND
GND
Reference
Bypass
Capacitor
Decoupling
Capacitor
DAC82001
VDD
VOUT
1
2
3
4
5
10
9
SDIN
8
Pull-up
7
Resistor
Pull-Down
Resistor
VDD
6
GND
(for Zero
Scale Reset)
GND
SYNC
SCLK
Pull-Down
Resistor
Ground and Power Planes Omitted for Clarity
图8-8. Layout Example
Copyright © 2023 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: DAC82001
DAC82001
www.ti.com.cn
ZHCSQ74A –SEPTEMBER 2022 –REVISED NOVEMBER 2022
9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation see the following: Texas Instruments, DAC82002EVM user's guide
9.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: DAC82001
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC82001DRXR
PDAC82001DRXR
ACTIVE
ACTIVE
WSON
WSON
DRX
DRX
10
10
3000 RoHS & Green
3000 TBD
NIPDAUAG
Level-2-260C-1 YEAR
Call TI
-40 to 85
-40 to 85
D821
Samples
Samples
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC82001DRXR
WSON
DRX
10
3000
178.0
8.4
2.75
2.75
0.95
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WSON DRX 10
SPQ
Length (mm) Width (mm) Height (mm)
205.0 200.0 33.0
DAC82001DRXR
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DRX0010A
WSON - 0.8 mm max height
SCALE 5.000
PLASTIC SMALL OUTLINE - NO LEAD
2.6
2.4
B
A
PIN 1 INDEX AREA
2.6
2.4
C
0.8 MAX
SEATING PLANE
0.08 C
SYMM
(0.2) TYP
1.1
0.9
10X
0.05
0.00
5
6
2X
2
SYMM
8X
0.5
10
1
0.30
0.18
10X
PIN 1 ID
(45 X0.15)
0.1
C A B
C
0.05
4223856/B 01/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DRX0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (1.2)
1
10
10X (0.24)
8X (0.5)
SYMM
6
5
SYMM
(1.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
EXPOSED METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223856/B 01/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DRX0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (1.2)
1
10
10X (0.24)
8X (0.5)
SYMM
5
6
SYMM
(1.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223856/B 01/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更,恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务,TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023,德州仪器 (TI) 公司
相关型号:
DAC8212AV
IC PARALLEL, WORD INPUT LOADING, 12-BIT DAC, CDIP24, CERDIP-24, Digital to Analog Converter
ADI
DAC8212AV883C
PARALLEL, WORD INPUT LOADING, 250 us SETTLING TIME, 12-BIT DAC, CDIP24, CERDIP-24
ROCHESTER
DAC8218SPAG
Octal, 14-Bit, Low-Power, High-Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER
TI
DAC8218SPAGR
Octal, 14-Bit, Low-Power, High-Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER
TI
DAC8218SRGZR
Octal, 14-Bit, Low-Power, High-Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER
TI
DAC8218SRGZT
Octal, 14-Bit, Low-Power, High-Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER
TI
©2020 ICPDF网 联系我们和版权申明