DAC7644_技术文档

®

DAC7644

For most current data sheet and other product

information, visit www.burr-brown.com

16-Bit, Quad Voltage Output

DIGITAL-TO-ANALOG CONVERTER

DESCRIPTION

FEATURES

The DAC7644 is a 16-bit, quad voltage output digital-

to-analog converter with guaranteed 15-bit monotonic

performance over the specified temperature range. It

accepts 16-bit parallel input data, has double-buffered

DAC input logic (allowing simultaneous update of all

DACs), and provides a readback mode of the internal

input registers. Programmable asynchronous reset clears

all registers to a mid-scale code of 8000_Hor to a zero-

scale of 0000_H. The DAC7644 can operate from a single

+5V supply or from +5V and –5V supplies.

● LOW POWER: 10mW

● UNIPOLAR OR BIPOLAR OPERATION

● SETTLING TIME: 10µs to 0.003%

● 15-BIT LINEARITY AND MONOTONICITY:

–40°C to +85°C

● PROGRAMMABLE RESET TO MID-SCALE

OR ZERO-SCALE

● DATA READBACK

● DOUBLE-BUFFERED DATA INPUTS

Low power and small size per DAC make the DAC7644

ideal for automatic test equipment, DAC-per-pin pro-

grammers, data acquisition systems, and closed-loop

servo-control. The DAC7644 is available in a 48-lead

SSOP package and offers guaranteed specifications

over the –40°C to +85°C temperature range.

APPLICATIONS

● PROCESS CONTROL

● CLOSED-LOOP SERVO-CONTROL

● MOTOR CONTROL

● DATA ACQUISITION SYSTEMS

● DAC-PER-PIN PROGRAMMERS

V_REF

L

V_REF

H

AB Sense

V_REFL AB V_REFH AB

V_DD

V_SS

V_CC

DAC7644

16

I/O

Buffer

Input

Register A

DAC

Register A

DATA I/O

DAC A

V_OUT

A

V_OUT

Sense

Input

Register B

DAC

Register B

DAC B

DAC C

DAC D

V_OUT

B

V_OUT

A1

A0

Input

Register C

DAC

Register C

Control

Logic

V_OUT

C

CS

R/W

V_OUT

Input

Register D

DAC

Register D

V_OUT

D

V_OUT

V_REFL CD V_REFH CD

V_REF

CD Sense

L

V_REF

CD Sense

H

AGND DGND

RST

RSTSEL LOADDACS

International Airport Industrial Park

•

Mailing Address: PO Box 11400, Tucson, AZ 85734

•

Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706

FAX: (520) 889-1510

•

Tel: (520) 746-1111

Twx: 910-952-1111

•

Internet: http://www.burr-brown.com/

•

Cable: BBRCORP Telex: 066-6491

•

Immediate Product Info: (800) 548-6132

®

^PDS-1^1535B

^PD^rintA^edC^{in U}7^.S6^.A4^.4^{November, 1999}

SBAS121

SPECIFICATIONS (Dual Supply)

At T_A= T_MINto T_MAX, V_DD= V_CC= +5V, V_SS= –5V, V_REFH = +2.5V, and V_REFL = –2.5V, unless otherwise noted.

DAC7644E

DAC7644EB

TYP

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

MAX

UNITS

ACCURACY

Linearity Error

Linearity Match

±3

±4

±2

±4

±3

±2

±1

±3

±2

LSB

Bits

mV

ppm/°C

mV

ppm/°C

mV

ppm/V

Differential Linearity Error

Monotonicity, T_MINto T_MAX

Bipolar Zero Error

Bipolar Zero Error Drift

Full-Scale Error

Full-Scale Error Drift

Bipolar Zero Matching

Full Scale Matching

Power Supply Rejection Ratio (PSRR)

14

15

±1

5

±1

5

±1

10

±2

10

±2

10

±2

✻

Channel-to-Channel Matching

At Full Scale

±1

✻

±2

✻

±2

100

ANALOG OUTPUT

Voltage Output

Output Current

Maximum Load Capacitance

Short-Circuit Current

Short-Circuit Duration

V_REF= –2.5V, R_L= 10kΩ, V_SS= –5V

No Oscillation

V_REF

–1.25

L

V_REF

+1.25

H

✻

V

mA

pF

500

–10, +30

Indefinite

✻

mA

GND or V_CCor V_SS

REFERENCE INPUT

Ref High Input Voltage Range

Ref Low Input Voltage Range

Ref High Input Current

V_REFL + 1.25

–2.5

+2.5

V_REFH – 1.25

✻

V

µA

500

–500

✻

Ref Low Input Current

DYNAMIC PERFORMANCE

Settling Time

Channel-to-Channel Crosstalk

Digital Feedthrough

Output Noise Voltage

DAC Glitch

To ±0.003%, 5V Output Step

8

0.5

2

60

40

10

✻

µs

LSB

nV-s

nV/√Hz

nV-s

See Figure 5.

f = 10kHz

7FFF_Hto 8000_Hor 8000_Hto 7FFF_H

DIGITAL INPUT

V_IH

V_IL

I_IH

0.7 • V_DD

✻

V

µA

0.3 • V_DD

±10

✻

I_IL

DIGITAL OUTPUT

V_OH

V_OL

I_OH= –0.8mA

I_OL= 1.2mA

3.6

4.5

0.3

✻

V

0.4

✻

POWER SUPPLY

V_DD

V_CC

V_SS

I_CC

I_DD

I_SS

+4.75

–5.25

+5.0

–5.0

1.5

50

–1.5

15

+5.25

–4.75

2

✻

V

mA

µA

mA

mW

–2.3

–40

✻

Power

20

✻

TEMPERATURE RANGE

Specified Performance

+85

°C

✻ Specifications same as DAC7644E.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant

any BURR-BROWN product for use in life support devices and/or systems.

®

2

DAC7644

SPECIFICATIONS (Single Supply)

At T_A= T_MINto T_MAX, V_DD= V_CC= +5V, V_SS= 0V, V_REFH = +2.5V, and V_REFL = 0V, unless otherwise noted.

DAC7644E

DAC7644EB

TYP

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

MAX

UNITS

ACCURACY

Linearity Error⁽¹⁾

Linearity Match

Differential Linearity Error

Monotonicity, T_MINto T_MAX

Zero Scale Error

Zero Scale Error Drift

Full-Scale Error

Full-Scale Error Drift

Zero Scale Matching

Full-Scale Matching

Power Supply Rejection Ratio (PSRR)

±3

±4

±2

±4

±3

±2

±1

±3

±2

LSB

Bits

mV

ppm/°C

mV

ppm/°C

mV

ppm/V

14

15

±1

5

±1

5

±1

10

±2

10

±2

10

±2

✻

Channel-to-Channel Matching

At Full Scale

±1

✻

±2

✻

±2

100

ANALOG OUTPUT

Voltage Output

Output Current

Maximum Load Capacitance

Short-Circuit Current

Short-Circuit Duration

V_REFL = 0V, V_SS= 0V, R_L= 10kΩ

No Oscillation

0

V_REF

+1.25

H

✻

V

mA

pF

–1.25

500

±30

Indefinite

✻

mA

GND or V_CC

REFERENCE INPUT

Ref High Input Voltage Range

Ref Low Input Voltage Range

Ref High Input Current

V_REFL + 1.25

0

+2.5

V_REFH – 1.25

✻

V

µA

250

–250

✻

Ref Low Input Current

DYNAMIC PERFORMANCE

Settling Time

Channel-to-Channel Crosstalk

Digital Feedthrough

Output Noise Voltage, f = 10kHz

DAC Glitch

To ±0.003%, 2.5V Output Step

8

0.5

2

60

40

10

✻

µs

LSB

nV-s

nV/√Hz

nV-s

See Figure 6.

7FFF_Hto 8000_Hor 8000_Hto 7FFF_H

DIGITAL INPUT

V_IH

V_IL

I_IH

0.7 • V_DD

✻

V

µA

0.3 • V_DD

±10

✻

I_IL

DIGITAL OUTPUT

V_OH

V_OL

I_OH= –0.8mA

I_OL= 1.2mA

3.6

4.5

0.3

✻

V

0.4

✻

POWER SUPPLY

V_DD

V_CC

V_SS

I_CC

I_DD

Power

+4.75

0

+5.0

0

1.5

50

+5.25

0

✻

V

mA

µA

mW

2

7.5

10

✻

TEMPERATURE RANGE

Specified Performance

–40

+85

✻

°C

NOTE: (1) If V_SS= 0V specification applies at Code 0040_Hand above due to possible negative zero-scale error.

✻ Specifications same as DAC7644E.

®

3

DAC7644

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

V_CCand V_DDto V_SS.............................................................. –0.3V to 11V

V_CCand V_DDto GND ........................................................... –0.3V to 5.5V

V_REFL to V_SS............................................................. –0.3V to (V_CC– V_SS

V_CCto V_REFH ............................................................ –0.3V to (V_CC– V_SS

V_REFH to V_REFL ......................................................... –0.3V to (V_CC– V_SS

Digital Input Voltage to GND ................................... –0.3V to V_DD+ 0.3V

Digital Output Voltage to GND ................................. –0.3V to V_DD+ 0.3V

Maximum Junction Temperature ................................................... +150°C

Operating Temperature Range ........................................–40°C to +85°C

Storage Temperature Range ......................................... –65°C to +125°C

Lead Temperature (soldering, 10s)............................................... +300°C

)

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

PACKAGE/ORDERING INFORMATION

LINEARITY

ERROR

(LSB)

DIFFERENTIAL

NONLINEARITY

(LSB)

PACKAGE

DRAWING

NUMBER⁽¹⁾

SPECIFICATION

TEMPERATURE

RANGE

ORDERING

NUMBER⁽²⁾

TRANSPORT

MEDIA

PRODUCT

PACKAGE

DAC7644E

±4

"

±3

"

±3

"

±2

"

48-Lead SSOP

333

"

333

"

–40°C to +85°C

DAC7644E

DAC7644E/1K

DAC7644EB

Rails

Tape and Reel

Rails

"

DAC7644EB

48-Lead SSOP

–40°C to +85°C

"

DAC7644EB/1K

Tape and Reel

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/)

are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC7644/1K” will get a single

1000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

®

4

DAC7644

PIN CONFIGURATION

Top View

SSOP

DB15

DB14

DB13

DB12

DB11

DB10

DB9

1

2

3

4

5

6

7

8

9

48 NC

47 NC

46 NC

45 NC

44 V_OUTA Sense

43 V_OUT

A

42 V_REFL AB Sense

41 V_REFL AB

DB8

DB7

40 V_REFH AB

DB6 10

DB5 11

39 V_REFH AB Sense

38 V_OUTB Sense

DB4 12

37 V_OUT

36 V_OUTC Sense

35 V_OUT

B

DAC7644

DB3 13

DB2 14

C

DB1 15

34 V_REFH CD Sense

33 V_REFH CD

DB0 16

RSTSEL 17

RST 18

32 V_REFL CD

31 V_REFL CD Sense

30 V_OUTD Sense

LOADDACS 19

R/W 20

29 V_OUT

28 V_SS

D

A1 21

A0 22

27 AGND

26 V_CC

25 V_DD

CS 23

DGND 24

PIN DESCRIPTIONS

NAME

DESCRIPTION

NAME

DESCRIPTION

1

2

DB15

DB14

DB13

DB12

DB11

DB10

DB9

Data Bit 15, MSB

Data Bit 14

Data Bit 13

Data Bit 12

Data Bit 11

Data Bit 10

Data Bit 9

23

24

CS

DGND

V_DD

Chip Select. Active LOW.

Digital Ground

3

25

26

27

28

29

30

Positive Power Supply (digital)

Positive Power Supply (analog)

Analog Ground

4

V_CC

5

AGND

V_SS

6

Negative Power Supply

DAC D Voltage Output

7

V_OUTD

8

DB8

Data Bit 8

V_OUTD Sense

DAC D’s Output Amplifier Inverting Input. Used to

close the feedback loop at the load.

9

DB7

Data Bit 7

31

32

33

34

35

36

V_REFL CD Sense DAC C and D Reference Low Sense Input

10

11

12

13

14

15

16

17

DB6

Data Bit 6

V

_REFL CD

DAC C and D Reference Low Input

DAC C and D Reference High Input

DB5

Data Bit 5

V_REFH CD

DB4

Data Bit 4

V_REFH CD Sense DAC C and D Reference High Sense Input

DB3

Data Bit 3

V_OUTC

DAC C Voltage Output

DB2

Data Bit 2

V

_OUTC Sense

DAC C’s Output Amplifier Inverting Input. Used to

close the feedback loop at the load.

DB1

Data Bit 1

DB0

Data Bit 0, LSB

37

38

V_OUTB

DAC B Voltage Output

RSTSEL

Reset Select. Determines the action of RST. If

HIGH, a RST command will set the DAC registers to

mid-scale. IfLOW, aRSTcommandwillsettheDAC

registers to zero.

_OUTB Sense

DAC B’s Output Amplifier Inverting Input. Used to

close the feedback loop at the load.

39

40

41

42

43

44

V_REFH AB Sense DAC A and B Reference High Sense Input

18

RST

Reset, Rising Edge Triggered. Depending on the

state of RSTSEL, the DAC registers are set to either

mid-scale or zero.

V

_REFH AB

DAC A and B Reference High Input

DAC A and B Reference Low Input

V

_REFL AB

V_REFL AB Sense DAC A and B Reference Low Sense Input

19

20

21

22

LOADDACS

DAC Output Registers Load Control. Rising edge

triggered.

V_OUTA

DAC A Voltage Input

V

_OUTA Sense

DAC A’s Output Amplifier Inverting Input. Used to

close the feedback loop at the load.

R/W

A1

Enabled by the CS, Controls Data Read and Write

from the Input Registers.

45

46

47

48

NC

No Connection

Enabled by the CS, in Combination With A0 Selects

the Individual DAC Input Registers.

A0

Enabled by the CS, in Combination With A1 Selects

the Individual DAC Input Registers.

®

5

DAC7644

TYPICAL PERFORMANCE CURVES: V_SS= 0V

At T_A= +25°C, V_DD= V_CC= +5V, V_SS= 0V, V_REFH= +2.5V, V_REFL= 0V, representative unit, unless otherwise specified.

+25°C

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC A, +25°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC B, +25°C)

2.0

1.5

2.0

1.5

1.0

0.5

0

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

2.0

1.5

2.0

1.5

1.0

0.5

0

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Digital Input Code

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC C, +25°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC D, +25°C)

2.0

1.5

1.0

1.5

1.0

0.5

0

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

2.0

1.5

2.0

1.5

1.0

0.5

0

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Digital Input Code

+85°C

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC B, +85°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC B, +85°C)

2.0

1.5

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0.5

0

–0.5

–1.0

–1.5

–2.0

2.0

1.5

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Digital Input Code

®

6

DAC7644

TYPICAL PERFORMANCE CURVES: V_SS= 0V (CONT)

At T_A= +25°C, V_DD= V_CC= +5V, V_SS= 0V, V_REFH= +2.5V, V_REFL= 0V, representative unit, unless otherwise specified.

+85°C (cont)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC C, +85°C)

(DAC D, +85°C)

2.0

1.5

2.0

1.5

1.0

0.5

0

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

2.0

1.5

2.0

1.5

1.0

0.5

0

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Digital Input Code

–40°C

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC A, –40°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC B, –40°C)

2.0

1.5

2.0

1.5

1.0

0.5

0

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

2.0

1.5

2.0

1.5

1.0

0.5

0

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Digital Input Code

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC C, –40°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC D, –40°C)

2.0

1.5

1.0

0.5

0

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

2.0

1.5

2.0

1.5

1.0

0.5

0

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Digital Input Code

®

7

DAC7644

TYPICAL PERFORMANCE CURVES: V_SS= 0V (CONT)

At T_A= +25°C, V_DD= V_CC= +5V, V_SS= 0V, V_REFH= +2.5V, V_REFL= 0V, representative unit, unless otherwise specified.

FULL-SCALE ERROR vs TEMPERATURE

Code (FFFF_H)

ZERO-SCALE ERROR vs TEMPERATURE

Code (0040_H)

2

1.5

1

2

1.5

1

DAC B

DAC C

DAC D

0.5

0

0.5

0

–0.5

–1

–0.5

–1

DAC A

DAC D

DAC A

DAC B

–1.5

–2

–1.5

–2

–40

–25

0

25

55

85

–40

–25

0

25

55

85

Temperature (°C)

V_REFHCURRENT vs CODE

(all DACs sent to indicated code)

V_REFLCURRENT vs CODE

(all DACs sent to indicated code)

0.30

0.25

0.20

0.15

0.10

0.05

0.00

–0.05

–0.10

–0.15

–0.20

–0.25

–0.30

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Digital Input Code

POSITIVE SUPPLY CURRENT

vs DIGITAL INPUT CODE

POSITIVE SUPPLY CURRENT vs TEMPERATURE

2

No Load

Data = FFFF_H(all DACs)

No Load

1.5

All DACs

One DAC

1

0.5

0

1

0.5

0

–40

–25

0

25

55

85

0000_H0200_H0400_H0800_H1000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Temperature (°C)

Digital Input Code

®

8

DAC7644

TYPICAL PERFORMANCE CURVES: V_SS= 0V (CONT)

At T_A= +25°C, V_DD= V_CC= +5V, V_SS= 0V, V_REFH= +2.5V, V_REFL= 0V, representative unit, unless otherwise specified.

OUTPUT VOLTAGE vs SETTLING TIME

(0V to +2.5V)

(+2.5V to 2mV)

+5V

LDAC

0

+5V

LDAC

0

Large-Signal Settling Time: 0.5V/div

Small-Signal Settling Time: 4LSB/div

Large-Signal Settling Time: 0.5V/div

Time (2µs/div)

OUTPUT VOLTAGE

vs MIDSCALE GLITCH PERFORMANCE

+5V

LDAC

0

+5V

LDAC

0

7FFF_Hto 8000_H

8000_Hto 7FFF_H

Time (1µs/div)

BROADBAND NOISE

OUTPUT NOISE VOLTAGE vs FREQUENCY

1000

100

10

BW = 10kHz

Code = 8000_H

10

100

1000

10000

100000

1000000

Time (10µs/div)

Frequency (Hz)

®

9

DAC7644

TYPICAL PERFORMANCE CURVES: V_SS= 0V (CONT)

At T_A= +25°C, V_DD= V_CC= +5V, V_SS= 0V, V_REFH= +2.5V, V_REFL= 0V, representative unit, unless otherwise specified.

LOGIC SUPPLY CURRENT

vs LOGIC INPUT LEVEL FOR DATA BITS

V_OUTvs R_LOAD

5

4

3

2

1

0

12

10

8

Source

6

4

2

Sink

0

0.01

0.1

1

10

100

0

1

2

3

4

5

R_LOAD(kΩ)

Logic Input Level for Data Bits (V)

®

10

DAC7644

TYPICAL PERFORMANCE CURVES: V_SS= –5V

At T_A= +25°C, V_DD= V_CC= +5V, V_SS= –5V, V_REFH= +2.5V, V_REFL= –2.5V, representative unit, unless otherwise specified.

+25°C

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC A, +25°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC B, +25°C)

2.0

1.5

1.0

0.5

1.0

0

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

2.0

1.5

2.0

1.5

1.0

0.5

0

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Digital Input Code

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC D, +25°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC C, +25°C)

1.0

2.0

1.5

0.5

0

1.0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

0.5

0

–0.5

–1.0

–1.5

–2.0

1.0

0.5

2.0

1.5

0

1.0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Digital Input Code

+85°C

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC B, +85°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC A, +85°C)

1.0

0.5

0

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

1.0

0.5

2.0

1.5

0

1.0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Digital Input Code

®

11

DAC7644

TYPICAL PERFORMANCE CURVES: V_SS= –5V (CONT)

At T_A= +25°C, V_DD= V_CC= +5V, V_SS= –5V, V_REFH= +2.5V, V_REFL= –2.5V, representative unit, unless otherwise specified.

+85°C (cont)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC C, +85°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC D, +85°C)

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–0.5

–1.0

–1.5

–2.0

–2.5

2.0

1.5

1.0

0.5

1.0

0

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Digital Input Code

–40°C

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC B, –40°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC A, –40°C)

1.5

2.0

1.5

1.0

0.5

1.0

0

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

–2.5

2.0

1.5

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Digital Input Code

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC C, –40°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC D, –40°C)

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

–0.5

–1.0

–1.5

–2.0

–2.5

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0

–0.5

–1.0

–1.5

–2.0

–2.5

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Digital Input Code

®

12

DAC7644

TYPICAL PERFORMANCE CURVES: V_SS= –5V (CONT)

At T_A= +25°C, V_DD= V_CC= +5V, V_SS= –5V, V_REFH= +2.5V, V_REFL= –2.5V, representative unit, unless otherwise specified.

V_REFLCURRENT vs CODE

(all DACs sent to indicated code)

V_REFHCURRENT vs CODE

(all DACs sent to indicated code)

0.0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

+0.6

+0.5

+0.4

+0.3

+0.2

+0.1

0.0

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Digital Input Code

POSITIVE FULL-SCALE ERROR vs TEMPERATURE

ZERO-SCALE ERROR vs TEMPERATURE

(Code FFFF_H)

(Code 8000_H)

2

1.5

2

1.5

1

0.5

0

1

0.5

0

DAC A

DAC B

DAC A

DAC B

DAC D

–0.5

–1

–0.5

–1

DAC C

DAC D

DAC C

–1.5

–2

–1.5

–2

–40

–25

0

25

55

85

–40

–25

0

25

55

85

Temperature (°C)

POWER SUPPLY CURRENT

vs TEMPERATURE

NEGATIVE FULL-SCALE ERROR vs TEMPERATURE

(Code 0000_H)

3

2.5

2

1.5

1

Data = FFFF_H(all DACs)

No Load

I_CC

1.5

1

DAC D

DAC A

DAC C

0.5

0

0.5

0

–0.5

–1

–0.5

–1

DAC B

I_SS

–1.5

–2

–1.5

–2

–2.5

–3

–40

–25

0

25

55

85

–40

–25

0

25

55

85

Temperature (°C)

®

13

DAC7644

TYPICAL PERFORMANCE CURVES: V_SS= –5V (CONT)

At T_A= +25°C, V_DD= V_CC= +5V, V_SS= –5V, V_REFH= +2.5V, V_REFL= –2.5V, representative unit, unless otherwise specified.

POSITIVE SUPPLY CURRENT

vs DIGITAL INPUT CODE

V_OUTvs R_LOAD

5

4

2

1.5

1

No Load

All DACs

Source

3

2

One DAC

1

0

–1

–2

–3

–4

–5

Sink

0.5

0

0000_H0200_H0400_H0800_H1000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

0.01

0.1

1

10

100

Digital Input Code

R_LOAD(kΩ)

OUTPUT VOLTAGE vs SETTLING TIME

(–2.5V to +2.5V)

OUTPUT VOLTAGE vs SETTLING TIME

(+2.5V to –2.5V)

+5V

LDAC

0

LDAC

0

Large-Signal Settling Time: 1V/div

Small-Signal Settling Time: 2LSB/div

Small-Signal Settling Time:

2LSB/div

Large-Signal Settling Time: 1V/div

Time (2µs/div)

®

14

DAC7644

by the external voltage references (V_REFL and V_REFH, re-

spectively). The digital input is a 16-bit parallel word and

the DAC input registers offer a readback capability. The

converters can be powered from either a single +5V supply

or a dual ±5V supply. The device offers a reset function

which immediately sets all DAC output voltages and DAC

registers to mid-scale code 8000_Hor to zero-scale, code

0000_H. See Figures 2 and 3 for the basic operation of the

DAC7644.

THEORY OF OPERATION

The DAC7644 is a quad voltage output, 16-bit digital-to-

analog converter (DAC). The architecture is an R-2R ladder

configuration with the three MSB’s segmented followed by

an operational amplifier that serves as a buffer. Each DAC

has its own R-2R ladder network, segmented MSBs and

output op amp (see Figure 1). The minimum voltage output

(zero-scale) and maximum voltage output (full-scale) are set

R_F

V_OUTSense

V_OUT

R

2R

V_REF

V_REFH Sense

V_REF

H

L

V_REFL Sense

FIGURE 1. DAC7644 Architecture.

1

2

3

4

5

6

7

8

9

DB15

NC 48

DB14

DB13

DB12

DB11

DB10

DB9

NC 47

NC 46

NC 45

V

_OUTA Sense 44

0V to +2.5V

+2.5000V

V_OUT

_REFL AB Sense 42

_REFL AB 41

_REFH AB 40

A

43

V

DB8

V

Data

Bus

DB7

V

10 DB6

11 DB5

12 DB4

13 DB3

14 DB2

15 DB1

16 DB0

17 RSTSEL

18 RST

19 LOADDACS

20 R/W

21 A1

V

_REFH AB Sense 39

V_OUTB Sense 38

0V to +2.5V

+2.5000V

V

_OUTB 37

_OUTC Sense 36

_OUTC 35

DAC7644

V

_REFH CD Sense 34

V_REFH CD 33

V

_REFL CD 32

_REFL CD Sense 31

_OUTD Sense 30

V_OUT

29

Reset DACs

Load DAC Registers

READ/WRITE

V

0V to +2.5V

D

V_SS28

AGND 27

V_CC26

Address

22 A0

0.1µF

1µF

Chips Select

23 CS

+

+5V

24 DGND

V_DD25

NC = No Connection

FIGURE 2. Basic Single-Supply Operation of the DAC7644.

15

®

DAC7644

1

2

3

4

5

6

7

8

9

DB15

DB14

DB13

DB12

DB11

DB10

DB9

NC 48

NC 47

NC 46

NC 45

V

_OUTA Sense 44

–2.5V to +2.5V

V

_OUTA 43

V_REFL AB Sense 42

V_REFL AB 41

–2.5V

+2.5V

DB8

Data

Bus

DB7

V

_REFH AB 40

V_REFH AB Sense 39

_OUTB Sense 38

V_OUT

37

_OUTC Sense 36

V_OUT

35

10 DB6

11 DB5

12 DB4

13 DB3

14 DB2

15 DB1

16 DB0

17 RSTSEL

18 RST

19 LOADDACS

20 R/W

21 A1

V

–2.5V to +2.5V

B

DAC7644

V

C

V

_REFH CD Sense 34

+2.5V

–2.5V

V_REFH CD 33

+5V

Reset DACs

V_REFL CD 32

V

_REFL CD Sense 31

Load DAC Registers

READ/WRITE

V_OUTD Sense 30

–2.5V to +2.5V

V

_OUTD 29

V_SS28

–5V

+5V

Address

0.1µF

1.0µF

+

22 A0

AGND 27

V_CC26

V_DD25

0.1µF

Chips Select

23 CS

24 DGND

NC = No Connection

FIGURE 3. Basic Dual-Supply Operation of the DAC7644.

The DAC7644 offers a force and sense output configuration

for the high open-loop gain output amplifier. This feature

allows the loop around the output amplifier to be closed at

the load (see Figure 4), thus ensuring an accurate output

voltage.

ANALOG OUTPUTS

When V_SS= –5V (dual supply operation), the output ampli-

fier can swing to within 2.25V of the supply rails, guaran-

teed over the –40°C to +85°C temperature range. With V_SS

= 0V (single-supply operation), and with R_LOADalso con-

nected to ground, the output can swing to ground. Care must

also be taken when measuring the zero-scale error when V_SS

= 0V. Since the output voltage cannot swing below ground,

the output voltage may not change for the first few digital

input codes (0000_H, 0001_H, 0002_H, etc.) if the output ampli-

fier has a negative offset. At the negative limit of –2mV, the

first specified output starts at code 0040_H.

NC 48

NC 47

NC 46

R_W1

NC 45

V

_OUTA Sense 44

_OUTA 43

V_REFL AB Sense 42

_REFL AB 41

_REFH AB 40

R_W2

Due to the high accuracy of these D/A converters, system

design problems such as grounding and contact resistance

become very important. A 16-bit converter with a 2.5V full-

scale range has a 1LSB value of 38µV. With a load current

of 1mA, series wiring and connector resistance (see Figure

4) of only 40mΩ (R_W2) will cause a voltage drop of 40µV.

To understand what this means in terms of a system layout,

the resistivity of a typical 1 ounce copper-clad printed circuit

board is 1/2 mΩ per square. For a 1mA load, a 10 milli-inch

wide printed circuit conductor 600 milli-inches long will

result in a voltage drop of 30µV.

V_OUT

+V

V

DAC7644

V

+2.5V

V_REFH AB Sense 39

R_W1

V_OUTB Sense 38

V

_OUTB 37

R_W2

V_OUT

FIGURE 4. Analog Output Closed-Loop Configuration

(1/2 DAC7644). R_Wrepresents wiring resis-

tances.

®

16

DAC7644

REFERENCE INPUTS

The current into the V_REFH input and out of V_REFL depends

on the DAC output voltages and can vary from a few

microamps to approximately 0.5mA. The reference input

appears as a varying load to the reference. If the reference

can sink or source the required current, a reference buffer is

not required. The DAC7644 features a reference drive and

sense connection such that the internal errors caused by the

changing reference current and the circuit impedances can

be minimized. Figures 5 through 12 show different reference

configurations and the effect on the linearity and differential

linearity.

The reference inputs, V_REFL and V_REFH, can be any voltage

between V_SS+ 2.5V and V_CC– 2.5V provided that V_REFH is

at least 1.25V greater than V_REFL. The minimum output of

each DAC is equal to V_REFL plus a small offset voltage

(essentially, the offset of the output op amp). The maximum

output is equal to V_REFH plus a similar offset voltage. Note

that V_SS(the negative power supply) must either be

connected to ground or must be in the range of –4.75V to

–5.25V. The voltage on V_SSsets several bias points within

the converter. If V_SSis not in one of these two configura-

tions, the bias values may be in error and proper operation

of the device is not guaranteed.

NC 48

NC 47

NC 46

NC 45

+V

V

_OUTA Sense 44

_OUTA 43

_REFL AB Sense 42

_REFL AB 41

_REFH AB 40

_REFH AB Sense 39

_OUTB Sense 38

_OUTB 37

OPA2234

V_OUT

V

DAC7644

V

–2.5V

V

500pF

V

–V

+V

V

500pF

V

V_OUT

+2.5V

–V

FIGURE 5. Dual Supply Configuration-Buffered References, used for Dual Supply Performance Curves (1/2 DAC7644).

NC 48

NC 47

NC 46

+V

NC 45

V_OUTA Sense 44

OPA2350

V_OUT

V

_OUTA 43

_REFL AB Sense 42

_REFL AB 41

_REFH AB 40

_REFH AB Sense 39

_OUTB Sense 38

_OUTB 37

DAC7644

V

2kΩ

100Ω

2200pF

V

1000pF

0.050V

V

+V

98kΩ

V

+2.5V

V

V_OUT

NOTE: V_REFL has been chosen to be 50mV to allow for current sinking voltage

drops across the 100Ω resistor and the output stage of the buffer op amp.

FIGURE 6. Single-Supply Buffered Reference with a Reference Low of 50mV (1/2 DAC7644).

®

17

DAC7644

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC A, +25°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC A, +25°C)

2.5

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0.5

0

–0.5

–1.0

–1.5

2.5

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0.5

0

–0.5

–1.0

–1.5

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Digital Input Code

FIGURE 8. Integral Linearity and Differential Linearity

Error Curves for Figure 9.

FIGURE 7. Integral Linearity and Differential Linearity

Error Curves for Figure 6.

NC 48

NC 47

NC 46

NC 45

+V

V

_OUTA Sense 44

V_OUT

43

_REFL AB Sense 42

_REFL AB 41

_REFH AB 40

V_REFH AB Sense 39

_OUTB Sense 38

_OUTB 37

+V

OPA2350

V_OUT

A

DAC7644

V

100Ω

2200pF

+1.25V

V

1000pF

V

+V

V

+2.5V

V_OUT

FIGURE 9. Single-Supply Buffered Reference with V_REFL = +1.25V and V_REFH = +2.5V (1/2 DAC7644).

NC 48

NC 47

NC 46

NC 45

V

_OUTA Sense 44

V_OUT

43

_REFL AB Sense 42

_REFL AB 41

V_REFH AB 40

_REFH AB Sense 39

_OUTB Sense 38

V_OUT

37

V_OUT

A

DAC7644

+V

V

+V

OPA350

100Ω

+2.5V

V

1000pF

2200pF

V

V_OUT

B

FIGURE 10. Single-Supply Buffered V_REFH (1/2 DAC7644).

®

18

DAC7644

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC A, +25°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC A, +25°C)

2.5

2.0

3.0

2.5

2.0

1.5

1.0

0.5

0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–0.5

–1.0

2.0

1.5

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Digital Input Code

FIGURE 13. Linearity and Differential Linearity Error Curves

for Figure 12.

FIGURE 11. Linearity and Differential Linearity Error Curves

for Figure 10.

DIGITAL INTERFACE

Table I shows the basic control logic for the DAC7644. Note

that each internal register is edge triggered and not level

triggered. When the LOADDACS signal is transitioned to

HIGH, the digital word currently in the register is latched.

The first set of registers (the input registers) are triggered via

the A0, A1, R/W, and CS inputs. Only one of these registers

is transparent at any given time.

NC 48

NC 47

NC 46

NC 45

V

_OUTA Sense 44

_OUTA 43

_REFL AB Sense 42

_REFL AB 41

_REFH AB 40

_REFH AB Sense 39

_OUTB Sense 38

_OUTB 37

V_OUT

V

DAC7644

The double-buffered architecture is designed mainly so each

DAC input register can be written to at any time and then all

DAC voltages updated simultaneously by the rising edge of

LOADDACS. It also allows a DAC input register to be

written to at any point and the DAC voltages to be synchro-

nously changed via a trigger signal connected to

LOADDACS.

V

+V

V

+2.5V

V

V_OUT

V

FIGURE 12. Low Cost Single-Supply Configuration.

INPUT

DAC

A1

A0

R/W

CS

RST

RSTSEL LOADDACS

REGISTER

MODE

DAC

L

H

L

H

L

H

L

H

X

H

↑

X

L

X

↑

Write

Read

Hold

Write

Write Input

Read Input

Update

A

B

C

D

A

B

C

D

All

L

H

X

L

H

L

H

X

H

X

H

X

Hold

Reset to Zero

Reset to Midscale

Reset to Zero

Reset to Midscale

↑

H

TABLE I. DAC7644 Logic Truth Table.

®

19

DAC7644

DIGITAL TIMING

V

_REFH – V_REFL • N

(

)

Figure 14 and Table II provide detailed timing for the digital

interface of the DAC7644.

V_OUT= V_REFL +

(1)

65,536

DIGITAL INPUT CODING

where N is the digital input code. This equation does not

include the effects of offset (zero-scale) or gain (full-scale)

errors.

The DAC7644 input data is in Straight Binary format. The

output voltage is given by Equation 1.

t_WCS

CS

t_WS

t_WH

R/W

t_RCS

t_AH

CS

t_AS

t_RDH

t_RDS

A0/A1

t_LH

R/W

t_LS

t_LWD

t_LX

t_AS

t_AH

±0.003% of FSR

Error Band

LOADDACS

Data In

A0/A1

t_DH

t_DS

t_DZ

t_S

Data Out

Data Valid

t_CSD

V_OUT

Data Read Timing

Data Write Timing

±0.003% of FSR

Error Band

t_SS

t_SH

RESET SEL

t_RSH

t_RSS

RST

+FS

V_OUT,RESET SEL LOW

–FS

+FS

MS

V_OUT,RESET SEL HIGH

–FS

DAC7644 Reset Timing

FIGURE 14. Digital Input and Output Timing.

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

t_RCS

t_RDS

t_RDH

t_DZ

t_CSD

t_WCS

t_WS

t_WH

t_AS

t_AH

t_LS

t_LH

t_LX

t_DS

t_DH

t_LWD

t_SS

t_SH

t_RSS

t_RSH

t_S

CS LOW for Read

R/W HIGH to CS LOW

R/W HIGH after CS HIGH

CS HIGH to Data Bus in High Impedance

CS LOW to Data Bus Valid

CS LOW for Write

150

10

ns

µs

10

100

150

100

40

0

10

0

10

30

100

0

10

100

0

R/W LOW to CS LOW

R/W LOW after CS HIGH

Address Valid to CS LOW

Address Valid after CS HIGH

CS LOW to LOADDACS HIGH

CS LOW after LOADDACS HIGH

LOADDACS HIGH

Data Valid to CS LOW

Data Valid after CS HIGH

LOADDACS LOW

RSTSEL Valid Before RESET HIGH

RSTSEL Valid After RESET HIGH

RESET LOW Before RESET HIGH

RESET LOW After RESET HIGH

Settling Time

200

10

TABLE II. Timing Specifications (T_A= –40°C to +85°C).

®

20

DAC7644

DIGITALLY-PROGRAMMABLE

CURRENT SOURCE

Figure 15 shows a DAC7644 in a 4mA to 20mA current

output configuration. The output current can be determined

by Equation 3:

The DAC7644 offers a unique set of features that allows a

wide range of flexibility in designing applications circuits

such as programmable current sources. The DAC7644 offers

both a differential reference input as well as an open-loop

configuration around the output amplifier. The open-loop

configuration around the output amplifier allows transistor

to be placed within the loop to implement a digitally-

programmable, uni-directional current source. The availabil-

ity of a differential reference also allows programmability

for both the full-scale and zero-scale currents. The output

current is calculated as:

(3)

2.5V – 0.5V

N Value

65,536

0.5V

I_OUT

=

•

+

125Ω

At full-scale, the output current is 16mA plus the 4mA for

the zero current. At zero scale the output current is the offset

current of 4mA (0.5V/125Ω).

V_REFH – V_REF

R_SENSE

L

N Value

65,536

(2)

I_OUT

=

•

+ V_REFL / R_SENSE

(

)

I_OUT

V_PROGRAMMED

NC 48

NC 47

125Ω

NC 46

NC 45

+V

V_OUTA Sense 44

OPA2350

V_OUT

V_REFL AB Sense 42

_REFL AB 41

A

43

DAC7644

20kΩ

100Ω

2200pF

V

1000pF

+0.5V

V_REFH AB 40

V_REFH AB Sense 39

V_OUTB Sense 38

100Ω

80kΩ

+V

2200pF

V

_OUTB 37

+2.5V

I_OUT

V_PROGRAMMED

125Ω

GND

FIGURE 15. 4-to-20mA Digitally Controlled Current Source (1/2 DAC7644).

®

21

DAC7644

PACKAGE OPTION ADDENDUM

www.ti.com

30-Jul-2007

PACKAGING INFORMATION

Orderable Device

DAC7644E

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SSOP

DL

48

25 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

DAC7644E/1K

DAC7644E/1KG4

DAC7644EB

SSOP

DL

1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

25 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

DAC7644EB/1K

DAC7644EB/1KG4

DAC7644EBG4

DAC7644EG4

1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

25 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

25 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

DAC7644E/1K

SSOP

DL

48

1000

330.0

32.4

11.35

16.2

3.1

16.0

32.0

Q1

DAC7644EB/1K

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DAC7644E/1K

SSOP

DL

48

1000

346.0

49.0

DAC7644EB/1K

Pack Materials-Page 2

IMPORTANT NOTICE

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sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

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Products

Applications

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Medical

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Data Converters

DSP

Clocks and Timers

Interface

amplifier.ti.com

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dsp.ti.com

www.ti.com/clocks

interface.ti.com

logic.ti.com

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www.ti.com/medical

www.ti.com/military

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power.ti.com

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www.ti.com/opticalnetwork

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RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DAC7644
厂家：	TEXAS INSTRUMENTS
描述：	16-Bit, Quad Voltage Output DIGITAL-TO-ANALOG CONVERTER
文件：	总25页 (文件大小：555K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC7644 [TI]

相关型号：

DAC7644E

DAC7644E

DAC7644E/1K

DAC7644EB

DAC7644EB

DAC7644EB/1K

DAC7644EB/1KG4

DAC7644EBG4

DAC7644EG4

DAC7654

DAC7654

DAC7654YBR