DAC71408RHAT [TI]
具有集成内部基准电压的 8 通道 14 位高电压输出 DAC | RHA | 40 | -40 to 125;型号: | DAC71408RHAT |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有集成内部基准电压的 8 通道 14 位高电压输出 DAC | RHA | 40 | -40 to 125 转换器 |
文件: | 总60页 (文件大小:3689K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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DAC81408, DAC71408, DAC61408
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
具有内部基准电压的 DACx1408 8 通道 16/14/12 位高电压输出 DAC
1 特性
3 说明
1
•
性能
DAC81408、DAC71408 和 DAC61408 (DACx1408)
是具有引脚兼容性和 16/14/12 位分辨率的 8 通道缓冲
高电压输出数模转换器 (DAC) 系列产品。DACx1408
包括一个低漂移 2.5V 内部电压基准,因此在大多数应
用中无需使用外部精密 基准。这些器件具有单调性,
并能提供 ±1 LSB INL 的高线性度。
–
–
–
在 16 位分辨率下具有单调性
INL:16 位分辨率下为 ±1 LSB(最大值)
TUE:FSR 最大值 ±0.1%
•
•
集成 2.5V 精密内部基准
–
–
初始精度:±2.5mV(最大值)
低温漂:5ppm/˚C(典型值)
用户可自行选择输出配置,包括满量程双极输出电压 ±
20V、±10V、±5V 或 ±2.5V 和满量程非双极输出电压
40V、20V、10V 或 5V。而且可以对每个 DAC 通道的
满量程输出电压进行单独编程控制。集成的 DAC 输出
缓冲器可实现高达 25mA 的灌电流或拉电流,从而减
少了对额外的运算放大器的需求。每个通道对都可进行
相应配置,从而提供经过失调校准的差分输出。通过三
个专用 A-B 切换引脚,可以生成最多具有三种频率的
抖动信号。
灵活的输出配置
–
输出范围:±2.5V、±5V、±10V、±20V
0 至 5V、0 至 10V、0 至 20V、0 至 40V
–
差分输出模式
•
高驱动能力:±25mA(相对于电源轨的摆幅为
1.5V)
•
•
三个专用 A-B 切换引脚可用于生成抖动信号
模拟温度输出
–
传感器增益为 –4mV/˚C
DACx1408 包含的上电复位电路可在加电时将 DAC 输
出端连接至接地端。输出端会保持该状态,直至器件寄
存器得到适当的运行配置。
•
50MHz SPI 兼容型串行接口
–
–
–
4 线制模式,工作电压为 1.7V 至 5.5V
菊链运行方式
CRC 误差校验
与 DACx1408 之间的通信通过一个支持 1.7V 至 5.5V
工作电压的 4 线制串行接口进行。
•
•
温度范围:–40˚C 至 +125˚C
小型封装
器件信息(1)
–
6mm × 6mm,40 引脚 VQFN
器件型号
DAC81408
封装
封装尺寸(标称值)
2 应用
DAC71408
DAC61408
VQFN (40)
6.00mm × 6.00mm
•
•
•
光纤网络:马赫-曾德调制器偏置控制
工业自动化
测试和测量
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
功能方框图
REF
REFCMP REFGND
VIO
VAA
VDD
VCC
Internal
Reference
DAC
Buffer
DAC
Register
SCLK
SDI
Range Config
SDO
DAC
BUF
OUT0
CS
LDAC
Channel 0
Channel 1
RESET
OUT1
OUT7
CLR
TOGGLE0
TOGGLE1
TOGGLE2
Channel 7
Power Down Logic
Resistive Network
ALMOUT
Power On Reset
Temperature Sensor
TEMPOUT
DACx1408
GND
VSS
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLASER3
DAC81408, DAC71408, DAC61408
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
www.ti.com.cn
目录
9.4 Device Functional Modes........................................ 26
9.5 Programming........................................................... 28
9.6 Register Maps......................................................... 31
10 Application and Implementation........................ 46
10.1 Application Information.......................................... 46
10.2 Typical Application ............................................... 46
11 Power Supply Recommendations ..................... 49
12 Layout................................................................... 50
12.1 Layout Guidelines ................................................. 50
12.2 Layout Example .................................................... 50
13 器件和文档支持 ..................................................... 51
13.1 文档支持 ............................................................... 51
13.2 相关链接................................................................ 51
13.3 接收文档更新通知 ................................................. 51
13.4 社区资源................................................................ 51
13.5 商标....................................................................... 51
13.6 静电放电警告......................................................... 51
13.7 术语表 ................................................................... 51
14 机械、封装和可订购信息....................................... 51
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 Timing Requirements.............................................. 11
7.7 Typical Characteristics............................................ 13
Parameter Measurement Information ................ 21
Detailed Description ............................................ 22
9.1 Overview ................................................................. 22
9.2 Functional Block Diagram ....................................... 22
9.3 Feature Description................................................. 23
8
9
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Original (July 2018) to Revision A
Page
•
•
已更改 将 DAC81408 从“预告信息”更改为“生产数据”............................................................................................................. 1
已更改 将 DAC71408 和 DAC61408 从“产品预览”更改为“生产数据” ..................................................................................... 1
2
Copyright © 2018, Texas Instruments Incorporated
DAC81408, DAC71408, DAC61408
www.ti.com.cn
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
5 Device Comparison Table
DEVICE
RESOLUTION
16-Bit
DAC81408
DAC71408
DAC61408
14-Bit
12-Bit
6 Pin Configuration and Functions
RHA Package
40-Pin VQFN
Top View
NC
NC
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
NC
NC
NC
NC
NC
NC
OUT0
OUT1
OUT2
OUT3
VIO
OUT7
OUT6
OUT5
OUT4
TEMPOUT
ALMOUT
Thermal
Pad
GND
Not to scale
Copyright © 2018, Texas Instruments Incorporated
3
DAC81408, DAC71408, DAC61408
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
www.ti.com.cn
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
OUT[0:7]
NO.
5 - 8, 23 - 26
O
O
Analog DAC output voltages.
No connection.
1, 2, 3, 4, 27,
28, 29, 30
NC
VIO
9
PWR
GND
IO supply voltage. (1.7 V to 5.5 V). This pin sets the I/O operating voltage for the device.
Ground reference point for all circuitry on the device.
GND
10, 36
Serial interface data output. The SDO pin must be enabled before operation by setting the SDO-EN bit.
Data are clocked out of the input shift register on either rising or falling edges of the SCLK pin as specified
by the FSDO bit (rising edge by default).
SDO
11
O
SCLK
SDI
12
13
I
I
Serial interface clock.
Serial interface data input. Data are clocked into the input shift register on each falling edge of the SCLK
pin.
Active low serial data enable. This input is the frame synchronization signal for the serial data. When the
signal goes low, it enables the serial interface input shift register.
CS
14
I
TOGGLE0
TOGGLE1
TOGGLE2
15
16
17
I
I
I
Toggle pins. Control signals for those DAC outputs configured for toggle operation to switch between the
two DAC data registers associated with each DAC. A logic low updates the DAC output to the value set by
Register A. A logic high updates the DAC output to the value set by Register B. Connect the TOGGLE
pins to ground if not using the toggle operation.
Active low synchronization signal. When the LDAC pin is low, the DAC outputs of those channels
configured in synchronous mode are updated simultaneously. Connect to VIO if unused.
LDAC
RESET
CLR
18
19
20
I
I
I
Active low reset input. Logic low on this pin causes the device to issue a power-on-reset event.
Active low clear input. Logic low on this pin clears all DAC outputs to their clear code. Connect to VIO if
unused.
ALMOUT is an open drain alarm output. An external 10-kΩ pull-up resistor to a voltage no higher than VIO
is required.
ALMOUT
21
O
TEMPOUT
VCC
22
O
Analog temperature monitor output.
31, 40
32, 39
PWR
PWR
Output positive analog power supply (9 V to 41.5 V).
Output negative analog power supply (-21.5 V to 0 V).
VSS
Reference input to the device when operating with external reference. When using internal reference, this
is the reference output voltage pin. Connect a 150-nF capacitor to ground.
REF
33
34
I/O
I/O
Reference compensation capacitor connection. Connect a 330-pF capacitor between REFCMP and
REFGND.
REFCMP
REFGND
VAA
35
37
38
GND
PWR
PWR
Ground reference point for the internal reference.
Analog supply voltage (4.5 V to 5.5 V). This pin must be at the same potential as the VDD pin.
Digital supply voltage (4.5 V to 5.5 V). This pin must be at the same potential as the VAA pin.
VDD
THERMAL
PAD
The thermal pad is located on the package underside. The thermal pad should be connected to any
internal PCB ground plane through multiple vias for good thermal performance.
–
–
4
Copyright © 2018, Texas Instruments Incorporated
DAC81408, DAC71408, DAC61408
www.ti.com.cn
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
-0.3
MAX
UNIT
V
VDD to GND
VIO to GND
VCC to GND
6
6
-0.3
V
-0.3
44
V
Supply voltage
VSS to GND
-22
0.3
V
REFGND to GND
VDD to VAA
-0.3
0.9
V
-0.3
0.3
V
VCC to VSS
-0.3
44
V
DAC outputs to GND
TEMPOUT to GND
REF and REFCMP to GND
Digital inputs to GND
SDO to GND
VSS - 0.3
-0.3
VCC + 0.3
VDD + 0.3
VDD + 0.3
VIO + 0.3
VIO + 0.3
6
V
V
-0.3
V
Pin voltage
-0.3
V
-0.3
V
ALARMOUT to GND
-0.3
V
Operating junction temperature, TJ
Storage temperature, Tstg
-40
150
°C
°C
-60
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)
±1000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per
JEDEC specification JESD22-C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
4.5
1.7
9
NOM
MAX
5.5
5.5
5.5
41.5
0
UNIT
V
(1)
(1)
VAA
VDD
VIO
V
V
VCC
VSS
V
(2)
-21.5
9
V
VCC – VSS
43
V
Digital input voltage
0
VIO
2.51
0.6
125
V
VREFIN
VREFGND
TA
Reference input voltage to VREFGND
2.49
0
2.5
0
V
(3)
REFGND pin voltage
V
Operating ambient temperature
-40
°C
(1) VAA and VDD must be at the same potential.
(2) VSS is only connected to GND when all DAC outputs are unipolar.
(3) If VREFGND is not connected to GND, a buffered source must be used to drive it.
Copyright © 2018, Texas Instruments Incorporated
5
DAC81408, DAC71408, DAC61408
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
www.ti.com.cn
7.4 Thermal Information
DACx1408
THERMAL METRIC(1)
RHA (VQFN)
40 PINS
26.8
RΘJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RΘJC(top)
RΘJB
14.1
3.4
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ΨJB
3.4
RΘJC(bot)
0.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6
版权 © 2018, Texas Instruments Incorporated
DAC81408, DAC71408, DAC61408
www.ti.com.cn
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
7.5 Electrical Characteristics
all minimum/maximum specifications at TA = -40℃ to +125℃ and all typical specifications at TA = 25℃, VCC = 9 V to 41.5 V,
VSS = -21.5 V to 0 V, VDD = VAA = 4.5 V to 5.5 V, VREFIN = 2.5 V, VIO = 1.7 V to 5.5 V, DAC outputs unloaded, Digital inputs at
VIO or GND (unless otherwise noted)
PARAMETER
STATIC PERFORMANCE(1)
Resolution
TEST CONDITIONS
MIN
TYP
MAX UNIT
16
-1
Bits
All ranges, except 0 to 40 V and ±2.5 V
0 to 40 V and ±2.5 V range
±0.5
±1
1
2
1
LSB
LSB
LSB
Bits
DAC81408
Integral nonlinearity (INL)
-2
Differential nonlinearity (DNL) Specified 16-bit monotonic
-1
±0.5
Resolution
14
DAC71408
Integral nonlinearity (INL)
All ranges
-1
±0.5
±0.5
1
1
LSB
LSB
Bits
Differential nonlinearity (DNL) Specified 14-bit monotonic
Resolution
-1
12
DAC61408
TUE
Integral nonlinearity (INL)
All ranges
-1
±0.5
±0.5
1
1
LSB
LSB
Differential nonlinearity (DNL) Specified 12-bit monotonic
-1
All ranges, except ±2.5 V
Total unadjusted error
-0.1
-0.2
-0.03
0
±0.01
±0.02
±0.015
0.04
0.1
0.2
%FSR
±2.5 V range
Unipolar offset error
Unipolar zero-code error
Bipolar zero error
All unipolar ranges
All unipolar ranges
All bipolar ranges
All ranges
0.03 %FSR
0.1 %FSR
0.2 %FSR
0.2 %FSR
-0.2
-0.2
-0.1
-0.2
±0.02
±0.075
±0.02
±0.02
Full-scale error
All ranges, except ±2.5 V
±2.5 V range
0.1
Gain error
%FSR
0.2
ppm of
FSR/°C
Unipolar offset error drift
Bipolar zero error drift
Gain error drift
All unipolar ranges
All bipolar ranges
All ranges
±2
±2
±2
5
ppm of
FSR/°C
ppm of
FSR/°C
ppm of
FSR
Output voltage drift over time TA = 40°C, Full-scale code, 1900 hours
DIFFERENTIAL MODE PERFORMANCE(1)
All ranges
-0.1
-0.2
-0.1
±0.01
±0.02
±0.01
0.1
TUE
Total unadjusted error
Common mode error
%FSR
0.2
±2.5 V range
All bipolar ranges. Midscale code
0.1 %FSR
OUTPUT CHARACTERISTICS
to VSS and VCC
(-10 mA ≤ IOUT ≤ 10 mA)
1
Output voltage headroom
V
to VSS and VCC
(-15 mA ≤ IOUT ≤ 15 mA)
1.5
Full-scale output shorted to VSS
Zero-scale output shorted to VCC
Midscale code, -15 mA ≤ IOUT ≤ 15 mA
RLOAD = open
40
40
70
Short circuit current(2)
mA
Load regulation
Maximum capacitive load(3)
μV/mA
0
1
nF
Midscale code
0.05
40
DC output impedance
Ω
Full-scale code
(1) End point fit between codes. 16-bit: Code 256 to 65280, 14-bit: Code 128 to 16256, 12-bit: Code 32 to 4064.
(2) Temporary overload condition protection. Junction temperature can be exceeded during current limit. Operation above the specified
maximum junction temperature may impair device reliability.
(3) Specified by design and characterization, not production tested.
Copyright © 2018, Texas Instruments Incorporated
7
DAC81408, DAC71408, DAC61408
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
www.ti.com.cn
Electrical Characteristics (continued)
all minimum/maximum specifications at TA = -40℃ to +125℃ and all typical specifications at TA = 25℃, VCC = 9 V to 41.5 V,
VSS = -21.5 V to 0 V, VDD = VAA = 4.5 V to 5.5 V, VREFIN = 2.5 V, VIO = 1.7 V to 5.5 V, DAC outputs unloaded, Digital inputs at
VIO or GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DYNAMIC PERFORMANCE
¼ to ¾ scale and ¾ to ¼ scale settling
time to ±1 LSB, ±10 V range,
RL = 5 kΩ, CL = 200 pF
Output voltage settling time
12
µs
V/µs
V
0 to 5 V range
1
4
Slew rate
All other output ranges
Power-down to active DAC output.
±20 V range, midscale code,
RL = 5 kΩ, CL = 200 pF
Power-on glitch magnitude
0.3
0.1 Hz to 10 Hz, midscale code,
0 to 5 V range
Output noise
15
78
µVpp
Output noise density
1 kHz, midscale code, 0 to 5 V range
nV/Hz
Midscale code, frequency = 60 Hz,
amplitude 200 mVpp superimposed on
VDD, VCC or VSS
AC PSRR
1
LSB/V
LSB/V
Midscale code, VDD = 5 V ± 5%,
VCC = 20 V, VSS = -20 V
1
1
1
4
Midscale code, VDD = 5 V,
VCC = 20 V ± 5%, VSS = -20 V
DC PSRR
Midscale code, VDD = 5 V, VCC = 20 V,
VSS = -20 V ± 5%
1 LSB change around major carrier,
0 to 5 V range
Code change glitch impulse
nV-s
nV-s
0 to 5 V range. Measured channel at
midscale. Full-scale swing on all other
channels
Channel to Channel AC
crosstalk
4
0 to 5 V range. Measured channel at
midscale. All other channels at full-
scale
Channel to Channel DC
crosstalk
0.25
1
LSB
nV-s
0 to 5 V range. Midscale code,
fSCLK = 1 MHz
Digital feedthrough
8
Copyright © 2018, Texas Instruments Incorporated
DAC81408, DAC71408, DAC61408
www.ti.com.cn
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
Electrical Characteristics (continued)
all minimum/maximum specifications at TA = -40℃ to +125℃ and all typical specifications at TA = 25℃, VCC = 9 V to 41.5 V,
VSS = -21.5 V to 0 V, VDD = VAA = 4.5 V to 5.5 V, VREFIN = 2.5 V, VIO = 1.7 V to 5.5 V, DAC outputs unloaded, Digital inputs at
VIO or GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
EXTERNAL REFERENCE INPUT
Reference input voltage
VREFIN
range
to VREFGND
2.49
2.5
2.51
V
Reference input current
Reference input impedance
Reference input capacitance
INTERNAL REFERENCE
50
50
20
µA
kΩ
pF
Reference output voltage
VREFOUT
range
TA = 25°C
2.4975
2.5025
V
Reference output drift
5
0.1
12
15 ppm/°C
Reference output impedance
Reference output noise
Ω
0.1 Hz to 10 Hz
µVpp
Reference output noise
density
10 kHz, REFLOAD = 10 nF
150
nV/Hz
Reference load current
Reference load regulation
Reference line regulation
5
80
20
mA
µV/mA
µV/V
Source
Reference output drift over
time
TA = 25°C, 1900 hours
250
µV
µV
First cycle
±700
±50
Reference thermal hysteresis
Additional cycle
DIGITAL INPUTS AND OUTPUTS
VIH
VIL
High-level input voltage
Low-level input voltage
Input current
0.7 × VIO
V
0.3 × VIO
V
µA
pF
V
±2
2
Input pin capacitance
High-level output voltage
Low-level output voltage
Output pin capacitance
VOH
VOL
IOH = 0.2 mA
IOL = 0.2 mA
VIO - 0.2
0.4
0.4
V
5
5
pF
ALARM OUTPUT
Output pin capacitance
Low-level output voltage
pF
V
VOL
ILOAD = -0.2 mA
TEMPERATURE OUTPUT
VTEMPOUT,0C Output voltage offset at 0℃
Sensor gain
1.34
-4
V
mV/°C
Copyright © 2018, Texas Instruments Incorporated
9
DAC81408, DAC71408, DAC61408
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
www.ti.com.cn
Electrical Characteristics (continued)
all minimum/maximum specifications at TA = -40℃ to +125℃ and all typical specifications at TA = 25℃, VCC = 9 V to 41.5 V,
VSS = -21.5 V to 0 V, VDD = VAA = 4.5 V to 5.5 V, VREFIN = 2.5 V, VIO = 1.7 V to 5.5 V, DAC outputs unloaded, Digital inputs at
VIO or GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER REQUIREMENTS
Active mode. Internal reference
enabled. Full-scale code. ±20 V output
range. SPI static.
0.05
0.5
mA
IDD
IAA
ICC
VDD supply current
VAA supply current
VCC supply current
Active mode. Internal reference
disabled. Full-scale code. ±20 V output
range. SPI static.
0.05
0.05
20
0.5
0.5
30
mA
mA
mA
Power-down mode
Active mode. Internal reference
enabled. Full-scale code. ±20 V output
range. SPI static.
Active mode. Internal reference
disabled. Full-scale code. ±20 V output
range. SPI static.
18
2
28
85
10
mA
µA
Power-down mode
Active mode. Internal reference
enabled. Full-scale code. ±20 V output
range. SPI static.
5
mA
Active mode. Internal reference
disabled. Full-scale code. ±20 V output
range. SPI static.
5
10
-5
10
30
mA
µA
Power-down mode
Active mode. Internal reference
enabled. Full-scale code. ±20 V output
range. SPI static.
-10
mA
ISS
VSS supply current
VIO supply current
Active mode. Internal reference
disabled. Full-scale code. ±20 V output
range. SPI static.
-10
-30
-5
mA
Power-down mode
-10
µA
µA
IIO
SCLK and SDI toggling at 50 MHz
350
500
10
Copyright © 2018, Texas Instruments Incorporated
DAC81408, DAC71408, DAC61408
www.ti.com.cn
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
7.6 Timing Requirements
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
SERIAL INTERFACE - WRITE OPERATION
VIO = 1.7 V to 2.7 V
25
f(SCLK)
Serial clock frequency
SCLK high time
SCLK low time
SDI setup time
SDI hold time
MHz
50
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
20
10
20
10
10
5
tSCLKHIGH
tSCLKLOW
tSDIS
ns
ns
ns
ns
ns
ns
ns
µs
µs
10
5
tSDIH
30
15
10
5
CS to SCLK falling edge
setup time
tCSS
SCLK falling edge to CS
rising edge
tCSH
50
25
2.4
2.4
4
tCSHIGH
tDACWAIT
tBCASTWAIT
CS hight time
Sequential DAC update wait
time
Broadcast DAC update wait
time
4
SERIAL INTERFACE - READ AND DAISY CHAIN OPERATION, FSDO = 0
VIO = 1.7 V to 2.7 V
15
f(SCLK)
tSCLKHIGH
tSCLKLOW
tSDIS
Serial clock frequency
SCLK high time
SCLK low time
SDI setup time
SDI hold time
MHz
20
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
33
25
33
25
10
5
ns
ns
ns
ns
ns
ns
ns
10
5
tSDIH
30
20
8
CS to SCLK falling edge
setup time
tCSS
SCLK falling edge to CS
rising edge
tCSH
5
50
25
0
tCSHIGH
tSDOZD
tSDODLY
CS high time
20
ns
20
SDO tri-state to driven
SDO output delay
0
0
35
ns
20
0
Copyright © 2018, Texas Instruments Incorporated
11
DAC81408, DAC71408, DAC61408
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
www.ti.com.cn
Timing Requirements (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
SERIAL INTERFACE - READ AND DAISY CHAIN OPERATION, FSDO = 1
VIO = 1.7 V to 2.7 V
25
f(SCLK)
tSCLKHIGH
tSCLKLOW
tSDIS
Serial clock frequency
SCLK high time
SCLK low time
SDI setup time
SDI hold time
MHz
35
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
20
14
20
14
10
5
ns
ns
ns
ns
ns
ns
ns
10
5
tSDIH
30
20
8
CS to SCLK falling edge
setup time
tCSS
SCLK falling edge to CS
rising edge
tCSH
5
50
25
0
tCSHIGH
tSDOZD
tSDODLY
CS high time
20
ns
20
SDO tri-state to driven
SDO output delay
0
0
35
ns
20
0
DIGITAL LOGIC
CS rising edge to LDAC or
tLOGDLY
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
40
20
CLR falling edge delay time
ns
CS rising edge to LDAC or
CLR falling edge delay time
tLOGDLY
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
20
10
20
10
tLDAC
LDAC low time
CLR low time
ns
ns
tCLR
1
tRESET
POR reset delay
TOGGLE frequency
ms
1
100
kHz
100
fTOGGLE
12
版权 © 2018, Texas Instruments Incorporated
DAC81408, DAC71408, DAC61408
www.ti.com.cn
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
7.7 Typical Characteristics
at TA = 25°C, VDD = VAA = 5 V, VREFIN = 2.5 V. Unipolar ranges: VSS = 0 V and VCC ≥ VMAX + 1.5 V for the DAC range. Bipolar
ranges: VSS ≤ VMIN – 1.5 V and VCC ≥ VMAX + 1.5 V for the DAC range. DAC outputs unloaded, unless otherwise noted.
1.0
0.8
1.0
0.8
±2.5V
±5V
±10V
±20V
0-5V
0-10 V
0-20 V
0-40 V
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
Code
D001
D002
图 1. Integral Linearity Error vs Digital Input Code (Bipolar
图 2. Integral Linearity Error vs Digital Input Code (Unipolar
Outputs)
Outputs)
1.0
1.0
±2.5V
±5V
±10V
±20V
0-5V
0-10 V
0-20 V
0-40 V
0.8
0.6
0.8
0.6
0.4
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
Code
D003
D004
图 3. Differential Linearity Error vs Digital Input Code
图 4. Differential Linearity Error vs Digital Input Code
(Bipolar Outputs)
(Unipolar Outputs)
0.100
0.075
0.050
0.025
0.000
-0.025
-0.050
-0.075
-0.100
0.100
0.075
0.050
0.025
0.000
-0.025
-0.050
-0.075
-0.100
±2.5V
±5V
±10V
±20V
0-5V
0-10 V
0-20 V
0-40 V
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
Code
D005
D006
图 5. Total Unadjusted Error vs Digital Input Code (Bipolar
图 6. Total Unadjusted Error vs Digital Input Code (Unipolar
Outputs)
Outputs)
版权 © 2018, Texas Instruments Incorporated
13
DAC81408, DAC71408, DAC61408
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, VDD = VAA = 5 V, VREFIN = 2.5 V. Unipolar ranges: VSS = 0 V and VCC ≥ VMAX + 1.5 V for the DAC range. Bipolar
ranges: VSS ≤ VMIN – 1.5 V and VCC ≥ VMAX + 1.5 V for the DAC range. DAC outputs unloaded, unless otherwise noted.
0.0500
0.0375
0.0250
0.0125
0.0000
-0.0125
-0.0250
-0.0375
-0.0500
0.0500
0.0375
0.0250
0.0125
0.0000
-0.0125
-0.0250
-0.0375
-0.0500
±2.5V
±5V
±10V
±20V
0-5 V
0-10 V
0-20 V
0-40 V
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
Code
D007
D008
图 7. Common Mode Error vs Digital Input Code (Differential
图 8. Common Mode Error vs Digital Input Code (Differential
Bipolar Outputs)
Unipolar Outputs)
1.0
1.0
INL MAX
INL MIN
DNL MAX
DNL MIN
0.8
0.8
0.6
0.4
0.6
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D009
D010
±20-V Output Range
±20-V Output Range
图 9. Integral Linearity Error vs Temperature
图 10. Differential Linearity Error vs Temperature
0.100
0.075
0.050
0.025
0.000
-0.025
-0.050
-0.075
-0.100
0.03
0.02
0.01
0.00
-0.01
-0.02
-0.03
0-5 V
±2.5 V
±5 V
±10 V
±20 V
0-5 V
0-10 V
0-20 V
0-40 V
0-10 V
0-20 V
0-40 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D011
D012
图 11. Total Unadjusted Error vs Temperature
图 12. Unipolar Offset Error vs Temperature
14
版权 © 2018, Texas Instruments Incorporated
DAC81408, DAC71408, DAC61408
www.ti.com.cn
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
Typical Characteristics (接下页)
at TA = 25°C, VDD = VAA = 5 V, VREFIN = 2.5 V. Unipolar ranges: VSS = 0 V and VCC ≥ VMAX + 1.5 V for the DAC range. Bipolar
ranges: VSS ≤ VMIN – 1.5 V and VCC ≥ VMAX + 1.5 V for the DAC range. DAC outputs unloaded, unless otherwise noted.
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
0-5 V
±2.5 V
±5 V
±10 V
±20 V
0-10 V
0-20 V
0-40 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D013
D014
图 13. Unipolar Zero Code Error vs Temperature
图 14. Bipolar Zero Error vs Temperature
0.100
0.075
0.050
0.025
0.000
-0.025
-0.050
-0.075
-0.100
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
±2.5 V
±5 V
±10 V
±20 V
0-5 V
±2.5 V
±5 V
±10 V
±20 V
0-5 V
0-10 V
0-20 V
0-40 V
0-10 V
0-20 V
0-40 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D015
D016
图 15. Gain Error vs Temperature
图 16. Full-Scale Error vs Temperature
0.0500
0.0375
0.0250
0.0125
0.0000
-0.0125
-0.0250
-0.0375
-0.0500
0.0500
0.0375
0.0250
0.0125
0.0000
-0.0125
-0.0250
-0.0375
-0.0500
±2.5 V
±5 V
±10 V
±20 V
0-5 V
0-10 V
0-20 V
0-40 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D017
D018
图 17. Common Mode Error vs Temperature (Differential
图 18. Common Mode Error vs Temperature (Differential
Bipolar Outputs)
Unipolar Outputs)
版权 © 2018, Texas Instruments Incorporated
15
DAC81408, DAC71408, DAC61408
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, VDD = VAA = 5 V, VREFIN = 2.5 V. Unipolar ranges: VSS = 0 V and VCC ≥ VMAX + 1.5 V for the DAC range. Bipolar
ranges: VSS ≤ VMIN – 1.5 V and VCC ≥ VMAX + 1.5 V for the DAC range. DAC outputs unloaded, unless otherwise noted.
25
20
15
10
5
30
25
20
15
10
5
30
25
20
15
10
5
ICC
ISS
IDD
IAA
0
-5
-10
-15
-20
-25
0
0
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
Code
D019
D020
±20-V Output Range
±20-V Output Range
图 19. Supply Current (IDD, IAA) vs Digital Input Code
图 20. Supply Current (ICC, ISS) vs Digital Input Code
25
20
15
10
5
500
450
400
350
300
250
200
150
100
50
0
-5
-10
-15
-20
-25
IDD
IAA
ICC
ISS
0
1.7
2.65
3.6
VIO (V)
4.55
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D021
D022
±20-V Output Range
±20-V Output Range
图 21. Supply Current (IIO) vs Supply Voltage
图 22. Supply Current vs Temperature
90
75
60
45
30
15
0
40
30
IDD
IAA
ICC
ISS
20
10
0
-10
-20
-30
-40
-15
-30
Code 0x0000
Code 0x8000
Code 0xFFFF
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-50 -40 -30 -20 -10
0
10
20
30
40
50
Load Current (mA)
D023
D024
±20-V Output Range
图 23. Power-Down Current vs Temperature
±20-V Output Range
图 24. Source and Sink Capability
16
版权 © 2018, Texas Instruments Incorporated
DAC81408, DAC71408, DAC61408
www.ti.com.cn
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
Typical Characteristics (接下页)
at TA = 25°C, VDD = VAA = 5 V, VREFIN = 2.5 V. Unipolar ranges: VSS = 0 V and VCC ≥ VMAX + 1.5 V for the DAC range. Bipolar
ranges: VSS ≤ VMIN – 1.5 V and VCC ≥ VMAX + 1.5 V for the DAC range. DAC outputs unloaded, unless otherwise noted.
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
±20 V
±10 V
±20 V
±10 V
0
3
6
9
12
15
18
21
24
27
30
0
3
6
9
12
15
18
21
24
27
30
Sourcing Current (mA)
Sinking Current (mA)
D025
D026
Full-scale Code
Zero Code
图 25. VCC Headroom vs Sourcing Current
图 26. VSS Footroom vs Sinking Current
LDAC (5V/div)
VOUT (5V/div)
LDAC (5V/div)
VOUT (5V/div)
Time (5 msec/div)
Time (5 msec/div)
D027
D028
±20-V Output Range
±20-V Output Range
图 27. Full-Scale Settling Time, Rising Edge
图 28. Full-Scale Settling Time, Falling Edge
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
LDAC (5V/div)
VOUT (5mV/div)
Time (0.5msec/div)
Time (5 msec/div)
D030
D029
0 to 5-V Output Range
Power-down to Active DAC Mode
±20-V Output Range
图 30. Glitch Impulse, 1 LSB Step
图 29. DAC Output Enable Glitch
版权 © 2018, Texas Instruments Incorporated
17
DAC81408, DAC71408, DAC61408
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, VDD = VAA = 5 V, VREFIN = 2.5 V. Unipolar ranges: VSS = 0 V and VCC ≥ VMAX + 1.5 V for the DAC range. Bipolar
ranges: VSS ≤ VMIN – 1.5 V and VCC ≥ VMAX + 1.5 V for the DAC range. DAC outputs unloaded, unless otherwise noted.
20
15
10
5
20
15
10
5
0
0
-5
-5
Time (25 msec/div)
Time (25 msec/div)
D031
D032
±20-V Output Range
Toggle signal: 1 VPP
±20-V Output Range
Toggle signal: 1 VPP
DC value: 3/4 Full-scale
DC Change: Midscale to 3/4 Full-scale
图 31. Toggle Output Change Response
图 32. Toggle Enable Response
VOUT
VCC
VSS
VOUT
VCC
VSS
VDD = VAA = VIO
VDD = VAA = VIO
Time (50 msec/div)
Time (50 msec/div)
D033
D034
图 33. Power-Up Response
图 34. Power-Down Response
CLR (5 V/div)
VOUT (5 V/div)
CLR (5 V/div)
VOUT (5 V/div)
Time (1 msec/div)
Time (0.5 msec/div)
D035
D036
±20-V Output Range
Full-scale Code to 0 V
±20-V Output Range
Toggle signal: 1 VPP
DC value at 20 V
图 35. Clear Command Response
图 36. Clear Command Response in Toggle Mode
版权 © 2018, Texas Instruments Incorporated
18
DAC81408, DAC71408, DAC61408
www.ti.com.cn
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
Typical Characteristics (接下页)
at TA = 25°C, VDD = VAA = 5 V, VREFIN = 2.5 V. Unipolar ranges: VSS = 0 V and VCC ≥ VMAX + 1.5 V for the DAC range. Bipolar
ranges: VSS ≤ VMIN – 1.5 V and VCC ≥ VMAX + 1.5 V for the DAC range. DAC outputs unloaded, unless otherwise noted.
1500
1350
1200
1050
900
750
600
450
300
150
0
Time (1 sec/div)
100
1000
10000
100000
Frequency (Hz)
D038
D037
0 to 5-V Output Range
Midscale Code
0 to 5-V Output Range
Midscale Code
图 38. DAC Output Noise
图 37. DAC Output Noise Density vs Frequency
2.505
2.504
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.496
2.495
2.5005
2.5004
2.5003
2.5002
2.5001
2.5000
2.4999
2.4998
2.4997
2.4996
2.4995
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
VDD, VAA (V)
D039
D040
图 39. Internal Reference Voltage vs Temperature
图 40. Internal Reference Voltage vs Supply Voltage
2.5005
2.5004
2.5003
2.5002
2.5001
2.5000
2.4999
2.4998
2.4997
2.4996
2.4995
1500
1350
1200
1050
900
750
600
450
300
150
0
0
200 400 600 800 1000 1200 1400 1600 1800 2000
100
1000
10000
100000
Hours
Frequency (Hz)
D041
D042
图 41. Internal Reference Voltage vs Time
图 42. Internal Reference Noise Density vs Frequency
版权 © 2018, Texas Instruments Incorporated
19
DAC81408, DAC71408, DAC61408
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, VDD = VAA = 5 V, VREFIN = 2.5 V. Unipolar ranges: VSS = 0 V and VCC ≥ VMAX + 1.5 V for the DAC range. Bipolar
ranges: VSS ≤ VMIN – 1.5 V and VCC ≥ VMAX + 1.5 V for the DAC range. DAC outputs unloaded, unless otherwise noted.
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
0
Time (1 sec/div)
0
1
2
3
4
5
6
7
8
9
10
D043
Temperature Drift (ppm/oC)
D044
图 43. Internal Reference Noise
图 44. Internal Reference Temperature Drift Histogram
20
版权 © 2018, Texas Instruments Incorporated
DAC81408, DAC71408, DAC61408
www.ti.com.cn
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
8 Parameter Measurement Information
tCSHIGH
tCSS
tCSH
CS
tSCLKLOW
SCLK
tSCLKHIGH
SDI
Bit 23
Bit 1
Bit 0
tSDIH
tSDIS
图 45. Serial Interface Write Timing Diagram
tCSHIGH
tCSS
tCSH
CS
tSCLKLOW tSCLKHIGH
SCLK
FIRST READ COMMAND
ANY COMMAND
Bit 1
SDI
Bit 23
tSDIS tSDIH
Bit 22
Bit 0
Bit 23
Bit 23
Bit 0
Bit 0
SDO
Bit 1
FSDO = 0
tSDODLY
tSDODZ
DATA FROM FIRST READ COMMAND
SDO
Bit 23
Bit 1 Bit 0
FSDO = 1
tSDODLY
DATA FROM FIRST READ COMMAND
图 46. Serial Interface Read Timing Diagram
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9 Detailed Description
9.1 Overview
The DACx1408 is a pin-compatible family of 8-channel, buffered, high-voltage output digital-to-analog converters
(DACs) with 16-, 14- and 12-bit resolution. The DACx1408 includes a 2.5-V internal reference. A user selectable
output configuration enables full-scale bipolar output voltages: ±20 V, ±10 V, ±5 V or ±2.5 V and full-scale
unipolar output voltages: 40 V, 20 V, 10 V or 5 V. The full-scale output range for each DAC channel is
independently programmable. In addition, each pair of DAC channels can be configured to provide a differential
output. Three dedicated A-B toggle pins enable dither signal generation with up to three possible frequencies.
The DACx1408 operates from five supply voltages: VDD, VAA, VCC, VSS and VIO. VDD and VAA are the digital and
analog supplies for the DACs, internal reference and other low voltage components and must be set at the same
potential. VCC and VSS are the positive and analog supplies for the DAC output amplifiers. VIO sets the logic
levels for the digital inputs and outputs.
Communication to the DACx1408 is performed through a 4-wire serial interface that supports stand-alone and
daisy-chain operation. The optional frame-error checking provides added robustness to the DACx1408 serial
interface.
The DACx1408 incorporates a power-on-reset circuit that connects the DAC outputs to ground at power-up. The
outputs remain at this state until the device registers are properly configured for operation.
9.2 Functional Block Diagram
REF
REFCMP REFGND
VIO
VAA
VDD
VCC
Internal
Reference
DAC
Buffer
DAC
Register
SCLK
SDI
Range Config
SDO
DAC
BUF
OUT0
CS
LDAC
Channel 0
Channel 1
RESET
OUT1
OUT7
CLR
TOGGLE0
TOGGLE1
TOGGLE2
Channel 7
Power Down Logic
Resistive Network
ALMOUT
Power On Reset
Temperature Sensor
TEMPOUT
DACx1408
GND
VSS
22
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9.3 Feature Description
9.3.1 Digital-to-Analog Converters (DACs) Architecture
Each output channel in the DACx1408 consists of an R-2R ladder architecture followed by an output buffer
amplifier capable of rail-to-rail operation. The output amplifiers can drive 25 mA with 1.5-V headroom from either
VCC or VSS while maintaining the specified TUE specification for the device. The full-scale output voltage for each
channel can be individually configured to the following ranges:
•
•
•
•
•
•
•
•
-20 V to +20 V
-10 V to +10 V
-5 V to +5 V
-2.5 V to +2.5 V
0 V to +40V
0 V to +20 V
0 V to +10 V
0 V to +5 V
图 47 shows a block diagram of the DAC architecture.
REF
VCC
2.5V
Reference
DAC Range
Select
Register
Serial
Asynchronous
Mode
DAC Buffer
Register
(Toggle Reg B)
DAC Active
Interface
Register
Synchronous Mode
(Toggle Reg A)
(LDAC(1) Trigger)
WRITE
DAC
Output
VOUT
DAC
(1)The DAC trigger is generated by either by writing '1' to the LDAC bit or by the /
LDAC pin in synchronous mode. In asynchronous mode, the DAC latch is transparent.
TOGGLE
GND
VSS
图 47. DACx1408 DAC Block Diagram
9.3.1.1 DAC Transfer Function
The input data are written to the individual DAC Data registers in straight binary format for all output ranges. The
DAC transfer function is given by 公式 1.
≈ CODE
’
V
=
× FSR + V
MIN
∆
÷
OUT
n
«
2
◊
(1)
where
•
CODE is the decimal equivalent of the binary code that is loaded to the DAC register. CODE range is from 0
to 2n – 1.
•
•
•
n is the DAC resolution in bits. Either 12 (DAC61408), 14 (DAC71408) or 16 (DAC81408).
FSR is the DAC full-scale range. Equal to VMAX – VMIN for the selected DAC output range.
VMIN is the lowest voltage for the selected DAC output range.
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Feature Description (接下页)
9.3.1.2 DAC Register Structure
Data written to the DAC data registers is initially stored in the DAC buffer registers. Transfer of data from the
DAC buffer registers to the active DAC registers can be configured to happen immediately (asynchronous mode)
or initiated by a DAC trigger signal (synchronous mode). Once the DAC active registers are updated, the DAC
outputs change to the new values.
After a power-on or reset event, all DAC registers are set to zero code, the DAC output amplifiers are powered
down, and the DAC outputs are clamped to ground.
9.3.1.2.1 DAC Register Synchronous and Asynchronous Updates
The update mode for each DAC channel is determined by the status of its corresponding SYNC-EN bit. In
asynchronous mode, a write to the DAC data register results in an immediate update of the DAC active register
and DAC output on a CS rising edge. In synchronous mode, writing to the DAC data register doe not
automatically update the DAC output. Instead the update occurs only after a trigger event. A DAC trigger signal
is generated either through the LDAC bit or by the LDAC pin. The synchronous update mode enables
simultaneous update of multiple DAC outputs. In both update modes a minimum wait time of 1 µs is required
between DAC output updates.
9.3.1.2.2 Broadcast DAC Register
The DAC broadcast register enables a simultaneous update of multiple DAC outputs with the same value with a
single register write. Broadcast operation is only possible when all DAC channels are in single-ended mode
operation. If one or more outputs are configured in differential mode the broadcast command is ignored.
Each DAC channel can be configured to update or remain unaffected by a broadcast command by setting the
corresponding DAC-BRDCAST-EN bit. A register write to the BRDCAST-DATA register forces those DAC
channels that have been configured for broadcast operation to update their DAC buffer registers to this value.
The DAC outputs update to the broadcast value according to their synchronous mode configuration.
9.3.1.2.3 Clear DAC Operation
The DAC outputs are set in clear mode through the CLEAR pin. In clear mode each DAC data channel is set to
the clear code associated with its configuration as shown in . A CLR pin logic low forces all DAC channels to
clear the contents of their buffer and active registers to the clear code, and sets the analog outputs accordingly
regardless of their synchronization setting.
表 1. Clear DAC Value
UNIPOLAR / BIPOLAR RANGE
DIFFERENTIAL MODE
CLEAR CODE
Zero code
Unipolar
Unipolar
Bipolar
Bipolar
No
Yes
No
Midscale code
Midscale code
Midscale code
Yes
When a DAC is operating in toggle mode, a clear command sets both toggle registers to the clear value.
9.3.2 Internal Reference
The DAx1408 include a 2.5-V bandgap reference with a typical temperature drift of 5 ppm/ºC. The internal
reference is externally available at the REF pin. An external buffer amplifier with a high impedance input is
required to drive any external load.
A minimum 150-nF capacitor is recommended between the reference output and GND for noise filtering. A
compensation capacitor (330 pF, typical) should be connected between the REFCMP pin and REFGND.
Operation from an external reference is also supported by powering down the internal reference. The external
reference is applied to the REF pin.
24
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9.3.3 Device Reset Options
9.3.3.1 Power-on-Reset (POR)
The DACx1408 includes a power-on reset function. After the supplies have been established, a POR event is
issued. The POR causes all registers to initialize to their default values and communication with the device is
valid only after a 1 ms power-on-reset delay. After a POR event, the device is set in power-down mode where all
DAC channels and internal reference are powered down and the DAC output pins are connected to ground
through a 10-kΩ internal resistor.
9.3.3.2 Hardware Reset
A device hardware reset event is initiated by a minimum 500 ns logic low on the RESET pin. A hardware reset
initiates a POR event.
9.3.3.3 Software Reset
A device software reset event is initiated by writing the reserved code 0x1010 to SOFT-RESET in the TRIGGER
register. The software reset command is triggered on the CS rising edge of the instruction. A software reset
initiates a POR event.
9.3.4 Thermal Protection
Due to the DACx1408 DAC channel density and high drive capability it is important to understand the effects of
power dissipation on the temperature of the device and ensure it does not exceed the maximum junction
temperature.
9.3.4.1 Analog Temperature Sensor: TEMPOUT Pin
The DACx1408 includes an analog temperature monitor with an unbuffered output voltage that is inversely
proportional to the device junction temperature. The TEMPOUT pin output voltage has a temperature slope of -4
mV/°C and a 1.34-V offset as described by 公式 2.
-4 mV
°C
≈
’
V
=
× T + 1.34 V
TEMPOUT
∆
«
÷
◊
(2)
where:
•
•
T is the device junction temperature in °C.
VTEMPOUT is the temperature monitor output voltage.
9.3.4.2 Thermal Shutdown
The DACx1408 incorporates a thermal shutdown that is triggered when the die temperature exceeds 140ºC. A
thermal shutdown sets the TEMP-ALM bit and causes all DAC outputs to power-down, however the internal
reference remains powered on. The ALMOUT pin can be configured to monitor a thermal shutdown condition by
setting the TEMPALM-EN bit. Once a thermal shutdown is triggered, the device stays in shutdown even after the
device temperature lowers.
The die temperature must fall below 140ºC before the device can be returned to normal operation. To resume
normal operation, the thermal alarm must be cleared through the ALM-RESET bit while the DAC channels are in
power-down mode.
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9.4 Device Functional Modes
9.4.1 Toggle Mode
Each DAC in the device can be independently configured to operate in toggle mode. A DAC channel in toggle
mode incorporates two DAC registers (Register A and Register B) and can be set to switch repetitively between
these two values. The DACx1408 toggle mode operation can be configured to introduce a dither signal to the
DAC output, to generate a periodic signal or to implement ON/OFF signaling, among some examples.
To update the toggle registers the following sequence should be followed:
1. Set DAC channel in synchronous mode and disable toggle mode for that channel
2. Write the desired Register A value to the DAC data register
3. Issue a DAC trigger signal to load Register A
4. Write the desired Register B value to the DAC data register
5. Enable toggle mode to load Register B
Once both registers are loaded with data, any of the three TOGGLE[2:0] pins can be used to switch those DACs
configured for toggle operation back and forth between the contents of their two DAC specific registers by using
an external clock or logic signal. A TOGGLE pin logic low updates the DAC output to the value set by Register A.
A logic high updates the DAC output to the value set by Register B. The three TOGGLE[2:0] pins give the
DACx1408 the option to operate with up to three toggle rates.
Additionally, the device can be configured for software controlled toggle operation by setting the SOFTTOGGLE-
EN bit. In this mode, any of the three AB-TOG[2:0] bits can be used as a toggle control signal. Setting the
ABTOG bit to 1 enables Register B and clearing it to 0 enables Register A.
9.4.2 Differential Mode
Each pair of DAC channels in the device can be independently configured to operate as a differential output pair.
The differential output of a DACx-y pair is updated by writing to the DACx channel. For proper operation, the two
DAC pairs must be configured to the same output range prior to enabling differential mode. 图 48 and 图 49
show the ideal differential output voltages (VDIFF) and common mode voltages (VCM) for a DAC differential pair
configured for ±20-V and 0 to 40-V operation, respectively.
Once configured as a differential output, the DACx-y pair can be set for toggle operation by updating the DACx
toggle registers as described in Toggle Mode.
Imbalances between the two differential signals result in common-mode and amplitude errors. The device
incorporates an offset register that enables the user to introduce a voltage offset to the DACy channel of the
DACx-y differential pair to compensate for a DC offset error between the two channels. The offset compensation
gives a ±0.2%FSR adjustment window. The differential DAC data register must be rewritten after an update to
the offset register.
40
30
40
30
20
20
10
10
0
0
-10
-20
-30
-40
-10
-20
-30
-40
DACx
DACy
VCM
VDIFF
DACx
DACy
VCM
VDIFF
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
Code
D045
D046
图 48. Differential Bipolar Output (16-Bit):
图 49. Differential Unipolar Output (16-Bit):
±20-V Output Range
0 to 40-V Output Range
26
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Device Functional Modes (接下页)
9.4.3 Power-Down Mode
The DACx1408 DAC output amplifiers and internal reference power-down status can be individually configured
and monitored though the PWDWN registers. Setting a DAC channel in power-down mode disables the output
amplifier and clamps the output pin to ground through an internal 10-kΩ resistor.
The DAC data registers are not cleared when the DAC goes into power-down which makes it possible to have
the same output voltage upon return to normal operation. The DAC data registers can also be updated while in
power-down mode.
After a power-on or reset event all the DAC channels and the internal reference are in power-down mode. The
entire device can be configured into power-down or active modes through the DEV-PWDWN bit.
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9.5 Programming
The DACx1408 is controlled through a flexible four-wire serial interface that is compatible with SPI type
interfaces used on many microcontrollers and DSP controllers. The interface provides access to the DACx1408
registers and can be configured to daisy-chain multiple devices for write operations. The DACx1408 incorporates
an optional error checking mode to validate SPI data communication integrity in noisy environments.
9.5.1 Stand-Alone Operation
A serial interface access cycle is initiated by asserting the CS pin low. The serial clock SCLK can be a
continuous or gated clock. SDI data are clocked on SCLK falling edges. A regular serial interface access cycle is
24 bits long with error checking disabled and 32 bits long with error checking enabled, thus the CS pin must stay
low for at least 24 or 32 SCLK falling edges. The access cycle ends when the CS pin is de-asserted high. If the
access cycle contains less than then minimum clock edges, the communication is ignored. If the access cycle
contains more than the minimum clock edges, only the first 24 or 32 bits are used by the device. When CS is
high, the SCLK and SDI signals are blocked and the SDO is in a Hi-Z state.
In an error checking disabled access cycle (24 bits long) the first byte input to SDI is the instruction cycle which
identifies the request as a read or write command and the 6-bit address to be accessed. The last 16 bits in the
cycle form the data cycle.
表 2. Serial Interface Access Cycle
BIT
23
FIELD
DESCRIPTION
Identifies the communication as a read or write command to the address
register. R/W = 0 sets a write operation. R/W = 1 sets a read operation.
RW
22
x
Don't care bit.
Register address. Specifies the register to be accessed during the read or
write operation.
21-16
A[5:0]
Data cycle bits. If a write command, the data cycle bits are the values to
be written to the register with address A[5:0]. If a read command, the data
cycle bits are don't care values.
15-0
DI[15:0]
Read operations require that the SDO pin is first enabled by setting the SDO-EN bit. A read operation is initiated
by issuing a read command access cycle. After the read command, a second access cycle must be issued to get
the requested data. Data are clocked out on SDO pin either on the falling edge or rising edge of SCLK according
to the FSDO bit.
表 3. SDO Output Access Cycle
BIT
23
FIELD
RW
DESCRIPTION
Echo RW from previous access cycle.
22
x
Echo bit 22 from previous access cycle.
21-16
15-0
A[5:0]
DO[15:0]
Echo address from previous access cycle.
Readback data requested on previous access cycle.
28
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9.5.1.1 Streaming Mode Operation
Since updating the eight channels data registers requires a large amount of data to be passed to the device, the
device supports streaming mode. In streaming mode the DAC data registers can be written to the device without
providing an instruction command for each data register. Streaming mode is enabled by setting the STREN bit.
Once enabled the streaming operation is implemented by holding the CS active and continuing to shift new data
into the device.
The instruction cycle includes the starting address. The device starts writing to this address and automatically
increments the address as long as CS is asserted. If the last DAC data register address has been reached and
CS is still asserted, the additional data is ignored by the device.
/CS
1
2
X
3
4
5
6
7
8
9
23
24
25
39
40
41
55
56
57
71
72
SCLK
SDI
STREAM WRITE COMMAND
ADDRESS N
ADDRESS N+1
ADDRESS N+2
ADDRESS N+3
W
A5
A4
A3
A2
A1
A0
D15 œ D0
D15 œ D0
D15 œ D0
D15 œ D0
SDO
图 50. Serial Interface Streaming Write Cycle
9.5.2 Daisy-Chain Operation
For systems that contain more than one DACx1408 devices, the SDO pin can be used to daisy-chain them
together. The SDO pin must be enabled by setting the SDO-EN bit before initiating the daisy-chain operation.
Daisy-chain operation is useful in reducing the number of serial interface lines.
The first falling edge on the CS pin starts the operation cycle. If more than 24 SCLK pulses are applied while the
CS pin is kept low, the data ripples out of the shift register and is clocked out on the SDO pin either on the falling
edge or rising edge of SCLK according to the FSDO bit. By connecting the SDO output of the first device to the
SDI input of the next device in the chain, a multiple-device interface is constructed. Each device in the system
requires 24 clock pulses. As a result the total number of clock cycles must be equal to 24 × N, where N is the
total number of DACx1408 devices in the daisy chain. When the serial transfer to all devices is complete the CS
signal is taken high. This action transfers the data from the SPI shift registers to the internal registers of each
device in the daisy chain and prevents any further data from being clocked into the input shift register. Daisy-
chain operation is not supported while in streaming mode.
C
B
A
DACx1408
DACx1408
DACx1408
SDO
SDO
SDO
SDI
SDI
SDI
SCLK
SCLK
SCLK
CS
CS
CS
图 51. Daisy-Chain Layout
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9.5.3 Frame Error Checking
If the DACx1408 is used in a noisy environment, error checking can be used to check the integrity of SPI data
communication between the device and the host processor. This feature is enabled by setting the CRC-EN bit.
The error checking scheme is based on the CRC-8-ATM (HEC) polynomial x8 + x2 + x + 1 (that is, 100000111).
When error checking is enabled, the serial interface access cycle width is 32 bits. The normal 24-bit SPI data is
appended with an 8-bit CRC polynomial by the host processor before feeding it to the device. In all serial
interface readback operations the CRC polynomial is output on the SDO pin as part of the 32-bit cycle.
表 4. Error Checking Serial Interface Access Cycle
BIT
31
FIELD
DESCRIPTION
Identifies the communication as a read or write command to the address
register. R/W = 0 sets a write operation. R/W = 1 sets a read operation.
RW
30
CRC-ERROR
A[5:0]
Reserved bit. Set to zero.
Register address. Specifies the register to be accessed during the read or
write operation.
29-24
Data cycle bits. If a write command, the data cycle bits are the values to
be written to the register with address A[5:0]. If a read command, the data
cycle bits are don't care values.
23-8
7-0
DI[15:0]
CRC
8-bit CRC polynomial.
The DACx1408 decodes the 32-bit access cycle to compute the CRC remainder on CS rising edges. If no error
exists, the CRC remainder is zero and data are accepted by the device.
A write operation failing the CRC check causes the data to be ignored by the device. After the write command, a
second access cycle can be issued to determine the error checking results (CRC-ERROR bit) on the SDO pin.
If there is a CRC error, the CRC-ALM bit of the status register is set to 1. The ALMOUT pin can be configured to
monitor a CRC error by setting the CRCALM-EN bit.
表 5. Write Operation Error Checking Cycle
BIT
31
FIELD
RW
DESCRIPTION
Echo RW from previous access cycle (RW = 0).
Returns a 1 when a CRC error is detected, 0 otherwise.
Echo address from previous access cycle.
Echo data from previous access cycle.
30
CRC-ERROR
A[5:0]
29-24
23-8
7-0
DO[15:0]
CRC
Calculated CRC value of bits 31:8.
A read operation must be followed by a second access cycle to get the requested data on the SDO pin. The
error check result (CRC-ERROR bit) from the read command is output on the SDO pin.
As in the case of a write operation failing the CRC check, the CRC-ALM bit of the status register is set to 1 and
the ALMOUT pin, if configured for CRC alerts, is set low.
表 6. Read Operation Error Checking Cycle
BIT
31
FIELD
RW
DESCRIPTION
Echo RW from previous access cycle (RW = 1).
Returns a 1 when a CRC error is detected, 0 otherwise.
Echo address from previous access cycle.
Echo data from previous access cycle.
30
CRC-ERROR
A[5:0]
29-24
23-8
7-0
DO[15:0]
CRC
Calculated CRC value of bits 31:8.
30
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9.6 Register Maps
表 7 lists the memory-mapped registers for the device. All register offset addresses not listed in 表 7 should be
considered as reserved locations and the register contents should not be modified.
表 7. DACx1408 Registers
Offset
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Bh
0Ch
0Eh
0Fh
14h
15h
16h
17h
18h
19h
1Ah
1Bh
21h
22h
Acronym
NOP
Register Name
Section
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
NOP Register
DEVICEID
STATUS
Device ID Register
Status Register
SPICONFIG
GENCONFIG
BRDCONFIG
SYNCCONFIG
TOGGCONFIG0
TOGGCONFIG1
DACPWDWN
DACRANGE0
DACRANGE1
TRIGGER
BRDCAST
DAC0
SPI Configuration Register
General Configuration Register
Broadcast Configuration Register
Sync Configuration Register
DAC[7:4] Toggle Configuration Register
DAC[3:0] Toggle Configuration Register
DAC Power-Down Register
DAC[7:4] Range Register
DAC[3:0] Range Register
Trigger Register
Broadcast Data Register
DAC0 Data Register
DAC1
DAC1 Data Register
DAC2
DAC2 Data Register
DAC3
DAC3 Data Register
DAC4
DAC4 Data Register
DAC5
DAC5 Data Register
DAC6
DAC6 Data Register
DAC7
DAC7 Data Register
OFFSET0
OFFSET1
DAC[6-7;4-5] Differential Offset Register
DAC[2-3;0-1] Differential Offset Register
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Complex bit access types are encoded to fit into small table cells. 表 8 shows the codes that are used for access
types in this section.
表 8. Access Type Codes
Access Type
Code
R
Description
Read Type
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default value
Register Array Variables
When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
i,j,k,l,m,n
When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.
y
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9.6.1 NOP Register (Offset = 00h) [reset = 0000h]
NOP is shown in 图 52 and described in 表 9.
Return to Summary Table.
图 52. NOP Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOP
W-0h
表 9. NOP Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
No operation. Write 0000h for proper no-operation command.
NOP
W
0h
9.6.2 DEVICEID Register (Offset = 01h) [reset = ----h]
DEVICEID is shown in 图 53 and described in 表 10.
Return to Summary Table.
图 53. DEVICEID Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
DEVICEID
R----h
4
3
DEVICEID
R----h
VERSIONID
R-0h
表 10. DEVICEID Register Field Descriptions
Bit
Field
Type
Reset
Description
Device ID
DAC81408: 298h
DAC71408: 288h
DAC61408: 248h
15-2
1-0
DEVICEID
R
---h
VERSIONID
R
0h
Version ID. Subject to change.
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9.6.3 STATUS Register (Offset = 02h) [reset = 0000h]
STATUS is shown in 图 54 and described in 表 11.
Return to Summary Table.
图 54. STATUS Register
15
7
14
6
13
12
4
11
10
9
8
RESERVED
R-0h
5
3
2
1
0
RESERVED
R-0h
CRC-ALM
R-0h
DAC-BUSY
R-0h
TEMP-ALM
R-0h
表 11. STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15-3
RESERVED
CRC-ALM
R
0h
This bit is reserved.
2
1
R
R
0h
0h
CRC-ALM = 1 indicates a CRC error.
DAC-BUSY
DAC-BUSY = 1 indicates DAC registers are not ready for updates.
TEMP-ALM = 1 indicates die temperature is over +140°C. A thermal
alarm event forces the DAC outputs to go into power-down mode.
0
TEMP-ALM
R
0h
34
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9.6.4 SPICONFIG Register (Offset = 03h) [reset = 0A24h]
SPICONFIG is shown in 图 55 and described in 表 12.
Return to Summary Table.
图 55. SPICONFIG Register
15
14
13
12
11
10
9
8
RESERVED
R-0h
TEMPALM-EN DACBUSY-EN
CRCALM-EN
R/W-1h
RESERVED
R-0h
R/W-1h
R/W-0h
7
6
5
4
3
2
1
0
RESERVED
SOFTTOGGLE DEV-PWDWN
-EN
CRC-EN
STR-EN
SDO-EN
FSDO
RESERVED
R-1h
R/W-0h
R/W-1h
R/W-0h
R/W-0h
R/W-1h
R/W-0h
R-0h
表 12. SPICONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
RESERVED
R
0h
This bit is reserved.
11
10
TEMPALM-EN
R/W
R/W
1h
0h
When set to 1 a thermal alarm triggers the ALMOUT pin.
When set to 1 the ALMOUT pin is set between DAC output updates.
Contrary to other alarm events, this alarm resets automatically.
DACBUSY-EN
9
8
7
6
CRCALM-EN
RESERVED
R/W
R
1h
0h
1h
0h
When set to 1 a CRC error triggers the ALMOUT pin.
This bit is reserved.
RESERVED
R
This bit is reserved.
SOFTTOGGLE-EN
R/W
When set to 1 enables soft toggle operation.
DEV-PWDWN = 1 sets the device in power-down mode
DEV-PWDWN = 0 sets the device in active mode
5
DEV-PWDWN
R/W
1h
4
3
2
CRC-EN
STR-EN
SDO-EN
R/W
R/W
R/W
0h
0h
1h
When set to 1 frame error checking is enabled.
When set to 1 streaming mode operation is enabled.
When set to 1 the SDO pin is operational.
Fast SDO bit (half-cycle speedup). When 0, SDO updates during
SCLK rising edges. When 1, SDO updates during SCLK falling
edges.
1
0
FSDO
R/W
R
0h
0h
RESERVED
This bit is reserved.
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9.6.5 GENCONFIG Register (Offset = 04h) [reset = 7F00h]
GENCONFIG is shown in 图 56 and described in 表 13.
Return to Summary Table.
图 56. GENCONFIG Register
15
14
13
12
11
10
2
9
8
RESERVED
R-0h
REF-PWDWN
R/W-1h
RESERVED
R-1h
7
6
5
4
3
1
0
RESERVED
RESERVED
DAC-6-7-DIFF- DAC-4-5-DIFF- DAC-2-3-DIFF- DAC-0-1-DIFF-
RESERVED
RESERVED
EN
EN
EN
EN
R-0h
R-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R-0h
R-0h
表 13. GENCONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R
0h
This bit is reserved.
REF-PWDWN = 1 powers down the internal reference
REF-PWDWN = 0 activates the internal reference
14
REF-PWDWN
R/W
1h
13-8
RESERVED
RESERVED
RESERVED
R
R
R
1h
0h
0h
This bit is reserved.
This bit is reserved.
This bit is reserved.
7
6
5
4
3
2
DAC-6-7-DIFF-EN
DAC-4-5-DIFF-EN
DAC-2-3-DIFF-EN
DAC-0-1-DIFF-EN
R/W
R/W
R/W
R/W
0h
0h
0h
0h
When set to 1 the corresponding DAC pair is set to operate in
differential mode. The DAC data registers must be rewritten after
enabling or disabling differential operation.
1
0
RESERVED
RESERVED
R
R
0h
0h
This bit is reserved.
This bit is reserved.
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9.6.6 BRDCONFIG Register (Offset = 05h) [reset = FFFFh]
BRDCONFIG is shown in 图 57 and described in 表 14.
Return to Summary Table.
图 57. BRDCONFIG Register
15
14
13
12
11
10
9
8
RESERVED
RESERVED
RESERVED
RESERVED
DAC7-
DAC6-
DAC5-
DAC4-
BRDCAST-EN BRDCAST-EN BRDCAST-EN BRDCAST-EN
R-1h
R-1h
R-1h
R-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
7
6
5
4
3
2
1
0
DAC3-
DAC2-
DAC1-
DAC0-
RESERVED
RESERVED
RESERVED
RESERVED
BRDCAST-EN BRDCAST-EN BRDCAST-EN BRDCAST-EN
R/W-1h
R/W-0h
R/W-0h
R/W-0h
R-1h
R-1h
R-1h
R-1h
表 14. BRDCONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
RESERVED
RESERVED
RESERVED
R
1h
This bit is reserved.
This bit is reserved.
This bit is reserved.
This bit is reserved.
14
13
12
R
R
R
1h
1h
1h
11
10
9
DAC7-BRDCAST-EN
DAC6-BRDCAST-EN
DAC5-BRDCAST-EN
DAC4-BRDCAST-EN
DAC3-BRDCAST-EN
DAC2-BRDCAST-EN
DAC1-BRDCAST-EN
DAC0-BRDCAST-EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1h
1h
1h
1h
1h
1h
1h
1h
When set to 1 the corresponding DAC is set to update its output to
the value set in the BRDCAST register. All DAC channels must be
configured in single-ended mode for broadcast operation. If one or
more outputs are configured in differential mode the broadcast mode
is ignored.
8
7
6
When cleared to
0 the corresponding DAC output remains
unaffected by a BRDCAST command.
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
R
R
R
R
1h
1h
1h
1h
This bit is reserved.
This bit is reserved.
This bit is reserved.
This bit is reserved.
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9.6.7 SYNCCONFIG Register (Offset = 06h) [reset = 0000h]
SYNCCONFIG is shown in 图 58 and described in 表 15.
Return to Summary Table.
图 58. SYNCCONFIG Register
15
14
13
12
11
10
9
8
RESERVED
RESERVED
RESERVED
RESERVED
DAC7-SYNC-
EN
DAC6-SYNC-
EN
DAC5-SYNC-
EN
DAC4-SYNC-
EN
R-0h
7
R-0h
6
R-0h
5
R-0h
4
R/W-0h
R/W-0h
R/W-0h
R/W-0h
3
2
1
0
DAC3-SYNC-
EN
DAC2-SYNC-
EN
DAC1-SYNC-
EN
DAC0-SYNC-
EN
RESERVED
RESERVED
RESERVED
RESERVED
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R-0h
R-0h
R-0h
R-0h
表 15. SYNCCONFIG Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
15
R
0h
This bit is reserved.
This bit is reserved.
This bit is reserved.
This bit is reserved.
14
13
12
RESERVED
RESERVED
RESERVED
R
R
R
0h
0h
0h
11
10
9
DAC7-SYNC-EN
DAC6-SYNC-EN
DAC5-SYNC-EN
DAC4-SYNC-EN
DAC3-SYNC-EN
DAC2-SYNC-EN
DAC1-SYNC-EN
DAC0-SYNC-EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
0h
When set to 1 the corresponding DAC output is set to update in
response to an LDAC trigger (synchronous mode).
8
7
When cleared to 0 the corresponding DAC output is set to update
immediately (asynchronous mode).
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
R
R
R
R
0h
0h
0h
0h
This bit is reserved.
This bit is reserved.
This bit is reserved.
This bit is reserved.
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9.6.8 TOGGCONFIG0 Register (Offset = 07h) [reset = 0000h]
TOGGCONFIG0 is shown in 图 59 and described in 表 16.
Return to Summary Table.
图 59. TOGGCONFIG0 Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R-0h
RESERVED
R-0h
RESERVED
R-0h
RESERVED
R-0h
7
6
5
4
3
DAC7-AB-TOGG-EN
R/W-0h
DAC6-AB-TOGG-EN
R/W-0h
DAC5-AB-TOGG-EN
R/W-0h
DAC4-AB-TOGG-EN
R/W-0h
表 16. TOGGCONFIG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-14
13-12
11-10
9-8
RESERVED
R
0h
This bit is reserved.
This bit is reserved.
This bit is reserved.
This bit is reserved.
RESERVED
RESERVED
RESERVED
R
R
R
0h
0h
0h
7-6
5-4
3-2
DAC7-AB-TOGG-EN
DAC6-AB-TOGG-EN
DAC5-AB-TOGG-EN
R/W
R/W
R/W
0h
0h
0h
Enables toggle mode operation and configures the toggle pin or soft
toggle bit:
0h = Toggle mode disabled
1h = Toggle mode enabled: TOGGLE0
2h = Toggle mode enabled: TOGGLE1
3h = Toggle mode enabled: TOGGLE2
1-0
DAC4-AB-TOGG-EN
R/W
0h
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9.6.9 TOGGCONFIG1 Register (Offset = 08h) [reset = 0000h]
TOGGCONFIG1 is shown in 图 60 and described in 表 17.
Return to Summary Table.
图 60. TOGGCONFIG1 Register
15
14
13
12
11
10
9
8
DAC3-AB-TOGG-EN
R/W-0h
DAC2-AB-TOGG-EN
R/W-0h
DAC1-AB-TOGG-EN
R/W-0h
DAC0-AB-TOGG-EN
R/W-0h
7
6
5
4
3
2
1
0
RESERVED
R-0h
RESERVED
R-0h
RESERVED
R-0h
RESERVED
R-0h
表 17. TOGGCONFIG1 Register Field Descriptions
Bit
Field
Type
R/W
R/W
R/W
Reset
0h
Description
15-14
13-12
11-10
DAC3-AB-TOGG-EN
DAC2-AB-TOGG-EN
DAC1-AB-TOGG-EN
Enables toggle mode operation and configures the toggle pin or soft
toggle bit:
0h
0h = Toggle mode disabled
0h
1h = Toggle mode enabled: TOGGLE0
2h = Toggle mode enabled: TOGGLE1
3h = Toggle mode enabled: TOGGLE2
9-8
DAC0-AB-TOGG-EN
R/W
0h
7-6
5-4
3-2
1-0
RESERVED
RESERVED
RESERVED
RESERVED
R
R
R
R
0h
0h
0h
0h
This bit is reserved.
This bit is reserved.
This bit is reserved.
This bit is reserved.
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9.6.10 DACPWDWN Register (Offset = 09h) [reset = FFFFh]
DACPWDWN is shown in 图 61 and described in 表 18.
Return to Summary Table.
图 61. DACPWDWN Register
15
14
13
12
11
10
9
8
RESERVED
R-1h
RESERVED
R-1h
RESERVED
R-1h
RESERVED
R-1h
DAC7-PWDWN DAC6-PWDWN DAC5-PWDWN DAC4-PWDWN
R/W-1h
R/W-1h
R/W-1h
R/W-1h
7
6
5
4
3
2
1
0
DAC3-PWDWN DAC2-PWDWN DAC1-PWDWN DAC0-PWDWN
RESERVED
R-1h
RESERVED
R-1h
RESERVED
R-1h
RESERVED
R-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
表 18. DACPWDWN Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
RESERVED
RESERVED
RESERVED
R
1h
This bit is reserved.
This bit is reserved.
This bit is reserved.
This bit is reserved.
14
13
12
R
R
R
1h
1h
1h
11
10
9
DAC7-PWDWN
DAC6-PWDWN
DAC5-PWDWN
DAC4-PWDWN
DAC3-PWDWN
DAC2-PWDWN
DAC1-PWDWN
DAC0-PWDWN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1h
1h
1h
1h
1h
1h
1h
1h
8
When set to 1 the corresponding DAC is in power-down mode and
its output is connected to GND through a 10-kΩ internal resistor.
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
R
R
R
R
1h
1h
1h
1h
This bit is reserved.
This bit is reserved.
This bit is reserved.
This bit is reserved.
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9.6.11 DACRANGEn Register (Offset = 0Bh - 0Ch) [reset = 0000h]
DACRANGEn is shown in 图 62 and described in 表 19.
Return to Summary Table.
图 62. DACRANGEn Register
15
7
14
13
12
4
11
3
10
9
8
0
DACa-RANGE[3:0]
W-0h
DACb-RANGE[3:0]
W-0h
6
5
2
1
DACc-RANGE[3:0]
W-0h
DACd-RANGE[3:0]
W-0h
表 19. DACRANGEn Register Field Descriptions
Bit
Field
Type
W
Reset
0h
Description
15-12
11-8
7-4
DACa-RANGE[3:0]
DACb-RANGE[3:0]
DACc-RANGE[3:0]
Sets the output range for the corresponding DAC.
0000 = 0 to 5 V
W
0h
W
0h
0001 = 0 to 10 V
0010 = 0 to 20 V
0100 = 0 to 40 V
1001 = -5 V to +5 V
1010 = -10 V to +10 V
1100 = -20 V to +20 V
1110 = -2.5 V to +2.5 V
All others: invalid
3-0
DACd-RANGE[3:0]
W
0h
The two outputs of a differential DAC pair must be configured to the
same output range prior to setting them up as a differential pair.
a: 7 or 3; b: 6 or 2; c: 5 or 1; d: 4 or 0
42
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9.6.12 TRIGGER Register (Offset = 0Eh) [reset = 0000h]
TRIGGER is shown in 图 63 and described in 表 20.
Return to Summary Table.
图 63. TRIGGER Register
15
14
13
12
11
10
2
9
1
8
RESERVED
W-0h
ALM-RESET
W-0h
7
6
5
4
3
0
AB-TOG2
W-0h
AB-TOG1
W-0h
AB-TOG0
W-0h
LDAC
W-0h
SOFT-RESET[3:0]
W-0h
表 20. TRIGGER Register Field Descriptions
Bit
Field
Type
Reset
Description
15-9
RESERVED
W
0h
This bit is reserved
Set this bit to 1 to clear an alarm event. Not applicable for a DAC-
BUSY alarm event.
8
ALM-RESET
W
0h
If soft toggle is enabled set, this bit controls the toggle between
values for those DACs that have been set in toggle mode 2 in the
TOGGCONFIG register. Set to 1 to update to Register B and clear to
0 for Register A.
7
AB-TOG2
AB-TOG1
AB-TOG0
W
0h
If soft toggle is enabled set, this bit controls the toggle between
values for those DACs that have been set in toggle mode 1 in the
TOGGCONFIG register. Set to 1 to updated to Register B and clear
to 0 for Register A.
6
5
W
W
0h
0h
If soft toggle is enabled set, this bit controls the toggle between
values for those DACs that have been set in toggle mode 0 in the
TOGGCONFIG register. Set to 1 to update to Register B and clear to
0 for Register A.
Set this bit to 1 to synchronously load those DACs who have been
set in synchronous mode in the SYNCCONFIG register.
4
LDAC
W
W
0h
0h
When set to the reserved code 1010 resets the device to its default
state.
3-0
SOFT-RESET[3:0]
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9.6.13 BRDCAST Register (Offset = 0Fh) [reset = 0000h]
BRDCAST is shown in 图 64 and described in 表 21.
Return to Summary Table.
图 64. BRDCAST Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BRDCAST-DATA[15:0]
R/W-0h
表 21. BRDCAST Register Field Descriptions
Bit
Field
Type
Reset
Description
Writing to the BRDCAST register forces those DAC channels that
have been set to broadcast in the BRDCONFIG register to update its
active register data to the BRDCAST-DATA one.
Data is MSB aligned in straight binary format and follows the format
below:
15-0
BRDCAST-DATA[15:0]
R/W
0h
DAC81408: { DATA[15:0] }
DAC71408: { DATA[13:0], x, x }
DAC61408: { DATA[11:0], x, x, x, x}
x – Don 't care bits
9.6.14 DACn Register (Offset = 14h - 1Bh) [reset = 0000h]
DACn is shown in 图 65 and described in 表 22.
Return to Summary Table.
图 65. DACn Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DACn-DATA[15:0]
R/W-0h
表 22. DACn Register Field Descriptions
Bit
Field
Type
Reset
Description
Stores the 16-, 14- or 12-bit data to be loaded to DACn in MSB
aligned straight binary format. In differential DAC mode data is
loaded into the lowest-valued DAC in the DAC pair (in pair DAC 01,
data is loaded into DAC0 and writes to DAC1 are ignored).
Data follows the format below:
DAC81408: { DATA[15:0] }
DAC71408: { DATA[13:0], x, x }
DAC61408: { DATA[11:0], x, x, x, x}
x – Don 't care bits
15-0
DACn-DATA[15:0]
R/W
0h
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9.6.15 OFFSETn Register (Offset = 21h - 22h) [reset = 0000h]
OFFSETn is shown in 图 66 and described in 表 23.
Return to Summary Table.
图 66. OFFSETn Register
15
7
14
6
13
5
12
11
10
2
9
1
8
0
OFFSETab[7:0]
R/W-0h
4
3
OFFSETcd[7:0]
R/W-0h
表 23. OFFSETn Register Field Descriptions
Bit
15-8
Field
OFFSETab[7:0]
Type
Reset
Description
R/W
0h
Provides offset adjustment to DACy in the differential DACx-y pair in
two 's complement format.
Data follows the format below:
•
•
•
DAC81408:
–
–
Format: { OFFSET[7:0] }
Range: -128 LSB to +127 LSB
DAC71408:
–
–
Format: { OFFSET[5:0], x, x }
Range: -32 LSB to +31 LSB
7-0
OFFSETcd[7:0]
R/W
0h
DAC61408:
–
–
Format: { OFFSET[3:0], x, x, x, x}
Range: -8 LSB to +7 LSB
x – Don 't care bits
The differential DAC data register must be rewritten after updating
the offset register.
ab: 6-7 or 2-3; cd: 4-5 or 0-1
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10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The DACx1408 family provides 8-channel high-voltage and high-current output in both single-ended and
differential configurations. The outputs can be configured to multiple ranges and square waves can be generated
using the toggle modes. This makes the DAC family suitable for Automatic Test Equipment (ATE) and servo
control applications. In addition to these features, the low power-on glitch of this DAC makes it suitable for Motor
Control applications like CNC machines as well.
10.2 Typical Application
图 67. Schematic for Remote Ground Tracking
10.2.1 Design Requirements
In ATE and Motor Control applications, typically the systems are designed modular wherein the control module is
located spatially away from the Device Under Test (DUT) module. Such a scheme allows ground potentials
across modules to vary due to the impedance of the interconnects. This ground potential variation, in turn
introduces inaccuracies to the DAC output when measured with respect to the remote or DUT ground. 图 67
provides a method to compensate the variations in the remote ground. The ground variation in such applications
is typically within ±300 mV that includes DC and 50 Hz/60 Hz mains frequency components. While the best way
to handle this variation is to put opamps in level shifter configuration at each output, a low cost and low footprint
solution is always preferable. The following sections focus on the latter approach.
46
版权 © 2018, Texas Instruments Incorporated
DAC81408, DAC71408, DAC61408
www.ti.com.cn
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
Typical Application (接下页)
10.2.2 Detailed Design Procedure for Remote Ground Tracking
In order to make the DAC outputs follow the remote ground, the best approach is to level shift the reference
input. 图 67 depicts a method wherein both the REF and REFGND inputs are level shifted with respect to
DUTGND. However, as the DAC doesn’t allow the REFGND to become negative compared to GND, an offset
voltage of 300mV needs to be applied as shown. This method requires an external 2.5V reference and a way to
generate a stable 300-mV reference. A dual opamp U1 is used to shift both REFGND and REF by (DUTGND +
300-mV offset). 表 24 provides the nodal analysis of the circuit. As evident, the DAC outputs track the DUTGND
with an offset of 300mV. This offset can be easily compensated in software. Note that the absolute max values
between REFGND and GND must be respected. When the absolute max values are reached, they should only
be for a transient period and not for sustained amount of time.
表 24. Nodal Analysis of the Circuit
DUTGND
(GND±0.3V)
VOUT-GND AT
0V CODE
VOUT-GND AT 5V VOUT-DUTGND AT VOUT-DUTGND
REFGND PIN
REF PIN
CODE
5.3V
5.6V
5V
0V CODE
AT 5V CODE
0V
0.3V
0.6V
0V
2.8V
3.1V
2.5V
0.3V
0.6V
0V
0.3V
5.3V
0.3V
-0.3V
0.3V
5.3V
0.3V
5.3V
10.2.2.1 Generating 300mV Offset
There is no off-the-shelf solution for generating a 300-mV offset, unfortunately. 图 67 depicts a method to
generate it using discrete components. It uses LM4041 adjustable shunt regulator on high-side from the 2.5-V
reference. It has a reference input pin that sets the voltage across this device. Given that VRef is 1.233 V,
choosing R1 = 16 kΩ and R2 = 12 kΩ the voltage Vo can be calculated by superposition as 2.16 V. This will
provide an offset of (2.5 V – 2.16 V) = 340 mV that will provide a safe margin from DAC ground.
10.2.2.2 Amplifier Selection
The amplifier needs to be bipolar in order to operate linearly near ground. A dual package is preferable for
optimizing area. Considering these factors, TLV2442A seems to be the best option from cost and accuracy
points of view. Other parts like OPA2277 can be used when higher accuracy is required.
10.2.2.3 Passive Component Selection
In order to minimize additional offset and gain error the gain resistors around the opamps need to be matched.
An 8-channel resistor network can be used for better matching. Rc and Cc values can be chosen as 22 Ω and
1000 pF, respectively in order to compensate the pole caused by the large bypass capacitor at the opamp
outputs.
版权 © 2018, Texas Instruments Incorporated
47
DAC81408, DAC71408, DAC61408
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
www.ti.com.cn
10.2.3 Application Curves
图 68. Power-On Glitch With DUTGND Compensation
图 69. INL (Major Code) at Different Values of DUTGND
48
版权 © 2018, Texas Instruments Incorporated
DAC81408, DAC71408, DAC61408
www.ti.com.cn
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
11 Power Supply Recommendations
The DACx1408 requires 5 power supply inputs: VIO, VDD, VAA, VCC and VSS. VDD and VAA should be at
same level. Assuming VIO and VDD/VAA to be different, there are 4 separate power supply sources required. It
is recommended to provide a 0.1-µF ceramic capacitor close to each power supply pin. Please note that VCC
and VSS have 2 pins each. In addition, a 4.7-µF or 10-µF bulk capacitor is recommended for each power supply.
Tantalum or aluminum types can be chosen for the bulk capacitors. There is no sequencing requirement for the
power supplies. As the DAC output range is configurable, the power supply headroom should be taken care of
for achieving linearity at codes close to power supply rails. When sourcing or sinking current from or to the DAC
output, the heat dissipation needs to be considered. For example, a typical application of MZM bias with 25-mA
load current from or to 12 channels with 2.5-V power supply headroom can create a power dissipation across the
DAC of (12*2.5*25 mA) = 0.75 W. The thermal design to dissipate this much of power may involve inclusion of
heat sinks in order to avoid thermal shutdown of the device.
版权 © 2018, Texas Instruments Incorporated
49
DAC81408, DAC71408, DAC61408
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
www.ti.com.cn
12 Layout
12.1 Layout Guidelines
The pin out of DACx1408 has been designed in such a way that the analog, digital and power pins are spatially
separated from each other, which makes the PCB layout simple. An example layout is shown in 图 70. As
evident, every power supply pin has a 0.1-µF capacitor close to it. The layout of the analog and digital signals
should be laid out away from each other or on different PCB layers. It is recommended to provide an unbroken
reference plane (either ground or VIO) for the digital signals. The higher frequency signals such as SCLK and
SDI should have appropriate impedance termination in order to address signal integrity.
12.2 Layout Example
图 70. Example Layout
50
版权 © 2018, Texas Instruments Incorporated
DAC81408, DAC71408, DAC61408
www.ti.com.cn
ZHCSIG8A –JULY 2018–REVISED NOVEMBER 2018
13 器件和文档支持
13.1 文档支持
13.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件,以及申请样片或购买产品的快速链
接。
表 25. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
DAC81408
DAC71408
DAC61408
13.3 接收文档更新通知
要接收文档更新通知,请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册,即可每周接收产
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
13.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
13.5 商标
E2E is a trademark of Texas Instruments.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
版权 © 2018, Texas Instruments Incorporated
51
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC61408RHAR
DAC61408RHAT
DAC71408RHAR
DAC71408RHAT
DAC81408RHAR
DAC81408RHAT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHA
RHA
RHA
RHA
RHA
RHA
40
40
40
40
40
40
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
DAC61408
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
DAC61408
DAC71408
DAC71408
DAC81408
DAC81408
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC61408RHAR
DAC61408RHAT
DAC71408RHAR
DAC71408RHAT
DAC81408RHAR
DAC81408RHAT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHA
RHA
RHA
RHA
RHA
RHA
40
40
40
40
40
40
2500
250
330.0
180.0
330.0
180.0
330.0
180.0
16.4
16.4
16.4
16.4
16.4
16.4
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
1.1
1.1
1.1
1.1
1.1
1.1
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
2500
250
2500
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC61408RHAR
DAC61408RHAT
DAC71408RHAR
DAC71408RHAT
DAC81408RHAR
DAC81408RHAT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHA
RHA
RHA
RHA
RHA
RHA
40
40
40
40
40
40
2500
250
367.0
213.0
367.0
213.0
367.0
213.0
367.0
191.0
367.0
191.0
367.0
191.0
38.0
35.0
38.0
35.0
38.0
35.0
2500
250
2500
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHA 40
6 x 6, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225870/A
www.ti.com
PACKAGE OUTLINE
RHA0040C
VQFN - 1 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
0.5
0.3
PIN 1 INDEX AREA
6.1
5.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
4.7 0.1
2X 4.5
(0.2) TYP
11
20
36X 0.5
10
21
EXPOSED
THERMAL PAD
2X
41
SYMM
4.5
SEE TERMINAL
DETAIL
1
30
0.3
0.2
40X
40
31
PIN 1 ID
(OPTIONAL)
0.1
0.05
C A B
SYMM
0.5
0.3
40X
4219053/B 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHA0040C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.7)
SYMM
40
31
40X (0.6)
1
30
40X (0.25)
4X
(1.35)
(
0.2) TYP
VIA
(0.75)
TYP
41
(5.8)
SYMM
4X
(1.5)
36X (0.5)
10
21
(R0.05)
TYP
11
(0.75) TYP
20
4X (1.5)
(5.8)
4X (1.35)
LAND PATTERN EXAMPLE
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219053/B 03/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHA0040C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.5) TYP
9X ( 1.3)
(R0.05) TYP
40
31
40X (0.6)
1
30
40X (0.25)
41
(1.5)
TYP
SYMM
(5.8)
36X (0.5)
10
21
METAL
TYP
11
20
SYMM
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 41:
69% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
4219053/B 03/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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