DAC70502 [TI]
双通道、1LSB INL、14 位、SPI 电压输出数模转换器 (DAC);
| 型号： | DAC70502 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双通道、1LSB INL、14 位、SPI 电压输出数模转换器 (DAC) 转换器 数模转换器 |
| 文件： | 总47页 (文件大小：2136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DAC80502, DAC70502, DAC60502
ZHCSKJ2A –NOVEMBER 2019–REVISED APRIL 2020
具有精密内部基准的 DACx0502 双通道 16 位、14 位和 12 位 1LSB INL
电压输出 DAC
1 特性
3 说明
1
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•
•
•
•
•
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16 位性能：1LSB INL 和 DNL（最大值）
16 位 DAC80502、14 位 DAC70502 和 12 位
DAC60502 (DACx0502) 数模转换器 (DAC) 均为具有
电压输出的高精度、低功耗器件。
低毛刺脉冲能量：4nV-s
宽电源电压范围：2.7V 至 5.5V
缓冲输出范围：5V、2.5V 或 1.25V
低功耗：1mA/通道 (5.5V)
DACx0502 线性度小于 1LSB。凭借高精度和微型封装
特性，DACx0502 非常适合以下 应用： 增益和失调电
压校准、电流或电压设置点设定和电源控制。这些器件
包括一个 2.5V、5ppm/°C 内部基准，可提供 1.25V、
2.5V 或 5V 的满量程输出电压范围。DACx0502 采用
了上电复位电路，可确保 DAC 输出根据 RSTSEL 引
脚的状态以零电平或中间电平上电，并在向器件写入有
效代码之前一直保持该电平。
集成 5ppm/˚C（最大值）、2.5V 精密基准
引脚可选串行接口
–
–
3 线制，兼容 SPI，高达 50MHz
两线制，兼容 I2C
•
•
•
•
上电复位：零电平或中间电平
VDD = 5.5V 时的 VIH 为 1.62V
温度范围：–40˚C 至 +125˚C
封装：微型 10 引脚 WSON
DACx0502 的数字接口可通过 SPI2C 引脚配置为 SPI
或 I2C 模式。在 SPI 模式下，DACx0502 使用一个在
高达 50MHz 的时钟频率下运行的通用 3 线制串行接
口。在 I2C 模式下，DACx0502 支持标准 (100kbps)、
快速 (400kbps) 和快速+ (1.0Mbps) 工作模式。
2 应用
•
•
•
•
•
•
•
•
•
示波器 (DSO)
电池测试
半导体测试
器件信息(1)
数据采集 (DAQ)
器件型号
DAC80502
封装
封装尺寸（标称值）
LCD 测试
小型蜂窝基站
DAC70502
DAC60502
WSON (10)
2.50mm × 2.50mm
模拟输出模块
过程分析（pH、气体、浓度、力和湿度）
直流电源、交流电源、电子负载
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
功能方框图
VREFIO
VDD
Internal
Reference
SPI2C
SCLK or SCL
DAC
Buffer
DAC
Register
BUF
VOUTA
VOUTB
DAC
SDIN or SDA
or A0
Channel A
Channel B
SYNC
RSTSEL
Power Down Logic
Resistive Network
Power On Reset
AGND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS793
DAC80502, DAC70502, DAC60502
ZHCSKJ2A –NOVEMBER 2019–REVISED APRIL 2020
www.ti.com.cn
目录
8.5 Programming........................................................... 23
8.6 Register Maps......................................................... 29
Application and Implementation ........................ 34
9.1 Application Information............................................ 34
9.2 Typical Application .................................................. 34
9.3 System Examples .................................................. 36
9.4 What To Do and What Not To Do........................... 37
9.5 Initialization Setup................................................... 37
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements : SPI Mode............................. 9
7.7 Timing Requirements : I2C Standard Mode.............. 9
7.8 Timing Requirements : I2C Fast Mode...................... 9
7.9 Timing Requirements : I2C Fast-Mode Plus ........... 10
7.10 Typical Characteristics.......................................... 11
Detailed Description ............................................ 20
8.1 Overview ................................................................. 20
8.2 Functional Block Diagram ....................................... 20
8.3 Feature Description................................................. 20
8.4 Device Functional Modes........................................ 22
9
10 Power Supply Recommendations ..................... 38
11 Layout................................................................... 38
11.1 Layout Guidelines ................................................. 38
11.2 Layout Example .................................................... 38
12 器件和文档支持 ..................................................... 39
12.1 文档支持................................................................ 39
12.2 相关链接................................................................ 39
12.3 接收文档更新通知 ................................................. 39
12.4 支持资源................................................................ 39
12.5 商标....................................................................... 39
12.6 静电放电警告......................................................... 39
12.7 Glossary................................................................ 39
13 机械、封装和可订购信息....................................... 39
8
4 修订历史记录
Changes from Original (November 2019) to Revision A
Page
•
已更改 将器件从“预告信息（预发布）”更改为“生产数据（正在供货）”.................................................................................. 1
2
Copyright © 2019–2020, Texas Instruments Incorporated
DAC80502, DAC70502, DAC60502
www.ti.com.cn
ZHCSKJ2A –NOVEMBER 2019–REVISED APRIL 2020
5 Device Comparison Table
DEVICE
RESOLUTION
16-bit
REFERENCE
DAC80502
DAC70502
DAC60502
Internal (default) or external
Internal (default) or external
Internal (default) or external
14-bit
12-bit
6 Pin Configuration and Functions
DRX Package
10-Pin WSON
Top View
VDD
VOUTA
RSTSEL
AGND
1
2
3
4
5
10
VREFIO
9
8
7
6
VOUTB
SDIN/SDA
SYNC/A0
SCLK/SCL
SPI2C
Not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
AGND
4
Ground
Ground reference point for all circuitry on the device
Reset select pin.
RSTSEL
3
6
Input
Input
DACs power up to zero scale if RSTSEL = AGND.
DACs power up to midscale if RSTSEL = VDD
Serial interface clock. SPI or I2C mode.
SCLK/SCL
SDIN/SDA
SPI mode: Serial interface data input. Data are clocked into the input shift register on each falling
edge of the SCLK pin.
8
Input/Output
I2C mode: Data are clocked into or out of the input register. This pin is a bidirectional, SDA drain
data line that must be connected to the supply voltage with an external pull-up resistor.
Interface select pin. The SPI2C pin must be kept static after device powers up.
If SPI2C = 0, the digital interface is in SPI mode
SPI2C
5
7
Input
Input
If SPI2C = 1, the digital interface is in I2C mode
SPI mode: Active low serial data enable. This input is the frame-synchronization signal for the
serial data. When the signal goes low, the serial interface input shift register is enabled.
I2C mode: Four-state address input.
SYNC/A0
VDD
1
2
9
Power
Output
Output
Analog supply voltage (2.7 V to 5.5 V)
Analog output voltage from DAC A
Analog output voltage from DAC B
VOUTA
VOUTB
When using the internal reference, this pin is the reference output voltage pin (default).
When operating with an external reference, this pin is the reference input to the device.
VREFIO
10
Input/Output
Copyright © 2019–2020, Texas Instruments Incorporated
3
DAC80502, DAC70502, DAC60502
ZHCSKJ2A –NOVEMBER 2019–REVISED APRIL 2020
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–10
MAX
6
UNIT
VDD to AGND
Input voltage
VREFIO to AGND
VDD + 0.3
VDD + 0.3
VDD + 0.3
10
V
Digital input(s) to AGND
VOUTx to AGND
Output voltage
Input current
V
Current into any pin
Junction temperature (TJ)
Storage temperature (Tstg
mA
–40
150
Temperature
°C
)
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-
001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
MAX
UNIT
POWER SUPPLY
VDD to AGND
DIGITAL INPUTS
VIH
Positive supply voltage to ground
5.5
V
Input high voltage
Input low voltage
1.62
V
V
VIL
0.45
REFERENCE INPUT
2.7 V ≤ VDD < 3.3 V,
reference divider disabled (REF-DIV bit = 0)
VREFIO to AGND
VREFIO to AGND
VREFIO to AGND
VREFIO to AGND
1.2
2.4
1.2
2.4
0.5 × (VDD – 0.2)
(VDD – 0.2)
0.5 × VDD
VDD
V
V
V
V
2.7 V ≤ VDD < 3.3 V,
reference divider enabled (REF-DIV bit = 1)
3.3 V ≤ VDD ≤ 5.5 V,
reference divider disabled (REF-DIV bit = 0)
3.3 V ≤ VDD ≤ 5.5 V,
reference divider enabled (REF-DIV bit = 1)
TEMPERATURE
TA
Operating temperature
–40
125
°C
4
Copyright © 2019–2020, Texas Instruments Incorporated
DAC80502, DAC70502, DAC60502
www.ti.com.cn
ZHCSKJ2A –NOVEMBER 2019–REVISED APRIL 2020
7.4 Thermal Information
DACx0502
THERMAL METRIC(1)
DRX (WSON)
10 PINS
99.7
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
49.9
35.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.7
ΨJB
35.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
all minimum and maximum values at TA = –40°C to +125°C and all typcal values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, external
or internal VREFIO = 1.25 V to 5.5 V , RLOAD = 2 kΩ to AGND, CLOAD = 200 pF to AGND, and digital inputs at VDD or AGND
(unless otherwise noted)
PARAMETER
STATIC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC80502
DAC70502
DAC60502
16
14
Resolution
Bits
12
INL
Integral nonlinearity(1)
Differential nonlinearity(1)
Total unadjusted error(1)
Zero code error(1)
–1
1
1
LSB
LSB
DNL
TUE
–1
–0.1
–1.5
0.04
0.5
0.1 %FSR
DAC loaded with zero scale code
1.5
mV
µV/°C
mV
Zero code error temperature
coefficient(1)
Offset error(1)
±2
0.5
±2
–1.5
–0.1
–0.1
1.5
Offset error temperature
µV/°C
(1)
coefficient
Gain error(1)
0.04
±1
0.1 %FSR
Gain error temperature
coefficient(1)
Full-scale error(1)
ppm
FSR/°C
0.04
±2
0.1 %FSR
Full-scale error temperature
coefficient(1)
ppm
FSR/°C
(1) End point fit between code 256 to code 64,511 for 16-bit, code 64 to code 16,127 for 14-bit, code 16 to code 4031 for 12-bit, DAC
output unloaded, performance under resistive and capacitive load conditions are specified by design and characterization, DAC output
range ≥ 2.5 V.
Copyright © 2019–2020, Texas Instruments Incorporated
5
DAC80502, DAC70502, DAC60502
ZHCSKJ2A –NOVEMBER 2019–REVISED APRIL 2020
www.ti.com.cn
Electrical Characteristics (continued)
all minimum and maximum values at TA = –40°C to +125°C and all typcal values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, external
or internal VREFIO = 1.25 V to 5.5 V , RLOAD = 2 kΩ to AGND, CLOAD = 200 pF to AGND, and digital inputs at VDD or AGND
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT CHARACTERISTICS
2 ×
VREFIO
BUFF-GAIN bit set to 1, REF-DIV bit set to 0
BUFF-GAIN bit set to 1, REF-DIV bit set to 1
BUFF-GAIN bit set to 0, REF-DIV bit set to 1
0
0
0
VO
Output voltage
VREFIO
V
0.5 ×
VREFIO
VDD = 2.7 V
0.25
0.5
RLOAD
Resistive load(2)
kΩ
VDD = 5.5 V
RLOAD = infinite
2
CLOAD
Capacitive load(2)
Load regulation
nF
RLOAD = 2 kΩ
10
DAC at midscale, –10 mA ≤ IOUT ≤ 10 mA
80
30
µV/mA
Full scale output shorted to AGND (per
channel)
Short circuit current
mA
Zero output shorted to VDD (per channel)
30
to VDD, DAC at full code, IOUT = 10 mA
(sourcing)
Output voltage headroom
Output voltage footroom
0.3
0.3
0.1
V
V
to AGND, DAC at zero code, IOUT = 10 mA
(sinking)
DAC at midscale
0.1
10
ZO
DC small signal output impedance DAC at code 256
DAC at code 65279
Ω
10
Power supply rejection ratio (DC) DAC at midscale; VDD = 5 V ± 10%
0.15
mV/V
ppm of
FSR
Output voltage drift vs time
TA = 35°C, VOUT = midscale, 1900 hr
20
VOLTAGE REFERENCE INPUT
Reference input impedance
(VREFIO)
ZVREFIO
100
5
kΩ
Reference input capacitance
(VREFIO)
CVREFIO
pF
VOLTAGE REFERENCE OUTPUT
Output (initial accuracy)
TA = 25°C
2.4975
2.5025
V
DAC80502
5
Output drift
ppm/℃
DAC70502, DAC60502
10
Output impedance
Output noise
0.1
14
Ω
µVPP
nV/√Hz
mA
0.1 Hz to 10 Hz
Output noise density
Load current
Measured at 10 kHz, reference load = 10 nF
140
±5
Load regulation
Sourcing and sinking
90
µV/mA
µV/V
µV
Line regulation
20
Output voltage drift vs time
TA = 35°C, 1900 hr
1st cycle
20
480
25
ppm
Thermal hysteresis
Additional cycle
ppm
(2) Not production tested.
6
Copyright © 2019–2020, Texas Instruments Incorporated
DAC80502, DAC70502, DAC60502
www.ti.com.cn
ZHCSKJ2A –NOVEMBER 2019–REVISED APRIL 2020
Electrical Characteristics (continued)
all minimum and maximum values at TA = –40°C to +125°C and all typcal values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, external
or internal VREFIO = 1.25 V to 5.5 V , RLOAD = 2 kΩ to AGND, CLOAD = 200 pF to AGND, and digital inputs at VDD or AGND
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
¼ to ¾ scale and ¾ to ¼ scale settling to ±2
LSB, VDD = 5.5 V, VREFIO = 2.5 V
5
3
ts
Output voltage settling time(3)
µs
10-mV settling to ±2 LSB, VDD = 5.5 V,
VREFIO = 2.5 V
Slew rate(3)
VDD = 5.5 V, VREFIO = 2.5 V
CLOAD = 50 pF
2
V/µs
mV
Power on glitch magnitude
200
0.1 Hz to 10 Hz, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V
14
23
µVPP
Vn
Output noise(3)
100-kHz Bandwidth, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V
µVrms
Measured at 1 kHz, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V,
gain = 2X (BUFF-GAIN bit = 1)
78
74
55
Measured at 10 kHz, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V,
gain = 2X (BUFF-GAIN bit = 1)
Vn
Output noise density
nV/√Hz
Measured at 1 kHz, DAC at full scale,
VDD = 2.7 V, external VREFIO = 2.5 V,
gain = 1X (BUFF-GAIN bit = 0)
Measured at 10 kHz, DAC at full scale,
VDD = 2.7 V, external VREFIO = 2.5 V,
gain = 1X (BUFF-GAIN bit = 0)
50
70
70
1-kHz sinusiod at DAC output, DAC updated
at 500 kHz, include up to 7th harmonics, no
filter on DAC output
SFDR
THD
Spurious free dynamic range
Total harmonic distortion
dB
dB
1-kHz sinusiod at DAC output, DAC updated
at 500 kHz, include up to 7th harmonics, no
filter on DAC output
200-mV, 50-Hz to 60-Hz sine wave on VDD,
DAC at midscale.
Power supply rejection ratio (ac)
Code change glitch impulse
Code change glitch magnitude
85
4
dB
nV-s
mV
Midcode ±1 LSB (including feedthrough)
Midcode ±1 LSB (including feedthrough)
gain = 1X (BUFF-GAIN bit = 0)
7.5
Full scale swing on adjacent channel,
measured channel at midscale
Channel to channel ac crosstalk
4
nV-s
Full scale swing on adjacent channel,
measured channel at midscale
Channel to channel dc crosstalk
Digital feedthrough
1
4
LSB
nV-s
At SCLK = 1 MHz, DAC output at midscale
DIGITAL INPUTS
Hysteresis voltage
0.4
10
V
Input current
–5
5
µA
pF
Pin capacitance
Per pin
(3) Output buffer in gain = 2X setting (BUFF-GAIN bit = 1).
Copyright © 2019–2020, Texas Instruments Incorporated
7
DAC80502, DAC70502, DAC60502
ZHCSKJ2A –NOVEMBER 2019–REVISED APRIL 2020
www.ti.com.cn
Electrical Characteristics (continued)
all minimum and maximum values at TA = –40°C to +125°C and all typcal values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, external
or internal VREFIO = 1.25 V to 5.5 V , RLOAD = 2 kΩ to AGND, CLOAD = 200 pF to AGND, and digital inputs at VDD or AGND
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER
IVDD
Normal mode, internal reference enabled, all
DACs at full scale, SPI static
1.9
1.5
2.6
1.9
mA
Current flowing into VDD
Normal mode, external reference = 2.5 V, all
DACs at full scale, SPI static
All DACs and Internal reference power-down
0-V to 5-V range, midscale code
15
25
µA
µA
IVREFIO
Current flowing into VREFIO
8
Copyright © 2019–2020, Texas Instruments Incorporated
DAC80502, DAC70502, DAC60502
www.ti.com.cn
ZHCSKJ2A –NOVEMBER 2019–REVISED APRIL 2020
7.6 Timing Requirements : SPI Mode
all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V,
VIH = 1.62 V, VIL = 0.15 V, VREFIO = 1.25 V to 5.5 V, and TA = –40°C to +125°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
MHz
ns
fSCLK
SCLK frequency
50
tSCLKHIGH
tSCLKLOW
tSDIS
SCLK high time
9
9
SCLK low time
ns
SDIN setup
5
ns
tSDIH
SDIN hold
10
13
10
160
15
1
ns
tSYNCS
SYNC falling edge to SCLK falling edge setup
SCLK falling edge to SYNC rising edge
SYNC high time
ns
tSYNCH
ns
tSYNCHIGH
tSYNCIGNORE
tDACWAIT
ns
SCLK falling edge to SYNC ignore
Sequential DAC update wait time
ns
µs
7.7 Timing Requirements : I2C Standard Mode
all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V,
VIH = 1.62 V, VIL = 0.45 V, VREFIO = 1.25 V to 5.5 V, and TA = – 40°C to +125°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
MHz
µs
fSCLK
tBUF
SCL frequency
0.1
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
4.7
4
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
µs
4.7
4
µs
µs
0
ns
Data setup time
250
4700
4000
ns
SCL clock low period
ns
tHIGH
tR
SCL clock high period
ns
Clock and data fall time
Clock and data rise time
Sequential DAC update wait time
300
ns
tF
1000
ns
tUPDATE
1
µs
7.8 Timing Requirements : I2C Fast Mode
all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V,
VIH = 1.62 V, VIL = 0.45 V, VREFIO = 1.25 V to 5.5 V, and TA = – 40°C to +125°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
MHz
µs
fSCLK
tBUF
SCL frequency
0.4
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
1.3
0.6
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
µs
0.6
µs
0.6
µs
0
ns
Data setup time
100
1300
600
ns
SCL clock low period
ns
tHIGH
tR
SCL clock high period
ns
Clock and data fall time
Clock and data rise time
Sequential DAC update wait time
300
300
ns
tF
ns
tUPDATE
1
µs
Copyright © 2019–2020, Texas Instruments Incorporated
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DAC80502, DAC70502, DAC60502
ZHCSKJ2A –NOVEMBER 2019–REVISED APRIL 2020
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7.9 Timing Requirements : I2C Fast-Mode Plus
all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V,
VIH = 1.62 V, VIL = 0.45 V, VREFIO = 1.25 V to 5.5 V, and TA = – 40°C to +125°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
MHz
µs
fSCLK
tBUF
SCL frequency
1
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
0.5
0.26
0.26
0.26
0
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
µs
µs
µs
ns
Data setup time
50
ns
SCL clock low period
500
260
ns
tHIGH
tR
SCL clock high period
ns
Clock and data fall time
Clock and data rise time
Sequential DAC update wait time
120
120
ns
tF
ns
tUPDATE
1
µs
tSYNCHIGH
tSYNCH
tSYNCS
SYNC
tSYNCIGNORE
tSCLKLOW
SCLK
tSCLKHIGH
SDIN
Bit 23
Bit 1
Bit 0
tSDIS
tSDIH
图 1. SPI Mode Timing
Low byte ACK cycle
tR
tLOW
tF
SCL
tSUSTA
tHDSTA
tHIGH
tSUSTO
tHDDAT
tSUDAT
tHDSTA
SDA
tBUF
S
P
S
P
图 2. I2C Mode Timing
10
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DAC80502, DAC70502, DAC60502
www.ti.com.cn
ZHCSKJ2A –NOVEMBER 2019–REVISED APRIL 2020
7.10 Typical Characteristics
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, channel A shown, and DAC outputs
unloaded (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
DACA Unloaded
DACA 5 kW || 200 pF
DACB Unloaded
DACA Unloaded
DACA 5 kW || 200 pF
DACB Unloaded
DACB 5 kW || 200 pF
DACB 5 kW || 200 pF
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
D001
D002
图 3. Integral Linearity Error vs Digital Input Code
图 4. Differential Linearity Error vs Digital Input Code
0.08
0.06
0.04
0.02
0
1
DACA Unloaded
DACA 5 kW || 200 pF
DACB Unloaded
INL Max, Unloaded
INL Min, Unloaded
INL Max, 5 kW || 200 pF
INL Min, 5 kW || 200 pF
0.75
DACB 5 kW || 200 pF
0.5
0.25
0
-0.25
-0.5
-0.75
-1
-0.02
-0.04
-0.06
-0.08
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
D004
D003
图 6. Integral Linearity Error vs Temperature
图 5. Total Unadjusted Error vs Digital Input Code
0.08
0.06
0.04
0.02
0
1
Unloaded
5 kW || 200 pF
DNL Max, Unloaded
DNL Min, Unloaded
DNL Max, 5 kW || 200 pF
DNL Min, 5 kW || 200 pF
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
-0.02
-0.04
-0.06
-0.08
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D005
D006
图 7. Differential Linearity Error vs Temperature
图 8. Total Unadjusted Error vs Temperature
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Typical Characteristics (接下页)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, channel A shown, and DAC outputs
unloaded (unless otherwise noted)
1.5
1.5
1.25
1
Unloaded
5 kW || 200 pF
1
0.5
0
0.75
0.5
0.25
0
-0.5
-1
-1.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D007
D008
图 9. Zero-Code Error vs Temperature
图 10. Offset Error vs Temperature
0.08
0.06
0.04
0.02
0
0.08
0.06
0.04
0.02
0
Unloaded
5 kW || 200 pF
Unloaded
5 kW || 200 pF
-0.02
-0.04
-0.06
-0.08
-0.02
-0.04
-0.06
-0.08
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
DD0a0t9a
D010
图 11. Full-Scale Error vs Temperature
图 12. Gain Error vs Temperature
1
1
0.75
0.5
Max DNL
Min DNL
Max INL
Min INL
0.75
0.5
0.25
0
0.25
0
-0.25
-0.5
-0.75
-1
-0.25
-0.5
-0.75
-1
2.7
3.1
3.5
3.9
Supply Voltage, VDD (V)
4.3
4.7
5.1
5.5
2.7
3.1
3.5
3.9
Supply Voltage, VDD (V)
4.3
4.7
5.1
5.5
D011
D012
REF-DIV = 0 and BUFF-GAIN = 0
图 13. Integral Linearity Error vs Supply Voltage
REF-DIV = 0 and BUFF-GAIN = 0
图 14. Differential Linearity Error vs Supply Voltage
12
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ZHCSKJ2A –NOVEMBER 2019–REVISED APRIL 2020
Typical Characteristics (接下页)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, channel A shown, and DAC outputs
unloaded (unless otherwise noted)
0.08
0.06
0.04
0.02
0
1.5
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
1
0.5
0
-0.02
-0.04
-0.06
-0.08
-0.5
-1
-1.5
2.7
3.1
3.5
3.9
4.3
Supply Voltage, VDD (V)
4.7
5.1
5.5
2.7
3.1
3.5
3.9
4.3
Supply Voltage, VDD (V)
4.7
5.1
5.5
D013
D014
图 15. Total Unadjusted Error vs Supply Voltage
图 16. Zero-Code Error vs Supply Voltage
0.08
0.06
0.04
0.02
0
1.5
1
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
0.5
0
-0.02
-0.04
-0.06
-0.08
-0.5
-1
-1.5
2.7
3.1
3.5
3.9
Supply Voltage, VDD (V)
4.3
4.7
5.1
5.5
2.7
3.1
3.5
3.9
Supply Voltage, VDD (V)
4.3
4.7
5.1
5.5
D015
D016
图 17. Offset Error vs Supply Voltage
图 18. Gain Error vs Supply Voltage
0.08
0.06
0.04
0.02
0
1
0.75
0.5
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
Max, REFDIV = 0
Max, REFDIV = 1
Min, REFDIV = 0
Min, REFDIV = 1
0.25
0
-0.02
-0.04
-0.06
-0.08
-0.25
-0.5
-0.75
-1
2.7
3.1
3.5
3.9
Supply Voltage, VDD (V)
4.3
4.7
5.1
5.5
1.25
2
2.75
Supply Volltage, VREFIN (V)
3.5
4.25
5
5.5
D017
D018
图 19. Full-Scale Error vs Supply Voltage
图 20. Integral Linearity Error vs Reference Voltage
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Typical Characteristics (接下页)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, channel A shown, and DAC outputs
unloaded (unless otherwise noted)
1
0.75
0.5
0.08
0.06
0.04
0.02
0
Max, REFDIV = 0
Max, REFDIV = 1
Min, REFDIV = 0
Min, REFDIV = 1
REFDIV = 0
REFDIV = 1
0.25
0
-0.25
-0.5
-0.75
-1
-0.02
-0.04
-0.06
-0.08
1.25
2
2.75
Supply Volltage, VREFIN (V)
3.5
4.25
5
5.5
1.25
2
2.75
Supply Volltage, VREFIN (V)
3.5
4.25
5
5.5
D019
D020
图 21. Differential Linearity Error vs Reference Voltage
图 22. Total Unadjusted Error vs Reference Voltage
1.5
1.5
1
REF-DIV = 0, BUFF-GAIN = 0
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
REF-DIV = 1, BUFF-GAIN = 1
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-1.5
1.25
2
2.75
3.5
Supply Volltage, VREFIN (V)
4.25
5
5.5
1.25
2
2.75
3.5
Supply Volltage, VREFIN (V)
4.25
5
5.5
D021
D022
图 23. Zero-Code Error vs Reference Voltage
图 24. Offset Error vs Reference Voltage
0.08
0.06
0.04
0.02
0
0.08
0.06
0.04
0.02
0
REF-DIV = 0, BUFF-GAIN = 0
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
REF-DIV = 1, BUFF-GAIN = 1
-0.02
-0.04
-0.06
-0.08
-0.02
-0.04
-0.06
-0.08
1.25
2
2.75
Supply Volltage, VREFIN (V)
3.5
4.25
5
5.5
1.25
2
2.75
Supply Volltage, VREFIN (V)
3.5
4.25
5
5.5
D023
D024
图 25. Gain Error vs Reference Voltage
图 26. Full-Scale Error vs Reference Voltage
14
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ZHCSKJ2A –NOVEMBER 2019–REVISED APRIL 2020
Typical Characteristics (接下页)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, channel A shown, and DAC outputs
unloaded (unless otherwise noted)
2
1.75
1.5
1.25
1
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0.75
0.5
0.25
0
Internal Reference, BUFF-GAIN = 0
Internal Reference, BUFF-GAIN = 1
External Reference, BUFF-GAIN = 0
External Reference, BUFF-GAIN = 1
Internal Reference, BUFF-GAIN = 0
Internal Reference, BUFF-GAIN = 1
External Reference, BUFF-GAIN = 0
External Reference, BUFF-GAIN = 1
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D025
D026
DAC code at midscale
图 27. Supply Current vs Digital Input Code
图 28. Supply Current vs Temperature
3
2.5
2
12
10
8
Internal Reference, BUFF-GAIN = 0
Internal Reference, BUFF-GAIN = 1
External Reference, BUFF-GAIN = 0
External Reference, BUFF-GAIN = 1
1.5
1
6
4
0.5
2
0
0
2.7
3.1
3.5
3.9
4.3
Supply Voltage, VDD (V)
4.7
5.1
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D027
D028
DAC code at midscale
REF-DIV = 0 and BUFF-GAIN = 0
图 29. Supply Current vs Supply Voltage
图 30. Power-Down Current vs Temperature
15
2.5
2
Sourcing, VDD = 2.7, REF-DIV = 1, BUFF-GAIN = 1
Sourcing, VDD = 5.5, REF-DIV = 0, BUFF-GAIN = 0
Sinking VDD = 2.7,REF-DIV = 1, BUFF-GAIN = 1
Sinking VDD = 5.5, REF-DIV = 0, BUFF-GAIN = 0
12
9
1.5
1
6
3
0.5
0
0
2.7
3.1
3.5
3.9
Supply Voltage, VDD (V)
4.3
4.7
5.1
5.5
0
5
10 15
Load Current (mA)
20
25
D029
D030
External reference = 2.5 V, REF-DIV = 1 and BUFF-GAIN = 0
External reference = 2.5 V
图 31. Power Down Current vs Supply Voltage
图 32. Headroom and Footroom vs Load Current
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DAC80502, DAC70502, DAC60502
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Typical Characteristics (接下页)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, channel A shown, and DAC outputs
unloaded (unless otherwise noted)
7
8
0xFFFF
0xC000
0x8000
0x4000
0x0
0xFFFF
0xC000
0x8000
0x4000
0x0
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
-1
-1
-50 -40 -30 -20 -10
0
10
Load Current (mA)
20
30
40
50
-50 -40 -30 -20 -10
0
10
Load Current (mA)
20
30
40
50
D031
D032
REF-DIV = 0 and BUFF-GAIN = 0
REF-DIV = 0 and BUFF-GAIN = 1
图 33. Source and Sink Capability
图 34. Source and Sink Capability
7
6
0xFFFF
0xC000
0x8000
0x4000
0x0
5
4
3
3 nV-s
2
1
VOUT (2.5 mV/div)
CS (5 V/div)
0
-1
Time (0.5 ms/div)
-50 -40 -30 -20 -10
0
Load Current (mA)
10
20
30
40
50
D034
D033
DAC code transition from midscale – 1 to midscale LSB,
REF-DIV = 0 and BUFF-GAIN = 0
REF-DIV = 1 and BUFF-GAIN = 0
图 36. Glitch Impulse, Rising Edge, 1-LSB Step
图 35. Source and Sink Capability
Small Singal VOUT (3 LSB/div)
Large Singal VOUT (2 V/div)
CS (5 V/div)
2 nV-s
VOUT (2.5mV/div)
CS (5 V/div)
Time (0.5 ms/div)
Time (2 ms/div)
D035
D036
DAC code transition from midscale to midscale – 1 LSB,
REF-DIV = 0 and BUFF-GAIN = 0
REF-DIV = 0 and BUFF-GAIN = 0
图 37. Glitch Impulse, Falling Edge, 1-LSB Step
图 38. Full-Scale Settling Time, Rising Edge
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ZHCSKJ2A –NOVEMBER 2019–REVISED APRIL 2020
Typical Characteristics (接下页)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, channel A shown, and DAC outputs
unloaded (unless otherwise noted)
Small Singal VOUT (3 LSB/div)
Large Singal VOUT (2 V/div)
CS (5 V/div)
VDD (2 V/div)
DAC Output (40 mV/div)
Time (2 ms/div)
Time (1 ms/div)
D037
D038
REF-DIV = 0 and BUFF-GAIN = 0
REF-DIV = 0 and BUFF-GAIN = 0
图 39. Full-Scale Settling Time, Falling Edge
图 40. Power-On Glitch
0
-10
VDD (2 V/div)
DAC Output (40 mV/div)
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
1
10
100 1000
Frequency (Hz)
10000
100000
Time (1 ms/div)
D040
D039
DAC code at midscale, VDD = 5.0 V + 0.2 VPP
,
REF-DIV = 0 and BUFF-GAIN = 0
REF-DIV = 0 and BUFF-GAIN = 0
图 42. DAC Output AC PSRR vs Frequency
图 41. Power-Off Glitch
20
0
300
250
200
150
100
50
DAC Code = 0x0
DAC Code = 0x8000
DAC Code = 0xFFFF
-20
-40
-60
-80
-100
-120
-140
0
0
4000
8000 12000
Frequency (Hz)
16000
20000
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
D041
D042
fo = 1 kHz, fs = 400 kHz, includes 7 harmonics,
Gain = 1X (REF-DIV = 1 and BUFF-GAIN = 1),
external reference = 2.5 V,
measurement bandwidth = 20 kHz, external reference = 2.5 V,
REF-DIV = 0 and BUFF-GAIN = 0
REF-DIV = 0 and BUFF-GAIN = 0
图 43. DAC Output THD+N vs Frequency
图 44. DAC Output Noise Spectral Density
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DAC80502, DAC70502, DAC60502
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Typical Characteristics (接下页)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, channel A shown, and DAC outputs
unloaded (unless otherwise noted)
D043
D044
DAC code at midscale, external reference = 2.5 V,
REF-DIV = 0 and BUFF-GAIN = 0
DAC code at midscale, internal reference = 2.5 V,
REF-DIV = 0 and BUFF-GAIN = 0
图 45. DAC Output Noise: 0.1 Hz to 10 Hz
图 46. DAC Output Noise: 0.1 Hz to 10 Hz
2.505
SCLK (5 V/div)
2.5025
2.5
VOUT (1 mV/div)
2.4975
2.495
Time (5 ms/div)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D045
D046
SCLK = 1 MHz, DAC code at midscale, external reference = 2.5 V,
REF-DIV = 0 and BUFF-GAIN = 0
30 units
图 47. Clock Feedthrough
图 48. Internal Reference Voltage vs Temperature
100
75
2.505
2.5025
2.5
50
25
0
-25
-50
-75
-100
2.4975
2.495
2.7
3.1
3.5
3.9
4.3
Supply Voltage, VDD (V)
4.7
5.1
5.5
0
200
400
600
Time (Hours)
800
1000
1200
D047
D048
图 49. Internal Reference Voltage vs Supply Voltage
图 50. Internal Reference Voltage vs Time
18
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DAC80502, DAC70502, DAC60502
www.ti.com.cn
ZHCSKJ2A –NOVEMBER 2019–REVISED APRIL 2020
Typical Characteristics (接下页)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, channel A shown, and DAC outputs
unloaded (unless otherwise noted)
800
700
600
500
400
300
200
100
0
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
D050
D049
图 52. Internal Reference Noise: 0.1 Hz to 10 Hz
图 51. Internal Reference Noise Density vs Frequency
55
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
Presolder Heat Reflow
Postsolder Heat Reflow
50
45
40
35
30
25
20
15
10
5
0
0
1
2
3
4
5
2.4975 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010
VREFOUT (V)
D051
D053
Temperature Drift (ppm/èC)
图 53. Internal Reference Temperature Drift Histogram
图 54. Internal Reference Initial Accuracy
(Pre- and Post-Solder) Histogram
28%
26%
24%
22%
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0
-3 -2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
3
D054
VREFOUT Drift Delta (ppm/èC)
图 55. Internal Reference Temperature Drift (Pre-Solder and Post-Solder) Histogram
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8 Detailed Description
8.1 Overview
The DAC80502, DAC70502, DAC60502 (DACx0502) family of devices are dual-channel, buffered voltage output,
16-bit, 14-bit, or 12-bit digital-to-analog converters (DACs), respectively. These devices include a 2.5-V, 5-
ppm/˚C internal reference, giving full-scale output voltage ranges of 1.25 V, 2.5 V, or 5 V. The DACx0502
devices incorporate a power-on-reset circuit that makes sure that the DAC output powers up at zero scale or
midscale, depending on status of the RSTSEL pin, and remains at that scale until a valid code is written to the
device.
The digital interface of the DACx0502 can be configured to SPI or I2C mode using the SPI2C pin. In SPI mode,
the DACx0502 family uses a 3-wire serial interface that operates at clock rates up to 50 MHz. In I2C mode, the
DACx0502 devices operate in standard (100 kbps), fast (400 kbps), and fast+ (1.0 Mbps) modes.
8.2 Functional Block Diagram
VREFIO
VDD
Internal
Reference
SPI2C
SCLK or SCL
DAC
Buffer
DAC
Register
BUF
VOUTA
VOUTB
DAC
SDIN or SDA
Channel A
Channel B
or A0
SYNC
RSTSEL
Power Down Logic
Resistive Network
Power On Reset
AGND
8.3 Feature Description
8.3.1 Digital-to-Analog Converter (DAC) Architecture
Each output channel in the DACx0502 family of devices consists of a rail-to-rail ladder architecture with an output
buffer amplifier. The devices include an internal 2.5-V reference. 图 56 shows a block diagram of the DAC
architecture.
VREFIO
2.5 V
Reference
REF divider
(x1 or x0.5)
REF-DIV
bit
Serial interface
DAC data register
BUFF-GAIN
bit
Gain
(x1 or x2)
DAC
buffer register
DAC
active register
R-2R
VOUT
DAC
output
AGND
图 56. DACx0502 DAC Block Diagram
20
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Feature Description (接下页)
8.3.1.1 DAC Transfer Function
The input data writes to the individual DAC data registers in straight binary format. After a power-on or a reset
event, all DAC registers are set to zero code (RSTSEL = 0) or midscale code (RSTSEL = 1). The DAC transfer
function is shown by 公式 1.
DAC_DATA VREFIO
ì
VOUT
=
ì GAIN
2N
DIV
where:
•
•
N = resolution in bits = either 12 (DAC60502), 14 (DAC70502) or 16 (DAC80502).
DAC_DATA = decimal equivalent of the binary code that is loaded to the DAC register (address 8h), DAC_DATA
ranges from 0 to 2N – 1.
•
VREFIO = DAC reference voltage. Either VREFIO from the internal 2.5-V reference or VREFIO from an external
reference.
•
•
DIV = 1 (default) or 2 as set by the REF-DIV bit in the GAIN register (address 4h).
GAIN = 1 or 2 (default) as set by the BUFF-GAIN bit for that DAC channel in the GAIN register (address 4h).
(1)
8.3.1.2 DAC Register Structure
Data written to the DAC data registers are initially stored in the DAC buffer registers. The update mode of the
DAC output is determined by the status of the DAC_SYNC_EN bit (address 2h).
In asynchronous mode (default, DAC_SYNC_EN = 0), a write to the DAC buffer register results in an immediate
update of the DAC active register. In SPI mode, the DAC output (VOUTx pin) updates on the rising edge of
SYNC. In I2C mode, the DAC output (VOUT pin) updates on the falling edge of SCL on the last acknowledge bit.
In synchronous mode (DAC_SYNC_EN = 1), writing to the DAC buffer register does not automatically update the
DAC active register. Instead, the update occurs only after a software LDAC trigger event. A software LDAC
trigger generates through the LDAC bit in the TRIGGER register (address 5h). When the host reads from a DAC
buffer register, the value held in the DAC buffer register is returned (not the value held in the DAC active
register).
8.3.1.3 Output Amplifier
The output buffer amplifier generates rail-to-rail voltages on the output, giving a maximum output range of 0 V to
VDD. 公式 1 shows that the full-scale output range of the DAC output is determined by the voltage on the
VREFIO pin, the reference divider setting (DIV) as set by the REF-DIV bit (address 4h), and the gain
configuration for that channel set by the corresponding BUFF-GAIN bit (address 4h).
8.3.2 Internal Reference
The DAx0502 family of devices includes a 2.5-V precision band-gap reference enabled by default. Operation
from an external reference is supported by disabling the internal reference in the REF_PWDWN bit (address 3h).
The internal reference is externally available at the VREFIO pin and sources up to 5 mA. For noise filtering, use
a minimum 150-nF capacitor between the reference output and AGND.
The reference voltage to the device, either from the internal reference or an external one, can be divided by a
factor of two by setting the REF-DIV bit (address 4h) to 1. The REF-DIV bit provides additional flexibility in setting
the full-scale output range of the DAC output. Make sure to configure REF-DIV so that there is sufficient
headroom from VDD to the DAC operating reference voltage, VREFIO (see 公式 1). See the Recommended
Operating Conditions for more information.
Improper configuration of the reference divider triggers a reference alarm condition. In this case, the reference
buffer is shut down, and all the DAC outputs go to 0 V. The DAC data registers are unaffected by the alarm
condition, and thus enable the DAC output to return to normal operation after the reference divider is configured
correctly.
8.3.2.1 Solder Heat Reflow
A known behavior of IC reference voltage circuits is the shift induced by the soldering process. 图 54 and 图 55
show the effect of solder heat reflow for the DACx0502 internal reference.
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Feature Description (接下页)
8.3.3 Power-On Reset (POR)
The DACx0502 family of devices includes a power-on reset function that controls the output voltage at power up.
After the VDD supply has been established, a POR event is issued. The POR causes all registers to initialize to
default values, and communication with the device is valid only after a 250-µs, power-on-reset delay. The default
value for all DACs is zero code if RSTSEL = 0, and midscale code if RSTSEL = 1. Each DAC channel remains at
the power-up voltage until a valid command is written to a channel.
When the device powers up, a POR circuit sets the device to the default mode. The POR circuit requires specific
VDD levels, as indicated in 图 57, in order to make sure that the internal capacitors discharge and reset the
device on power up. In order to make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms.
When VDD drops to less than 2.2 V but remains greater than 0.7 V (shown as the undefined region), the device
may or may not reset under all specified temperature and power-supply conditions. In this case, initiate a POR.
When VDD remains greater than 2.2 V, a POR does not occur.
VDD (V)
5.50
Specified supply
voltage range
No power-on reset
2.70
2.20
Undefined
0.70
Power-on reset
0.00
图 57. Threshold Levels for the VDD POR Circuit
8.3.4 Software Reset
A device software reset event is initiated by writing the reserved code 0x1010 to the SOFT-RESET bit in the
TRIGGER register (address 5h). A software reset initiates a POR event.
8.4 Device Functional Modes
The DACx0502 have two modes of operation: normal and power-down.
8.4.1 Power-Down Mode
The DACx0502 output amplifiers and internal reference can be independently powered down through the
CONFIG register (3h). At power up, the DAC output and the internal reference are active by default. In power-
down mode, the DACs output (VOUTx pin) is internally connected to AGND through a 1-kΩ resistor.
22
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8.5 Programming
8.5.1 Serial Interface
The DACx0502 family of devices is controlled through either a 3-wire SPI or a 2-wire I2C interface.
The type of interface is determined at device power up based on the logic level of the SPI2C pin. A logic 0 on the
SPI2C pin puts the DACx0502 in SPI mode; whereas, logic 1 on SPI2C puts the DACx0502 in I2C mode. The
SPI2C pin must be kept static after the device powers up.
8.5.1.1 SPI Mode
The DACx0502 digital interface is programmed to work in SPI mode when the logic level of the SPI2C pin is 0 at
power up. 表 1 shows the frame format for SPI mode. In SPI mode, the DACx0502 have a 3-wire serial interface:
SYNC, SCLK, and SDIN. The serial interface is compatible with SPI, QSPI, and Microwire interface standards,
and most digital signal processors (DSPs). The serial interface operates at up to 50 MHz. The input shift register
is 24-bits wide.
表 1. SPI Mode Frame Format
BIT
23
22 21 20 19 18 17 16 15 14 13 12 11 10
16-Bit MSB-Aligned DAC Data:
DAC80502 {15:0}, DAC70502 {13:0, x, x}, DAC60502 {11:0, x, x, x, x}
9
8
7
6
5
4
3
2
1
0
DESC R/W Register Address - Command Byte
Serial clock SCLK is a continuous or a gated clock. The first falling edge of SYNC starts the operation cycle.
When SYNC is high, the SCLK and SDIN signals are blocked. The device internal registers are updated from the
shift register on the rising edge of SYNC.
8.5.1.1.1 SYNC Interrupt
For SPI-mode operation, the SYNC line stays low for at least 24 falling edges of SCLK, and the addressed DAC
register updates on the SYNC rising edge. However, if the SYNC line is brought high before the 24th SCLK
falling edge, this event acts as an interrupt to the write sequence. The shift register resets and the write
sequence is discarded. The data buffer contents and the DAC register contents do not update, and the the
operating mode does not change, as shown in 图 58.
SCLK
1
2
24
SYNC
SDIN
DB23
DB0
Invalid/Interrupted write sequence
SCLK
1
2
24
SYNC
SDIN
DB23
DB0
Valid write sequence
图 58. SYNC Interrupt
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8.5.1.2 I2C Mode
The DACx0502 digital interface is programmed to work in I2C mode when the logic level of the SPI2C pin is 1 at
power up. In I2C mode, the DACx0502 have a 2-wire serial interface: SCL, SDA, and one address pin, A0. The
I2C bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both
the SDA and SCL lines are pulled high. All the I2C-compatible devices connect to the I2C bus through open-drain
I/O pins SDA and SCL.
The I2C specification states that the device that controls communication is called a master, and the devices that
are controlled by the master are called slaves. The master device generates the SCL signal. The master device
also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus
to indicate the start or stop of a data transfer. Device addressing is completed by the master. The master device
on an I2C bus is typically a microcontroller or DSP. The DACx0502 operate as a slave device on the I2C bus. A
slave device acknowledges master commands, and upon master control, receives or transmits data.
Typically, the DACx0502 operate as a slave receiver. A master device writes to the DACx0502, a slave receiver.
However, if a master device requires the DACx0502 internal register data, the DACx0502 operate as a slave
transmitter. In this case, the master device reads from the DACx0502 According to I2C terminology, read and
write refer to the master device.
The DACx0502 are slave devices that support the following data transfer modes:
1. Standard mode (100 kbps)
2. Fast mode (400 kbps)
3. Fast-mode plus (1.0 Mbps)
The data transfer protocol for standard and fast modes is exactly the same; therefore, these modes are referred
to as F/S-mode in this document. The fast-mode plus protocol is supported in terms of data transfer speed, but
not output current. The low-level output current would be 3 mA, similar to the case of standard and fast modes.
The DACx0502 support 7-bit addressing. The 10-bit addressing mode is not supported. These devices support
the general call reset function. Sending the following sequence initiates a software reset within the device:
start/repeated start, 0x00, 0x06, stop. The reset is asserted within the device on the falling edge of the ACK bit,
following the second byte.
Other than specific timing signals, the I2C interface works with serial bytes. At the end of each byte, a ninth clock
cycle generates and detects an acknowledge signal. Acknowledge is when the SDA line is pulled low during the
high period of the ninth clock cycle. A not-acknowledge is when the SDA line is left high during the high period of
the ninth clock cycle as shown in 图 59.
Data output
by Transmitter
Not acknowledge
Data output
by Receiver
Acknowledge
2
9
1
8
SCL from
Master
S
Clock pulse for
acknowledgement
Start
condition
图 59. Acknowledge and Not Acknowledge on the I2C Bus
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8.5.1.2.1 F/S Mode Protocol
1. The master initiates data transfer by generating a start condition. The start condition is when a high to-low
transition occurs on the SDA line while SCL is high, as shown in 图 60. All I2C-compatible devices recognize
a start condition.
SDA
SCL
S
P
Start
condition
Stop
condition
图 60. Start and Stop Conditions
SDA
SCL
Change of data
allowed
Data line stable
Data valid
图 61. Bit Transfer on the I2C Bus
2. The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
(R/W) on the SDA line. During all transmissions, the master makes sure that data are valid. A valid data
condition requires the SDA line to be stable during the entire high period of the clock pulse, as shown in 图
61. All devices recognize the address sent by the master and compare it to their internal fixed addresses.
Only the slave device with a matching address generates an acknowledge by pulling the SDA line low during
the entire high period of the 9th SCL cycle, as shown in 图 59. Upon detecting this acknowledge, the master
knows the communication link with a slave has been established.
3. The master generates further SCL cycles to transmit (R/W bit 0) or receive (R/W bit 1) data to the slave. In
either case, the receiver must acknowledge the data sent by the transmitter so that the acknowledge signal
can be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data
sequences consists of eight data bits and one acknowledge-bit, and can continue for as long as necessary.
4. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from
low-to-high while the SCL line is high (see 图 60). This action releases the bus and stops the communication
link with the addressed slave. All I2C-compatible devices recognize the stop condition. Upon receipt of a stop
condition, the bus is released, and all slave devices then wait for a start condition followed by a matching
address.
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8.5.1.2.2 DACx0502 I2C Update Sequence
For a single update, the DACx0502 requires a start condition, a valid I2C address byte, a command byte, and two
data bytes (the most significant data byte, MSDB, and least significant data byte, LSDB), as listed in 表 2.
表 2. Update Sequence
MSB
....
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
Address (A) byte
DB [31:24]
Command byte
DB [23:16]
MSDB
LSDB
DB [7:0]
DB [15:8]
After each byte is received, the DACx0502 acknowledges the byte by pulling the SDA line low during the high
period of a single clock pulse, as shown in 图 62. These four bytes and acknowledge cycles make up the 36
clock cycles required for a single update to occur. A valid I2C™ address byte selects the DACx0502 devices.
Recognize
START or
REPEATED
Recognize
STOP or
REPEATED
Generate ACKNOWLEDGE
START
START
signal
condition
condition
P
SDA
Sr
MSB
Acknowledgement
signal from Slave
Address
R/W
1
SCL
1
7
8
9
2 - 8
9
Sr
S
or
Sr
or
P
ACK
ACK
START or
REPEATED
START or
STOP
REPEATED
START
condition
Clock line held low while
interrupts are serviced
condition
图 62. I2C Bus Protocol
The command byte sets the operating mode of the selected DACx0502 device. When the operating mode is
selected by this byte, the DACx0502 series must receive two data bytes, the most significant data byte (MSDB)
and least significant data byte (LSDB), for a data update to occur. The DACx0502 devices perform an update on
the falling edge of the acknowledge signal that follows the LSDB.
When using fast mode (clock = 400 kHz), the maximum DAC update rate is limited to 22.22 kSPS. Using the
fast-mode plus (clock = 1 MHz), the maximum DAC update rate is limited to 55.55 kSPS. When a stop condition
is received, the DACx0502 family releases the I2C bus and awaits a new start condition.
26
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8.5.1.2.2.1 DACx0502 Address Byte
The address byte, as shown in 表 3, is the first byte received following the start condition from the master device.
The first four bits (MSBs) of the address are factory preset to 1001. The next three bits of the address are
controlled by the A0 pin. The A0 pin input can be connected to VDD, AGND, SCL, or SDA. The A0 pin is
sampled during the first byte of each data frame to determine the address. The device latches the value of the
address pin and consequently responds to that particular address according to 表 4.
表 3. DACx0502 Address Byte
B31
AD6
1
B30
AD5
0
B29
AD4
0
B28
AD3
1
B27
B26
B25
B24
R/W
COMMENT
AD2
AD1
AD0
See 表 4 (slave address column)
0 or 1
General address
表 4. Address Format
SLAVE ADDRESS
1001 000
A0 PIN
AGND
VDD
1001 001
1001 010
SDA
1001 011
SCL
8.5.1.2.2.2 DACx0502 Command Byte
The DACx0502 command byte (shown in 表 5) controls which command is executed and which register is being
accessed when writing to or reading from the DACx0502 series.
表 5. DACx0502 Command Byte
B23
0
B22
0
B21
0
B20
0
B19
0
B18
0
B17
0
B16
0
REGISTER
NOOP
0
0
0
0
0
0
0
1
DEVID
0
0
0
0
0
0
1
0
SYNC
0
0
0
0
0
0
1
1
CONFIG
GAIN
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
TRIGGER
BRDCAST
STATUS
DAC-A DATA
DAC-B DATA
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
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8.5.1.2.2.3 DACx0502 Data Byte (MSDB and LSDB)
The MSDB and LSDB contain the data that are passed to the register(s) specified by the command byte, as
shown in 表 6. The DACx0502 updates at the falling edge of the acknowledge signal that follows the LSDB[0] bit.
表 6. DACx0502 Data Byte
REGISTER
NAME
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MSDB
LSDB
NOOP
NOOP - No operation
DEVID
0
RESOLUTION
RESERVED
0
0
1
0
0
0
0
1
0
1
0
1
DAC-B-
BRDCST BRDCST
-EN
DAC-A-
DAC-B-
SYNC-
EN
DAC-A-
SYNC-
EN
SYNC
RESERVED
RESERVED
-EN
REF-
PWDWN
DAC-B-
PWDWN PWDWN
DAC-A-
CONFIG
GAIN
RESERVED
RESERVED
BUF-B-
GAIN
BUF-A-
GAIN
REF-DIV
RESERVED
LDAC
TRIGGER
BRDCAST
SOFT-RESET [3:0]
BROADCAST-DAC-DATA [15:0] / BROADCAST-DAC-DATA [13:0] / BROADCAST-DAC-DATA [11:0] -- left Aligned
RESERVED
REF-
ALARM
STATUS
DAC-A
DAC-B
DAC-A-DATA [15:0] for 16-bit / DAC-A-DATA [13:0] for 14-bit / DAC-A-DATA [11:0] for 12-bit -- left Aligned
DAC-B-DATA [15:0] for 16-bit / DAC-B-DATA [13:0] for 14-bit / DAC-B-DATA [11:0] for 12-bit -- left Aligned
8.5.1.2.3 DACx0502 I2C Read Sequence
To read any register the following command sequence must be used:
1. Send a start or repeated start command with a slave address and the R/W bit set to 0 for writing. The device
acknowledges this event.
2. Send a command byte for the register to be read. The device acknowledges this event again.
3. Send a repeated start with the slave address and the R/W bit set to 1 for reading. The device acknowledges
this event.
4. The device writes the MSDB byte of the addressed register. The master must acknowledge this byte.
5. Finally, the device writes out the LSDB of the register
An alternative reading method allows for reading back the value of the last register written. The sequence is a
start or repeated start with the slave address and the R/W bit set to 1, and the two bytes of the last register are
read out. All the registers in DACx0502 family can be read out with the exception of SOFT-RESET register. 表 6
shows the read command set.
表 7. Read Sequence
S
MSB
...
R/W(0) ACK
MSB
...
LSB
ACK
Sr
MSB
...
R/W(1) ACK
MSB
...
LSB
ACK
MSB
...
LSB
NACK
ADDRESS BYTE
From Master
COMMAND BYTE
From Master
Sr
ADDRESS BYTE
From Master
MSDB
LSDB
Mast
er
Slave
Slave
Slave
From Slave
From Slave
Master
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8.6 Register Maps
8.6.1 Registers
Table 8. DACx0502 Register Map
Offset
0h
Register Name
Section
No Operation
Device Identification
Synchronization
Configuration
Gain
NOOP Register
DEVID Register
SYNC Register
CONFIG Register
GAIN Register
1h
2h
3h
4h
5h
Trigger
TRIGGER Register
BRDCAST Register
STATUS Register
DAC-A Register
DAC-B Register
6h
Broadcast
7h
Device Status
DAC-A
8h
9h
DAC-B
8.6.1.1 NOOP Register (offset = 0h) [reset = 0000h]
Figure 63. NOOP Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOOP
W-0h
Table 9. NOOP Register Field Descriptions
Bit
15-0
Field
No operation
Type
Reset
Description
W
0h
No Operation command
8.6.1.2 DEVID Register (offset = 1h) [reset = 0214h for DAC80502, 1214h for DAC70502, 2214h for
DAC60502]
Figure 64. DEVID Register
15
0
14
13
12
11
0
10
0
9
1
8
0
7
0
6
0
5
0
4
1
3
0
2
1
1
0
0
1
RESOLUTION
R-0h R/W-0000h (DAC80502) R-0h
or 0001h (DAC70502) or
R-0h
R-1h
R-0h
R-0h
R-0h
R-0h
R-1h
R-0h
R-1h
R-0h
R-1h
0020h (DAC60502)
Table 10. DEVID Register Field Descriptions
Bit
15
Field
Type
R
Reset
Description
RESERVED
RESOLUTION
0h
RESERVED
14-12
R
0000h
DAC Resolution:
(DAC80502)
0001h
(DAC70502)
0020h
0000h (DAC80502 16-bit)
0001h (DAC70502 14-bit)
0020h (DAC60502 12-bit)
(DAC60502)
11-0
RESERVED
R
0215h
RESERVED
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8.6.1.3 SYNC Register (offset = 2h) [reset = 0300h]
Figure 65. SYNC Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
DAC-B-
DAC-A-
RESERVED
DAC-B-
DAC-A-
BRDCAST- BRDCAST-
SYNC-EN
SYNC-EN
EN
EN
R/W-0h
R/W-1h
R/W-1h
R/W-0h
R/W-0h
R/W-0h
Table 11. SYNC Register Field Descriptions
Bit
Field
RESERVED
Type
RW
Reset
0h
Description
15-10
9
RESERVED
DAC-B-BRDCAST-EN
RW
1h
When set to 1 the corresponding DAC is set to update its output
after a serial interface write to the BRDCAST register.
When cleared to 0 the corresponding DAC output remains
unaffected after
register.
a serial interface write to the BRDCAST
8
DAC-A-BRDCAST-EN
RW
1h
When set to 1 the corresponding DAC is set to update its output
after a serial interface write to the BRDCAST register.
When cleared to 0 the corresponding DAC output remains
unaffected after
register.
a serial interface write to the BRDCAST
7-2
1
RESERVED
RW
RW
0h
0h
RESERVED
DAC-B-SYNC-EN
When set to 1, the DAC output is set to update in response to
an LDAC trigger (synchronous mode).
When cleared to 0 ,the DAC output is set to update immediately
(asynchronous mode), default.
0
DAC-A-SYNC-EN
RW
0h
When set to 1, the DAC output is set to update in response to
an LDAC trigger (synchronous mode).
When cleared to 0 ,the DAC output is set to update immediately
(asynchronous mode), default.
8.6.1.4 CONFIG Register (offset = 3h) [reset = 0000h]
Figure 66. CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
REF-PWDWN
RESERVED
DAC-B-
DAC-A-
PWDWN
PWDWN
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 12. CONFIG Register Field Descriptions
Bit
Field
Type
RW
RW
RW
RW
Reset
0h
Description
15-9
8
RESERVED
RESERVED
REF-PWDWN
RESERVED
0h
When set to 1 disables the device internal reference
RESERVED
7-2
1
0h
DAC-B-PWDWN
0h
When set to 1, the corresponding DAC in power-down mode and
output is connected to GND through a 1-kΩ internal resistor.
0
DAC-A-PWDWN
RW
0h
When set to 1, the corresponding DAC in power-down mode and
output is connected to GND through a 1-kΩ internal resistor.
30
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ZHCSKJ2A –NOVEMBER 2019–REVISED APRIL 2020
8.6.1.5 GAIN Register (offset = 4h) [reset = 0003h]
Figure 67. GAIN Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
REF-DIV
RESERVED
BUFF-B-
GAIN
BUFF-A-
GAIN
R/W-0h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
Table 13. GAIN Register Field Descriptions
Bit
Field
Type
RW
Reset
0h
Description
15-9
8
RESERVED
REF-DIV
RESERVED
RW
0h
The reference voltage to the device (either from the internal or
external reference) can be divided by a factor of two by setting
the REF-DIV bit to 1. Make sure to configure REF-DIV so that
there is sufficient headroom from VDD to the DAC operating
reference voltage. Improper configuration of the reference
divider triggers a reference alarm condition. In the case of an
alarm condition, the reference buffer is shut down, and all the
DAC outputs go to 0 V. The DAC data registers are unaffected
by the alarm condition, and thus enable the DAC output to return
to normal operation after the reference divider is configured
correctly.
When set to 1 the reference voltage is internally divided by a
factor of 2.
When cleared to 0 the reference voltage is unaffected.
RESERVED
7-2
1
RESERVED
RW
RW
0h
1h
BUFF-B-GAIN
When set to 1 the buffer amplifier for corresponding DAC has a
gain of 2.
When cleared to 0 the buffer amplifier for corresponding DAC
has a gain of 1.
0
BUFF-A-GAIN
RW
1h
When set to 1 the buffer amplifier for corresponding DAC has a
gain of 2.
When cleared to 0 the buffer amplifier for corresponding DAC
has a gain of 1.
8.6.1.6 TRIGGER Register (offset = 5h) [reset = 0000h]
Figure 68. TRIGGER Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
LDAC
W-0h
SOFT-RESET [3:0]
W-0h
Table 14. TRIGGER Register Field Descriptions
Bit
Field
Type
RW
W
Reset
0h
Description
15-5
4
RESERVED
LDAC
RESERVED
0h
Set this bit to 1 to synchronously load those DACs who have
been set in synchronous mode in the SYNC register. This is a
self resetting bit.
3-0
SOFT-RESET [3:0]
W
0h
When set to the reserved code 1010 resets the device to its
default state. This is a self resetting bit.
Copyright © 2019–2020, Texas Instruments Incorporated
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8.6.1.7 BRDCAST Register (offset = 6h) [reset = 0000h for RSTSEL = 0, or reset = 8000h for RSTSEL = 1]
Figure 69. BRDCAST Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAC-DATA [15:0]
W-0000h when RSTSEL = 0 or reset = 8000h when RSTSEL = 1
Table 15. BRDCAST Register Field Descriptions
Bit
15-0
Field
BRDCAST-DATA [15:0]
Type
Reset
Description
W
0000h when
RSTSEL = 0
or
8000h when
RSTSEL = 1
Writing to the BRDCAST register forces those DAC channels
who have been set to broadcast in the SYNC register to update
its active register data to the BRDCAST-DATA one.
Data is MSB aligned in straight binary format and follows the
format below:
DAC80502: { DATA[15:0] }
DAC70502: { DATA[13:0], x, x }
DAC60502: { DATA[11:0], x, x, x, x}
x – Don’t care bits
8.6.1.8 STATUS Register (offset = 7h) [reset = 0000h]
Figure 70. STATUS Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
REF-ALARM
R-0h
Table 16. STATUS Register Field Descriptions
Bit
Field
Type
RW
R
Reset
0h
Description
15-1
0
RESERVED
REF-ALARM
RESERVED
0
REF-ALARM bit. Reads 1 when the difference between the
reference and supply pins is below a minimum analog threshold.
Reads 0 otherwise. When 1, the reference buffer is shut down,
and the DAC outputs are all 0 V. The DAC codes are
unaffected, and the DAC output returns to normal when the
difference is above the analog threshold.
32
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8.6.1.9 DAC-n Register (offset = 8h–9h) [reset = 0000h for RSTSEL = 0, or reset = 8000h for RSTSEL = 1]
Figure 71. DAC-n Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAC-n-DATA [15:0]
R/W-0000h when RSTSEL = 0 or reset = 8000h when RSTSEL = 1
Table 17. DAC-A Data Register Field Descriptions (8h)
Bit
Field
Type
Reset
Description
15-0
DAC-A-DATA [15:0]
RW
0000h when
RSTSEL = 0
or
8000h when
RSTSEL = 1
Data is MSB aligned in straight binary format and follows the
format below:
DAC80502: { DATA[15:0] }
DAC70502: { DATA[13:0], x, x }
DAC60502: { DATA[11:0], x, x, x, x}
x – Don’t care bits
Table 18. DAC-B Data Register Field Descriptions (9h)
Bit
Field
Type
Reset
Description
15-0
DAC-B-DATA [15:0]
RW
0000h when
RSTSEL = 0
or
8000h when
RSTSEL = 1
Data is MSB aligned in straight binary format and follows the
format below:
DAC80502: { DATA[15:0] }
DAC70502: { DATA[13:0], x, x }
DAC60502: { DATA[11:0], x, x, x, x}
x – Don’t care bits
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Generating accurate, stable programmable dc voltages is a key requirement in most precision end equipment.
The DACx0502 family of precision DACs are an excellent choice for such applications. The DACx0502 tiny
package, high resolution, and simple interface makes these devices a great choice for applications such as offset
and gain control, VCO tuning, programmable reference, and more. With the aforementioned features, this family
of DACs caters to a wide range of end equipment, such as battery testers, communications equipment, factory
automation and control, test and measurement, and more.
9.2 Typical Application
Battery test equipment requires a two-channel DAC for every channel of battery test output. A battery tester
operates in constant-current (CC) and constant-voltage (CV) modes. The two DAC channels are used to set the
voltage and current for battery charge and discharge control. The low INL of the DACx0502 makes system
calibration simple. The integrated reference and the small package make the design very compact.
VDD
Battery
Charge/
Discharge
Circuit
VSET
ISET
DACx0502
RSENSE
图 72. Battery Test Equipment
9.2.1 Design Requirements
•
•
•
DAC output range: 0 V to 2.5 V
DAC output accuracy after calibration: 0.05%FSR
Operating temperature: 0°C to 100°C
9.2.2 Detailed Design Procedure
图 72 shows a simplified circuit diagram of a battery test system. Use the internal reference (2.5 V) and gain of 1
for an output range of 2.5 V. The reference divider is 1. Select the 16-bit DAC80502 for the best accuracy. The
typical value of the TUE is 0.02%FSR, as specified in the Typical Characteristics table. The absolute error at the
DAC output includes the error from the reference, the error from the DAC, and the temperatures drifts of offset
error, gain error, and reference. Ignore the load regulation, line regulation, and long-term drift of the reference as
compared to the initial accuracy and temperature drift. Write the total TUE at the DAC output, as given in 公式 2.
34
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Typical Application (接下页)
TUETOTAL
=
TUE 2 + (TCOE )2 + (TCGE)2 + (EREF ìGAIN)2 + (TCREF ìGAIN)2
(
)
where
•
•
•
•
•
TCOE is the temperature drift of the offset error.
TCGE is the temperature drift of the gain error.
EREF is the initial accuracy of the reference.
TCREF is the temperature drift of the reference.
GAIN is the gain setting of the DAC in combination with the reference divider.
(2)
(3)
Convert the INL value in LSB to %FSR using 公式 3.
LSB
%FSR=
ì100
2N
Convert the temperature drift values in ppm/°C to %FSR using 公式 4.
PPM / èC ì DT
(
)
%FSR =
104
where
•
∆T is the temperature range.
(4)
(5)
Calculate the total error after the offset and gain of DAC are calibrated using 公式 5
2
TUETOTAL
=
INL + (TCOE )2 + (TCGE )2 + (TCREF ìGAIN)2
(
)
The total error at the DAC output calculated using the previous equations is 0.112%FSR before calibration, and
0.05%FSR after calibration. For better accuracy, perform a temperature calibration. 图 73 and 图 74 show the
drift in the internal reference voltage and TUE, respectively over 0°C to 100°C.
9.2.3 Application Curves
图 73. Internal Reference vs Temperature
图 74. TUE vs Temperature
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9.3 System Examples
The DACx0502 come with a pin-selectable SPI or I2C interface. This configuration makes the system design
generic. Pull the SPI2C pin low for SPI or high for I2C. The RSTSEL pin provides a known output at the DAC
channels at power up, which helps the system achieve a predictable behavior during start up. When using a
processor with multiple power-supply domains, make sure the input/output power (IOVDD) never exceeds the
VDD voltage of the DAC. Switching on the IOVDD before VDD can violate the absolute maximum ratings. When
there is no power-supply sequencing implemented on the system between the processor and the DAC, use a
series resistor on the digital lines so that the current flow on the digital lines is limited to ±10 mA on any pin.
9.3.1 SPI Connection to a Processor
The DACx0502 provides a 3-wire serial peripheral interface (SPI). The connections can be made to a processor,
as shown in 图 75. Connect the SPI2C pin to ground either directly or through a pulldown resistor. Pull the
RSTSEL pin low or high based on the desired output state at power-up. Use a pullup resistor on the SYNC
signal so that the signal is high by default. Use termination resistors at the digital source so that the transmission
line reflections are minimized. The source termination resistors also help in slowing down the rise and fall times
of the digital signals, and in turn, help in minimizing the digital feedthrough of the DAC.
IOVDD
RPULLUP
IOVDD
VDD
RS
RS
RS
SCLK
MOSI
CS
SCLK
SDIN
PROCESSOR
DACx0502
SYNC
RSTSEL
SPI2C
图 75. SPI Connection to a Processor
9.3.2 I2C Interface Connection to a Processor
The I2C interface on DACx0502 provides a slave address selection pin A0 in addition to the standard SCL and
SDA signals. The A0 can be configured to provide four slave addresses, as specified in 表 3. Pull up the SCL
and SDA pins, as shown in 图 76. The pullup resistor must be selected considering the parasitic capacitance of
the I2C bus on the printed circuit board (PCB). A small resistance provides better speed, but at the cost of
increased power consumption.
IOVDD
RPULLUP
IOVDD
VDD
SCL
SDA
SCL
SDA
PROCESSOR
DACx0502
A0
IOVDD
RSTSEL
SPI2C
图 76. I2C Interface Connection to a Processor
36
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ZHCSKJ2A –NOVEMBER 2019–REVISED APRIL 2020
9.4 What To Do and What Not To Do
9.4.1 What To Do
•
When using an external reference, disable the internal reference. This step must be the first step after power
on, especially when the external reference is greater than the 2.5-V internal reference.
•
•
Maintain the required headroom between the reference voltage and VDD.
Use the reference divider when the headroom exceeds the limit.
9.4.2 What Not To Do
•
Do not use an external reference when the internal reference is on. There is no current limit on the internal
reference.
9.5 Initialization Setup
The DACx0502 requires a simple software initialization process based on the interface, power supply, and
reference selection. The initialization steps are as follows:
1. When using an external reference, disable the internal reference.
2. Divide the reference by two when the reference voltage exceeds the headroom required from VDD. For
example, when using 3.3-V VDD and the internal reference of 2.5 V, the DAC outputs are disabled unless
the reference is divided by two.
3. Set the output gain.
4. Write to the DAC register.
The following text shows the pseudocode to get started with the DACx0502:
//SPI Settings
//Mode: Mode-1 (CPOL: 0, CPHA: 1)
//CS Type: Active Low, Per Packet
//Frame length: 24
//SYNTAX: <WRITE REGISTER (HEX ADDRESS)>, <HEX DATA>
//Disable internal reference (only in case of external reference)
WRITE CONFIG (0x03), 0x0100
//Select REFDIV=1 (reference divided by 2) and GAIN=1 (gain at both the DAC outputs is 2)
WRITE GAIN (0x04), 0x0103
//Write mid-code to DACA
WRITE DAC-A (0x08), 0x7FFF
//Write Full-code to DACB
WRITE DAC-B (0x09), 0xFFFF
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10 Power Supply Recommendations
The DACx0502 operate within the specified VDD supply range of 2.7 V to 5.5 V. The DACx0502 do not require
specific supply sequencing. The VDD supply must be well regulated and low noise. Switching power supplies
and DC/DC converters often have high-frequency glitches or spikes riding on the output voltage. In addition,
digital components create similar high-frequency spikes. This noise can easily couple into the DAC output
voltage through various paths between the power connections and analog output. To further minimize noise from
the power supply, include a 1-μF to 10- μF capacitor and 0.1-μF bypass capacitor. The current consumption on
the VDD pin, the short-circuit current limit, and the load current for the device is listed in the Electrical
Characteristics section. The power supply must meet the aforementioned current requirements.
11 Layout
11.1 Layout Guidelines
A precision analog component requires careful layout. The following list provides some insight into good layout
practices.
•
•
•
•
Bypass the VDD to ground with a low ESR ceramic bypass capacitor. The typical recommended bypass
capacitance is 0.1-µF to 0.22-µF ceramic capacitor, with a X7R or NP0 dielectric.
Place power supplies and REF bypass capacitors close to the pins to minimize inductance and optimize
performance.
Use a high-quality, ceramic-type NP0 or X7R for optimal performance across temperature, and a very low
dissipation factor.
The digital and analog sections must have proper placement with respect to the digital pins and analog pins
of the DACx0502 devices. The separation of analog and digital blocks minimizes coupling into neighboring
blocks, as well as interaction between analog and digital return currents.
11.2 Layout Example
GND
Decoupling
GND
Reference
Bypass
Capacitor
Capacitor
VDD
VOUTA
Optional
REFIN or
REFOUT
DACx0502
1
2
3
4
5
10
9
VOUTB
8
SDIN/SDA
Pull-up
7
VDD
6
GND
GND
SYNC/A0
SCLK/SCL
Pull-down for
SPI Mode
(Note: Ground and Power planes omitted for clarity)
图 77. Layout Example
38
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ZHCSKJ2A –NOVEMBER 2019–REVISED APRIL 2020
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：DAC80502EVM 用户指南
12.2 相关链接
表 19 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速
链接。
表 19. 相关链接
器件
产品文件夹
单击此处
单击此处
单击此处
立即订购
单击此处
单击此处
单击此处
技术文档
单击此处
单击此处
单击此处
工具和软件
单击此处
单击此处
单击此处
支持和社区
单击此处
单击此处
单击此处
DAC80502
DAC70502
DAC60502
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2019–2020, Texas Instruments Incorporated
39
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC60502DRXR
DAC60502DRXT
DAC70502DRXR
DAC70502DRXT
DAC80502DRXR
DAC80502DRXT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
DRX
DRX
DRX
DRX
DRX
DRX
10
10
10
10
10
10
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
D652
D652
D752
D752
D852
D852
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC60502DRXR
DAC60502DRXT
DAC70502DRXR
DAC70502DRXT
DAC80502DRXR
DAC80502DRXT
WSON
WSON
WSON
WSON
WSON
WSON
DRX
DRX
DRX
DRX
DRX
DRX
10
10
10
10
10
10
3000
250
178.0
178.0
178.0
178.0
178.0
178.0
8.4
8.4
8.4
8.4
8.4
8.4
2.75
2.75
2.75
2.75
2.75
2.75
2.75
2.75
2.75
2.75
2.75
2.75
0.95
0.95
0.95
0.95
0.95
0.95
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC60502DRXR
DAC60502DRXT
DAC70502DRXR
DAC70502DRXT
DAC80502DRXR
DAC80502DRXT
WSON
WSON
WSON
WSON
WSON
WSON
DRX
DRX
DRX
DRX
DRX
DRX
10
10
10
10
10
10
3000
250
205.0
205.0
205.0
205.0
205.0
205.0
200.0
200.0
200.0
200.0
200.0
200.0
33.0
33.0
33.0
33.0
33.0
33.0
3000
250
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
DRX0010A
WSON - 0.8 mm max height
SCALE 5.000
PLASTIC SMALL OUTLINE - NO LEAD
2.6
2.4
B
A
PIN 1 INDEX AREA
2.6
2.4
C
0.8 MAX
SEATING PLANE
0.08 C
SYMM
(0.2) TYP
1.1
0.9
10X
0.05
0.00
5
6
2X
2
SYMM
8X
0.5
10
1
0.30
0.18
10X
PIN 1 ID
(45 X0.15)
0.1
C A B
C
0.05
4223856/B 01/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
DRX0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (1.2)
1
10
10X (0.24)
8X (0.5)
SYMM
6
5
SYMM
(1.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
EXPOSED METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223856/B 01/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DRX0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (1.2)
1
10
10X (0.24)
8X (0.5)
SYMM
5
6
SYMM
(1.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223856/B 01/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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