DAC3283_14_技术文档

DAC3283

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SLAS693A –MARCH 2010–REVISED APRIL 2010

Dual-Channel, 16-Bit, 800 MSPS, Digital-to-Analog Converter (DAC)

Check for Samples: DAC3283

1

FEATURES

APPLICATIONS

•

Cellular Base Stations

Diversity Transmit

Wideband Communications

Digital Synthesis

•

Dual, 16-Bit, 800 MSPS DACs

•

8-Bit Input LVDS Data Bus

–

Byte-Wide Interleaved Data Load

8 Sample Input FIFO

Optional Data Pattern Checker

DESCRIPTION

•

Multi-DAC Synchronization

The DAC3283 is a dual-channel 16-bit 800 MSPS

digital-to-analog converter (DAC) with an 8-bit LVDS

input data bus with on-chip termination, optional

2x-4x interpolation filters, digital IQ compensation and

internal voltage reference. The DAC3283 offers

superior linearity, noise and crosstalk performance.

Selectable 2x-4x Interpolation Filters

–

Stop-Band Attenuation > 85 dB

•

Fs/2 and ± Fs/4 Coarse Mixer

Digital Quadrature Modulator Correction

–

Gain, Phase and Offset Correction

Input data can be interpolated by 2x or 4x through

on-chip interpolating FIR filters with over 85 dB of

stop-band attenuation. Multiple DAC3283 devices can

be fully synchronized.

•

Temperature Sensor

3- or 4-Wire Serial Control Interface

On-Chip 1.2-V Reference

Differential Scalable Output: 2 to 20 mA

The DAC3283 allows either a complex or real output.

An optional coarse mixer in complex mode provides

frequency upconversion and the dual DAC output

produces a complex Hilbert Transform pair. The

digital IQ compensation feature allows optimization of

phase, gain and offset to maximize sideband rejection

and minimize LO feed-through of an external

quadrature modulator performing the final single

sideband RF up-conversion.

Single-Carrier TM1 WCDMA ACLR: 82 dBc at

f_OUT= 122.88 MHz

•

Low Power: 1.3 W at 800 MSPS

Space Saving Package: 48-pin 7×7mm QFN

The DAC3283 is characterized for operation over the

entire industrial temperature range of –40°C to 85°C

and is available in a 48-pin 7×7mm QFN package.

ORDERING INFORMATION

T_A

ORDER CODE

DAC3283IRGZT

DAC3283IRGZR

PACKAGE DRAWING/TYPE^{(1) (2) (3)}

TRANSPORT MEDIA

QUANTITY

250

–40°C to 85°C

RGZ/64QFN Quad Flatpack No-Lead

Tape and Reel

2000

(1) Thermal Pad Size: 5,6 mm × 5,6 mm

(2) MSL Peak Temperature: Level-3-260C-168 HR

(3) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DAC3283

SLAS693A –MARCH 2010–REVISED APRIL 2010

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

FUNCTIONAL BLOCK DIAGRAM

DACCLKP

EXTIO

BIASJ

LVPECL

LVDS

Clock Distribution

1.2 V

Reference

DACCLKN

DATACLKP

DATACLKN

D7P

QMC

A-offset

A

gain

FIR0

x2

FIR1

LVDS

IOUTA1

IOUTA2

16-b

DAC

x2

16

D7N

59 taps

23 taps

LVDS

D0P

D0N

IOUTB1

IOUTB2

16-b

DAC

x2

16

FRAMEP

FRAMEN

OSTRP

OSTRN

QMC

B-offset

B

gain

Frame Strobe

Temp

Sensor

LVPECL

Control Interface

AVDD33

2

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SLAS693A –MARCH 2010–REVISED APRIL 2010

DAC3283

RGZ PACKAGE

(TOP VIEW)

1

36

35

34

33

32

31

30

29

28

27

26

25

DACVDD18

CLKVDD18

ALARM_SDO

SDENB

SCLK

CLKVDD18

DACVDD18

DACCLKP

DACCLKN

GND

2

3

4

5

DAC3283

OSTRP

OSTRN

DIGVDD18

D7P

6

SDIO

RGZ Package

48-QFN 7x7mm

(Top View)

7

TXENABLE

DIGVDD18

D0N

8

9

D7N

10

11

12

D0P

D6P

D1N

D6N

D1P

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

37, 40, 42,

45, 48

Analog supply voltage. (3.3 V)

AVDD33

I

1.8V CMOS output for ALARM condition. The ALARM output functionality is defined through the

CONFIG6 register. Default polarity is active low, but can be changed to active high via CONFIG0

alarm_pol control bit. Optionally, it can be used as the uni-directional data output in 4-pin serial

interface mode (CONFIG 23 sif4_ena = '1').

ALARM_SDO

34

O

BIASJ

43

O

I

Full-scale output current bias. For 20mA full-scale output current, connect a 960Ω resistor to GND.

Internal clock buffer supply voltage. (1.8 V) It is recommended to isolate this supply from DACVDD18

and DIGVDD18.

CLKVDD18

1, 35

LVDS positive input data bits 0 through 7. Each positive/negative LVDS pair has an internal 100 Ω

termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR) with two

data transfers per DATACKP/N clock cycle. Dual channel 16-bit data is transferred byte-wide on this

single 8-bit data bus using FRAMEP/N as a frame strobe indicator.

9, 11, 13,

15, 21, 23,

25, 27

D[7..0]P

D[7..0]N

I

D7P is most significant data bit (MSB) – pin 9

D0P is least significant data bit (LSB) – pin 27

The order of the bus can be reversed via CONFIG19 rev bit.

LVDS negative input data bits 0 through 15. (See D[7:0]P description above)

D7N is most significant data bit (MSB) – pin 10

10, 12, 14,

16, 22, 24,

26, 28

D0N is least significant data bit (LSB) – pin 28

DACCLKP

DACCLKN

3

4

I

Positive external LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2.

Complementary external LVPECL clock input for DAC core. (see the DACCLKP description)

DAC core supply voltage. (1.8 V) It is recommended to isolate this supply from CLKVDD18 and

DIGVDD18.

DACVDD18

2, 36

I

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TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

LVDS positive input data clock. This positive/negative pair has an internal 100 Ω termination resistor.

Input data D[7:0]P/N is latched on both edges of DATACLKP/N (Double Data Rate) with two data

transfers input per DATACLKP/N clock cycle.

DATACLKP

17

I

DATACLKN

DIGVDD18

18

I

LVDS negative input data clock. (See DATACLKP description)

Digital supply voltage. (1.8V) It is recommended to isolate this supply from CLKVDD18 and

DACVDD18.

8, 29

Used as external reference input when internal reference is disabled through CONFIG25 extref_ena

= '1'. Used as internal reference output when CONFIG25 extref_ena = '0' (default). Requires a 0.1µF

decoupling capacitor to AGND when used as reference output.

EXTIO

44

I/O

I

LVDS frame indicator positive input. This positive/negative pair has an internal 100Ω termination

resistor. This signal is captured with the rising edge of DATACLKP/N and used to indicate the

beginning of the frame. It is also used as a reset signal by the FIFO. The FRAMEP/N signal should be

edge-aligned with D[7:0]P/N.

FRAMEP

19

20

FRAMEN

GND

I

LVDS frame indicator negative input. (See the FRAMEN description)

5, Thermal

Pad

Pin 5 and the Thermal Pad located on the bottom of the QFN package is ground for all supplies.

A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a

full scale current sink and the least positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data input

results in a 0 mA current sink and the most positive voltage on the IOUTA1 pin.

IOUTA1

IOUTA2

38

39

O

A-Channel DAC complementary current output. The IOUTA2 has the opposite behavior of the

IOUTA1 described above. An input data value of 0x0000 results in a 0 mA sink and the most positive

voltage on the IOUTA2 pin.

IOUTB1

IOUTB2

47

46

O

B-Channel DAC current output. Refer to IOUTA1 description above.

B-Channel DAC complementary current output. Refer to IOUTA2 description above.

LVPECL output strobe positive input. This positive/negative pair is captured with the rising edge of

DACCLKP/N. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it

can be left floating.

OSTRP

6

I

OSTRN

SCLK

7

I

LVPECL output strobe negative input. (See the OSTRP description)

1.8V CMOS serial interface clock. Internal pull-down.

32

33

SDENB

1.8V CMOS active low serial data enable, always an input to the DAC3283. Internal pull-up.

1.8V CMOS serial interface data. Bi-directional in 3-pin mode (default). In 4-pin interface mode, the

SDIO pin is an input only. Internal pull-down.

SDIO

31

30

41

I/O

1.8V CMOS active high input. TXENABLE must be high for the DATA to the DAC to be enabled.

When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored.

Internal pull-down.

TXENABLE

VFUSE

I

Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to

DACVDD18 pins for normal operation.

4

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SLAS693A –MARCH 2010–REVISED APRIL 2010

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE

–0.5 to 2.3

UNIT

V

DACDVDD18⁽²⁾

DIGVDD18⁽²⁾

–0.5 to 2.3

V

Supply voltage range CLKVDD18⁽²⁾

VFUSE⁽²⁾

–0.5 to 2.3

V

–0.5 to 2.3

V

AVDD33⁽²⁾

–0.5 to 4

V

CLKVDD18 to DIGDVDD18

DACVDD18 TO DIGVDD18

–0.5 to 0.5

V

–0.5 to 0.5

V

D[7..0]P ,D[7..0]N, DATACLKP, DATACLKN, FRAMEP, FRAMEN⁽²⁾

DACCLKP, DACCLKN, OSTRP, OSTRN⁽²⁾

ALARM_SDO, SDIO, SCLK, SDENB, TXENABLE⁽²⁾

IOUTA1/B1, IOUTA2/B2⁽²⁾

–0.5 to DIGVDD18 + 0.5

–0.5 to CLKVDD18 + 0.5

–0.5 to DIGCLKVDD18 + 0.5

–1.0 to AVDD33 + 0.5

–0.5 to AVDD33 + 0.5

20

V

Terminal voltage

range

V

EXTIO, BIASJ⁽²⁾

V

Peak input current (any input)

mA

°C

Peak total input current (all inputs)

Operating free-air temperature range, T_A: DAC3283

Storage temperature range

–30

–40 to 85

–65 to 150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of these or any other conditions beyond those indicated under recommended operating conditions is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Measured with respect to GND.

THERMAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

THERMAL CONDUCTIVITY

48ld QFN

UNIT

(1) (2)

T_J

Maximum junction temperature

125

30

24

8

°C

Theta junction-to-ambient (still air)

Theta junction-to-ambient (150 lfm)

Theta junction-to-board

q_JA

°C/W

q_JB

q_Jp

°C/W

Theta junction-to-pad

1.3

(1) Air flow or heat sinking reduces q_JAand may be required for sustained operation at 85° under maximum operating conditions.

(2) It is strongly recommended to solder the device thermal pad to the board ground plane.

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ELECTRICAL CHARACTERISTICS — DC SPECIFICATIONS⁽¹⁾

over operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RESOLUTION

16

Bits

DC ACCURACY

DNL

INL

Differential nonlinearity

Integral nonlinearity

±2

±4

1 LSB = IOUTFS/2¹⁶

LSB

ANALOG OUTPUT

Coarse gain linearity

±0.04

±0.01

±2

LSB

%FSR

mA

Offset error

Mid code offset

With external reference

With internal reference

Gain error

±2

Gain mismatch

–2

2

Minimum full scale output current

Maximum full scale output current

Output compliance range⁽²⁾

Output resistance

2

Nominal full-scale current, IOUTFS = 16 x IBIAS

current.

20

mA

IOUTFS = 20 mA

AVDD –0.5V

AVDD +0.5V

V

300

5

kΩ

Output capacitance

pF

REFERENCE OUTPUT

V_ref

Reference output voltage

Reference output current⁽³⁾

1.14

0.1

1.2

1.26

1.25

V

100

nA

REFERENCE INPUT

V_EXTIOInput voltage range

1.2

1

V

External reference mode

Input resistance

MΩ

kHz

pF

Small signal bandwidth

Input capacitance

472

100

TEMPERATURE COEFFICIENTS

ppm of

FSR/°C

Offset drift

With external reference

With internal reference

±1

±15

±30

±8

ppm of

FSR/°C

Gain drift

Reference voltage drift

POWER SUPPLY

ppm/°C

AVDD33

3.0

1.7

3.3

1.8

149

340

55

3.6

1.9

V

DACVDD18, DIGVDD18, CLKVDD18

Analog supply current

Digital supply current

V

I_(AVDD33)

mA

I_(DIGDVDD)

Mode 1 (below)

I_(DACVDD18)DAC supply current

I_(CLKVDD18)Clock supply current

37

Mode 1: f_DAC= 800MSPS,

4x interpolation, Fs/4 mixer on, QMC on

1300

1000

1450

mW

Mode 2: f_DAC= 491.52MSPS,

2x interpolation, Mixer off, QMC on

Mode 3: Sleep mode

f_DAC= 800MSPS, 4x interpolation, Fs/4 mixer on,

CONFIG24 sleepa, sleepb set = 1

P

Power dissipation

750

7

mW

Mode 4: Power-Down mode

No clock, static data pattern,

CONFIG23 clkpath_sleep_a, clkpath_sleepb set = 1

CONFIG24 clkrecv_sleep, sleepa, sleepb set = 1

18

85

PSRR

T

Power supply rejection ratio

Operating range

DC tested

±0.2

25

%FSR/V

°C

–40

(1) Measured differential across IOUTA1 and IOUTA2 with 25 Ω each to AVDD.

(2) The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,

resulting in reduced reliability of the DAC3283 device. The upper limit of the output compliance is determined by the load resistors and

full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.

(3) Use an external buffer amplifier with high impedance input to drive any external load.

6

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ELECTRICAL CHARACTERISTICS — AC SPECIFICATIONS

Over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)

PARAMETER

ANALOG OUTPUT⁽¹⁾

TEST CONDITIONS

MIN

TYP MAX UNIT

1x Interpolation

312.5

625

f_DAC

Maximum DAC output update rate 2x Interpolation

4x Interpolation

MSPS

800

t_s(DAC)

t_pd

Output settling time to 0.1%

Output propagation delay

Transition: Code 0x0000 to 0xFFFF

10.4

2

ns

DAC outputs are updated on the falling edge of DAC

clock. Does not include digital latency (see below).

t_r(IOUT)

t_f(IOUT)

Output rise time 10% to 90%

Output fall time 90% to 10%

220

ps

IOUT current settling to 1% of IOUTFS. Measured

from SDENB rising edge; Register CONFIG24,

toggle sleepa from 1 to 0.

DAC wake-up time

DAC sleep time

90

Power-up

time

µs

IOUT current settling to less than 1% of IOUTFS.

Measured from SDENB rising edge; Register

CONFIG24, toggle sleepa from 0 to 1.

1x Interpolation

2x Interpolation

4x Interpolation

QMC

59

139

290

24

DAC

clock

cycles

Digital latency

AC PERFORMANCE⁽²⁾

f_DAC= 800 MSPS, f_OUT= 20.1 MHz

f_DAC= 800 MSPS, f_OUT= 50.1 MHz

f_DAC= 800 MSPS, f_OUT= 70.1 MHz

f_DAC= 800 MSPS, f_OUT= 30 ± 0.5 MHz

f_DAC= 800 MSPS, f_OUT= 50 ± 0.5 MHz

f_DAC= 800 MSPS, f_OUT= 100 ± 0.5 MHz

f_DAC= 800 MSPS, f_OUT= 10.1 MHz

f_DAC= 800 MSPS, f_OUT= 80.1 MHz

f_DAC= 737.28 MSPS, f_OUT= 30.72MHz

f_DAC= 737.28 MSPS, f_OUT= 153.6MHz

f_DAC= 737.28 MSPS, f_OUT= 30.72MHz

f_DAC= 737.28 MSPS, f_OUT= 153.6MHz

f_DAC= 800 MSPS, f_OUT= 10MHz

85

76

Spurious free dynamic range (0 to

f_DAC/2)Tone at 0 dBFS

SFDR

dBc

72

93

Third-order two-tone

intermodulation distortion

Each tone at –12 dBFS

IMD3

NSD

90

86

162

160

85

Noise spectral density tone at

0dBFS

dBc/Hz

dBc

Adjacent channel leakage ratio,

single carrier

81

WCDMA⁽³⁾

91

Alternate channel leakage ratio,

single carrier

dBc

85

Channel isolation

84

(1) Measured single-ended into 50Ω load.

(2) 4:1 transformer output termination, 50Ω doubly terminated load

(3) Single carrier, W-CDMA with 3.84 MHz BW, 5-MHz spacing, centered at f_OUT, PAR = 12dB. TESTMODEL 1, 10 ms

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ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS

over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(1)

LVDS INTERFACE:D[7:0]P/N, DATACLKP/N, FRAMEP/N

Byte-wide DDR format

DATACLK frequency = 625 MHz

f_DATA

Input data rate

312.5

1250

MSPS

f_BUS

V_A,B+

V_A,B–

V_COM

Z_T

Byte-wide LVDS data transfer rate

MSPS

mV

V

Logic high differential input voltage threshold

Logic low differential input voltage threshold

Input common mode

150

–150

0.9

400

–400

1.2

1.5

Internal termination

85

110

2

135

Ω

C_L

LVDS Input capacitance

pF

TIMING LVDS INPUTS: DATACLKP/N DOUBLE EDGE LATCHING – See Figure 40

Setup time, D[7:0]P/N and FRAMEP/N, valid FRAMEP/N latched on rising edge of

t_s(DATA)

–25

ps

to either edge of DATACLKP/N

DATACLKP/N only

Hold time, D[7:0]P/N and FRAMEP/N, valid

after either edge of DATACLKP/N

FRAMEP/N latched on rising edge of

DATACLKP/N only

t_h(DATA)

t_(FRAME)

t_{_align}

375

ps

ns

FRAMEP/N pulse width

f_DATACLKis DATACLK frequency in MHz

1/2f_DATACLK

Maximum offset between DATACLKP/N and FIFO bypass mode only f_DACCLKis

DACCLKP/N rising edges

1/2f_DACCLK

–0.55

DACCLK frequency in MHz

CLOCK INPUT (DACCLKP/N)

Duty cycle

40%

0.4

60%

800

Differential voltage⁽²⁾

DACCLKP/N Input Frequency

OUTPUT STROBE (OSTRP/N)

1.0

V

MHz

f_OSTR= f_DACCLK/ (n × 8 × Interp) where n is

any positive integer f_DACCLKis DACCLK

frequency in MHz

f_DACCLK/ (8

x interp)

f_OSTR

Frequency

Duty cycle

40%

0.4

60%

Differential voltage

1.0

V

TIMING OSTRP/N INPUT: DACCLKP/N RISING EDGE LATCHING

Setup time, OSTRP/N valid to rising edge of

DACCLKP/N

t_s(OSTR)

200

ps

Hold time, OSTRP/N valid after rising edge

of DACCLKP/N

t_h(OSTR)

CMOS INTERFACE: ALARM_SDO, SDIO, SCLK, SDENB, TXENABLE

V_IH

V_IL

I_IH

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

CMOS input capacitance

1.25

V

0.54

40

–40

mA

pF

I_IL

40

CI

2

DIGVDD18

–0.2

I_load= –100 mA

V

V_OH

ALARM_SDO, SDIO

0.8 x

DIGVDD18

I_load= –2mA

I_load= 100 mA

0.2

0.5

V

V_OL

I_load= 2 mA

SERIAL PORT TIMING – See Figure 32 and Figure 33

t_s(SDENB)

t_s(SDIO)

t_h(SDIO)

Setup time, SDENB to rising edge of SCLK

20

10

5

ns

ms

ns

Setup time, SDIO valid to rising edge of

SCLK

Hold time, SDIO valid to rising edge of SCLK

Register CONFIG5 read (temperature

sensor read)

1

t_(SCLK)

Period of SCLK

All other registers

100

(1) See LVDS INPUTS section for terminology.

(2) Driving the clock input with a differential voltage lower than 1V will result in degraded performance.

8

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ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued)

over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

0.4

40

TYP

MAX

UNIT

ms

Register CONFIG5 read (temperature

sensor read)

t_(SCLKH)

High time of SCLK

All other registers

ns

Register CONFIG5 read (temperature

sensor read)

0.4

40

ms

t_(SCLKL)

Low time of SCLK

All other registers

ns

t_d(Data)

Data output delay after falling edge of SCLK

10

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TYPICAL CHARACTERISTICS

5

4

3

2

1

0

-1

-2

-3

-4

-5

-1

-2

-3

-4

-5

0

10000 20000 30000 40000 50000 60000 70000

0

10000 20000 30000 40000 50000 60000 70000

Code

Figure 1. INTEGRAL NON-LINEARITY

Figure 2. DIFFERENTIAL NON-LINEARITY

100

f

= 800 MSPS, 4x Interpolation,

DAC

f

= 800 MSPS, 4x Interpolation,

DAC

IOUTFS = 20 mA

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

IOUTFS = 20 mA

-6 dBFS

-12 dBFS

-6 dBFS

-12 dBFS

0 dBFS

0

50

100

150

200

- MHz

250

300

350

0

50

100

150

200

- MHz

250

300

350

f

OUT

f

OUT

Figure 3. SPURIOUS FREE DYNAMIC RANGE vs INPUT SCALE

Figure 4. SECOND HARMONIC vs INPUT SCALE

10

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TYPICAL CHARACTERISTICS (continued)

105

100

95

90

85

80

75

70

65

60

55

100

95

90

85

80

75

70

65

60

55

50

f

= 800 MSPS, 4x Interpolation,

f

= 312.5 MSPS, 0 dBFS,

DAC

IOUTFS = 20 mA

-6 dBFS

1x interpolation

-12 dBFS

2x interpolation

4x interpolation

0 dBFS

50

0

20

40

60

- MHz

80

100

120

50

100

150

200

- MHz

250

300

350

f

OUT

f

OUT

Figure 5. THIRD HARMONIC vs INPUT SCALE

Figure 6. SPURIOUS FREE DYNAMIC RANGE vs

INTERPOLATION

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

4x Interpolation, 0 dBFS

IOUTFS = 20 mA

f

= 800 MSPS, 4x Interpolation,

DAC

0 dBFS

f_DAC= 200 MSPS

10 mA

f_DAC= 400 MSPS

20 mA

f_DAC= 800 MSPS

2 mA

250

0

50

100

150

200

- MHz

300

350

0

50

100

150

200

- MHz

250

300

350

f

OUT

Figure 7. SPURIOUS FREE DYNAMIC RANGE vs f_DAC

Figure 8. SPURIOUS FREE DYNAMIC RANGE vs IOUTFS

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TYPICAL CHARACTERISTICS (continued)

10

0

10

0

2x Interpolation,

f_DAC= 500 MSPS,

2x Interpolation,

f_DAC= 500 MSPS,

f_OUT= 100 MHz

f_OUT= 50 MHz

-10

-20

-30

-40

-50

-60

-70

-80

-90

-10

-20

-30

-40

-50

-60

-70

-80

-90

10

60

110 160

f - Frequency - MHz

210

10

60

110 160

f - Frequency - MHz

210

Figure 9. SINGLE TONE SPECTRAL PLOT

Figure 10. SINGLE TONE SPECTRAL PLOT

10

0

100

f

= 800 MSPS, 4x Interpolation,

DAC

4x Interpolation, 0 dBFS

f_DAC= 800 MSPS,

95

90

85

80

75

70

65

60

Tones at f

0ꢀ5 MHz,

OUT

f_OUT= 150 MHz

IOUTFS = 20 mA

-10

-20

-30

-40

-50

-60

-70

-80

-90

-6 dBFS

0 dBFS

-12 dBFS

55

50

0

50

100

150

200

- MHz

250

300

350

10

60

110 160 210 260 310 360

f - Frequency - MHz

f

OUT

Figure 11. SINGLE TONE SPECTRAL PLOT

Figure 12. IMD3 vs INPUT SCALE

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TYPICAL CHARACTERISTICS (continued)

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

f

= 312.5 MSPS,

DAC

Tones at f

0.5 MHz,

OUT

0 dBFS, IOUTFS = 20 mA

f_DAC= 200 MSPS

f_DAC= 800 MSPS

1x interpolation

4x interpolation

f_DAC= 400 MSPS

4x Interpolation,

Tones at f 0ꢀ5 MHz,

0 dBFS, IOUTFS = 20 mA

2x interpolation

OUT

55

50

65

0

50

100

150

200

- MHz

250

300

350

20

40

60

80

100 120 140 160

- MHz

f

OUT

Figure 13. IMD3 vs INTERPOLATION

Figure 14. IMD3 vs f_DAC

105

100

95

90

85

80

75

70

65

60

55

170

165

160

155

150

145

140

135

130

f

= 800 MSPS, 4x Interpolation,

DAC

Tones at f

0ꢀ5 Mhz, 0 dBFS

OUT

-6 dBFS

0 dBFS

20 mA

10 mA

-12 dBFS

2 mA

f

= 800 MSPS, 4x Interpolation,

DAC

IOUTFS = 20 mA

50

0

50

100

150

200

- MHz

250

300

350

50

100

150

200

- MHz

250

300

350

f

OUT

Figure 15. IMD3 vs IOUTFS

Figure 16. NSD vs INPUT SCALE

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TYPICAL CHARACTERISTICS (continued)

170

165

160

155

150

145

140

135

130

170

165

160

155

150

145

140

f

= 312.5 MSPS, 0 dBFS,

DAC

IOUTFS = 20 mA

f_DAC= 400 MSPS

f_DAC= 800 MSPS

2x interpolation

1x interpolation

4x interpolation

f_DAC= 200 MSPS

4x interpolation, 0 dBFS,

IOUTFS = 20 mA

0

20

40

60

80

100 120 140 160

0

50

100

150

200

- MHz

250

300

350

f

- MHz

f

OUT

Figure 17. NSD vs INTERPOLATION

Figure 18. NSD vs f_DAC

100

95

90

85

80

75

70

65

85

80

75

70

65

60

f

= 737.28 MSPS, 4x Interpolation,

f

= 737.28 MSPS, 4x Interpolation,

DAC

IOUTFS = 20 mA

Aternate, 0 dBFS

ACLR, 0 dBFS

Alternate -6 dBFS

Alternate 0 dBFS

Alternate, -6 dBFS

Adjacent 0 dBFS

Adjacent -6 dBFS

ACLR -6 dBFS

0

50

100

150

- MHz

200

250

300

0

50

100

150

- MHz

200

250

300

f

OUT

Figure 19. SINGLE CARRIER WCDMA ACLR vs INPUT SCALE

Figure 20. FOUR CARRIER WCDMA ACLR vs INPUT SCALE

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TYPICAL CHARACTERISTICS (continued)

*

RBW 30 kHz

VBW 300 kHz

SWT 10

*

RBW 30 kHz

VBW 300 kHz

Ref -12.3 dBm

*

Att

10 dB

s

Ref -12.8 dBm

-20

*

Att

10 dB

SWT 10 s

-20

-30

-40

-50

-60

-70

-80

-90

-100

4x Interpolation, 0 dBFS

-30

-40

-50

-60

-70

-80

f

= 737.28 MSPS,

f

= 737.28 MSPS,

A

DAC

OUT

DAC

OUT

f

= 70 MHz

f

= 153.6 MHz

1

RM

*

1

RM

*

CLRWR

-90

NOR

-100

-110

-120

-110

-120

Center 70 MHz

2.55 MHz/

Span 25.5 MHz

Center 153.6 MHz

2.55 MHz/

Span 25.5 MHz

T x C h a n n e l

W - C D M A 3 G P P F W D

T x C h a n n e l

W - C D M A 3 G P P F W D

B a n d w i d t h

3 . 8 4 M H z

B a n d w i d t h

3 . 8 4 M H z

P o w e r

- 7 . 7 1 d B m

P o w e r

- 8 . 0 7 d B m

A d j a c e n t C h a n n e l

B a n d w i d t h

A d j a c e n t C h a n n e l

B a n d w i d t h

L o w e r

U p p e r

- 8 2 . 2 0 d B

- 8 2 . 0 7 d B

L o w e r

U p p e r

- 8 0 . 6 9 d B

- 8 1 . 0 0 d B

3 . 8 4 M H z

M H z

3 . 8 4 M H z

M H z

S p a c i n g

5

S p a c i n g

5

A l t e r n a t e C h a n n e l

B a n d w i d t h

A l t e r n a t e C h a n n e l

B a n d w i d t h

L o w e r

U p p e r

- 8 6 . 1 1 d B

- 8 5 . 8 6 d B

L o w e r

U p p e r

- 8 4 . 0 7 d B

- 8 4 . 1 6 d B

3 . 8 4 M H z

1 0 M H z

3 . 8 4 M H z

1 0 M H z

S p a c i n g

Figure 21. SINGLE CARRIER W-CDMA TEST MODEL 1

Figure 22. SINGLE CARRIER W-CDMA TEST MODEL 1

*

RBW 30 kHz

*

RBW 30 kHz

VBW 300 kHz

Ref -17.9 dBm

-20

*

Att

10 dB

SWT 10 s

Ref -17.4 dBm

-20

*

Att

10 dB

SWT 10 s

4x Interpolation, 0 dBFS

-30

-40

-50

-60

-70

-80

-30

-40

-50

-60

-70

-80

-90

f

= 737.28 MSPS,

f

= 737.28 MSPS,

A

DAC

OUT

A

DAC

OUT

f

= 153.6 MHz

f

= 70 MHz

1

RM *

1

RM

*

CLRWR

-90

NOR

-100

-110

-120

Center 153.6 MHz

3.5 MHz/

Span 35 MHz

Center 70 MHz

3.5 MHz/

Span 35 MHz

T x C h a n n e l

W - C D M A 3 G P P F W D

T x C h a n n e l

W - C D M A 3 G P P F W D

B a n d w i d t h

1 0 M H z

B a n d w i d t h

1 0 M H z

P o w e r

- 8 . 8 9 d B m

P o w e r

- 8 . 5 0 d B m

A d j a c e n t C h a n n e l

B a n d w i d t h

A d j a c e n t C h a n n e l

B a n d w i d t h

L o w e r

U p p e r

- 7 8 . 2 1 d B

- 7 8 . 1 2 d B

L o w e r

U p p e r

- 7 9 . 6 4 d B

- 8 0 . 0 5 d B

1 0 M H z

S p a c i n g

1 0 . 5 M H z

S p a c i n g

1 0 . 5 M H z

Figure 23. 10MHZ SINGLE CARRIER LTE

Figure 24. 10MHZ SINGLE CARRIER LTE

*

RBW 30 kHz

VBW 300 kHz

*

RBW 30 kHz

VBW 300 kHz

Ref -19 dBm

*

Att

10 dB

SWT 10 s

Ref -19.6 dBm

*

Att

10 dB

SWT 10 s

4x Interpolation, 0 dBFS

= 737.28 MSPS,

2x Interpolation, 0 dBFS

-30

-40

f

= 492.52 MSPS,

A

-40 DAC

A

DAC

OUT

f

-50

= 70 MHz

f

= 153.6 MHz

-50

OUT

1

RM *

1

RM

*

-60

CLRWR

-70

-80

-90

NOR

-100

-110

-120

-100

-110

-120

Center 70 MHz

6.5 MHz/

Span 65 MHz

Center 153.6 MHz

6.5 MHz/

Span 65 MHz

T x Ch a n n el

W - C D MA 3 G PP F W D

T x Ch an ne l

W -C DM A 3 GP P FW D

B a n dw i d t h

2 0 M Hz

B an dw id th

20 M Hz

P o w e r

- 7 . 3 8 d B m

P o w e r

- 8 . 0 2 d B m

A d j ac e n t C h a n ne l

B a n dw i d t h

A dj ac en t Ch a nn el

B an dw id th

L o w e r

U p p e r

- 7 7 . 2 8 d B

- 7 7 . 0 7 d B

L o w e r

U p p e r

- 7 3 . 4 1 d B

- 7 3 . 5 4 d B

2 0 M Hz

20 M Hz

S p a ci n g

2 0. 5 M Hz

S pa ci ng

20 . 5 M Hz

Figure 25. 20MHZ SINGLE CARRIER LTE

Figure 26. 20MHZ SINGLE CARRIER LTE

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TYPICAL CHARACTERISTICS (continued)

1200

1000

800

350

300

250

200

150

100

50

2x

4x

2x

600

1x

4x

400

QMC

Mixer

200

0

Mixer

1x

QMC

0

100 200 300 400 500 600 700 800 900

- MSPS

0

100 200 300 400 500 600 700 800 900

- MSPS

f

DAC

Figure 27. POWER vs f_DAC

Figure 28. DVDD18 vs f_DAC

80

70

60

50

40

30

20

10

0

40

35

30

25

20

15

10

5

Mixer On

Mixer Off

0

100 200 300 400 500 600 700 800 900

- MSPS

0

100 200 300 400 500 600 700 800 900

f

- MSPS

DAC

Figure 29. DACVDD18 vs f_DAC

Figure 30. CLKVDD18 vs f_DAC

16

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TYPICAL CHARACTERISTICS (continued)

200

180

160

140

120

100

80

60

40

20

0

100 200 300 400 500 600 700 800 900

- MSPS

f

DAC

Figure 31. AVDD33 vs f_DAC

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FUNCTIONAL DESCRIPTION

DEFINITION OF SPECIFICATIONS

Adjacent Carrier Leakage Ratio (ACLR): Defined for a 3.84Mcps 3GPP W-CDMA input signal measured in a

3.84MHz bandwidth at a 5MHz offset from the carrier with a 12dB peak-to-average ratio.

Analog and Digital Power Supply Rejection Ratio (APSSR, DPSSR): Defined as the percentage error in the

ratio of the delta IOUT and delta supply voltage normalized with respect to the ideal IOUT current.

Differential Nonlinearity (DNL): Defined as the variation in analog output associated with an ideal 1 LSB

change in the digital input code.

Gain Drift: Defined as the maximum change in gain, in terms of ppm of full-scale range (FSR) per °C, from the

value at ambient (25°C) to values over the full operating temperature range.

Gain Error: Defined as the percentage error (in FSR%) for the ratio between the measured full-scale output

current and the ideal full-scale output current.

Integral Nonlinearity (INL): Defined as the maximum deviation of the actual analog output from the ideal output,

determined by a straight line drawn from zero scale to full scale.

Intermodulation Distortion (IMD3, IMD): The two-tone IMD3 or four-tone IMD is defined as the ratio (in dBc) of

the worst 3rd-order (or higher) intermodulation distortion product to either fundamental output tone.

Offset Drift: Defined as the maximum change in DC offset, in terms of ppm of full-scale range (FSR) per °C,

from the value at ambient (25°C) to values over the full operating temperature range.

Offset Error: Defined as the percentage error (in FSR%) for the ratio between the measured mid-scale output

current and the ideal mid-scale output current.

Output Compliance Range: Defined as the minimum and maximum allowable voltage at the output of the

current-output DAC. Exceeding this limit may result reduced reliability of the device or adversely affecting

distortion performance.

Reference Voltage Drift: Defined as the maximum change of the reference voltage in ppm per degree Celsius

from value at ambient (25°C) to values over the full operating temperature range.

Spurious Free Dynamic Range (SFDR): Defined as the difference (in dBc) between the peak amplitude of the

output signal and the peak spurious signal.

Signal to Noise Ratio (SNR): Defined as the ratio of the RMS value of the fundamental output signal to the

RMS sum of all other spectral components below the Nyquist frequency, including noise, but excluding the first

six harmonics and dc.

18

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REGISTER DESCRIPTIONS

Table 1. Register Map

(MSB)

Bit 7

(LSB)

Bit 0

Name

Address

Default

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

CONFIG0

CONFIG1

CONFIG2

0x00

0x01

0x02

0x70

0x11

0x00

reserved

fifo_ena

fifo_reset_ena multi_sync_ena alarm_out_ena

alarm_pol

iotest_ena

unused

mixer_func(1:0)

unused

qmc_offset_ena qmc_correct_ena

fir0_ena

sif_sync

fir1_ena

unused

twos

unused

sif_sync_ena

output_delay(1:0)

alarm_

2away_ena

CONFIG3

0x03

0x10

64cnt_ena

unused

fifo_offset(2:0)

alarm_ 1away_ena

CONFIG4

CONFIG5

CONFIG6

0x04

0x05

0x06

0xFF

N/A

coarse_daca(3:0)

coarse_dacb(3:0)

tempdata(7:0)

0x00

unused

alarm_mask(6:0)

alarm_from_

zerochk

alarm_fifo_

collision

alarm_from_

iotest

alarm_fifo_

CONFIG7

0x07

0x00

reserved

unused

alarm_fifo_ 1away

2away

CONFIG8

CONFIG9

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x00

0x7A

0xB6

0xEA

0x45

0x1A

0x16

0xAA

0xC6

0x24

iotest_results(7:0)

iotest_pattern0(7:0)

iotest_pattern1(7:0)

iotest_pattern2(7:0)

iotest_pattern3(7:0)

iotest_pattern4(7:0)

iotest_pattern5(7:0)

iotest_pattern6(7:0)

iotest_pattern7(7:0)

CONFIG10

CONFIG11

CONFIG12

CONFIG13

CONFIG14

CONFIG15

CONFIG16

CONFIG17

reserved

bequalsa

reserved

aequalsb

reserved

clk_alarm_mask

reserved

tx_off_mask

reserved

clk_alarm_ena

clkdiv_sync_ena

multi_sync_sel

tx_off_ena

unused

rev

daca_

complement

dacb_

complement

CONFIG18

0x12

0x02

CONFIG19

CONFIG20

CONFIG21

CONFIG22

CONFIG23

CONFIG24

CONFIG25

CONFIG26

CONFIG27

CONFIG28

CONFIG29

CONFIG30

CONFIG31

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x00

0x83

0x00

0x24

0x52

unused

qmc_offseta(7:0)

qmc_offsetb(7:0)

qmc_offseta(12:8)

qmc_offsetb(12:8)

unused

sif4_ena

sleepa

unused

clkpath_sleep_a

reserved

unused

clkpath_sleep_b

reserved

tsense_ena

clkrecv_sleep

reserved

sleepb

reserved

extref_ena

reserved

unused

qmc_gaina(7:0)

reserved

qmc_gainb(7:0)

qmc_phase(7:0)

qmc_phase(9:8)

clk_alarm tx_off

qmc_gaina(10:8)

qmc_gainb(10:8)

version(5:0)

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Register name: CONFIG0 – Address: 0x00, Default = 0x70

Register

www.ti.com

Default

Value

Address

Bit

Name

Function

Name

CONFIG0

0x00

7

6

qmc_offset_ena When asserted the DAC offset correction is enabled.

0

1

fifo_ena

When asserted the FIFO is enabled. When the FIFO is bypassed

DACCCLKP/N and DATACLKP/N must be aligned to within t_align.

5

4

fifo_reset_ena

Allows the FRAME input to act as a FIFO write reset when asserted.

multi_sync_ena Allows the FRAME or OSTR signals to be used as a sync signal when

asserted. This selection is determined by multi_sync_sel in register

CONFIG19.

1

0

3

2

alarm_out_ena

When asserted the ALARM_SDO pin becomes an output. The functionality

of this pin is controlled by the CONFIG6 alarm_mask setting.

alarm_pol

This bit changes the polarity of the ALARM signal. (0=negative logic,

1=positive logic)

0

1:0

mixer_func(1:0) Controls the function of the mixer block.

00

Mode

Normal

mixer_func(1:0)

00

01

10

11

High Pass (Fs/2)

Fs/4

–Fs/4

Register name: CONFIG1 – Address: 0x01, Default = 0x11

Register

Name

Default

Value

Address

Bit

Name

Function

When asserted the QMC offset correction circuitry is enabled.

CONFIG1

0x01

7

6

5

4

qmc_offset_ena

0

qmc_correct_ena When asserted the QMC phase and gain correction circuitry is enabled.

fir0_ena

fir1_ena

When asserted FIR0 is activated enabling 2x interpolation.

When asserted FIR1 is activated enabling 4x interpolation. fir0_ena must

be set to '1' for 4x interpolation.

1

3

2

1

0

Unused

iotest_ena

Unused

twos

Reserved for factory use.

0

When asserted enables the data pattern checker operation.

Reserved for factory use.

When asserted the inputs are expected to be in 2's complement format.

When de-asserted the input format is expected to be offset-binary.

1

Register name: CONFIG2 – Address: 0x02, Default = 0x00

Register

Name

Default

Value

Address

Bit

Name

Unused

Function

CONFIG2

0x02

7

6

5

Reserved for factory use.

0

Unused

Serial interface created sync signal. Set to '1' to cause a sync and then

clear to '0' to remove it.

sif_sync

0

4

When asserted this bit allows the SIF sync to be used. Normal FIFO_ISTR

signals are ignored.

sif_sync_ena

3

2

Unused

Reserved for factory use.

0

1:0

output_delay(1:0) Delays the output to the DACs from 0 to 3 DAC clock cycles.

00

20

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Register name: CONFIG3 – Address: 0x03, Default = 0x10

Register

Name

Default

Value

Address

Bit

Name

64cnt_ena

Function

CONFIG1

0x03

7

This enables resetting the alarms after 64 good samples with the goal of

removing unnecessary errors. For instance, when checking setup/hold

through the pattern checker test, there may initially be errors. Setting this

bit removes the need for a SIF write to clear the alarm register.

0

6

5

Unused

Reserved for factory use.

0

Unused

4:2

fifo_offset(2:0)

When the FIFO is reset, this is the value loaded into the FIFO read

pointer. With this value the initial difference between write and read

pointers can be controlled. This may be helpful in controlling the delay

through the device.

100

1

0

alarm_2away_ena When asserted alarms from the FIFO that represent the write and read

pointers being 2 away are enabled.

0

alarm_1away_ena When asserted alarms from the FIFO that represent the write and read

pointers being 1 away are enabled.

Register name: CONFIG4 – Address: 0x04, Default = 0xFF

Register

Name

Default

Value

Address

Bit

Name

Function

CONFIG4

0x04

7:4

coarse_daca(3:0)

Scales the DACA output current in 16 equal steps.

1111

V_EXTIO

´ (coarse_daca/b + 1)

Rbias

3:0

coarse_dacb(3:0)

Scales the DACB output current in 16 equal steps.

1111

Register name: CONFIG5 – Address: 0x05, READ ONLY

Register

Name

Default

Value

Address

Bit

Name

Function

CONFIG5

0x05

7:0

tempdata(7:0)

This is the output from the chip temperature sensor. The value of this

register in two’s complement format represents the temperature in

degrees Celsius. This register must be read with a minimum SCLK

period of 1µs. (Read Only)

N/A

Register name: CONFIG6 – Address: 0x06, Default = 0x00

Register

Name

Default

Value

Address

Bit

Name

Function

CONFIG6

0x06

7

Unused

alarm_mask(6:0)

Reserved for factory use.

0

6:0

These bits control the masking of the alarm outputs. This means that the

ALARM_SDO pin will not be asserted if the appropriate bit is set. The

alarm will still show up in the CONFIG7 bits. (0=not masked, 1=

masked).

0000000

alarm_mask

Masked Alarm

alarm_from_zerochk

alarm_fifo_collision

reserved

6

5

4

3

2

1

0

alarm_from_iotest

not used (expansion)

alarm_fifo_2away

alarm_fifo_1away

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Register name: CONFIG7 – Address: 0x07, Default = 0x00 (WRITE TO CLEAR)

Register

Name

Default

Value

Address

Bit

Name

Unused

Function

CONFIG7

0x07

7

6

Reserved for factory use.

0

alarm_from_zerochk When this bit is asserted the FIFO write pointer has an all zeros

pattern in it. Since this pointer is a shift register, all zeros will cause

the input point to be stuck until the next sync. This alarm allows

checking for this condition.

5

4

3

alarm_fifo_collision

Reserved

Alarm occurs when the FIFO pointers over/under run each other.

When asserted the chip does 2X interpolation of the data.

0

alarm_from_iotest

This is asserted when the input data pattern does not match the

pattern in the iotest_pattern registers.

2

1

Unused

When asserted enables the data pattern checker operation.

0

alarm_fifo_2away

Alarm occurs with the read and write pointers of the FIFO are within 2

addresses of each other.

0

alarm_fifo_1away

Alarm occurs with the read and write pointers of the FIFO are within 1

address of each other.

0

Register name: CONFIG8 – Address: 0x08, Default = 0x00 (WRITE TO CLEAR)

Register

Name

Default

Value

Address

Bit

Name

Function

CONFIG8

0x08

7:0

iotest_results(7:0)

The values of these bits tell which bit in the word failed during the

pattern checker test.

0x00

Register name: CONFIG9 – Address: 0x09, Default = 0x7A

Register

Name

Default

Value

Address

Bit

Name

Function

CONFIG9

0x09

7:0

iotest_pattern0(7:0) This is dataword0 in the IO test pattern. It is used with the seven other

words to test the input data.

0x7A

Register name: CONFIG10 – Address: 0x0A, Default = 0xB6

Register

Name

Default

Value

Address

Bit

Name

Function

CONFIG10

0x0A

7:0

iotest_pattern1(7:0) This is dataword1 in the IO test pattern. It is used with the seven other

words to test the input data.

0xB6

Register name: CONFIG11 – Address: 0x0B, Default = 0xEA

Register

Name

Default

Value

Address

Bit

Name

Function

CONFIG11

0x0B

7:0

iotest_pattern2(7:0) This is dataword2 in the IO test pattern. It is used with the seven other

words to test the input data.

0xEA

Register name: CONFIG12 – Address: 0x0C, Default = 0x00

Register

Name

Default

Value

Address

Bit

Name

Function

CONFIG12

0x0C

7:0

iotest_pattern3(7:0) This is dataword3 in the IO test pattern. It is used with the seven other

words to test the input data.

0x45

Register name: CONFIG13 – Address: 0x0D, Default = 0x1A

Register

Name

Default

Value

Address

Bit

Name

Function

CONFIG13

0x0D

7:0

iotest_pattern4(7:0) This is dataword4 in the IO test pattern. It is used with the seven other

words to test the input data.

0x1A

22

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Register name: CONFIG14 – Address: 0x0E, Default = 0x16

Register

Name

Default

Value

Address

Bit

Name

Function

CONFIG14

0x0E

7:0

iotest_pattern5(7:0) This is dataword5 in the IO test pattern. It is used with the seven other

words to test the input data.

0x16

Register name: CONFIG15 – Address: 0x0F, Default = 0xAA

Register

Name

Default

Value

Address

Bit

Name

Function

CONFIG15

0x0F

7:0

iotest_pattern6(7:0) This is dataword6 in the IO test pattern. It is used with the seven other

words to test the input data.

0xAA

Register name: CONFIG16 – Address: 0x10, Default = 0xC6

Register

Name

Default

Value

Address

Bit

Name

Function

CONFIG16

0x10

7:0

iotest_pattern7(7:0) This is dataword7 in the IO test pattern. It is used with the seven other

words to test the input data.

0XC6

Register name: CONFIG17 – Address: 0x11, Default = 0x24

Register

Name

Default

Value

Address

Bit

Name

Reserved

Function

CONFIG17

0x11

7

6

5

4

Reserved for factory use.

0

1

Reserved

clk_alarm_mask

This bit controls the masking of the clock monitor alarm. This means

that the ALARM_SDO pin will not be asserted. The alarm will still show

up in the clk_alarm bit. (0=not masked, 1= masked).

0

3

This bit control the masking of the transmit enable alarm. This means

that the ALARM_SDO pin will not be asserted. The alarm will still show

up in the tx_off bit. (0=not masked, 1= masked).

tx_off_mask

2

1

0

Reserved

Reserved for factory use.

1

0

clk_alarm_ena

tx_off_ena

When asserted the DATACLK monitor alarm is enabled.

When asserted a clk_alarm event will automatically disable the DAC

outputs by setting them to midscale.

0

Register name: CONFIG18 – Address: 0x12, Default = 0x02

Register

Name

Default

Value

Address

Bit

Name

Reserved

Function

CONFIG18

0x12

7:5

4

Reserved for factory use.

000

0

Reserved

3

When asserted the output to the DACA is complemented. This allows to

effectively change the + and – designations of the LVDS data lines.

daca_complement

0

2

1

dacb_complement When asserted the output to the DACB is complemented. This allows to

effectively change the + and – designations of the LVDS data lines.

Enables the syncing of the clock divider using the OSTR signal or the

FRAME signal passed through the FIFO. This selection is determined

by multi_sync_sel in register CONFIG19. Syncing of the clock divider

should be done only during device initialization.

clkdiv_sync_ena

1

0

Unused

Reserved for factory use.

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Register name: CONFIG19 – Address: 0x13, Default = 0x00

Register

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Default

Value

Address

Bit

Name

Function

Name

CONFIG19

0x13

7

6

5

4

3

2

1

bequalsa

When asserted the DACA data is driven onto DACB.

When asserted the DACB data is driven onto DACA.

Reserved for factory use.

0

aequalsb

Reserved

Unused

Reserved for factory use.

Unused

Reserved for factory use.

Unused

Reserved for factory use.

multi_sync_sel

Selects the signal source for multiple device and clock divider

synchronization.

multi_sync_sel

Sync Source

OSTR

0

1

FRAME through FIFO handoff

0

rev

Reverse the input bits for the data word. MSB becomes LSB.

0

Register name: CONFIG20 – Address: 0x14, Default = 0x00 (CAUSES AUTOSYNC)

Register

Name

Default

Value

Address

Bit

Name

Function

CONFIG20

0x14

7:0

qmc_offseta(7:0)

Lower 8 bits of the DAC A offset correction. The offset is measured in

DAC LSBs. Writing this register causes an autosync to be

generated. This loads the values of all four qmc_offset registers

(CONFIG20-CONFIG23) into the offset block at the same time.

When updating the offset values CONFIG20 should be written last.

Programming any of the other three registers will not affect the

offset setting.

0X00

Register name: CONFIG21 – Address: 0x15, Default = 0x00

Register

Name

Default

Value

Address

Bit

Name

Function

CONFIG21

0x15

7:0

qmc_offsetb(7:0)

Lower 8 bits of the DAC B offset correction. The offset is measured in

DAC LSBs.

0X00

Register name: CONFIG22 – Address: 0x16, Default = 0x00

Register

Name

Default

Value

Address

Bit

Name

Function

CONFIG22

0x16

7:3

2

qmc_offseta(12:8) Upper 5 bits of the DAC A offset correction.

00000

Unused

Reserved for factory use.

0

1

0

Register name: CONFIG23 – Address: 0x17, Default = 0x00

Register

Name

Default

Value

Address

Bit

Name

Function

CONFIG23

0x17

7:3

2

qmc_offsetb(12:8) Upper 5 bits of the DAC B offset correction.

00000

0

sif4_ena

When asserted the SIF interface becomes a 4 pin interface. The

ALARM pin is turned into a dedicated output for the reading of data.

1

clkpath_sleep_a

When asserted puts the clock path through DAC A to sleep. This is

useful for sleeping individual DACs. Even if the DAC is asleep the clock

needs to pass through it for the logic to work. However, if the chip is

being put into a power down mode, then all parts of the DAC can be

turned off.

0

clkpath_sleep_b

When asserted puts the clock path through DAC B to sleep.

24

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Register name: CONFIG24 – Address: 0x18, Default = 0x83

Register

Name

Default

Value

Address

Bit

Name

tsense_ena

Function

CONFIG24

0x18

7

6

Turns on the temperature sensor when asserted.

1

When asserted the clock input receiver gets put into sleep mode. This

also affects the OSTR receiver.

clkrecv_sleep

0

5

4

3

2

1

0

Unused

Reserved

sleepb

Reserved for factory use.

0

1

Reserved for factory use.

When asserted DACB is put into sleep mode.

When asserted DACA is put into sleep mode.

Reserved for factory use.

sleepa

Reserved

Reserved for factory use.

Register name: CONFIG25 – Address: 0x19, Default = 0x00

Register

Name

Default

Value

Address

Bit

Name

Reserved

Function

CONFIG25

0x19

7:3

2

Turns on the temperature sensor when asserted.

00000

0

extref_ena

Allows the device to use an external reference or the internal

reference. (0=internal, 1=external)

1

0

Reserved

Reserved for factory use.

0

Register name: CONFIG26 – Address: 0x1a, Default = 0x00

Register

Name

Default

Value

Address

Bit

Name

Reserved

Function

CONFIG26

0x1A

7:6

5:4

3

Reserved for factory use.

00

0

Reserved

Unused

2:0

Reserved

000

Register name: CONFIG27 – Address: 0x1b, Default = 0x00 (CAUSES AUTOSYNC)

Register

Name

Default

Value

Address

Bit

Name

Function

CONFIG27

0x1B

7:0

qmc_gaina(7:0)

Lower 8 bits of the 11-bit DAC A QMC gain word. The upper 3 bits are

located in the CONFIG30 register. The full 11-bit qmc_gaina(10:0)

value is formatted as UNSIGNED with a range of 0 to 1.9990 and a

default gain of 1. The implied decimal point for the multiplication is

between bits 9 and 10. Writing this register causes an autosync to

be generated. This loads the values of all four qmc_phase/gain

registers (CONFIG27-CONFIG30) into the QMC block at the same

time. When updating the QMC phase and/or gain values

CONFIG27 should be written last. Programming any of the other

three registers will not affect the QMC settings.

0X00

Register name: CONFIG28 – Address: 0x1C, Default = 0x00

Register

Name

Default

Value

Address

Bit

Name

Function

CONFIG28

0x1C

7:0

qmc_gainb(7:0)

Lower 8 bits of the 11-bit DAC B QMC gain word. The upper 3 bits are

located in the CONFIG30 register. Refer to CONFIG27 for formatting.

0X00

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Register name: CONFIG29 – Address: 0x1D, Default = 0x00

Register

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Default

Value

Address

Bit

Name

Function

Name

CONFIG29

0x1D

7:0

qmc_phase(7:0)

Lower 8-bits of the 10-bit QMC phase word. The upper 2 bits are in

the CONFIG30 register. The full 10-bit qmc_phase(9:0) word is

formatted as two's complement and scaled to occupy a range of

–0.125 to 0.12475 (note this value does not correspond to degrees)

and a default phase correction of 0. To accomplish QMC phase

correction, this value is multiplied by the current 'Q' sample, then

summed into the ‘I’ sample.

0X00

Register name: CONFIG30 – Address: 0x1E, Default = 0x24

Register

Name

Default

Value

Address

Bit

Name

Function

CONFIG30

0x1E

7:6

5:3

2:0

qmc_phase(9:8)

qmc_gaina(10:8)

qmc_gainb(10:8)

Upper 2 bits of qmc_phase. Defaults to zero.

Upper 3 bits of qmc_gaina. Defaults to unity gain.

Upper 3 bits of qmc_gainb. Defaults to unity gain.

00

100

Register name: VERSION31 – Address: 0x1F, Default = 0x52 (PARTIAL READ ONLY)

Register

Name

Default

Value

Address

Bit

Name

clk_alarm

Function

VERSION31

0x1F

7

This bit is set to '1' when DATACLK is stopped for 4 clock cycles.

Once set, the bit needs to be cleared by writing a '0'.

0

6

tx_off

This bit is set to '1' when the clk_alarm is triggered. When set the

DAC outputs are forced to mid-level. Once set, the bit needs to be

cleared by writing a '0'.

0

5:0

version(5:0)

A hardwired register that contains the version of the chip. (Read

Only)

010010

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SERIAL INTERFACE

The serial port of the DAC3283 is a flexible serial interface which communicates with industry standard

microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the

operating modes of DAC3283. It is compatible with most synchronous transfer formats and can be configured as

a 3 or 4 pin interface by sif4_ena in register CONFIG23. In both configurations, SCLK is the serial interface input

clock and SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data in

and data out. For 4 pin configuration, SDIO is data in only and ALARM_SDO is data out only. Data is input into

the device with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.

Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low for 2 to 5 bytes,

depending on the data length to be transferred (1–4 bytes). The first frame byte is the instruction cycle which

identifies the following data transfer cycle as read or write, how many bytes to transfer, and what address to

transfer the data. Table 2 indicates the function of each bit in the instruction cycle and is followed by a detailed

description of each bit. Frame bytes 2 to 5 comprise the data transfer cycle.

Table 2. Instruction Byte of the Serial Interface

MSB

7

LSB

0

Bit

6

5

4

3

2

1

Description

R/W

N1

N0

A4

A3

A2

A1

A0

R/W

[N1:N0]

Identifies the following data transfer cycle as a read or write operation. A high indicates a read

operation from DAC3283 and a low indicates a write operation to DAC3283.

Identifies the number of data bytes to be transferred per Table 3. Data is transferred MSB first.

Table 3. Number of Transferred Bytes Within One

Communication Frame

N1

0

N0

0

Description

Transfer 1 Byte

Transfer 2 Bytes

Transfer 3 Bytes

Transfer 4 Bytes

0

1

0

1

[A4:A0]

Identifies the address of the register to be accessed during the read or write operation. For

multi-byte transfers, this address is the starting address. Note that the address is written to the

DAC3283 MSB first and counts down for each byte.

Figure 32 shows the serial interface timing diagram for a DAC3283 write operation. SCLK is the serial interface

clock input to DAC3283. Serial data enable SDENB is an active low input to DAC3283. SDIO is serial data in.

Input data to DAC3283 is clocked on the rising edges of SCLK.

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Instruction Cycle

Data Transfer Cycle

SDENB

SCLK

SDIO

rwb

N1

N0

-

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

t_S(SDENB)

t_SCLK

SDENB

SCLK

SDIO

t_SCLKL

t_SCLKH

t_H(SDIO)

t_S(SDIO)

Figure 32. Serial Interface Write Timing Diagram

Figure 33 shows the serial interface timing diagram for a DAC3283 read operation. SCLK is the serial interface

clock input to DAC3283. Serial data enable SDENB is an active low input to DAC3283. SDIO is serial data in

during the instruction cycle. In 3 pin configuration, SDIO is data out from DAC3283 during the data transfer

cycle(s), while ALARM_SDO is in a high-impedance state. In 4 pin configuration, ALARM_SDO is data out from

DAC3283 during the data transfer cycle(s). At the end of the data transfer, ALARM_SDO will output low on the

final falling edge of SCLK until the rising edge of SDENB when it will 3-state.

Instruction Cycle

Data Transfer Cycle

SDENB

SCLK

SDIO

rwb

N1

N0

-

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

3-pin interface

4-pin interface

ALARM_

SDO

SDENB

SCLK

SDIO or

ALARM_SDO

Data n

Data n-1

t (Data)

d

Figure 33. Serial Interface Read Timing Diagram

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DATA INTERFACE

The DAC3283 has a single 8-bit LVDS bus that accepts dual, 16-bit data input in byte-wide format. Data into the

DAC3283 is formatted according to the diagram shown in Figure 34 where index 0 is the data LSB and index 15

is the data MSB. The data is sampled by DATACLK, a double data rate (DDR) clock.

The FRAME signal is required to indicate the beginning of a frame. The frame signal can be either a pulse or a

periodic signal where the frame period corresponds to 8 samples. The pulse-width (t_(FRAME)) needs to be at least

equal to ½ of the DATACLK period. FRAME is sampled by a rising edge in DATACLK.

The setup and hold requirements listed in the specifications tables must be met to ensure proper sampling.

SAMPLE 0

SAMPLE 1

I

Q

I

Q

[15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0]

Q

1

0

1

D[7:0]P/N

t_(FRAME)

FRAMEP/N

DATACLKP /N

(DDR)

Figure 34. Byte-Wide Data Transmission Format

INPUT FIFO

The DAC3283 includes a 2-channel, 16-bits wide and 8-samples deep input FIFO which acts as an elastic buffer.

The purpose of the FIFO is to absorb any timing variations between the input data and the internal DAC data

rate clock such as the ones resulting from clock-to-data variations from the data source.

Figure 35 shows a simplified block diagram of the FIFO.

Clock Handoff

Input Side

Clocked by DATACLK

Output Side

Clocked by FIFO Out Clock

(DACCLK/Interpolation Factor)

FIFO:

2 x 16-bits wide

8-samples deep

x2

Two cycles, one for I-data and another

for Q-data

Initial

Position

Sample 0

I₀[15:0], Q₀[15:0]

Data[15:8]

8-bit

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

D[7:0]

I-data, 16-bit

Q-data, 16-bit

16-bit

Sample 1

I₁[15:0], Q₁[15:0]

32-bit

FIFO I Output

Frame Align

Sample 2

I₂[15:0], Q₂[15:0]

8-bit

FIFO Q Output

16-bit

Sample 3

I₃[15:0], Q₃[15:0]

Data[7:0]

Initial

Position

Sample 4

I₄[15:0], Q₄[15:0]

FRAME

Sample 5

I₅[15:0], Q₅[15:0]

Write Pointer Reset

Read Pointer Reset

Sample 6

I₆[15:0], Q₆[15:0]

Sample 7

I₇[15:0], Q₇[15:0]

Figure 35. DAC3283 FIFO Block Diagram

Data is written to the device 8-bits at a time on the rising and falling edges of DATACLK. In order to form a

complete 32-bit wide sample (16-bit I-data and 16-bit Q-data) two DATACLK periods are required as shown in

Figure 36. Each 32-bit wide sample is written into the FIFO at the address indicated by the write pointer.

Similarly, data from the FIFO is read by the FIFO Out Clock 32-bits at a time from the address indicated by the

read pointer. The FIFO Out Clock is generated internally from the DACCLK signal and its rate is equal to

DACCLK/Interpolation. Each time a FIFO write or FIFO read is done the corresponding pointer moves to the next

address.

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The reset position for the FIFO read and write pointers is set by default to addresses 0 and 4 as shown in

Figure 35. This offset gives optimal margin within the FIFO. The default read pointer location can be set to

another value using fifo_offset(2:0) in register CONFIG3. Under normal conditions data is written-to and

read-from the FIFO at the same rate and consequently the write and read pointer gap remains constant. If the

FIFO write and read rates are different, the corresponding pointers will be cycling at different speeds which could

result in pointer collision. Under this condition the FIFO attempts to read and write data from the same address at

the same time which will result in errors and thus must be avoided.

The FRAME signal besides acting as a frame indicator can also used to reset the FIFO pointers to their initial

location. Unlike Data, the FRAME signal is latched only on the rising edges of DATACLK. When a rising edge

occurs on FRAME, the pointers will return to their original position. The write pointer is always set back to

position 0 upon reset. The read pointer reset position is determined by fifo_offset (address 4 by default).

The reset can be done periodically or only once during initialization as the pointer automatically returns to the

initial position when the FIFO has been filled. To enable a single reset, fifo_reset_ena (CONFIG0, bit 5) must be

set to 0 after initialization.

D[7:0]P/N

Q₃[15:8] Q₃[7:0] I₄[15:8]

I₄[7:0] Q₄[15:8] Q₄[7:0] I₅[15:8]

I₅[7:0] Q₅[15:8] Q₅[7:0] I₆[15:8]

I₆[7:0] Q₆[15:8] Q₆[7:0] I₇[15:8]

I₇[7:0] Q₇[15:8]

Write sample 4 to FIFO (32-bits)

Write I₄[7:0] (8-bits) to Write Q₄[7:0] (8-bits) to

DAC on falling edge

t_s(DATA)

DATACLKP /N

(DDR)

t_h(DATA)

Write I₄[15:8] (8-bits) to Write Q₄[15:8] (8-bits) to

DAC on rising edge

t_h(DATA)

DAC on rising edge

t_s(DATA)

t_h(DATA)

FRAMEP/N

Resets write pointer to position 0

Figure 36. FIFO Write Description

FIFO ALARMS

The FIFO only operates correctly when the write and read pointers are positioned properly. If either pointer over

or under runs the other, samples will be duplicated or skipped. To prevent this, register CONFIG7 can be used to

track three FIFO related alarms:

•

alarm_fifo_2away. Occurs when the pointers are within two addresses of each other.

alarm_fifo_1away. Occurs when the pointers are within one address of each other.

alarm_fifo_collision. Occurs when the pointers are equal to each other.

These three alarm events are generated asynchronously with respect to the clocks and can be accessed either

through CONFIG7 or through the ALARM_SDO pin.

FIFO MODES OF OPERATION

The DAC3283 FIFO can be completely bypassed through register CONFIG1. The register configuration for each

mode is described in Table 4.

Register

Control Bits

CONFIG1

fifo_ena, fifo_reset_ena, multi_sync_ena

Table 4. FIFO Operation Modes

CONFIG1FIFO Bits

FIFO Mode

fifo_ena

fifo_reset_ena

multi_sync_ena

Enabled

Bypass

1

0

1

X

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a) Enabled Mode

This is the recommended mode of operation for the DAC3283. In FIFO enabled mode, the FIFO is active and

can be reset continuously or only once during initialization. To reset only once fifo_reset_ena must be set to 0

after initialization.

b) Bypass Mode

In FIFO bypass mode, the FIFO block is not used. As a result the input data is handed off from the DATACLK to

the DACCLK domain without any compensation. In this mode the relationship between DATACLK and DACCLK

(t_{_align}) is critical and used as a synchronizing mechanism for the internal logic. Due to the t_{_align}constraint it is

highly recommended that a clock synchronizer device such as Texas Instruments’ CDCM7005 or CDCE62005 is

used to provide both clock inputs. In bypass mode the pointers have no effect on the data path or handoff.

DATA PATTERN CHECKER

The DAC3283 incorporates a simple pattern checker test in order to determine errors in the data interface. The

test mode is enabled by asserting iotest_ena in register CONFIG1. In test mode the analog outputs are

deactivated regardless of the state of TXENABLE.

The data pattern key used for the test is 8 words long and is specified by the contents of iotest_pattern[0:7] in

registers CONFIG9 through CONFIG16. The data pattern key can be modified by changing the contents of these

registers.

The first word in the test frame is determined by a rising edge transition in FRAMEP/N. The test mode

determines if one or more words were received incorrectly by comparing the received data against the data

pattern key. The bits in iotest_results(7:0) in register CONFIG8 indicate which words were received incorrectly.

Furthermore, an error condition will trigger the alarm_from_iotest bit in register CONFIG7. Once set, the

alarm_from_iotest bit must be reset through the serial interface to allow further testing. Alternatively, the

64cnt_ena bit in register CONFIG3 can be enabled to reset the alarms automatically after 64 good samples

without the need for a SIF write to clear the alarm.

DATACLK MONITOR

The DAC3283 incorporates a clock monitor to determine if DATACLK is present. A missing DATACLK may result

in unexpected DAC outputs. The clock monitor circuit issues two alarms if a missing DATACLK event is detected:

clk_alarm (bit 7 in register VERSION31) and tx_off (bit 6 in register VERSION31). When tx_off is set the

DAC3283 outputs are automatically disabled by setting data to mid-scale.

Both alarms are set by default to trigger the ALARM_SDO pin. This functionality can be disabled by masking the

alarms in register CONFIG17. Once set, the alarms must be reset through the serial interface by writing a 0 to

the alarm bits. The clock monitor alarms can be disabled by setting clk_alarm_ena or tx_off_ena in register

CONFIG17 to 0.

The clock monitoring function is implemented as follows:

•

Power up the device using the recommended power-up sequence.

Clear clk_alarm and tx_off by writing a 1 and then a 0.

Unmask the alarms in register CONFIG17.

In the case of an alarm event, the ALARM_SDO pin will trigger.

Read registers CONFIG7 and VERSION31 registers to determine which alarm triggered the ALARM_SDO

pin.

•

In the case clk_alarm and/or tx_off are set, a DATACLK interruption has occurred.

Re-apply DATACLK and clear clk_alarm by writing 1 and then 0.

Re-read clk_alarm to verify the clock loss event has not re-triggered the alarm.

Keep clearing and reading clk_alarm until no error is reported.

If enabled re-synchronize the FIFO.

Clear the tx_off alarm by writing 1 and the 0. This will re-enable the DAC outputs.

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FIR FILTERS

Figure 37 and Figure 38 show the magnitude spectrum response for the FIR0 and FIR1 interpolating half-band

filters where f_INis the input data rate to the FIR filter. Figure 39 and Figure 40 show the composite filter response

for 2x and 4x interpolation. The transition band for all the interpolation settings is from 0.4 to 0.6 x f_DATA(the input

data rate to the device) with < 0.002dB of pass-band ripple and > 85dB stop-band attenuation.

The filter taps for all digital filters are listed in Table 5.

20

0

-20

-40

-20

-40

-60

-80

-100

-120

-100

-120

-140

-160

-140

-160

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

f/f

IN

f/f

IN

Figure 37. Magnitude Spectrum for FIR0

Figure 38. Magnitude Spectrum for FIR1

20

0

-20

-40

-60

-80

0

-20

-40

-60

-80

-100

-120

-140

-160

-140

-160

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

f/f

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

DATA

f/f

DATA

Figure 39. 2x Interpolation Composite Response

Figure 40. 4x Interpolation Composite Response

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Table 5. FIR Filter Coefficients

FIR0

FIR1

2x Interpolating

Half-band Filter

2x Interpolating

Half-Band Filter

59 Taps

23 Taps

4

–2

0

–12

0

–12

0

17

0

28

–75

0

–58

0

–58

0

238

0

108

0

108

0

–660

0

–188

0

–188

0

2530

4096⁽¹⁾

2530

0

308

0

308

0

–483

0

–483

0

–660

0

734

0

734

0

238

0

–1091

0

–1091

0

–75

0

1607

0

1607

0

17

0

–2392

0

–2392

0

–2

3732

0

3732

0

–6681

0

–6681

0

20768

32768⁽¹⁾

20768

(1) Center taps are highlighted in BOLD.

COARSE MIXER

The DAC3283 has a coarse mixer block capable of shifting the input signal spectrum by the fixed mixing

frequencies f_S/2 or f_S/4. The coarse mixing function is built into the interpolation filters and thus FIR0 (2x

interpolation) or FIR0 and FIR1 (4x interpolation) must be enabled to use it.

Treating channels A and B as a complex vector of the form I(t) + j Q(t), where I(t) = A(t) and Q(t) = B(t), the

outputs of the coarse mixer, A_OUT(t) and B_OUT(t) are equivalent to:

A_OUT(t) = A(t)cos(2pf_CMIXt) – B(t)sin(2pf_CMIXt)

B_OUT(t) = A(t)sin(2pf_CMIXt) + B(t)cos(2pf_CMIXt)

where f_CMIXis the fixed mixing frequency selected by mixer_func(1:0). For f_S/2, +f_S/4 and –f_S/4 the above

operations result in the simple mixing sequences shown in Table 6.

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Table 6. Coarse Mixer Sequences

Mode

mixer_func(1:0)

Mixing Sequence

Normal (Low Pass, No Mixing)

00

A_OUT= { +A, +A , +A, +A }

B_OUT= { +B, +B , +B, +B }

f_S/2

01

10

11

A_OUT= { +A, –A , +A, –A }

B_OUT= { +B, -B , +B, -B }

+f_S/4

–f_S/4

A_OUT= { +A, -B , –A, +B }

B_OUT= { +B, +A , –B, –A }

A_OUT= { +A, +B , –A, –B }

B_OUT= { +B, –A , –B, +A }

(x2 Bypass)

A Data In

A Data Out

x2

FIR

x2

B Data In

B Data Out

Block Diagram

A Mix In

0

1

A Mix Out

0

1

-1

1

B Mix Out

B Mix In

0

1

-1

mixer_func(1:0)

Mix Sequencer

Figure 41. Coarse Mixers Block Diagram

The coarse mixer in the DAC3283 treats the A and B inputs as complex input data and for most mixing

frequencies produces a complex output. Only when the mixing frequency is set to f_S/2 the A and B channels can

be maintained isolated as shown in Table 6. In this case the two channels are upconverted as independent

signals. By setting the mixer to f_S/2 the interpolation filter outputs are inverted thus behaving as a high-pass filter.

Table 7. Dual-Channel Real Upconversion Options

FIR MODE

Low Pass

High Pass

INPUT FREQUENCY⁽¹⁾OUTPUT FREQUENCY⁽¹⁾SIGNAL BANDWIDTH⁽¹⁾SPECTRUM INVERTED?

0.0 to 0.4 × f_DATA

0.6 to 1.0 × f_DATA

0.4 × f_DATA

No

Yes

(1) f_DATAis the input data rate of each channel after de-interleaving.

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QUADRATURE MODULATION CORRECTION (QMC)

The Quadrature Modulator Correction (QMC) block provides a means for adjusting the gain and phase of the

complex signal. At a quadrature modulator output, gain and phase imbalances result in an undesired sideband

signal.

The block diagram for the QMC is shown in Figure 42. The QMC block contains 3 programmable parameters:

qmc_gaina(10:0), qmc_gainb(10:0) and qmc_phase(9:0).

Registers qmc_gaina(10:0) and qmc_gainb(10:0) control the I and Q path gains and are 11 bit values with a

range of 0 to approximately 2. This value is used to scale the signal range. Register qmc_phase(9:0) controls the

phase imbalance between I and Q and is a 10-bit value that ranges from –1/8 to approximately +1/8. This value

is multiplied by each Q sample then summed into the I sample path. This operation is a simplified approximation

of a true phase rotation and covers the range from –3.75 to +3.75 degrees in 1024 steps.

A write to register CONFIG27 is required to load the gain and phase values (CONFIG27-CONFIG30) into the

QMC block simultaneously. When updating the gain and/or phase values CONFIG27 should be written last.

Programming any of the other three registers will not affect the gain and phase settings.

qmc_gaina (10:0)

11

16

A Data In

A Data Out

x

S

10

qmc_phase (9:0)

x

16

B Data In

B Data Out

x

11

qmc_gainb (10:0)

Figure 42. QMC Block Diagram

DIGITAL OFFSET CONTROL

The qmc_offseta(12:0) and qmc_offsetb(12:0) values in registers CONFIG20 through CONFIG23 can be used to

independently adjust the A and B path DC offsets. Both offset values are in represented in 2s-complement format

with a range from –4096 to 4095.

Note that a write to register CONFIG20 is required to load the values of all four qmc_offset registers

(CONFIG20-CONFIG23) into the offset block simultaneously. When updating the offset values CONFIG20 should

be written last. Programming any of the other three registers will not affect the offset setting.

The offset value adds a digital offset to the digital data before digital-to-analog conversion. Since the offset is

added directly to the data it may be necessary to back off the signal to prevent saturation. Both data and offset

values are LSB aligned.

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qma_offset

{-4096, -4095, … , 4095}

13

16

A Data In

A Data Out

B Data Out

S

B Data In

13

qmb_offset

{-4096, -4095, … , 4095}

Figure 43. Digital Offset Block Diagram

TEMPERATURE SENSOR

The DAC3283 incorporates a temperature sensor block which monitors the temperature by measuring the

voltage across 2 transistors. The voltage is converted to an 8-bit digital word using a successive-approximation

(SAR) analog to digital conversion process. The result is scaled, limited and formatted as a twos complement

value representing the temperature in degrees Celsius.

The sampling is controlled by the serial interface signals SDENB and SCLK. If the temperature sensor is enabled

(tsense_ena = 1 in register CONFIG24) a conversion takes place each time the serial port is written or read. The

data is only read and sent out by the digital block when the temperature sensor is read in register CONFIG5. The

conversion uses the first eight clocks of the serial clock as the capture and conversion clock, the data is valid on

the falling eighth SCLK. The data is then clocked out of the chip on the rising edge of the ninth SCLK. No other

clocks to the chip are necessary for the temperature sensor operation. As a result the temperature sensor is

enabled even when the device is in sleep mode.

In order for the process described above to operate properly, the serial port read from CONFIG5 must be done

with an SCLK period of at least 1µs. If this is not satisfied the temperature sensor accuracy is greatly reduced.

POWER-UP SEQUENCE

The following startup sequence is recommended to power-up the DAC3283:

•

Set TXENABLE low.

Supply 1.8V to DACVDD18, DIGVDD18, CLKVDD18 and VFUSE simultaneously and 3.3V to AVDD33.

Within AVDD33 the multiple AVDD33 pins should be powered up simultaneously. The 1.8V and 3.3V supplies

can be powered up simultaneously or in any order.

There are no specific requirements on the ramp rate for the supplies.

Provide all LVPECL inputs: DACCLKP/N and if used OSTRP/N.

Program the SIF registers.

•

Provide all LVDS inputs (D[7:0]P/N, DATACLKP/N and FRAMEP/N) simultaneously.

Sync the clock dividers and FIFO. After a FRAMEP/N low-to-high transition, clock divider syncing must be

disabled by setting clkdiv_sync_ena (CONFIG18, bit 1) to 0. Optionally, disable FIFO syncing by setting

fifo_reset_ena (CONFIG0, bit 5) and multi_sync_ena (CONFIG0, bit 4) to 0. Except when in Multi-DAC

operation it is recommended to sync the DACs and their FIFO’s only once during initialization.

•

Enable transmit of data by asserting the TXENABLE pin.

SLEEP MODES

The DAC3283 features independent sleep control of each DAC (sleepa and sleepb), their corresponding clock

path (clkpath_sleep_a and clkpath_sleep_b) as well as the clock input receiver of the device (clkrecv_sleep). The

sleep control of each of these components is done through the SIF interface and is enabled by setting a 1 to the

corresponding sleep register.

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Complete power down of the device is set by setting all of these components to sleep. Under this mode the

supply power consumption is reduced to 15mW. Power-up time in this case will be in the milliseconds range.

Alternatively for those applications were power-up and power-down times are critical it is recommended to only

set the DACs to sleep through the sleepa and sleepb registers. In this case both the sleep and wake-up times

are only 90µs.

LVPECL INPUTS

Figure 44 shows an equivalent circuit for the DAC input clock (DACCLP/N) and the output strobe clock

(OSTRP/N).

CLKVDD

500 W

DACCLKP

OSTRP

Note: Input common mode level is

approximately 1/2*CLKVDD18,

or 0.9V nominal.

2 kW

DACCLKN

OSTRN

500 W

GND

Figure 44. DACCLKP/N and OSTRP/N Equivalent Input Circuit

Figure 45 shows the preferred configuration for driving the CLKIN/CLKINC input clock with a differential

ECL/PECL source.

0.1 mF

CLKIN

+

-

Differential

ECL

or

C_AC

100 W

(LV)PECL

source

CLKINC

0.1 mF

R_T

150 W

Figure 45. Preferred Clock Input Configuration with a Differential ECL/PECL Clock Source

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LVDS INPUTS

The D[7:0]P/N, DATACLKP/N and FRAMEP/N LVDS pairs have the input configuration shown in Figure 46.

Figure 47 shows the typical input levels and common-move voltage used to drive these inputs.

To Adjacent

LVDS Input

D[7:0]P,

DATACLKP,

FRAMEP

100 pF

Total

LVDS

Receiver

Ref Note (1)

D[7:0]N,

DATACLKN,

FRAMEN

Note (1): R_CENTERnode common

to the D[7:0]P/N, DATACLKP/N and

FRAMEP/N receiver inputs

To Adjacent

LVDS Input

Figure 46. D[7:0]P/N, DATACLKP/N and FRAMEP/N LVDS Input Configuration

Example

D[7:0]P,

DATACLKP,

FRAMEP

V_A

1.40 V

1.00 V

DAC3283

V_B

LVDS

Receiver

V_A,B

400 mV

0 V

V_A

V_COM=

(V_A+V_B)/2

D[7:0]N,

DATACLKN ,

FRAMEN

-400 mV

V_B

GND

1

0

Logical Bit

Equivalent

Figure 47. LVDS Data (D[7:0]P/N, DATACLKP/N, FRAMEP/N Pairs) Input Levels

Table 8. Example LVDS Data Input Levels

RESULTING

DEFERENTIAL

VOLTAGE

RESULTING

COMMON-MODE

VOLTAGE

APPLIED VOLTAGES

LOGICAL BIT BINARY

EQUIVALENT

V_A

V_B

V_A,B

V_COM

1.4 V

1.0 V

1.2 V

0.8 V

1.0 V

1.4 V

0.8 V

1.2 V

400 mV

–400 mV

400 mV

–400 mV

1.2 V

1

0

1

0

1.0 V

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CMOS DIGITAL INPUTS

Figure 48 shows a schematic of the equivalent CMOS digital inputs of the DAC3283. SDIO, SCLK and

TXENABLE have pull-down resistors while SDENB has a pull-up resistors internal to the DAC3283. See the

specification table for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to 100kΩ.

DIGVDD18

SDIO

SCLK

TXENABLE

internal

SDENB

digital in

GND

Figure 48. CMOS/TTL Digital Equivalent Input

REFERENCE OPERATION

The DAC3283 uses a bandgap reference and control amplifier for biasing the full-scale output current. The

full-scale output current is set by applying an external resistor R_BIASto pin BIASJ. The bias current I_BIASthrough

resistor R_BIASis defined by the on-chip bandgap reference voltage and control amplifier. The default full-scale

output current equals 16 times this bias current and can thus be expressed as:

IOUTFS = 16 × I_BIAS= 16 × V_EXTIO/ R_BIAS

Each DAC has a 4-bit coarse gain control via coarse_daca(3:0) and coarse_dacb (3:0) in the CONFIG4

register. Using gain control, the IOUTFS can be expressed as::

IOUTAFS = (DACA_gain + 1) × I_BIAS= (DACA_gain + 1) × V_EXTIO/ R_BIAS

IOUTBFS = (DACB_gain + 1) x I_BIAS= (DACB_gain + 1) x V_EXTIO/ R_BIAS

where V_EXTIOis the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of

1.2V. This reference is active when extref_ena = '0' in CONFIG25. An external decoupling capacitor C_EXTof

0.1µF should be connected externally to terminal EXTIO for compensation. The bandgap reference can

additionally be used for external reference operation. In that case, an external buffer with high impedance input

should be applied in order to limit the bandgap load current to a maximum of 100nA. The internal reference can

be disabled and overridden by an external reference by setting the CONFIG25 extref_ena control bit. Capacitor

C_EXTmay hence be omitted. Terminal EXTIO thus serves as either input or output node.

The full-scale output current can be adjusted from 20mA down to 2mA by varying resistor R_BIASor changing the

externally applied reference voltage. The internal control amplifier has a wide input range, supporting the

full-scale output current range of 20dB.

DAC TRANSFER FUNCTION

The CMOS DAC’s consist of a segmented array of NMOS current sinks, capable of sinking a full-scale output

current up to 20mA. Differential current switches direct the current to either one of the complementary output

nodes IOUT1 or IOUT2. (DACA = IOUTA1 or IOUTA2 and DACB = IOUTB1 or IOUTB2.) Complementary output

currents enable differential operation, thus canceling out common mode noise sources (digital feed-through,

on-chip and PCB noise), dc offsets, even order distortion components, and increasing signal output power by a

factor of two.

The full-scale output current is set using external resistor R_BIASin combination with an on-chip bandgap voltage

reference source (+1.2V) and control amplifier. Current I_BIASthrough resistor R_BIASis mirrored internally to

provide a maximum full-scale output current equal to 16 times IBIAS.

The relation between IOUT1 and IOUT2 can be expressed as:

IOUT1 = – IOUTFS – IOUT2

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Current flowing into a node is denoted as – current and current flowing out of a node as + current. Since the

output stage is a current sink the current can only flow from AVDD into the IOUT1 and IOUT2 pins. The output

current flow in each pin driving a resistive load can be expressed as:

IOUT1 = IOUTFS × (65535 – CODE) / 65536

IOUT2 = IOUTFS × CODE / 65536

where CODE is the decimal representation of the DAC data input word.

For the case where IOUT1 and IOUT2 drive resistor loads R_Ldirectly, this translates into single ended voltages

at IOUT1 and IOUT2:

VOUT1 = AVDD – | IOUT1 | × R_L

VOUT2 = AVDD – | IOUT2 | × R_L

Assuming that the data is full scale (65536 in offset binary notation) and the R_Lis 25 Ω, the differential voltage

between pins IOUT1 and IOUT2 can be expressed as:

VOUT1 = AVDD – | –0 mA | × 25 Ω = 3.3 V

VOUT2 = AVDD – | –20 mA | × 25 Ω = 2.8 V

VDIFF = VOUT1 – VOUT2 = 0.5 V

Note that care should be taken not to exceed the compliance voltages at node IOUT1 and IOUT2, which would

lead to increased signal distortion.

ANALOG CURRENT OUTPUTS

Figure 49 shows a simplified schematic of the current source array output with corresponding switches.

Differential switches direct the current of each individual NMOS current source to either the positive output node

IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the stack of

the current sources and differential switches, and is typically >300 kΩ in parallel with an output capacitance of 5

pF.

The external output resistors are referenced to an external ground. The minimum output compliance at nodes

IOUT1 and IOUT2 is limited to AVDD – 0.5 V, determined by the CMOS process. Beyond this value, transistor

breakdown may occur resulting in reduced reliability of the DAC3283 device. The maximum output compliance

voltage at nodes IOUT1 and IOUT2 equals AVDD + 0.5 V. Exceeding the minimum output compliance voltage

adversely affects distortion performance and integral non-linearity. The optimum distortion performance for a

single-ended or differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not

exceed 0.5 V.

AVDD

R

LOAD

IOUT1

LOAD

IOUT2

S(1)

S(N)

S(2)

S(2)C

S(1)C

S(N)C

...

Figure 49. Equivalent Analog Current Output

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The DAC3283 can be easily configured to drive a doubly terminated 50Ω cable using a properly selected RF

transformer. Figure 50 and Figure 51 show the 50Ω doubly terminated transformer configuration with 1:1 and 4:1

impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to be

connected to AVDD to enable a dc current flow. Applying a 20 mA full-scale output current would lead to a 0.5

V_PPfor a 1:1 transformer, and a 1 V_PPoutput for a 4:1 transformer. The low dc-impedance between IOUT1 or

IOUT2 and the transformer center tap sets the center of the ac-signal at AVDD, so the 1 V_PPoutput for the 4:1

transformer results in an output between AVDD + 0.5 V and AVDD – 0.5 V.

AVDD (3.3 V)

50 W

1 : 1

IOUT1

R_LOAD

100 W

50 W

IOUT2

50 W

AVDD (3.3 V)

Figure 50. Driving a Doubly-Terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer

AVDD (3.3 V)

100 W

4 :1

IOUT1

R_LOAD

50 W

IOUT2

100 W

AVDD (3.3 V)

Figure 51. Driving a Doubly-Terminated 50-Ω Cable Using a 4:1 Impedance Ratio Transformer

PASSIVE INTERFACE TO ANALOG QUADRATURE MODULATORS

A common application in communication systems is to interface the DAC to an IQ modulator like the TRF3703

family of modulators from Texas Instruments. The input of the modulator is generally of high impedance and

requires a specific common-mode voltage. A simple resistive network can be used to maintain 50Ω load

impedance for the DAC3283 and also provide the necessary common-mode voltages for both the DAC and the

modulator.

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V_in~ Varies

V_out~ 2.8 to 3.8 V

I1

I2

IOUTA1

IOUTA2

S

Q1

Q2

RF

IOUTB1

IOUTB2

Quadrature modulator

Figure 52. DAC to Analog Quadrature Modulator Interface

The DAC3283 has a maximum 20mA full-scale output and a voltage compliance range of AVDD ± 0.5 V. The

TRF3703 IQ modulator family can be operated at three common-mode voltages: 1.5V, 1.7V, and 3.3V.

Figure 53 shows the recommended passive network to interface the DAC3283 to the TRF3703-17 which has a

common mode voltage of 1.7V. The network generates the 3.3V common mode required by the DAC output and

1.7V at the modulator input, while still maintaining 50Ω load for the DAC.

V1

R1

I

R2

R3

DAC3283

TRF3703-17

V2

R2

/I

R1

V1

Figure 53. DAC3283 to TRF3703-17 Interface

If V1 is set to 5V and V2 is set to -5V, the corresponding resistor values are R1 = 57Ω, R2 = 80Ω, and R3 =

336Ω. The loss developed through R2 is about -1.86 dB. In the case where there is no –5V supply available and

V2 is set to 0V, the resistor values are R1 = 66Ω, R2 = 101Ω, and R3 = 107Ω. The loss with these values is

–5.76dB.

Figure 54 shows the recommended network for interfacing with the TRF3703-33 which requires a common mode

of 3.3V. This is the simplest interface as there is no voltage shift. Because there is no voltage shift there is any

loss in the network. With V1 = 5V and V2 = 0V, the resistor values are R1 = 66Ω and R3 = 208Ω.

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V1

R1

I

R3

DAC3283

TRF3703-33

V2

/I

R1

V1

Figure 54. DAC3283 to TRF3703-33 Interface

In most applications a baseband filter is required between the DAC and the modulator to eliminate the DAC

images. This filter can be placed after the common-mode biasing network. For the DAC to modulator network

shown in Figure 55, R2 and the filter load R4 need to be considered into the DAC impedance. The filter has to be

designed for the source impedance created by the resistor combination of R3 // (R2+R1). The effective

impedance seen by the DAC is affected by the filter termination resistor resulting in R1 // (R2+R3 // (R4/2)).

V1

R1

R2

I

R3

R4

V2

R2

Filter

TRF3703

DAC3283

R3

/I

R1

V1

Figure 55. DAC3283 to Modulator Interface with Filter

Factoring in R4 into the DAC load, a typical interface to the TRF3703-17 with V1 = 5V and V2 = 0V results in the

following values: R1 = 72Ω, R2 = 116Ω, R3 = 124Ω and R4 = 150Ω. This implies that the filter needs to be

designed for 75Ω input and output impedance (single-ended impedance). The common mode levels for the DAC

and modulator are maintained at 3.3V and 1.7V and the DAC load is 50Ω. The added load of the filter

termination causes the signal to be attenuated by –10.8 dB.

A filter can be implemented in a similar manner to interface with the TRF3703-33. In this case it is much simpler

to balance the loads and common mode voltages due to the absence of R2. An added benefit is that there is no

loss in this network. With V1 = 5V and V2 = 0V the network can be designed such that R1 = 115Ω, R3 = 681Ω,

and R4 = 200Ω. This results in a filter impedance of R1 // R2=100Ω, and a DAC load of R1 // R3 // (R4/2) which

is equal to 50Ω. R4 is a differential resistor and does not affect the common mode level created by R1 and R3.

The common-mode voltage is set at 3.3 V for a full-scale current of 20mA.

For more information on how to interface the DAC3283 to an analog quadrature modulator please refer to the

application reports Passive Terminations for Current Output DACs (SLAA399) and Design of Differential Filters

for High-Speed Signal Chains (SLWA053).

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43

Product Folder Link(s): DAC3283

DAC3283

SLAS693A –MARCH 2010–REVISED APRIL 2010

www.ti.com

APPLICATION INFORMATION

DIRECT CONVERSION RADIO

Refer to Figure 56 for an example Direct Conversion Radio. The DAC3283 receives an interleaved complex I/Q

baseband input data stream and increases the sample rate through interpolation by a factor of 2 or 4. By

performing digital interpolation on the input data, undesired images of the original signal can be push out of the

band of interest and more easily suppressed with analog filters.

For a Zero IF (ZIF) frequency plan, complex mixing of the baseband signal is not required. Alternatively, for a

Complex IF frequency plan the input data can be pre-placed at an IF within the bandwidth limitations of the

interpolation filters. In addition, complex mixing is available using the coarse mixer block to up-convert the signal.

The output of both DAC channels is used to produce a Hilbert transform pair and can be expressed as:

A_OUT(t) = A(t)cos(w_ct) – B(t)sin(w_ct) = m(t)

B_OUT(t) = A(t)sin(w_ct) + B(t)cos(w_ct) = m_h(t)

where m(t) and m_h(t) connote a Hilbert transform pair and w_cis the mixer frequency. The complex output is input

to an analog quadrature modulator (AQM) such as the Texas Instruments TRF3720 for a single side-band (SSB)

up conversion to RF. A passive (resistor only) interface to the AQM with an optional LC filter network is

recommended. The TRF3720 includes a VCO/PLL to generate the LO frequency. Upper single-sideband

upconversion is achieved at the output of the analog quadrature modulator, whose output is expressed as:

RF(t) = A(t)cos(w_c+ w_LO)t – B(t)sin(w_c+ w_LO)t

Flexibility is provided to the user by allowing for the selection of negative mixing frequency to produce a

lower-sideband upconversion. Note that the process of complex mixing translates the signal frequency from 0Hz

means that the analog quadrature modulator IQ imbalance produces a sideband that falls outside the signal of

interest. DC offset error in DAC and AQM signal path may produce LO feed-through at the RF output which may

fall in the band of interest. To suppress the LO feed-through, the DAC3283 provides a digital offset correction

capability for both DAC-A and DAC-B paths. In addition phase and gain imbalances in the DAC and AQM result

in a lower-sideband product. The DAC3283 offers gain and phase correction capabilities to minimize the

sideband product.

The complex IF architecture has several advantages over the real IF architecture:

•

Uncalibrated side-band suppression ~ 35dBc compared to 0dBc for real IF architecture.

Direct DAC to AQM interface – no amplifiers required

DAC 2nd Nyquist zone image is offset f_DACcompared with f_DAC– 2 x IF for a real IF architecture, reducing the

need for filtering at the DAC output.

•

Uncalibrated LO feed through for AQM is ~ 35dBc and calibration can reduce or completely remove the LO

feed through.

44

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Product Folder Link(s): DAC3283

DAC3283

www.ti.com

SLAS693A –MARCH 2010–REVISED APRIL 2010

APPLICATION INFORMATION (continued)

5V

Byte-Wide

Data

FPGA

DAC3283 DAC

100

D7P/N

D0P/N

DAC-A

DAC-B

RF OUT

FRAMEP/N

DATACLKP /N

90

0

PLL/

DLL

Div

2/4/8

100

VCO

VCTRL_IN

N-

Divider

Loop

Filter

PFD

R-

Div

/1

/4

CPOUT

Div

Clock Divider/

Distribution

TRF3720

AQM with PLL/VCO

Loop

Filter

PFD/CP

Div

CDCE62005

Clock Generator with VCO

10 MHz

OSC

Figure 56. System Diagram of Direct Conversion Radio

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45

Product Folder Link(s): DAC3283

PACKAGE OPTION ADDENDUM

www.ti.com

9-Apr-2010

PACKAGING INFORMATION

Orderable Device

DAC3283IRGZR

DAC3283IRGZT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

VQFN

RGZ

48

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

VQFN

RGZ

48

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

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型号：	DAC3283_14
厂家：	TEXAS INSTRUMENTS
描述：	Dual-Channel, 16-Bit, 800 MSPS, Digital-to-Analog Converter (DAC)
文件：	总50页 (文件大小：1447K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC3283_14 [TI]

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