DAC3171IRGCR [TI]
14 位、500MSPS 数模转换器 (DAC) | RGC | 64 | -40 to 85;
| 型号： | DAC3171IRGCR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 14 位、500MSPS 数模转换器 (DAC) | RGC | 64 | -40 to 85 转换器 数模转换器 |
| 文件： | 总57页 (文件大小：1597K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC3151
DAC3161
DAC3171
www.ti.com
SLAS959A –AUGUST 2013–REVISED AUGUST 2013
Single 14-/12-/10-Bit 500 MSPS Digital-to-Analog Converters
Check for Samples: DAC3151, DAC3161, DAC3171
1
FEATURES
APPLICATIONS
2
•
•
Single Channel
Resolution
•
Wireless Infrastructure
PA Bias, Envelope Tracking, TX
–
–
–
–
DAC3151: 10-Bit
DAC3161: 12-Bit
DAC3171: 14-Bit
•
•
•
•
Radar
Software-Defined Radio
Signal/Waveform Generators
Cable Head-End Equipment
•
•
•
Maximum Sample Rate: 500 MSPS
Pin-Compatible Family
Input Interface:
DESCRIPTION
The DAC3151/DAC3161/DAC3171 is a family of
single channel 500MSPS digital-to-analog converters
with resolutions of 10-/12-/14-bits. The family uses a
10-/12-/14-bit wide LVDS digital bus with an input
FIFO. The 14-bit DAC3171 also supports a DDR 7-bit
LVDS interface mode. FIFO input and output pointers
can be synchronized across multiple devices for
precise signal synchronization. The DAC outputs are
current sourcing and terminate to GND with a
–
–
–
Parallel LVDS Inputs
Single or Dual DDR Data Clock
Internal FIFO
•
•
•
Chip to Chip Synchronization
Power Dissipation: 375mW
Spectral Performance at 20 MHz IF
–
SNR: 76 dBFS for DAC3171; 72dBFS for
DAC3161; 62 dBFS for DAC3151
compliance
range
of
-0.5
to
1V.
DAC3151/DAC3161/DAC3171 is pin compatible with
the dual-channel, 10-/12-/14-bit, 500MSPS digital-to-
analog converter DAC3154/DAC3164/DAC3174.
–
SFDR: 78 dBc for DAC3171; 77dBc for
DAC3161; 76 dBc for DAC3151
•
•
•
Current Sourcing DACs
The device is available in a QFN-64 PowerPAD™
package is specified over the full industrial
temperature range (–40°C to 85°C).
Compliance Range: -0.5V to 1V
Package: 64 Pin QFN (9x9mm)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
DAC3151
DAC3161
DAC3171
SLAS959A –AUGUST 2013–REVISED AUGUST 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
BLOCK DIAGRAMS
DACCLKP
DACCLKN
DATACLKP
DATACLKN
DATA9P
EXTIO
BIASJ
LVPECL
LVDS
Clock Distribution
1.2 V
Reference
Programmable
Delay
LVDS
DATA9N
DACA
Gain
10
QMC
A-offset
IOUTAP
IOUTAN
10-b
DACA
10
LVDS
DATA0P
DATA0N
LVDS
SYNCP
SYNCN
ALIGNP
ALIGNN
VDDA33
Optional Input
Used for multi-DAC sync
LVPECL
Control Interface
Figure 1. DAC3151 Full Word Interface Mode
2
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Product Folder Links: DAC3151 DAC3161 DAC3171
DAC3151
DAC3161
DAC3171
www.ti.com
SLAS959A –AUGUST 2013–REVISED AUGUST 2013
DACCLKP
DACCLKN
DATACLKP
DATACLKN
DATA11P
EXTIO
LVPECL
LVDS
Clock Distribution
1.2 V
Reference
BIASJ
Programmable
Delay
LVDS
DATA11N
DACA
Gain
12
QMC
A-offset
IOUTAP
12-b
DACA
IOUTAN
12
LVDS
DATA0P
DATA0N
LVDS
SYNCP
SYNCN
ALIGNP
ALIGNN
VDDA33
Optional Input
Used for multi-DAC sync
LVPECL
Control Interface
Figure 2. DAC3161 Full Word Interface Mode
Copyright © 2013, Texas Instruments Incorporated
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DAC3151
DAC3161
DAC3171
SLAS959A –AUGUST 2013–REVISED AUGUST 2013
www.ti.com
DACCLKP
EXTIO
BIASJ
LVPECL
LVDS
Clock Distribution
1.2 V
Reference
DACCLKN
DATACLKP
DATACLKN
DATA13P
Programmable
Delay
LVDS
DATA13N
DACA
Gain
14
QMC
A-offset
IOUTAP
IOUTAN
14-b
DACA
14
LVDS
DATA0P
DATA0N
LVDS
SYNCP
SYNCN
ALIGNP
ALIGNN
VDDA33
Optional Input
Used for multi-DAC sync
LVPECL
Control Interface
Figure 3. DAC3171 Full Word Interface Mode
4
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DAC3151
DAC3161
DAC3171
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SLAS959A –AUGUST 2013–REVISED AUGUST 2013
DACCLKP
DACCLKN
DA_CLKP
DA_CLKN
DA6P
EXTIO
LVPECL
LVDS
Clock Distribution
1.2 V
Reference
BIASJ
Programmable
Delay
LVDS
DACA
Gain
QMC
A-offset
DA6N
IOUTA1
14-b
DACA
IOUTA2
7
LVDS
DA0P
DA0N
VDDA33
Control Interface
Figure 4. DAC3171 7-bit Interface Mode
Copyright © 2013, Texas Instruments Incorporated
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DAC3151
DAC3161
DAC3171
SLAS959A –AUGUST 2013–REVISED AUGUST 2013
www.ti.com
PINOUT – DAC3151
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DACCLKP
DACCLKN
CLKVDD18
ALIGNP
ALIGNN
SYNCP
SYNCN
VFUSE
(MSB) D9P
D9N
TXENABLE
ALARM
SDO
IOVDD
SDIO
SCLK
SDENB
RESETB
NC
3
4
5
6
7
8
DAC3151
9
10
11
12
13
14
15
16
NC
D8P
NC
D8N
NC
D7P
NC
D7N
NC
GND PAD (backside)
D6P
NC
D6N
NC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PIN ASSIGNMENT TABLE – DAC3151
PIN
NO.
I/O
DESCRIPTION
NAME
CONTROL/SERIAL
SCLK
43
42
44
I
I
Serial interface clock. Internal pull-down.
Serial interface clock. Internal pull-up.
SDENB
SDIO
I/O Bi-directional serial data in 3 pin mode (default). In 4-pin interface mode (register sif4_ena (config 0, bit
9)), the SDIO pin in an input only. Internal Pull-down.
SDO
46
41
O
Uni-directional serial interface data in 4 pin mode (register sif4_ena (config 0, bit 9)). The SDO pin is tri-
stated in 3-pin interface mode (default). Internal Pulldown.
RESETB
I
Serial interface reset input. Active low. Initialized internal registers during high to low transition.
Assynchronous. Internal pull-up.
ALARM
47
48
O
I
CMOS output for ALARM condition.
TXENABLE
Transmit enable active high input. TXENABLE must be high for the DATA to the DAC to be enabled.
When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored. Internal
pull-down.
SLEEP
49
I
Puts device in sleep, active high. Internal pull-down.
6
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DAC3161
DAC3171
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NAME
SLAS959A –AUGUST 2013–REVISED AUGUST 2013
PIN ASSIGNMENT TABLE – DAC3151 (continued)
PIN
I/O
DESCRIPTION
NO.
DATA INTERFACE
DATA[9:0]P/N
9/10-
19/20
22/23
26/27,
29/30,
31/32
I
LVDS input data bits for both channels. Each positive/negative LVDS pair has an internal 100 Ω
termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR) with two data
transfers per DATACKP/N clock cycle.
The data format is interleaved with channel A (rising edge) and channel B falling edge.
In the default mode (reverse bus not enabled):
DATA13P/N is most significant data bit (MSB)
DATA0P/N is most significant data bit (LSB)
DATACLKP/N
SYNCP/N
24/25
6/7
I
I
I
DDR differential input data clock. Edge to center nominal timing. Ch A rising edge, Ch B falling edge in
multiplexed output mode.
Reset the FIFO or to be used as a syncing source. These two functions are captured with the rising edge
of DATACLKP/N. The signal captured by the falling edge of DATACLKP/N.
ALIGNP/N
4/5
LVPECL FIFO output syncrhonization. This positive/negative pair is captured with the rising edge of
DACCLKP/N. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it can
be left unconnected.
OUTPUT/CLOCK
DACCLKP/N
IOUTAP/N
1/2
I
LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2.
61/60
O
A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full
scale current source and the most positive voltage on the IOUTAP pin. Similarly, a 0xFFFF data input
results in a 0 mA current source and the least positive voltage on the IOUTAP pin.
REFERENCE
EXTIO
58
57
I/O Used as external reference input when internal reference is disabled. Requires a 0.1 µF decoupling
capacitor to GND when used as reference output.
BIASJ
O
Full-scale output current bias. For 20 mA full-scale output current, connect a 960 Ω resistor to GND.
POWER SUPPLY
IOVDD
45
3
I
I
I
I
I
Supply voltage for CMOS IO’s. 1.8V – 3.3V.
1.8V clock supply
CLKVDD18
DIGVDD18
VDDA18
21, 28
50, 64
1.8V digital supply. Also supplies LVDS receivers.
Analog 1.8V supply
VDDA33
55, 56,
59
Analog 3.3V supply
VFUSE
NC
8
I
Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to
DVDD pins for normal operation.
33/34-
39/40,
51, 52,
53, 54
62, 63
Not Used. These pins can be left open or tied to GROUND in actual application use. It is recommended
to turn off pin 33-40 (register lvdsdata_ena) to save power.
Copyright © 2013, Texas Instruments Incorporated
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Product Folder Links: DAC3151 DAC3161 DAC3171
DAC3151
DAC3161
DAC3171
SLAS959A –AUGUST 2013–REVISED AUGUST 2013
www.ti.com
PINOUT – DAC3161
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DACCLKP
DACCLKN
CLKVDD18
ALIGNP
ALIGNN
SYNCP
SYNCN
VFUSE
(MSB) D11P
D11N
TXENABLE
ALARM
SDO
3
4
IOVDD
SDIO
SCLK
SDENB
RESETB
NC
5
6
7
8
DAC3161
9
10
11
12
13
14
15
16
NC
D10P
NC
D10N
NC
D9P
D0N
D9N
D0P (LSB)
D1N
GND PAD (backside)
D8P
D8N
D1P
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PIN ASSIGNMENT TABLE – DAC3161
PIN
NO.
I/O
DESCRIPTION
NAME
CONTROL/SERIAL
SCLK
43
42
44
I
I
Serial interface clock. Internal pull-down.
Serial interface clock. Internal pull-up.
SDENB
SDIO
I/O Bi-directional serial data in 3 pin mode (default). In 4-pin interface mode (register sif4_ena (config 0, bit
9)), the SDIO pin in an input only. Internal Pull-down.
SDO
46
41
O
Uni-directional serial interface data in 4 pin mode (register sif4_ena (config 0, bit 9)). The SDO pin is tri-
stated in 3-pin interface mode (default). Internal Pulldown.
RESETB
I
Serial interface reset input. Active low. Initialized internal registers during high to low transition.
Assynchronous. Internal pull-up.
ALARM
47
48
O
I
CMOS output for ALARM condition.
TXENABLE
Transmit enable active high input. TXENABLE must be high for the DATA to the DAC to be enabled.
When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored. Internal
pull-down.
SLEEP
49
I
Puts device in sleep, active high. Internal pull-down.
8
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DAC3151
DAC3161
DAC3171
www.ti.com
NAME
SLAS959A –AUGUST 2013–REVISED AUGUST 2013
PIN ASSIGNMENT TABLE – DAC3161 (continued)
PIN
I/O
DESCRIPTION
NO.
DATA INTERFACE
DATA[11:0]P/N
9/10-
19/20
22/23
26/27,
29/30-
35/36
I
LVDS input data bits for both channels. Each positive/negative LVDS pair has an internal 100 Ω
termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR) with two data
transfers per DATACKP/N clock cycle.
The data format is interleaved with channel A (rising edge) and channel B falling edge.
In the default mode (reverse bus not enabled):
DATA13P/N is most significant data bit (MSB)
DATA0P/N is most significant data bit (LSB)
DATACLKP/N
SYNCP/N
24/25
6/7
I
I
I
DDR differential input data clock. Edge to center nominal timing. Ch A rising edge, Ch B falling edge in
multiplexed output mode.
Reset the FIFO or to be used as a syncing source. These two functions are captured with the rising edge
of DATACLKP/N. The signal captured by the falling edge of DATACLKP/N.
ALIGNP/N
4/5
LVPECL FIFO output syncrhonization. This positive/negative pair is captured with the rising edge of
DACCLKP/N. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it can
be left unconnected.
OUTPUT/CLOCK
DACCLKP/N
IOUTAP/N
1/2
I
LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2.
61/60
O
A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full
scale current source and the most positive voltage on the IOUTAP pin. Similarly, a 0xFFFF data input
results in a 0 mA current source and the least positive voltage on the IOUTAP pin.
REFERENCE
EXTIO
58
57
I/O Used as external reference input when internal reference is disabled. Requires a 0.1 µF decoupling
capacitor to GND when used as reference output.
BIASJ
O
Full-scale output current bias. For 20 mA full-scale output current, connect a 960 Ω resistor to GND.
POWER SUPPLY
IOVDD
45
3
I
I
I
I
I
Supply voltage for CMOS IO’s. 1.8V – 3.3V.
1.8V clock supply
CLKVDD18
DIGVDD18
VDDA18
21, 28
50, 64
1.8V digital supply. Also supplies LVDS receivers.
Analog 1.8V supply
VDDA33
55, 56,
59
Analog 3.3V supply
VFUSE
NC
8
I
Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to
DVDD pins for normal operation.
37, 38,
39, 40,
51, 52,
53, 54,
62, 63
Not Used. These pins can be left open or tied to GROUND in actual application use. It is recommended
to turn off pin 37-40 (register lvdsdata_ena) to save power.
Copyright © 2013, Texas Instruments Incorporated
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Product Folder Links: DAC3151 DAC3161 DAC3171
DAC3151
DAC3161
DAC3171
SLAS959A –AUGUST 2013–REVISED AUGUST 2013
www.ti.com
PIN OUT – DAC3171 7-BIT INTERFACE MODE
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DACCLKP
DACCLKN
CLKVDD18
NC
TXENABLE
ALARM
SDO
IOVDD
SDIO
SCLK
SDENB
RESETB
NC
3
4
5
NC
6
DA_CLKP
DA_CLKN
VFUSE
(MSB) DA6P
DA6N
7
8
DAC3171
9
10
11
12
13
14
15
16
NC
DA5P
NC
DA5N
NC
DA4P
NC
DA4N
NC
GND PAD (backside)
DA3P
NC
DA3N
NC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PIN ASSIGNMENT TABLE – DAC3171 7-BIT INTERFACE MODE
PIN
I/O
DESCRIPTION
NAME
NO.
CONTROL/SERIAL
SCLK
43
42
44
I
I
Serial interface clock. Internal pull-down.
Serial interface clock. Internal pull-up.
SDENB
SDIO
I/O Bi-directional serial data in 3 pin mode (default). In 4-pin interface mode (register XYZ), the SDIO pin
in an input only. Internal Pull-down.
SDO
46
41
O
Uni-directional serial interface data in 4 pin mode (register XYZ). The SDO pin is tri-stated in 3-pin
interface mode (default). Internal Pulldown.
RESETB
I
Serial interface reset input. Active low. Initialized internal registers during high to low transition.
Assynchronous. Internal pull-up.
ALARM
47
48
O
I
CMOS output for ALARM condition.
TXENABLE
Transmit enable active high input. TXENABLE must be high for the DATA to the DAC to be enabled.
When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored.
Internal pull-down.
SLEEP
49
I
Puts device in sleep, active high. Internal pull-down.
10
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DAC3151
DAC3161
DAC3171
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NAME
SLAS959A –AUGUST 2013–REVISED AUGUST 2013
PIN ASSIGNMENT TABLE – DAC3171 7-BIT INTERFACE MODE (continued)
PIN
I/O
DESCRIPTION
NO.
DATA INTERFACE
DA[6:0]P/N
9/10-
19/20
22/23
I
LVDS positive input data bits for channel A. Each positive/negative LVDS pair has an internal 100 Ω
termination resistor. Data format relative to DA_CLKP/N clock is Double Data Rate (DDR) with two
data transfers per DA_CLKP/N clock cycle.
The data format is 7 MSBs (rising edge)/7 LSBs falling edge.
In the default mode (reverse bus not enabled):
D6P/N is most significant data bit (MSB)
D0P/N is most significant data bit (LSB)
DA_CLKP/N
OUTPUT/CLOCK
DACCLKP/N
IOUTAP/N
6/7
I
DDR differential input data clock for channel A. Edge to center nominal timing.
1/2
I
LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2.
61/60
O
A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a
full scale current source and the most positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data
input results in a 0 mA current source and the least positive voltage on the IOUTA1 pin. The IOUTA2
pin is the complement of IOUTA1.
REFERENCE
EXTIO
58
57
I/O Used as external reference input when internal reference is disabled. Requires a 0.1 µF decoupling
capacitor to GND when used as reference output.
BIASJ
O
Full-scale output current bias. For 20 mA full-scale output current, connect a 960 Ω resistor to GND.
POWER SUPPLY
IOVDD
45
3
Supply voltage for CMOS IO’s. 1.8V – 3.3V.
1.8V clock supply
CLKVDD18
DIGVDD18
VDDA18
21, 28
50, 64
1.8V digital supply. Also supplies LVDS receivers.
Analog 1.8V supply
VDDA33
55, 56,
59
Analog 3.3V supply
VFUSE
NC
8
Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to
DVDD pins for normal operation.
4,5,
24/25,
26/27
Not used. Pin 4 can be left open or tied to DIGVDD18, and other pins can be left open or tied to
GROUND in actual application use. It is recommended to turn off pin 24/25, 26/27, 29/30-39/40
(register lvdsdataclk_ena, lvdsdata_ena) to save power.
29/30-
39/40,
51, 52,
53, 53,
62, 63
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DAC3151
DAC3161
DAC3171
SLAS959A –AUGUST 2013–REVISED AUGUST 2013
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PINOUT – DAC3171 14-BIT INTERFACE MODE
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DACCLKP
DACCLKN
CLKVDD18
ALIGNP
ALIGNN
SYNCP
SYNCN
VFUSE
(MSB) D13P
D13N
TXENABLE
ALARM
SDO
3
4
IOVDD
SDIO
5
6
SCLK
SDENB
RESETB
D0N
7
8
DAC3171
9
10
11
12
13
14
15
16
D0P (LSB)
D1N
D12P
D12N
D1P
D11P
D2N
D11N
D2P
GND PAD (backside)
D10P
D3N
D10N
D3P
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PIN ASSIGNMENT TABLE – DAC3171 14-BIT INTERFACE MODE
PIN
NO.
I/O
DESCRIPTION
NAME
CONTROL/SERIAL
SCLK
43
42
44
I
I
Serial interface clock. Internal pull-down.
Serial interface clock. Internal pull-up.
SDENB
SDIO
I/O Bi-directional serial data in 3 pin mode (default). In 4-pin interface mode (register sif4_ena (config 0, bit
9)), the SDIO pin in an input only. Internal Pull-down.
SDO
46
41
O
Uni-directional serial interface data in 4 pin mode (register sif4_ena (config 0, bit 9)). The SDO pin is tri-
stated in 3-pin interface mode (default). Internal Pulldown.
RESETB
I
Serial interface reset input. Active low. Initialized internal registers during high to low transition.
Assynchronous. Internal pull-up.
ALARM
47
48
O
I
CMOS output for ALARM condition.
TXENABLE
Transmit enable active high input. TXENABLE must be high for the DATA to the DAC to be enabled.
When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored. Internal
pull-down.
SLEEP
49
I
Puts device in sleep, active high. Internal pull-down.
12
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Product Folder Links: DAC3151 DAC3161 DAC3171
DAC3151
DAC3161
DAC3171
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NAME
SLAS959A –AUGUST 2013–REVISED AUGUST 2013
PIN ASSIGNMENT TABLE – DAC3171 14-BIT INTERFACE MODE (continued)
PIN
I/O
DESCRIPTION
NO.
DATA INTERFACE
DATA[13:0]P/N
9/10-
19/20
22/23
26/27,
29/30-
39/40
I
LVDS input data bits for both channels. Each positive/negative LVDS pair has an internal 100 Ω
termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR) with two data
transfers per DATACKP/N clock cycle.
The data format is interleaved with channel A (rising edge) and channel B falling edge.
In the default mode (reverse bus not enabled):
DATA13P/N is most significant data bit (MSB)
DATA0P/N is most significant data bit (LSB)
DATACLKP/N
SYNCP/N
24/25
6/7
I
I
I
DDR differential input data clock. Edge to center nominal timing. Ch A rising edge, Ch B falling edge in
multiplexed output mode.
Reset the FIFO or to be used as a syncing source. These two functions are captured with the rising edge
of DATACLKP/N. The signal captured by the falling edge of DATACLKP/N.
ALIGNP/N
4/5
LVPECL FIFO output syncrhonization. This positive/negative pair is captured with the rising edge of
DACCLKP/N. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it can
be left unconnected.
OUTPUT/CLOCK
DACCLKP/N
IOUTAP/N
1/2
I
LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2.
61/60
O
A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full
scale current source and the most positive voltage on the IOUTAP pin. Similarly, a 0xFFFF data input
results in a 0 mA current source and the least positive voltage on the IOUTAP pin.
REFERENCE
EXTIO
58
57
I/O Used as external reference input when internal reference is disabled. Requires a 0.1 µF decoupling
capacitor to GND when used as reference output.
BIASJ
O
Full-scale output current bias. For 20 mA full-scale output current, connect a 960 Ω resistor to GND.
POWER SUPPLY
IOVDD
45
3
I
I
I
I
I
Supply voltage for CMOS IO’s. 1.8V – 3.3V.
1.8V clock supply
CLKVDD18
DIGVDD18
VDDA18
21, 28
50, 64
1.8V digital supply. Also supplies LVDS receivers.
Analog 1.8V supply
VDDA33
55, 56,
59
Analog 3.3V supply
VFUSE
NC
8
I
Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to
DVDD pins for normal operation.
51, 52,
53, 54
62, 63
Not Used. These pins can be left open or tied to GROUND in actual application use.
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
TEMPERATUR
E RANGE
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
LEAD/BALL
FINISH
ODERING
NUMBER
TRANSPORT
MEDIA
PRODUCT
ECO PLAN
QUANTITY
DAC3151IRGCT
DAC3151IRGCR
DAC3161IRGCT
DAC3161IRGCR
DAC3171IRGCT
DAC3171IRGCR
250
2000
250
DAC3151
DAC3161
DAC3171
GREEN (RoHS
and no Sb/Br)
QFN-64
RGC
–40°C to 85°C
NiPdAu
Tape and Reel
2000
250
2000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
–0.5 to 4
UNIT
VDDA33 to GND
VDDA18 to GND
–0.5 to 2.3
–0.5 to 2.3
–0.5 to 4
Supply voltage
CLKVDD18 to GND
IOVDD to GND
V
DIGVDD18 to GND
CLKVDD18 to DIGVDD18
VDDA18 to DIGVDD18
–0.5 to 2.3
–0.5 to 0.5
–0.5 to 0.5
DA[6..0]P, DA[6..0]N, D[13..0]P, D[13..0]N, DATACLKP, DATACLKN,
DA_CLKP, DA_CLKPN, SYNCP, SYNCN to GND
–0.5 to DIGVDD18 + 0.5
Terminal voltage
range
V
DACCLKP, DACCLKN, ALIGNP, ALIGNN
TXENABLE, ALARM, SDO, SDIO, SCLK, SDENB, RESETB to GND
IOUTAP, IOUTAN to GND
–0.5 to CLKVDD18 + 0.5
–0.5 to IOVDD + 0.5
–0.7 to 1.4
EXTIO, BIASJ to GND
–0.5 to VDDA33 + 0.5
–65 to 150
Storage temperature range
ESD, Human Body Model
°C
kV
2
THERMAL INFORMATION
DAC3151, DAC3161,
DAC3171
THERMAL METRIC(1)
UNITS
QFN (64 PIN)
θJA
Junction-to-ambient thermal resistance
23.0
7.6
2.8
0.1
2.8
0.2
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
14
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SLAS959A –AUGUST 2013–REVISED AUGUST 2013
ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, DAC sample rate = 500MSPS, 50% clock
duty cycle, VDDA33/IOVDD = 3.3V, VDDA18/CLKVDD18/DIGVDD18 = 1.8V, IOUTFS = 20mA (unless otherwise noted).
DAC3151
DAC3161
DAC3171
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX MIN
TYP
MAX
Resolution
DC ACCURACY
DNL Differential nonlinearity
INL Integral nonlinearity
ANALOG OUTPUTS
10
12
14
Bits
±0.04
±0.15
±0.2
±0.5
±1
±2
1 LSB = IOUTFS/214
LSB
Coarse gain linearity
Offset error
±0.4
0.01
±2
±0.4
0.01
±2
±0.4
0.01
±2
LSB
Mid code offset
%FSR
With external reference
With internal reference
With internal reference
Gain error
%FSR
%FSR
±2
±2
±2
Gain mismatch
-2
2
-2
2
-2
2
1
Minimum full scale output
current
2
2
2
Nominal full-scale current,
IOUTFS = 16xIBAIS current
mA
Maximum full scale output
current
20
20
20
Output compliance range
Output resistance
IOUTFS = 20 mA
-0.5
1
5
-0.5
1
5
-0.5
V
300
300
300
5
kΩ
pF
Output capacitance
REFERENCE OUTPUT
VREF
Reference output voltage
Reference output current
1.14
0.1
1.2
1.26
1.14
0.1
1.2
1.26 1.14
1.2
1.26
1.25
V
100
100
100
nA
REFERENCE INPUT
VEXTIO Input voltage range
External reference mode
1.2
1
1.25
1.2
1
1.25
0.1
1.2
1
V
Input resistance
Small signal bandwidth
MΩ
kHz
pF
500
100
500
100
500
100
Input capacitance
TEMPERATURE COEFFICIENTS
ppm of
FSR
/°C
Offset drift
Gain drift
±1
±1
±1
With external reference
With internal reference
±15
±30
±8
±15
±30
±8
±15
±30
±8
ppm /°C
ppm /°C
ppm /°C
Reference voltage drift
POWER SUPPLY
DIGVDD18, VFUSE, VDDA18,
CLKVDD18
1.71
3.15
1.71
1.8
3.3
1.89
3.45
3.45
1.71
3.15
1.71
1.8
3.3
1.89 1.71
3.45 3.15
3.45 1.71
1.8
3.3
1.89
3.45
3.45
V
V
V
VDDA33
IOVDD
Sets CMOS IO voltage levels. Nominal
1.8V, 2.5V or 3.3V
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ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS (continued)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, DAC sample rate = 500MSPS, 50% clock
duty cycle, VDDA33/IOVDD = 3.3V, VDDA18/CLKVDD18/DIGVDD18 = 1.8V, IOUTFS = 20mA (unless otherwise noted).
DAC3151
DAC3161
DAC3171
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX MIN
TYP
MAX
POWER CONSUMPTION
IVDDA33
3.3V Analog supply current
28
47
28
47
28
47
35
56
mA
mA
ICLKVDD18
1.8V Clock supply current
MODE 1
fDAC = 491.52 MSPS, QMC on,
IF = 20 MHz, Input full word width
1.8V Digital supply current
(DIGVDD18 and VFUSE)
IDIGVDD18
110
110
110
125
mA
IIOVDD
1.8V IO Supply current
Total power dissipation
3.3V Analog supply current
1.8V Clock supply current
0.002
375
28
0.002
375
28
0.002
375
28
0.015
442
mA
mW
mA
mA
Pdis
IVDDA33
ICLKVDD18
37
37
37
MODE 2
fDAC = 320 MSPS, QMC on,
IF = 20 MHz, Input full word width
1.8V Digital supply current
(DIGVDD18 and VFUSE)
IDIGVDD18
80
80
80
mA
IIOVDD
1.8V IO Supply current
Total power dissipation
3.3V Analog supply current
1.8V Clock supply current
0.002
303
2.6
0.002
303
2.6
0.002
303
2.6
mA
mW
mA
mA
Pdis
IVDDA33
ICLKVDD18
43
43
43
MODE 3
Sleep mode, fDAC = 491.52 MSPS,
DAC in sleep mode, Input full word width
1.8V Digital supply current
(DIGVDD18 and VFUSE)
IDIGVDD18
106
106
106
mA
IIOVDD
1.8V IO Supply current
Total power dissipation
3.3V Analog supply current
1.8V Clock supply current
0.003
277
1.6
0.003
277
1.6
0.003
277
1.6
mA
mW
mA
mA
Pdis
IVDDA33
ICLKVDD18
4
4
4
4
4
4
1.8
1.8
1.8
MODE 4
Power-down mode, no clock,
DAC in sleep mode, Input full word width
1.8V Digital supply current
(DIGVDD18 and VFUSE)
IDIGVDD18
0.7
3
0.7
3
0.7
3
mA
IIOVDD
Pdis
1.8V IO Supply current
Total power dissipation
0.003
10
0.015
26
0.003
10
0.015
0.003
10
0.015
26
mA
26
mW
–0.4
–40
0.4
–0.4
–40
0.4 –0.4
0.4 %/FSR
/V
PSRR
T
Power supply rejection ratio
Operating temperature
DC tested
85
85
–40
85
°C
16
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SLAS959A –AUGUST 2013–REVISED AUGUST 2013
ELECTRICAL CHARACTERISTICS – AC SPECIFICATIONS
Typical values at T A = 25°C, full temperature range is T MIN = –40°C to T
= 85°C, DAC sample rate = 500MSPS, 50%
MAX
clock duty cycle, VDDA33/IOVDD = 3.3V, VDDA18/CLKVDD18/DIGVDD18 = 1.8V, IOUT FS = 20mA (unless otherwise
noted).
DAC3151
DAC3161
DAC3171
PARAMETER
TEST CONDITIONS
UNIT
MIN TYP
MAX
MIN
TYP
MAX
MIN TYP MAX
ANALOG OUTPUT
fDAC
Maximum sample rate
500
500
500
11
MSPS
ns
ts(DAC)
tPD
tr(IOUT)
tf(IOUT)
Output settling time to 0.1%
Output propagation delay
Output rise time 10% to 90%
Output fall time 90% to 10%
Transition: Code 0x0000 to 0x3FFF
Does not include digital latency
11
2
11
2
2
ns
200
200
200
200
200
200
ps
ps
Length of delay from DAC pin inputs to
DATA at output pins. In normal operation
mode including the latency of FIFO.
Digital Latency
26
26
26
µs
AC PERFORMANCE
fDAC = 500 MSPS, fout = 10.1 MHz
fDAC = 500 MSPS, fout = 20.1 MHz
fDAC = 500 MSPS, fout = 70.1 MHz
fDAC = 500 MSPS, fout = 10.1 ±0.5 MHz
fDAC = 500 MSPS, fout = 20.1 ±0.5 MHz
fDAC = 500 MSPS, fout = 70.1 ±0.5 MHz
fDAC = 500 MSPS, fout = 150.1 ±0.5 MHz
fDAC = 500 MSPS, fout = 10.1 MHz
fDAC = 500 MSPS, fout = 20.1 MHz
fDAC = 500 MSPS, fout = 70.1 MHz
81
76
82
77
82
78
SFDR
Spurious free dynamic range
dBc
dBc
69
70
74
82
83
84
81
82
84
IMD3
Intermodulation distortion
73.5
61
74
75
61
63
147
146
146
158
156
153
160
157
155
NSD
Noise spectral density
dBc/Hz
dBc
fDAC = 491.52 MSPS, fout = 30.72 MHz,
WCDMA TM1
69
68
77
73
78
74
ACLR
Adjacent channel leakage ratio
f AC = 491.52 MSPS, fout = 153.6 MHz,
WCDMA TM1
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ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS
Typical values at T A = 25°C, full temperature range is T MIN = –40°C to T
= 85°C, DAC sample rate = 500MSPS, 50%
MAX
clock duty cycle, VDDA33/IOVDD = 3.3V, VDDA18/CLKVDD18/DIGVDD18 = 1.8V, IOUT FS = 20mA (unless otherwise
noted).
DAC3151
DAC3161
DAC3171
TEST
CONDITIONS
PARAMETER
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
MIN TYP
MAX
CMOS DIGITAL INPUTS (RESETB, SDENB, SCLK, SDIO, TXENABLE)
0.6×
IOVDD
0.6×
IOVDD
0.6×
IOVDD
VIH
VIL
High-level input voltage
Low-level input voltage
V
V
0.25×
IOVDD
0.25×
IOVDD
0.25×
IOVDD
IOVDD = 3.3 V, 2.5 V or
1.8 V
IIH
IIL
High-level input current
Low-level input current
-40
-40
40
40
–40
–40
40
40
μA
μA
DIGITAL OUTPUTS – CMOS INTERFACE (SDOUT, SDIO)
IOVDD = 3.3 V, 2.5 V,
1.8 V
0.85×
IOVDD
0.85×
IOVDD
0.85×
IOVDD
VOH
VOL
High-level output voltage
Low-level output voltage
V
V
0.125×
IOVDD
0.125×
IOVDD
0.125×
IOVDD
SERIAL PORT TIMING
ts(SENDB)
ts(SDIO)
th(SDIO)
t(SCLK)
Setup time, SDENB to rising edge of SCLK
20
10
5
20
10
5
20
10
5
ns
ns
ns
ns
ns
ns
ns
ns
Setup time, SDIO to rising edge of SCLK
Hold time, SDIO from rising edge of SCLK
Period of SCLK
100
40
40
100
40
40
100
40
40
t(SCLKH)
t(SCLKL)
td(DATA)
TRESET
High time of SCLK
Low time of SCLK
Data output delay after falling edge of SCLK
Minimum RESTB pulsewidth
10
25
10
25
10
25
LVDS INTERFACE (D[x..0]P/N, DA[x..0]P/N , DB[x..0]P/N , DA_CLKP/N, DB_CLKP/N, DATACLKP/N, SYNCP/N, ALIGNP/N)
VA,B+
VA,B–
VCOM
ZT
Logic high differential input voltage threshold
Logic low differential input voltage threshold
Input Common Mode Range
175
175
175
mV
mV
V
–175
2.0
–175
2.0
–175
2.0
1.0
85
1.2
110
2
1.0
85
1.2
110
2
1.0
85
1.2
110
2
Internal termination
135
135
135
Ω
CL
LVDS input capacitance
pF
18
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SLAS959A –AUGUST 2013–REVISED AUGUST 2013
ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued)
Typical values at T A = 25°C, full temperature range is T MIN = –40°C to T
= 85°C, DAC sample rate = 500MSPS, 50%
MAX
clock duty cycle, VDDA33/IOVDD = 3.3V, VDDA18/CLKVDD18/DIGVDD18 = 1.8V, IOUT FS = 20mA (unless otherwise
noted).
DAC3151
DAC3161
DAC3171
TEST
CONDITIONS
PARAMETER
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
MIN TYP
MAX
LVDS INPUT TIMING
config3 Setting
datadly
clkdly
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
-20
-120
-220
-310
-390
-480
-560
-630
70
-20
-120
-220
-310
-390
-480
-560
-630
70
-20
-120
-220
-310
-390
-480
-560
-630
70
D[x..0] valid to DATACLK
rising or falling edge for
single bus single clock
mode ;
_
DA/DB[x…0] valid to
DB_CLK rising or falling edge
for dual bus single clock
mode;
ts(DATA)
Setup time
ps
_
DA[x..0] valid to DA_CLK
rising or falling edge, and
DB[x…0] valid for DB_CLK
rising or falling edge for dual
bus dual clock mode
150
230
330
430
530
620
150
230
330
430
530
620
150
230
330
430
530
620
congfig3 Setting
datadly clkdly
0
0
310
390
480
560
650
740
850
930
200
100
20
310
390
480
560
650
740
850
930
200
100
20
310
390
480
560
650
740
850
930
200
100
20
0
0
0
0
0
0
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
0
0
0
0
0
0
D[x..0] valid to DATACLK
rising or falling edge for
single bus single clock mode;
_
DA/DB[x…0] valid to
DB_CLK rising or falling edge
for dual bus single clock
mode;
th(DATA)
Hold time
ps
_
DA[x..0] valid to DA_CLK
rising or falling edge, and
DB[x…0] valid for DB_CLK
rising or falling edge for dual
bus dual clock mode.
-60
-60
-60
-140
-220
-290
-140
-220
-290
-140
-220
-290
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TYPICAL CHARACTERISTICS
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA full-
scale output current (unless otherwise noted).
0.2
0.15
0.1
0.05
0.04
0.03
0.02
0.01
0
0.05
0
−0.01
−0.02
−0.03
−0.04
−0.05
−0.05
−0.1
−0.15
−0.2
0
200
400
600
Code
800
1000
0
200
400
600
Code
800
1000
G003
G004
Figure 5. DAC3151 Integral Nonlinearity
Figure 6. DAC3151 Differential Nonlinearity
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
0dBFS
−6dBFS
−12dBFS
0dBFS
−6dBFS
−12dBFS
0
50
100
150
200
250
0
50
100
150
200
250
Output Frequency (dB)
Output Frequency (dB)
G005
G006
Figure 7. DAC3151 SFDR vs Output Frequency Over Input
Scale
Figure 8. DAC3151 Second-Order Harmonic Distortion vs
Output Frequency Over Input Scale
100
100
fDAC = 200 MSPS
0dBFS
−6dBFS
−12dBFS
90
90
80
70
60
50
40
30
20
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
80
70
60
50
40
30
20
10
0
50
100
150
200
250
0
50
100
150
200
250
Output Frequency (dB)
Output Frequency (MHz)
G007
G008
Figure 9. DAC3151 Third-Order Harmonic Distortion vs
Output Frequency Over Input Scale
Figure 10. DAC3151 SFDR vs Output Frequency Over fDAC
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SLAS959A –AUGUST 2013–REVISED AUGUST 2013
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA full-
scale output current (unless otherwise noted).
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
fDAC = 200 MSPS
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
0dBFS
−6dBFS
−12dBFS
0
50
100
150
200
250
0
50
100
150
200
250
Output Frequency (dB)
Output Frequency (MHz)
G009
G010
Figure 11. DAC3151 IMD3 vs Output Frequency Over Input
Scale
Figure 12. DAC3151 IMD3 vs Output Frequency Over fDAC
170
170
fDAC = 200 MSPS
0dBFS
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
−6dBFS
−12dBFS
160
150
140
130
120
110
100
160
150
140
130
120
110
100
0
50
100
150
200
250
0
100
200
250
Output Frequency (dB)
Output Frequency (MHz)
G011
G012
Figure 13. DAC3151 NSD vs Output Frequency Over Input
Scale
Figure 14. DAC3151 NSD vs Output Frequency Over fDAC
−50
−50
Adjacent channel
Alternate channel
−60
−70
−80
−90
−60
−70
−80
−90
fDAC = 500 MSPS
−100
fDAC = 500 MSPS
−100
0
50
100
150
200
250
0
50
100
150
200
250
Output Frequency (MHz)
Output Frequency (MHz)
G013
G012
Figure 15. DAC3151 ACLR (Adjacent Channel) vs Output
Frequency
Figure 16. DAC3151 ACLR (Alternate Channel) vs Output
Frequency
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA full-
scale output current (unless otherwise noted).
10
10
fDAC = 491. 52MSPS
fout = 20 MHz
fDAC = 491. 52MSPS
fout = 70 MHz
0
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−10
−20
−30
−40
−50
−60
−70
−80
−90
10
50
90
130
170
210
250
10
50
90
130
170
210
250
Frequency (MHz)
Frequency (MHz)
G011
G016
Figure 17. DAC3151 Single-Tone Spectral Plot (IF = 20MHz)
Figure 18. DAC3151 Single-Tone Spectral Plot (IF = 70MHz)
10
10
fDAC = 500 MSPS
fout = 20 MHz
fDAC = 500 MSPS
fout = 70 MHz
0
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
Tone spacing = 1 MHz
Tone spacing = 1 MHz
15
17
19
21
23
25
65
67
69
71
73
75
Frequency (MHz)
Frequency (MHz)
G017
G018
Figure 19. DAC3151 Two-Tone Spectral Plot (IF = 20MHz)
Figure 20. DAC3151 Two-Tone Spectral Plot (IF = 70MHz)
*
*
*
R B W 3 0 k H z
*
*
*
R B W 3 0 k H z
V B W 3 0 0 k H z
V B W 3 0 0 k H z
R e f - 2 0 d B m
*
A t t
5
d B
S W T
2
s
R e f - 1 0 d B m
*
A t t
5
d B
S W T
2 s
- 2 0
- 3 0
- 4 0
- 5 0
- 6 0
- 7 0
- 8 0
- 9 0
- 1 0 0
- 3 0
- 4 0
- 5 0
- 6 0
- 7 0
- 8 0
- 9 0
- 1 0 0
- 1 1 0
A
A
1
R M
*
1
R M
*
C L R W R
C L R W R
N O R
3 D B
N O R
3 D B
C e n t e r 7 0 M H z
1 . 5 5 M H z /
S p a n 1 5 . 5 M H z
W - C D M A 3 G P P F W D
C e n t e r 7 0 M H z
4 . 0 8 M H z /
S p a n 4 0 . 8 M H z
T x C h a n n e l
S t a n d a r d : W - C D M A 3 G P P F W D
T x C h a n n e l s
A d j a c e n t C h a n n e l
Lower
B a n d w i d t h
3 . 8 4 M H z
3 . 8 4 M H z
Power
-10.64 dBm
-61.24 dB
-61.34 dB
A d j a c e n t C h a n n e l
B a n d w i d t h
Upper
Lower
Upper
-69.11 dB
-69.15 dB
( R e f )
Ch1
Ch2
Ch3
Ch4
-18.62 dBm
-18.64 dBm
-18.72 dBm
-18.70 dBm
S p a c i n g
5
M H z
A l t e r n a t e C h a n n e l
Lower
Upper
-61.11 dB
-61.39 dB
Total
-12.65 dBm
Figure 21. DAC3151 ACPR Four-Carrier
WCDMA Test Mode 1
Figure 22. DAC3151 ACPR Single-Carrier
WCDMA Test Mode 1
22
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SLAS959A –AUGUST 2013–REVISED AUGUST 2013
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA full-
scale output current (unless otherwise noted).
*
*
*
R B W 3 0 k H z
*
*
*
R B W 3 0 k H z
V B W 3 0 0 k H z
V B W 3 0 0 k H z
R e f - 1 0 d B m
*
A t t
5
d B
S W T
2 s
R e f - 1 0 d B m
*
A t t
5
d B
S W T
2 s
- 2 0
- 3 0
- 4 0
- 5 0
- 6 0
- 7 0
- 8 0
- 9 0
- 1 0 0
- 2 0
- 3 0
- 4 0
- 5 0
- 6 0
- 7 0
- 8 0
- 9 0
- 1 0 0
A
A
1
R M *
1
R M
*
C L R W R
C L R W R
N O R
3 D B
N O R
3 D B
C e n t e r 7 0 M H z
5 . 8 5 5 0 3 4 5 3 8 M H z /
S p a n 5 8 . 5 5 0 3 4 5 3 8 M H z
E - U T R A / L T E S q u a r e
C e n t e r 7 0 M H z
2 . 9 2 8 2 7 4 1 9 M H z /
S p a n 2 9 . 2 8 2 7 4 1 9 M H z
E - U T R A / L T E S q u a r e
T x C h a n n e l
T x C h a n n e l
B a n d w i d t h
1 8 . 0 1 5 M H z
B a n d w i d t h
9 . 0 1 5 M H z
Power
-11.14 dBm
Power
-12.33 dBm
A d j a c e n t C h a n n e l
B a n d w i d t h
A d j a c e n t C h a n n e l
B a n d w i d t h
Lower
Upper
-61.93 dB
-62.21 dB
Lower
Upper
-64.00 dB
-64.09 dB
1 8 . 0 1 5 M H z
2 0 M H z
9 . 0 1 5 M H z
1 0 M H z
S p a c i n g
S p a c i n g
Figure 23. DAC3151 ACPR LTE 10-MHz FDD E-TM 1.1
Figure 24. DAC3151 ACPR LTE 20-MHz FDD E-TM 1.1
0.4
0.3
0.2
0.1
0
0.2
0.15
0.1
0.05
0
−0.1
−0.2
−0.3
−0.4
−0.5
−0.6
−0.05
−0.1
−0.15
−0.2
0
500 1000 1500 2000 2500 3000 3500 4000
Code
0
500 1000 1500 2000 2500 3000 3500 4000
Code
G024
G025
Figure 25. DAC3161 Integral Nonlinearity
Figure 26. DAC3161 Differential Nonlinearity
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
0dBFS
−6dBFS
−12dBFS
0dBFS
−6dBFS
−12dBFS
0
50
100
150
200
250
0
50
100
150
200
250
Output Frequency (dB)
Output Frequency (dB)
G026
G027
Figure 27. DAC3161 SFDR vs Output Frequency Over Input
Scale
Figure 28. DAC3161 Second-Order Harmonic Distortion vs
Output Frequency Over Input Scale
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA full-
scale output current (unless otherwise noted).
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
fDAC = 200 MSPS
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
0dBFS
−6dBFS
−12dBFS
0
50
100
150
200
250
0
50
100
150
200
250
Output Frequency (dB)
Output Frequency (MHz)
G028
G029
Figure 29. DAC3161 Third-Order Harmonic Distortion vs
Output Frequency Over Input Scale
Figure 30. DAC3161 SFDR vs Output Frequency Over fDAC
100
100
fDAC = 200 MSPS
0dBFS
−6dBFS
−12dBFS
90
90
80
70
60
50
40
30
20
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
80
70
60
50
40
30
20
10
0
50
100
150
200
250
0
50
100
150
200
250
Output Frequency (dB)
Output Frequency (MHz)
G030
G031
Figure 31. DAC3161 IMD3 vs Output Frequency Over Input
Scale
Figure 32. DAC3161 IMD3 vs Output Frequency Over fDAC
180
180
fDAC = 200 MSPS
0dBFS
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
−6dBFS
−12dBFS
170
160
150
140
130
120
110
170
160
150
140
130
120
110
0
50
100
150
200
250
0
100
200
250
Output Frequency (dB)
Output Frequency (MHz)
G032
G033
Figure 33. DAC3161 NSD vs Output Frequency Over Input
Scale
Figure 34. DAC3161 NSD vs Output Frequency Over fDAC
24
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SLAS959A –AUGUST 2013–REVISED AUGUST 2013
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA full-
scale output current (unless otherwise noted).
−50
−50
Adjacent channel
Alternate channel
−60
−60
−70
−70
−80
−80
−90
−90
fDAC = 500 MSPS
50
fDAC = 500 MSPS
50
−100
−100
0
100
150
200
250
0
100
150
200
250
Output Frequency (MHz)
Output Frequency (MHz)
G034
G035
Figure 35. DAC3161 ACLR (Adjacent Channel) vs Output
Frequency
Figure 36. DAC3161 ACLR (Alternate Channel) vs Output
Frequency
10
10
fDAC = 491. 52MSPS
fout = 20 MHz
fDAC = 491. 52MSPS
fout = 70 MHz
0
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−10
−20
−30
−40
−50
−60
−70
−80
−90
10
50
90
130
170
210
250
10
50
90
130
170
210
250
Frequency (MHz)
Frequency (MHz)
G036
G037
Figure 37. DAC3161 Single-Tone Spectral Plot (IF = 20MHz)
Figure 38. DAC3161 Single-Tone Spectral Plot (IF = 70MHz)
10
10
fDAC = 500 MSPS
fout = 20 MHz
fDAC = 500 MSPS
fout = 70 MHz
0
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
Tone spacing = 1 MHz
Tone spacing = 1 MHz
15
17
19
21
23
25
65
67
69
71
73
75
Frequency (MHz)
Frequency (MHz)
G038
G039
Figure 39. DAC3161 Two-Tone Spectral Plot (IF = 20MHz)
Figure 40. DAC3161 Two-Tone Spectral Plot (IF = 70MHz)
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA full-
scale output current (unless otherwise noted).
*
*
*
R B W 3 0 k H z
*
*
*
R B W 3 0 k H z
V B W 3 0 0 k H z
V B W 3 0 0 k H z
R e f - 1 0 d B m
*
A t t
5
d B
S W T
2
s
R e f - 1 0 d B m
*
A t t
5
d B
S W T
2 s
- 2 0
- 3 0
- 4 0
- 5 0
- 6 0
- 7 0
- 8 0
- 9 0
- 1 0 0
- 2 0
- 3 0
- 4 0
- 5 0
- 6 0
- 7 0
- 8 0
- 9 0
- 1 0 0
A
A
1
R M
*
1
R M
*
C L R W R
C L R W R
N O R
3 D B
N O R
3 D B
C e n t e r 7 0 M H z
4 . 0 8 M H z /
S p a n 4 0 . 8 M H z
C e n t e r 7 0 M H z
1 . 5 5 M H z /
S p a n 1 5 . 5 M H z
W - C D M A 3 G P P F W D
S t a n d a r d : W - C D M A 3 G P P F W D
T x C h a n n e l s
A d j a c e n t C h a n n e l
Lower
T x C h a n n e l
B a n d w i d t h
3 . 8 4 M H z
3 . 8 4 M H z
Power
-10.70 dBm
-70.74 dB
-70.87 dB
A d j a c e n t C h a n n e l
B a n d w i d t h
Upper
Lower
Upper
-77.84 dB
-77.14 dB
( R e f )
Ch1
Ch2
Ch3
Ch4
-18.70 dBm
-18.69 dBm
-18.77 dBm
-18.75 dBm
A l t e r n a t e C h a n n e l
S p a c i n g
5 M H z
Lower
Upper
-70.86 dB
-70.84 dB
Total
-12.71 dBm
Figure 41. DAC3161 ACPR Four-Carrier
WCDMA Test Mode 1
Figure 42. DAC3161 ACPR Single-Carrier
WCDMA Test Mode 1
*
*
*
R B W 3 0 k H z
*
*
*
R B W 3 0 k H z
V B W 3 0 0 k H z
V B W 3 0 0 k H z
R e f - 2 0 d B m
*
A t t
5
d B
S W T
2 s
R e f - 2 0 d B m
*
A t t
5
d B
S W T
2 s
- 3 0
- 4 0
- 5 0
- 6 0
- 7 0
- 8 0
- 9 0
- 1 0 0
- 1 1 0
- 3 0
- 4 0
- 5 0
- 6 0
- 7 0
- 8 0
- 9 0
- 1 0 0
- 1 1 0
A
A
1
R M
*
1
R M *
C L R W R
C L R W R
N O R
3 D B
N O R
3 D B
C e n t e r 7 0 M H z
5 . 8 5 5 0 3 4 5 3 8 M H z /
S p a n 5 8 . 5 5 0 3 4 5 3 8 M H z
E - U T R A / L T E S q u a r e
C e n t e r 7 0 M H z
2 . 9 2 8 2 7 4 1 9 M H z /
S p a n 2 9 . 2 8 2 7 4 1 9 M H z
E - U T R A / L T E S q u a r e
T x C h a n n e l
T x C h a n n e l
B a n d w i d t h
1 8 . 0 1 5 M H z
B a n d w i d t h
9 . 0 1 5 M H z
Power
-11.20 dBm
Power
-12.37 dBm
A d j a c e n t C h a n n e l
B a n d w i d t h
A d j a c e n t C h a n n e l
B a n d w i d t h
Lower
Upper
-70.91 dB
-70.66 dB
Lower
Upper
-73.67 dB
-73.46 dB
1 8 . 0 1 5 M H z
2 0 M H z
9 . 0 1 5 M H z
1 0 M H z
S p a c i n g
S p a c i n g
Figure 43. DAC3161 ACPR LTE 10-MHz FDD E-TM 1.1
Figure 44. DAC3161 ACPR LTE 20-MHz FDD E-TM 1.1
2
1.5
1
2
1.5
1
0.5
0
0.5
0
−0.5
−0.5
−1
−1.5
−2
−1
−1.5
−2
5000
10000
15000
5000
10000
15000
Code
Code
G019
G020
Figure 45. DAC3171 Integral Nonlinearity
Figure 46. DAC3171 Differential Nonlinearity
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SLAS959A –AUGUST 2013–REVISED AUGUST 2013
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA full-
scale output current (unless otherwise noted).
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
0dBFS
−6dBFS
−12dBFS
0dBFS
−6dBFS
−12dBFS
0
50
100
150
200
250
0
50
100
150
200
250
Output Frequency (dB)
Output Frequency (dB)
G001
G002
Figure 47. DAC3171 SFDR vs Output Frequency Over Input
Scale
Figure 48. DAC3171 Second-Order Harmonic Distortion vs
Output Frequency Over Input Scale
100
100
fDAC = 200 MSPS
0dBFS
−6dBFS
−12dBFS
90
90
80
70
60
50
40
30
20
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
80
70
60
50
40
30
20
10
0
50
100
150
200
250
0
50
100
150
200
250
Output Frequency (dB)
Output Frequency (MHz)
G003
G004
Figure 49. DAC3171 Third-Order Harmonic Distortion vs
Output Frequency Over Input Scale
Figure 50. DAC3171 SFDR vs Output Frequency Over fDAC
100
100
fDAC = 200 MSPS
0dBFS
−6dBFS
−12dBFS
90
90
80
70
60
50
40
30
20
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
80
70
60
50
40
30
20
10
0
50
100
150
200
250
0
50
100
150
200
250
Output Frequency (dB)
Output Frequency (MHz)
G005
G006
Figure 51. DAC3171 IMD3 vs Output Frequency Over Input
Scale
Figure 52. DAC3171 IMD3 vs Output Frequency Over fDAC
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA full-
scale output current (unless otherwise noted).
180
170
160
150
140
130
120
110
180
170
160
150
140
130
120
110
fDAC = 200 MSPS
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
0dBFS
−6dBFS
−12dBFS
0
50
100
150
200
250
0
100
200
250
Output Frequency (dB)
Output Frequency (MHz)
G007
G008
Figure 53. DAC3171 NSD vs Output Frequency Over Input
Scale
Figure 54. DAC3171 NSD vs Output Frequency Over fDAC
−50
−50
Adjacent channel
Altenate channel
−60
−70
−80
−90
−60
−70
−80
−90
fDAC = 500 MSPS
−100
fDAC = 500 MSPS
−100
0
50
100
150
200
250
0
50
100
150
200
250
Output Frequency (MHz)
Output Frequency (MHz)
G009
G010
Figure 55. DAC3171 ACLR (Adjacent Channel) vs Output
Frequency
Figure 56. DAC3171 ACLR (Alternate Channel) vs Output
Frequency
10
10
fDAC= 491.52 MSPS
f
fDAC= 491.52 MSPS
f
OUT = 20 MHz
0
0
OUT = 20 MHz
−10
−20
−30
−40
−50
−60
−70
−80
−90
−10
−20
−30
−40
−50
−60
−70
−80
−90
10
50
90
130
170
210
250
10
50
90
130
170
210
250
Frequency (MHz)
Frequency (MHz)
G011
G012
Figure 57. DAC3171 Single-Tone Spectral Plot (IF = 20MHz)
Figure 58. DAC3171 Single-Tone Spectral Plot (IF = 70MHz)
28
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SLAS959A –AUGUST 2013–REVISED AUGUST 2013
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA full-
scale output current (unless otherwise noted).
10
10
fDAC = 500 MSPS
fout = 20 MHz
fDAC = 500 MSPS
fout = 70 MHz
0
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
Tone spacing = 1 MHz
Tone spacing = 1 MHz
15
17
19
21
23
25
65
67
69
71
73
75
Frequency (MHz)
Frequency (MHz)
G013
G014
Figure 59. DAC3171 Two-Tone Spectral Plot (IF = 20MHz)
Figure 60. DAC3171 Two-Tone Spectral Plot (IF = 70MHz)
0dBFs,
0dBFs,
f
= 491.52MSPS,
DAC
OUT
f
= 491.52MSPS,
DAC
OUT
f
= 70MHz
f
= 70MHz
Figure 61. DAC3171 Four-Carrier WCDMA Test Mode 1
Figure 62. DAC3171 Single-Carrier WCDMA Test Mode 1
0dBFs,
0dBFs,
f
= 491.52MSPS,
f
= 491.52MSPS,
DAC
OUT
DAC
OUT
f
= 70MHz
f
= 70MHz
Figure 63. DAC3171 10-MHz Single Carrier LTE Test Mode
3.1
Figure 64. DAC3171 20-MHz Single Carrier LTE Test Mode
3.1
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA full-
scale output current (unless otherwise noted).
Figure 65. Power Consumption vs fDAC
30
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SLAS959A –AUGUST 2013–REVISED AUGUST 2013
DEFINITION OF SPECIFICATIONS
Adjacent Carrier Leakage Ratio (ACLR): Defined as the ratio in decibles relative to the carrier (dBc) between
the measured power within a channel and that of an adjacent channel.
Analog and Digital Power Supply Rejection Ratio (APSSR, DPSSR): Defined as the percentage error in the
ratio of the delta IOUT and delta supply voltage normalized with respect to the ideal IOUT current.
Differential Nonlinearity (DNL): Defined as the variation in analog output associated with an ideal 1 LSB
change in the digital input code.
Gain Drift: Defined as the maximum change in gain, in terms of ppm of full-scale range (FSR) per °C, from the
value at ambient (25°C) to values over the full operating temperature range.
Gain Error: Defined as the percentage error (in FSR%) for the ratio between the measured full-scale output
current and the ideal full-scale output current.
Integral Nonlinearity (INL): Defined as the maximum deviation of the actual analog output from the ideal output,
determined by a straight line drawn from zero scale to full scale.
Intermodulation Distortion (IMD3): The two-tone IMD3 is defined as the ratio (in dBc) of the 3rd-order
intermodulation distortion product to either fundamental output tone.
Offset Drift: Defined as the maximum change in DC offset, in terms of ppm of full-scale range (FSR) per °C,
from the value at ambient (25°C) to values over the full operating temperature range.
Offset Error: Defined as the percentage error (in FSR%) for the ratio between the measured mid-scale output
current and the ideal mid-scale output current.
Output Compliance Range: Defined as the minimum and maximum allowable voltage at the output of the
current-output DAC. Exceeding this limit may result reduced reliability of the device or adversely affecting
distortion performance.
Reference Voltage Drift: Defined as the maximum change of the reference voltage in ppm per degree Celsius
from value at ambient (25°C) to values over the full operating temperature range.
Spurious Free Dynamic Range (SFDR): Defined as the difference (in dBc) between the peak amplitude of the
output signal and the peak spurious signal.
Signal to Noise Ratio (SNR): Defined as the ratio of the RMS value of the fundamental output signal to the
RMS sum of all other spectral components below the Nyquist frequency, including noise, but excluding the first
six harmonics and dc.
TIMING DIAGRAMS
D[9:0]P/N
A3[9:0]
A4[9:0]
A5[9:0]
A6[9:0]
A7[9:0]
A8[9:0]
A9[9:0] A10[9:0] A11[9:0]
ts(DATA)
th(DATA)
DATACLKP/N
(SDR)
ts(DATA)
th(DATA)
SYNCP/N
Resets write pointer to position 0
Figure 66. DAC3151 Input Data Timing Diagram
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D[11:0]P/N
A3[11:0] A4[11:0] A5[11:0] A6[11:0] A7[11:0] A8[11:0] A9[11:0] A10[11:0] A11[11:0]
ts(DATA)
th(DATA)
DATACLKP/N
(SDR)
ts(DATA)
th(DATA)
SYNCP/N
Resets write pointer to position 0
Figure 67. DAC3161 Input Data Timing Diagram
DA[6:0]P/N
A3[13:7] A3[6:0] A4[13:7] A4[6:0] A5[13:7] A5[6:0] A6[13:7] A6[6:0] A7[13:7] A7[6:0]
ts(DATA)
th(DATA)
ts(DATA)
th(DATA)
DA_CLKP/N
Figure 68. DAC3171 Input Data Timing Diagram for 7-Bit Interface Mode
D[13:0]P/N
A3[13:0] A4[13:0] A5[13:0] A6[13:0] A7[13:0] A8[13:0] A9[13:0] A10[13:0] A11[13:0]
ts(DATA)
th(DATA)
DATACLKP/N
(SDR)
ts(DATA)
th(DATA)
SYNCP/N
Resets write pointer to position 0
Figure 69. DAC3171 Input Data Timing for 14-Bit Interface Mode
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DATA INPUT FORMATS
Table 1. DAC3151: 10-Bit Interface Mode
BITS
DIFFERENTIAL PAIR (P/N)
DATACLK RISING EDGE
DATACLK FALLING EDGE
D9
D8
A9
–
–
–
–
–
–
–
–
–
–
–
A8
D7
A7
D6
A6
D5
A5
D4
A4
D3
A3
D2
A2
D1
A1
A0
D0
SYNC
FIFO Write Reset
Table 2. DAC3161: 12-Bit Interface Mode
BITS
DIFFERENTIAL PAIR (P/N)
DATACLK RISING EDGE
DATACLK FALLING EDGE
D11
D10
D9
A11
–
–
–
–
–
–
–
–
–
–
–
A10
A9
D8
A8
D7
A7
D6
A6
D5
A5
D4
A4
D3
A3
A2
D2
SYNC
FIFO Write Reset
Table 3. DAC3171: 7-Bit Interface Mode
DIFFERENTIAL PAIR (P/N)
DA_CLK RISING EDGE
DA_CLK FALLING EDGE
DA6
DA5
DA4
DA3
DA2
DA1
DA0
A13
A12
A11
A10
A9
A6
A5
A4
A3
A2
A1
A0
A8
A7
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Table 4. DAC3171: 14-Bit Interface Mode
BITS
DIFFERENTIAL PAIR (P/N)
DATACLK RISING EDGE
DATACLK FALLING EDGE
D13
D12
D11
D10
D9
A13
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A12
A11
A10
A9
D8
A8
D7
A7
D6
A6
D5
A5
D4
A4
D3
A3
D2
A2
D1
A1
A0
D0
SYNC
FIFO Write Reset
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SERIAL INTERFACE DESCRIPTION
The serial port of the DAC3151/DAC3161/DAC3171 is a flexible serial interface which communicates with
industry standard microprocessors and microcontrollers. The interface provides read/write access to all registers
used to define the operating modes of DAC3151/DAC3161/DAC3171. It is compatible with most synchronous
transfer formats and can be configured as a 3 or 4 pin interface by sif4_ena in register XYZ. In both
configurations, SCLK is the serial interface input clock and SDENB is serial interface enable. For 3 pin
configuration, SDIO is a bidirectional pin for both data in and data out. For 4 pin configuration, SDIO is data in
only and SDO is data out only. Data is input into the device with the rising edge of SCLK. Data is output from the
device on the falling edge of SCLK.
Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low. The first frame byte
is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit
address to be accessed. Table 5 indicates the function of each bit in the instruction cycle and is followed by a
detailed description of each bit. The data transfer cycle consists of two bytes.
Table 5. Instruction Byte of the Serial interface
MSB
7
LSB
0
Bit
6
5
4
3
2
1
Description
R/W
A6
A5
A4
A3
A2
A1
A0
R/W
Identifies the following data transfer cycle as a read or write operation. A high indicates a read
operation from DAC3151/DAC3161/DAC3171 and a low indicates a write operation to
DAC3151/DAC3161/DAC3171.
[A6 : A0]
Identifies the address of the register to be accessed during the read or write operation.
Figure 70 shows the serial interface timing diagram for a DAC3151/DAC3161/DAC3171 write operation. SCLK is
the serial interface clock input to DAC3151/DAC3161/DAC3171. Serial data enable SDENB is an active low input
to DAC3151/DAC3161/DAC3171. SDIO is serial data in. Input data to DAC3151/DAC3161/DAC3171 is clocked
on the rising edges of SCLK.
Instruction Cycle
Data Transfer Cycle
SDENB
SCLK
SDIO
rwb
A6
A5
A4
A3
A2
A1
t
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
(SDENB)
S
SCLK
SDENB
SCLK
SDIO
t
(SDIO)
t
(SDIO)
H
S
Figure 70. Serial Interface Write Timing Diagram
Figure 71 shows the serial interface timing diagram for a DAC3151/DAC3161/DAC3171 read operation. SCLK is
the serial interface clock input to DAC3151/DAC3161/DAC3171. Serial data enable SDENB is an active low input
to DAC3151/DAC3161/DAC3171. SDIO is serial data in during the instruction cycle. In 3 pin configuration, SDIO
is data out from the DAC3151/DAC3161/DAC3171 during the data transfer cycle, while SDO is in a high-
impedance state. In
4
pin configuration, both SDIO and SDO are data out from the
DAC3151/DAC3161/DAC3171 during the data transfer cycle. At the end of the data transfer, SDIO and SDO will
output low on the final falling edge of SCLK until the rising edge of SDENB when they will 3-state.
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Instruction Cycle
Data Transfer Cycle
SDENB
SCLK
rwb
A6
A5
A4
A3
A2
A1
A0
D15
D15
D14
D14
D13
D13
D12
D12
D11
D11
D10
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
SDIO
SDO
D0
SDENB
SCLK
SDIO
SDO
Data n
Data n-1
t
(Data)
d
Figure 71. Serial Interface Read Timing Diagram
REGISTER DESCRIPTIONS
In the SIF interface there are four types of registers:
NORMAL: The NORMAL register type allows data to be written and read from. All 16-bits of the data are
registered at the same time. There is no synchronizing with an internal clock thus all register
writes are asynchronous with respect to internal clocks. There are three subtypes of NORMAL:
AUTOSYNC:
A NORMAL register that causes a sync to be generated after the write is
finished. These are most commonly used in things like offsets and phaseadd
where there is a word or block setup that extends across multiple registers
and all of the registers need to be programmed before any take effect on the
circuit. For example, the phaseadd is two registers long. It wouldn’t serve the
user to have the first write 16 of the 32 bits cause a change in the frequency,
so the design allows all the registers to be written and then when that last
one for this block is finished, an autosync is generated for the mixer telling it
to grab all the new SIF values. This will occur on a mixer clock cycle so that
no meta-stability errors occur.
No RESET Value: These are NORMAL registers, but for one reason or another reset value can
not be guaranteed. This could be because the register has some read_only
bits or some internal logic partially controls the bit values. An example is the
SIF_CONFIG6 register. The bits come from the temperature sensor and the
fuses. Depending on which fuses are blown and what the die temp is the
reset value will be different.
FUSE controlled: While this isn’t a type of register, you may see this description in the area
describing the default value for the register. What is means is that fuses will
change the default value and the value shown in the document is for when
no fuses are blown.
READ_ONLY:
Registers that are internal wires ANDed with the address bus then connected to the SIF
output data bus.
WRITE_TO_CLEAR: These registers are just like NORMAL registers with one exception. They can be written
and read, however, when the internal logic asynchronously sets a bit high in one of
these registers, that bit stays high until it is written to ‘0’. This way interrupts will be
captured and stay constant until cleared by the user.
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Table 6. Register Map
(MSB)
Bit 15
(LSB)
Bit 0
Name
Address
Default
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
config0
0x00
0x44FC
qmc
_offset
_ena
dual_ena
chipwidth (1:0)
rev
twos
sif4_ena
reserved
fifo_ena
alarm_out alarm_out
alignrx
_ena
lvdssyncrx
_ena
lvdsdataclk
_ena
reserved
synconly
_ena
_ena
_pol
config1
0x01
0x600E
iotest_ena reserved
fullword
_interface
_ena
64cnt
_ena
dacclkgone
_ena
dataclkgone
_end
collision
_ena
reserved
reserved
daca
_compliment
reserved
sif_sync
sif_
sync_ena
alarm_
2away
_ena
alarm
_1away
_ena
alarm
_collision
_ena
reserved
config2
config3
config4
config5
0x02
0x03
0x04
0x05
0x3FFF
0x0000
0x0000
0x0000
reserved
reserved
lvdsdata_ena (13:0)
datadlya (2:0)
clkdlya (2:0)
reserved
extref _ena
reserved
reserved
reserved
reserved
iotest_results (13:0)
alarm
_from
reserved
alarms_from_fifoa (2:0)
reserved
alarm
_dacclk
_gone
alarm
_dataclk
_ gone
clock
_gone
alarm
_from
_ iotesta
reserved
_zerochka
config6
config7
config8
config9
config10
0x06
0x07
0x08
0x09
0x0A
0x0000
0xFFFF
0x4000
0x8000
0xF080
tempdata (7:0)
fuse_cntl (5:0)
reserved
alarms_mask (15:0)
reserved
qmc_offseta (12:0)
reserved
fifo_offset (2:0)
coarse_dac (3:0)
fuse_ sleep
reserved
reserved
tsense
_sleep
clkrecv
_ena
sleepa
sleepb
reserved
reservedspares_west (3:0)
reserved
config11
config12
config13
config14
config15
config16
config17
config18
config19
config20
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x1111
0x3A7A
0x36B6
0x2AEA
0x0545
0x1A1A
0x1616
0x2AAA
0x06C6
0x0000
reserved
reserved
reserved
reserved
iotest_pattern0 (13:0)
iotest_pattern1 (13:0)
iotest_pattern2 (13:0)
iotest_pattern3 (13:0)
iotest_pattern4 (13:0)
iotest_pattern5 (13:0)
iotest_pattern6 (13:0)
iotest_pattern7 (13:0)
sifdac (13:0)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
sifdac
_ena
reserved
config21
config22
config23
config24
config25
config127
0x15
0x16
0x17
0x18
0x19
0x7F
0xFFFF
0x0000
0x0000
0x0000
0x0000
0x0044
sleepcntl (15:0)
fa002_data(15:0)
fa002_data(31:16)
fa002_data(47:32)
fa002_data(63:48)
reserved
reserved
reserved
reserved
reserved
titest_voh
titest_vol
vendorid (1:0)
versionid (2:0)
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Register name: config0 – Address: 0x00, Default: 0x4FC
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config0
0x00
15
14
qmc_offset_ena
dual_ena
Enable the offset function when asserted.
Utilizes both DACs when asserted.
0
0
FUSE
controlled
13:12 chipwidth
Programmable bits for setting the input interface width.
00: all 14 bits are used.
00
01: upper 12 bits are used10: upper 10 bits are used
11: upper 10 bits are used
11
10
9
rev
Reverses the input bits. When using the 7bit interface, this
reverse each 7-bit input, however when using the 14-bit
interface, all 14-bits are reversed as one word.
0
1
0
twos
When asserted, this bit tells the chip to presume 2’s
complement data is arriving at the input. Otherwise offset
binary is presumed.
sif4_ena
When asserted the SIF interface becomes a 4 pin interface.
This bit has a lower priority than the dieid_ena bit.
8
7
reserved
fifo_ena
reserved
0
1
When asserted, the FIFO is absorbing the difference between
INPUT clock and DAC clock. If it is not asserted then the
FIFO buffering is bypassed but the reversing of bits and
handling of offset binary input is still available. NOTE: When
the FIFO is bypassed the DACCCLK and DATACLK must
be aligned or there may be timing errors; and, it is not
recommended for actual application use.
6
5
4
alarm_out_ena
alarm_out_pol
alignrx_ena
When asserted the pin alarm becomes an output instead of a
tri-stated pin.
1
1
1
This bit changes the polarity of the ALARM signal.
(0=negative logic, 1=positive logic)
When asserted the ALIGN pin receiver is powered up. NOTE:
It is recommended to clear this bit when ALIGNP/N are
not used (dual bus mode, and SYNC ONLY and
SIF_SYNC modes in single bus mode).
3
lvdssyncrx_ena
When asserted the SYNC pin receiver is powered up. NOTE:
1 It is recommended to clear this bit when SYNCP/N are
not used (dual bus mode, and SIF_SYNC mode in single
bus mode.)
1
2
1
0
lvdsdataclk_ena
reserved
When asserted the DATACLK pin receiver is powered up.
reserved
1
0
0
synconly_ena
When asserted the chip is put into the SYNC ONLY mode
where the SYNC pin is used as the sync input for both the
front and back of the FIFO.
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Register name: config1 – Address: 0x01, Default: 0x600E
Register Addr
Default
Value
Bit
Name
Function
Name
(Hex)
config1
0x01 15
iotest_ena
Turns on the io-testing circuitry when asserted. This is the circuitry
that will compare a 8 sample input pattern to SIF programmed
registers to make sure the data coming into the chip meets
setup/hold requirements. If this bit is a ‘0’ then the clock to this
circuitry is turned off for power savings. NOTE: Sample 0 should
be aligned with the rising edge of SYNC.
0
14
13
reserved
reserved
1
1
fullwordinterface_ena
When asserted the input interface is changed to use the full 14-bits
for each word, instead of dual 8-bit buses for two half words. Note:
fixed to "1" for DAC3151/DAC3161.
12
64cnt_ena
This enables the resetting of the alarms after 64 good samples with
the goal of removing unnecessary errors. For instance on a lab
board, when checking the setup/hold through IO TEST, there may
initially be errors, but once the test is up and running everything
works. Setting this bit removes the need for a SIF write to clear the
alarm register.
0
11
10
dacclkgone_ena
dataclkgone_ena
This allows the DACCLK gone signal from the clock monitor to be
used to shut the output off.
0
0
This allows the DATACLK gone signal from the clock monitor to be
used to shut the output off.
9
8
7
collision_ena
reserved
This allows the collision alarm from the FIFO to shut the output off
reserved.
0
0
0
daca_compliment
When asserted the output to the DACA is complimented. This
allows the user of the chip to effectively change the + and –
designations of the DAC output pins.
6
5
reserved
sif_sync
reserved
0
0
This is the SIF_SYNC signal. Whatever is programmed into this
bitwill be used as the chip sync when SIF_SYNC mode is
enabled.Design is sensitive to rising edges so programming from 0-
>1 is when the sync pulse is generated. 1->0 has no effect.
4
3
sif_sync_ena
When asserted enable SIF_SYNC mode.
0
1
alarm_2away_ena
When asserted alarms from the FIFO that represent the pointers
being 2 away are enabled
2
1
0
alarm_1away_ena
alarm_collision_ena
reserved
When asserted alarms from the FIFO that represent the pointers
being 1 away are enabled
1
1
0
When asserted the collision of FIFO pointers causes an alarm to be
generated
reserved
Register name: config2 – Address: 0x02, Default: 0x3FFF
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config2
0x02
15
reserved
reserved.
reserved.
0
14
reserved
0
13:0
lvdsdata_ena
These 14 bits are individual enables for the 14 input pin receivers.
Note: for DAC3171 7-bit input interface mode, it is
recommended to turn off bits(6:0).
0x3FFF
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Register name: config3 – Address: 0x03, Default: 0x0000
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config3
0x03
15:13 datadlya
12:10 clkdlya
Controls the delay of the A data inputs through the LVDS receivers. 000
0= no additional delay and each LSB adds a nominal 80ps.
Controls the delay of the A data clock input through the LVDS
receivers. 0= no additional delay and each LSB adds a nominal
80ps.
000
9:7
6:4
3
reserved
reserved
extref_ ena
reserved
reserved
reserved.
000
000
0
reserved
Enable external reference for the DAC when set.
2:1
0
reserved
reserved
00
0
Register name: config4 – Address: 0x04, Default: 0x0000
Register
Name
Addr
(Hex)
Default
Value
Bit
Name
Function
config4
0x04
15:14 reserved
13:0 iotest_ results
reserved
00
WRITE TO
CLEAR/
No RESET
value
The values of these bits tell which bit in the input word failed during the 0x0000
io-test pattern comparison.
Register name: config5 – Address: 0x05, Default: 0x0000
Register
Name
Addr
(Hex)
Default
Value
Bit
Name
Function
config5
WRITE TO
CLEAR
0x05
15
alarm_from_ zerochka
When this bit is asserted the FIFOA write pointer has an all zeros
pattern in it. Since this pointer is a shift register, all zeros will cause
the input point to be stuck until the next sync. The result could be a
repeated 8T pattern at the output if the mixer is off and no syncs
occur. Check for this error will tell the user that another sync is
necessary to restart the FIFO write pointer.
0
14
reserved
reserved.
0
13:11 alarms_from_ fifoa
These bits report the FIFO A pointer status.
000: All fine
000
001: Pointers are 2 away
01X: Pointers are 1 away
1XX: FIFO Pointer collision
10:8
7
reserved
reserved
0
0
alarm_dacclk_ gone
Bit gets asserted when the DACCLK has been stopped long for
enough cycles to be caught. The number of cycles varies with
interpolation.
6
5
alarm_dataclk_ gone
clock_gone
Bit gets asserted when the DATACLK has been stopped long for
enough cycles to be caught. The number of cycles varies with
interpolation.
0
0
This bit gets set when either alarm_dacclk_gone or
alarm_dataclk_gone are asserted. It controls the output of the
CDRV_SER block. When high, the CDRV_SER block will output
“0x8000” for each output connected to a DAC. The bit must be
written to ‘0’ for CDRV_SER outputs to resume normal operation.
4
alarm_from_ iotesta
This is asserted when the input data pattern does not match the
pattern in the iotest_pattern registers.
0
3
2
1
0
reserved
reserved
reserved
reserved
reserved.
reserved
reserved
reserved
0
0
0
0
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Register name: config6 – Address: 0x06, Default: 0x0010(DAC3171); 0x0094(DAC3161); 0x0098(DAC3151)
Register
Name
Addr
(Hex)
Default
Value
Bit
Name
Function
config6
0x06
15:8
tempdata
This the output from the chip temperature sensor.
0x00
No RESET
Value
NOTE: when reading these bits the SIF interface must be exteremly
slow, 1MHz range.
7:2
fuse_cntl
These are the values of the blown fuses and are used to determine the
available functionality in the chip.
(*** NOTE ***) These bits are READ_ONLY and allow the user to check
what features have been disabled in the device.
bit5 = 1: Forces Full Word interface
bit4 = 0: reserved
bit3 = 0: reserved
0x10 for
DAC3171;
0x94 for
DAC3161;
0x98 for
DAC3151;
FUSE
controlled
bit2 = 1: Forces Single DAC Mode. Note: This does not force the
channel B in sleep mode. In order to do so, user needs to program
the sleepb SPI bit (config10, bit 5) to "1".
bit1:0 : Forces a different bits size.
“00” 14bit
“01” 12bit
“10” 10bit
“11” 10bit
1
0
reserved
reserved
reserved
reserved
0
0
Register name: config7 – Address: 0x07, Default: 0xFFFF
Register
Name
Addr
(Hex)
Default
Value
Bit
Name
Function
config7
0x07
15:0
alarms_ mask
Each bit is used to mask an alarm. Assertion masks the alarm: bit15 =
alarm_mask_zerochka
0xFFFF
bit14 = alarm_mask_zerochkb
bit13 = alarm_mask_fifoa_collision
bit12 = alarm_mask_fifoa_1away
bit11 = alarm_mask_fifoa_2away
bit10 = alarm_mask_fifob_collision
bit9 = alarm_mask_fifob_1away
bit8 = alarm_mask_fifob_2away
bit7 = alarm_mask_dacclk_gone
bit6 = alarm_mask_dataclk_gone
bit5 = Masks the signal which turns off the DAC output when a clock or
collision occurs. This bit has no effect on the PAD_ALARM output.
bit4 = alarm_mask_iotesta
bit3 = alarm_mask_iotestb
bit2 =
bit1 =
bit0 =
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Register name: config8 – Address: 0x08, Default: 0x4000
Register
Name
Addr
(Hex)
Default
Value
Bit
Name
Function
config8
0x08
15:13 reserved
12:0 qmc_ offseta
reserved
010
The DAC A offset correction. The offset is measured in DAC LSBs.
0x0000
Register name: config9 – Address: 0x09, Default: 0x8000
Register
Name
Addr
(Hex)
Default
Value
Bit
Name
Function
config9
AUTO
SYNC
0x09
15:13 fifo_ offset
This is the starting point for the READ_POINTER in the FIFO block.
The READ_POINTER is set to this location when a sync occurs on the
DACCLK side of the FIFO.
100
12:0
reserved
reserved
0x0000
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Register name: config10 – Address: 0x0A, Default: 0xF080
Register
Name
Addr
(Hex)
Default
Value
Bit
Name
Function
Config10
0x0A 15:12 coarse_ dac
Scales the output current is 16 equal steps.
1111
VrefIO
´ mem_coarse_daca + 1
(
)
Rbias
11
10
9
fuse_ sleep
reserved
Put the fuses to sleep when set high.
0
0
0
0
1
0
0
reserved
reserved
reserved
8
tsense_ sleep
clkrecv_ ena
sleepa
When asserted the temperature sensor is put to sleep.
Turn on the DAC CLOCK receiver block when asserted.
When asserted DACA is put to sleep.
7
6
5
sleepb
When asserted DACB is put to sleep. Note: This bit needs to be
programmed to "1" to save additional power.
4:0
reserved
reserved
00000
Register name: config11 – Address: 0x0B, Default: 0x1111
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config11
0x0B 15:12 reserved
reserved.
reserved.
reserved.
reserved.
0001
0001
0001
0001
11:8
7:4
reserved
reserved
reserved
3:0
Register name: config12 – Address: 0x0C, Default: 0x3A7A
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config12
0x0C 15:14 reserved
13:0 iotest_ pattern0
reserved.
00
This is dataword0 in the IO test pattern. It is used with the seven
other words to test the input data. (*** NOTE ***) This word should
be aligned with the rising edge of SYNC when testing the IO
interface.
0x3A7A
Register name: config13 – Address: 0x0D, Default: 0x36B6
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config13
0x0D 15:14 reserved
13:0 iotest_ pattern1
reserved.
00
This is dataword1 in the IO test pattern. It is used with the seven
other words to test the input data.
0x36B6
Register name: config14 – Address: 0x0E, Default: 0x2AEA
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config14
0x0E 15:14 reserved
13:0 iotest_ pattern2
reserved
00
This is dataword2 in the IO test pattern. It is used with the seven
other words to test the input data.
0x2AEA
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Register name: config15 – Address: 0x0F, Default: 0x0545
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config15
0x0F 15:14 reserved
13:0 iotest_ pattern3
reserved
00
This is dataword3 in the IO test pattern. It is used with the seven
other words to test the input data.
0x0545
Register name: config16 – Address: 0x10, Default: 0x1A1A
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config16
0x10
15:14 reserved
13:0 iotest_ pattern4
reserved
00
This is dataword4 in the IO test pattern. It is used with the seven
other words to test the input data.
0x1A1A
Register name: config17 – Address: 0x11, Default: 0x1616
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config17
0x11
15:14 reserved
13:0 iotest_ pattern5
reserved
00
This is dataword5 in the IO test pattern. It is used with the seven
other words to test the input data.
0x1616
Register name: config18 – Address: 0x12, Default: 0x2AAA
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config18
0x12
15:14 reserved
13:0 iotest_ pattern5
reserved
00
This is datawor6 in the IO test pattern. It is used with the seven
other words to test the input data.
0x2AAA
Register name: config19 – Address: 0x13, Default: 0x06C6
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config19
0x13
15:14 reserved
13:0 iotest_ pattern7
reserved
00
This is dataword7 in the IO test pattern. It is used with the seven
other words to test the input data.
0x06C6
Register name: config20– Address: 0x14, Default: 0x0000
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config20
0x14
15
sifdac_ ena
When asserted the DAC output is set to the value in sifdac. This
can be used for trim setting and other static tests.
0
14
reserved
sifdac
reserved
0
13:0
This is the value that is sent to the DACs when sifdac_ena is
asserted.
0x0000
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Register name: config21– Address: 0x15, Default: 0xFFFF
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config21
0x15
15:0
sleepcntl
This controls what blocks get sent a SLEEP signal when the
PAD_SLEEP pin is asserted. Programming a ‘1’ in a bit will pass
the SLEEP signal to the appropriate block.
0xFFFF
bit15 = DAC A
bit14 = DAC B
bit13 = FUSE Sleep
bit12 = Temperature Sensor
bit11 = Clock Receiver
bit10 = LVDS DATA Receivers
bit9 = LVDS SYNC Receiver
bit8 = PECL ALIGN Receiver
bit7 = LVDS DATACLK Receiver
bit6 = reserved
bit5 = reserved
bit4 = reserved
bit3 = reserved
bit2 = reserved
bit1 = reserved
bit0 = reserved
Register name: config22– Address: 0x16, Default: 0x0000
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
Default Value
Default Value
Default Value
config22
READ
ONLY
0x16
15:0
fa002_ data(15:0)
Lower 16bits of the DIE ID word
Register name: config23– Address: 0x17, Default: 0x0000
Register
Name
Addr
(Hex)
Bit
Name
Function
config23
READ
ONLY
0x17
15:0
fa002_ data(31:16)
Lower middle 16bits of the DIE ID word
Register name: config24– Address: 0x18, Default: 0x0000
Register
Name
Addr
(Hex)
Bit
Name
Function
config24
READ
ONLY
0x18
15:0
fa002_ data(47:32)
Upper middle 16bits of the DIE ID word
Register name: config25– Address: 0x19, Default: 0x0000
Register
Name
Addr
(Hex)
Bit
Name
Function
config25
READ
0x19
15:0
fa002_ data(63:48)
Upper 16bits of the DIE ID word
ONLY
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Register name: config127– Address: 0x7F, Default: 0x0045
Register
Name
Addr
(Hex)
Default
Value
Bit
Name
Function
config127
READ
ONLY/No
RESET
Value
0x7F 15:14 reserved
13:12 reserved
reserved
00
00
00
00
0
reserved
11:10 reserved
reserved
9:8
7
reserved
reserved
titest_voh
titest_vol
vendorid
versionid
reserved
reserved
6
A fixed ‘1’ that can be used to test the Voh at the SIF output.
A fixed ‘0’ that can be used to test the Vol at the SIF output.
Fixed at "01".
1
5
0
4:3
2:0
01
001
Chip version
Synchronization Modes
There are three modes of syncing included in the DAC3151/DAC3161/DAC3171.
•
•
•
NORMAL Dual Sync – The SYNC pin is used to align the input side of the FIFO (write pointers) with the A(0)
sample. The ALIGN pin is used to reset the output side of the FIFO (read pointers) to the offset value.
Multiple chip alignment can be accomplished with this kind of syncing.
SYNC ONLY – In this mode only the SYNC pin is used to sync both the read and write pointers of the FIFO.
There is an asynchronized handoff between the DATACLK and DACCLK when using this mode, therefore it is
impossible to accurately align multiple chips closer than 2 or 3T.
SIF_SYNC – When neither SYNC nor ALIGN are used, a programmable SYNC pulse can be used to sync
the design. However, the same issues as ISTROBE ONLY apply. There is an asynchronized handoff between
the serial clock domain and the two sides of the FIFO. Because of the asynchronous nature of the SIF_SYNC
it is impossible to align the sync up with any sample at the input. Note: SIF_SYNC mode is the only
synchronisation mode supported in the 7-bit interface mode.
Note: When ALIGNP/N are not used, it is recommended to clear the alignrx_ena register (config1, bit 4),
and tie ALIGNP to DIGVDD18 and ALIGNN to GROUND. When SYNCP/N are not used, it is recommended
to clear register lvdssyncrx_ena (config0, bit3), and the unused SYNCP/N pins can be left open or tied to
GROUND.
Alarm Monitoring
DAC3151/DAC3161/DAC3171 includes flexible alarm monitoring that can be used to alert a possible malfunction
scenario. All alarm events can be accessed either through the SIP registers and/or through the ALARM pin.
Once an alarm is set, the corresponding alarm bit in register config5 must be reset through the serial interface to
allow further testing. The set of alarms includes the following conditions:
Zero check alarm
•
Alarm_from_zerochk. Occurs when the FIFO write pointer has an all zeros pattern. Since the write pointer is a
shift register, all zeros will cause the input point to be stuck until the next sync event. When this happens a
sync to the FIFO block is required.
FIFO alarms
•
•
•
•
alarm_from_fifo. Occurs when there is a collision in the FIFO pointers or a collision event is close.
alarm_fifo_2away. Pointers are within two addresses of each other.
alarm_fifo_1away. Pointers are within one address of each other.
alarm_fifo_collision. Pointers are equal to each other.
Clock alarms
•
•
•
clock_gone. Occurs when either the DACCLK or DATACLOCK have been stopped.
alarm_dacclk_gone. Occurs when the DACCLK has been stopped.
alarm_dataclk_gone. Occurs when the DATACLK has been stopped.
Pattern checker alarm
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•
alarm_from_iotest. Occurs when the input data pattern does not match the pattern key.
To prevent unexpected DAC outputs from propagating into the transmit channel chain,
DAC3151/DAC3161/DAC3171 includes a feature that disables the outputs when a catastrophic alarm occurs.
The catastrophic alarms include FIFO pointer collision, the loss DACCLK or the loss of DATACLK. When any of
these alarms occur the internal TXenable signal is driven low, causing a zeroing of the data going to the DAC in
<10T. One caveat is if both clocks stop, the circuit cannot determine clock loss so no alarms are generated;
therefore, no zeroing of output data occurs.
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REVISION HISTORY
Changes from Original (August 2013) to Revision A
Page
•
Changed from Product Preview to Production Data ............................................................................................................. 1
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2013
PACKAGING INFORMATION
Orderable Device
DAC3151IRGCR
DAC3151IRGCT
DAC3161IRGC25
DAC3161IRGCR
DAC3161IRGCT
DAC3171IRGC25
DAC3171IRGCR
DAC3171IRGCT
DAC3171IRHBR
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGC
64
64
64
64
64
64
64
64
32
2000
Green (RoHS
& no Sb/Br)
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Call TI
DAC3151I
ACTIVE
PREVIEW
ACTIVE
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RHB
250
25
Green (RoHS
& no Sb/Br)
DAC3151I
DAC3161I
DAC3161I
DAC3161I
DAC3171I
DAC3171I
DAC3171I
Green (RoHS
& no Sb/Br)
2000
250
25
Green (RoHS
& no Sb/Br)
ACTIVE
Green (RoHS
& no Sb/Br)
PREVIEW
ACTIVE
Green (RoHS
& no Sb/Br)
2000
250
Green (RoHS
& no Sb/Br)
ACTIVE
Green (RoHS
& no Sb/Br)
PREVIEW
TBD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2013
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Aug-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC3151IRGCR
DAC3151IRGCT
DAC3161IRGCR
DAC3161IRGCT
DAC3171IRGCR
DAC3171IRGCT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGC
RGC
RGC
RGC
RGC
RGC
64
64
64
64
64
64
2000
250
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
1.5
1.5
1.5
1.5
1.5
1.5
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
Q2
Q2
Q2
Q2
Q2
Q2
2000
250
2000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Aug-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC3151IRGCR
DAC3151IRGCT
DAC3161IRGCR
DAC3161IRGCT
DAC3171IRGCR
DAC3171IRGCT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGC
RGC
RGC
RGC
RGC
RGC
64
64
64
64
64
64
2000
250
336.6
336.6
336.6
336.6
336.6
336.6
336.6
336.6
336.6
336.6
336.6
336.6
28.6
28.6
28.6
28.6
28.6
28.6
2000
250
2000
250
Pack Materials-Page 2
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