DAC161S055CISQX/NOPB [TI]
DAC161S055 Precision 16-Bit, Buffered Voltage-Output DAC; DAC161S055精密16位，缓冲电压输出DAC
| 型号： | DAC161S055CISQX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DAC161S055 Precision 16-Bit, Buffered Voltage-Output DAC |
| 文件： | 总27页 (文件大小：918K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC161S055
www.ti.com
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
DAC161S055 Precision 16-Bit, Buffered Voltage-Output DAC
Check for Samples: DAC161S055
1
FEATURES
DESCRIPTION
The DAC161S055 is a precision 16-bit, buffered
voltage output Digital-to-Analog Converter (DAC) that
operates from a 2.7V to 5.25V supply with a separate
I/O supply pin that operates down to 1.7V. The on-
chip precision output buffer provides rail-to-rail output
swing and has a typical settling time of 5 µsec. The
external voltage reference can be set between 2.5V
and VA (the analog supply voltage), providing the
widest dynamic output range possible.
2
•
•
•
•
16-bit DAC with a Two-buffer SPI Interface
Asynchronous Load DAC and Reset Pins
Compatibility with 1.8V Controllers
Buffered Voltage Output with Rail-to-Rail
Capability
•
•
•
Wide Voltage Reference Range of +2.5V to VA
Wide Temperature Range of −40°C to +105°C
Packaged in a 16-pin WQFN
The 4-wire SPI compatible interface operates at clock
rates up to 20 MHz. The part is capable of Diasy
Chain and Data Read Back. An on board power-on-
reset (POR) circuit ensures the output powers up to a
known state.
APPLICATIONS
•
•
•
•
•
•
•
Process Control
Automatic Test Equipment
Programmable Voltage Sources
Communication Systems
Data Acquisition
The DAC161S055 features a power-up value pin
(MZB), a load DAC pin (LDACB) and a DAC clear
(CLRB) pin. MZB sets the startup output voltage to
either GND or mid-scale. LDACB updates the output,
allowing multiple DACs to update their outputs
simultaneously. CLRB can be used to reset the
output signal to the value determined by MZB.
Industrial PLCs
Portable Battery Powered Instruments
The DAC161S055 has a power-down option that
reduces power consumption when the part is not in
use. It is available in a 16-lead WQFN package.
KEY SPECIFICATIONS
•
•
•
•
•
•
Resolution (Specified Monotonic) 16 bits
INL ±3 LSB (max)
Very Low Output Noise 120 nV/√Hz (typ)
Glitch Impulse 7 nV-s (typ)
Output Settling Time 5 µs (typ)
Power Consumption 5.5 mW at 5.25 V (max)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2012, Texas Instruments Incorporated
DAC161S055
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
www.ti.com
BLOCK DIAGRAM
VA Referenced Input
MZB VA
VDDIO
CLRB
VREF
CLR
COMMAND
SDO
CLR PRE
LOAD
PRE
LOAD
CLR
16
16
FIFO/
SPI/
INTERFACE
VOUT
SDI
BUF
R-DAC
DAC
REG
Bypass
PRE
REG
SCLK
CSB
10k
WRAL
WRUP
COMMANDS
GND
LDACB
CONNECTION DIAGRAM
1
2
3
4
12
11
10
9
VA
CSB
SDI
VOUT
NC
WQFN 16
SCLK
SDO
NC
DAP
PIN DESCRIPTIONS
Pin #
Pin Name
ESD Structure
Type
Function and Connection
WQFN-16
ESD
Clamp
VDDIO
16
Power
Power
SPI, CLRB, LDACB Supply Voltage.
ESD
Clamp
VA
1
Analog Supply Voltage.
2
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: DAC161S055
DAC161S055
www.ti.com
Pin Name
VOUT
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
PIN DESCRIPTIONS (continued)
Pin #
WQFN-16
ESD Structure
Type
Function and Connection
TO OUT DRIVE
2
Analog Output DAC output.
VREF
GND
SDI
6
7
Analog Input
Ground
Voltage Reference Input.
Ground (Analog and Digital).
11
Digital Input
SPI data input .
Chip select signal for SPI interface. On the falling edge of
CSB the chip begins to accept data and output data with
the SCLK signal. This pin is active low.
CSB
12
10
Digital Input
Digital Input
SCLK
Serial data clock for SPI Interface.
TO OUT DRIVE
SDO
9
Digital Output Data Out for daisy chain or data read back verification.
Load DAC signal. This signal transfers DAC data from
LDACB
CLRB
MZB
13
14
15
Digital Input
Digital Input
Digital Input
the SPI input register to the DAC output register. The
signal is active low.
Asynchronous Reset. If this pin is pulled low, the output
will be updated to its power up condition set by the MZB
pin. This pin is active low.
Power up at Zero/Mid-scale. Tie this pin to GND to power
up to Zero or to VA to power up to mid-scale.
No connect pins. Connect to GND in board layout will
result in the lowest amount of coupled noise.
NC
3,4,5,8
DAP
Attach die attach paddle to GND for best noise
performance.
DAP
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: DAC161S055
DAC161S055
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1) (2)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VA
−0.3V to 6.0V
−0.3V to VA+0.3V
6V, −0.3V
Supply Voltage VDDIO
Any pin relative to GND
Voltage on MZB or VREF Input Pin(3)
−0.3V to VA+0.3V
−0.3V to VDDIO+0.3V
−0.3V to VA+0.3V
−0.3V to VDDIO+0.3V
5mA
(3)
Voltage on any other Input Pin
(3)
Voltage on VOUT
(3)
Voltage on SDO
(3)
Input Current at Any Pin
Output Current Source or Sink by Vout
Output Current Source or Sink by SDO
Total Package Input and Output Current
10mA
3mA
20mA
ESD Susceptibility
Human Body Model
Machine Model
3000V
250V
Charged Device Model (CDM)
1250V
Storage Temperature Range
−65°C to +150°C
Junction Temperature
+150°C
For soldering specifications: see product folder at www.ti.com and SNOA549
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) The Electrical characteristics tables list specifications under the listed Recommended Conditions except as otherwise modified or
specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are NOT specified.
(3) When the input voltage (VI) at any pin exceeds the power supplies (VI < GND or VI > VDD) the current at that pin must be limited to
5mA and VI has to be within the Absolute Maximum Rating for that pin. The 20mA package input current rating limits the number of pins
that can safely exceed the power supplies with current flow to four.
(1) (2)
RECOMMENDED OPERATING CONDITIONS
Operating Temperature Range
−40°C to +105°C
+2.7V to 5.25V
+1.7 V to VA
+2.5V to VA
Supply Voltage, VA
Supply Voltage VDDIO
Reference Voltage VREF
Digital Input Voltage
0 to VDDIO
Output Load
0 to 200 pF
Package Thermal Resistance
(3)
θJA
θJC
41°C/W
6.5°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) The Electrical characteristics tables list specifications under the listed Recommended Conditions except as otherwise modified or
specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are NOT specified.
(3) The maximum power dissipation is a function of TJ(MAX) and θJA. The maximum allowable power dissipation at any ambient temperature
is PD=(TJ(MAX)-TA)/θJA
4
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: DAC161S055
DAC161S055
www.ti.com
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
ELECTRICAL CHARACTERISTICS
The following specifications apply for VA = 2.7V to 5.25V, VDDIO = VA, VREF = 2.5V to VA, RL = 10k to GND, CL = 200 pF to
GND, fSCLK = 20 MHz, input code range 512 to 65023. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits apply to TA
(2) (3)
= 25°C, unless otherwise specified.(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
STATIC PERFORMANCE
N
Resolution
16
Bits
LSB
LSB
No load. From code 512 to
Full Scale - 512. VA=5V, VREF=4.096V
± 1
±3
INL
Integral Non-Linearity
No load. From code 512 to
Full Scale - 512. VA=5V, VREF=4.096V
-1
1.1
DNL
Differential Non-Linearity
ZE
FSE
OE
Zero Code Error
Full Scale Error
Offset Error
4
15
15
11
mV
mV
-15
-11
±1
±4
mV
Offset Error Drift
Gain Error
µV/°C
% of FS
mV
GE
No load. From code 512 to
Full Scale - 512. VA=5V, VREF=4.096V
±0.05
-25
25
Gain Temperature Coefficient
No load. From code 512 to
± 2
ppm FS/°C
Full Scale - 512. VA=5V, VREF=4.096V
REFERENCE INPUT CHARACTERISTICS
VREF
Reference Input Voltage Range
Reference Input Impedance
VA = 2.7V to 5.25V
No load.
2.5
VA
V
12.5
kΩ
ANALOG OUTPUT CHARACTERISTICS
Output Voltage Range
0.015
VA-0.04
V
DC Output Impedance
2
3
Ω
VA=3V, IOUT=200 µA; VREF=2.5
VA=3V, IOUT=1mA; VREF=2.5
VA=5V, IOUT=200 µA; VREF=4.096
VA=5V, IOUT=1mA; VREF=4.096
VA=3V, IOUT=200 µA; VREF=2.5
VA=3V, IOUT=1mA; VREF=2.5
VA=5V, IOUT=200 µA; VREF=4.096
VA=5V, IOUT=1mA; VREF=4.096
Parallel R = 10KΩ
4
ZCO
Zero Code Output
mV
V
4
4
2.495
2.494
4.091
4.089
500
15
FSO
CL
Full Scale Output
Maximum Capacitive Load
pF
µF
Series R = 50Ω
RL
ISC
tPU
Minimum Resistive Load
Short Circuit Current
Power-up Time
10
kΩ
mA
ms
VA = +5V, VREF=4.096
From Power Down Mode
353
25
ANALOG OUTPUT DYNAMIC CHARCTERISTICS
SR
ts
Voltage Output Slew Rate
Positive and negative
2
5
V/µs
µs
Voltage Output Settling Time
1/4 scale to 3/4 scale VREF= VA = +5V,
settle to ±1 LSB.
Digital Feedthrough
Code 0, all digital inputs from GND to
VDDIO
1
7
nV-s
nV-s
Major Code Transition Analog
Glitch Impulse
VA=5V, VREF=2.5V. Transition from mid-
scale − 1LSB to mid-scale.
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) The Electrical characteristics tables list specifications under the listed Recommended Conditions except as otherwise modified or
specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are NOT specified.
(3) Typical values represent most likely parametric norms at specific conditions (Example VA; specific temperature) and at the
recommended Operating Conditions at the time of product characterizations and are NOT specified.
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: DAC161S055
DAC161S055
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
The following specifications apply for VA = 2.7V to 5.25V, VDDIO = VA, VREF = 2.5V to VA, RL = 10k to GND, CL = 200 pF to
GND, fSCLK = 20 MHz, input code range 512 to 65023. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits apply to TA
= 25°C, unless otherwise specified.(1) (2) (3)
Symbol
Parameter
Output Noise
Integrated Output Noise
DIGITAL INPUT CHARACTERISTICS
Conditions
Spot noise at 20 kHz
Min
Typ
120
18
Max
Units
nV/√Hz
µV
1Hz to 10 kHz
IIN
Input Current
±1
0.8
0.8
0.4
µA
V
VIL
Input Low Voltage
VDDIO=5V
VDDIO=3V
VDDIO=1.8V
VDDIO=5V
VDDIO=3V
VDDIO=1.8V
VA=5V
2.1
2.1
1.4
VIH
Input High Voltage
V
VILMZB
MZB Input Low Voltage
0.8
0.8
V
V
VA=3V
VA=5V
2.1
2.1
V
VIHMZB
CIN
MZB Input High Voltage
Input Capacitance
VA=3V
V
4
pF
DIGITAL OUTPUT CHARACTERISTICS
VOL
Output Low Voltage
Isink=200 µA; VDDIO>3V
Isink=2mA;VDDIO>3V
400
400
400
400
mV
V
Isink=200 µA; VDDIO=1.8V
Isink=2mA;VDDIO=1.8V
Isink=200 µA; VDDIO>3V
Isink=2mA;VDDIO>3V
VOH
Output High Voltage
VDDIO - 0.2
VDDIO - 0.2
VDDIO - 0.2
1.15
Isink=200 µA; VDDIO=1.8V
Isink=2mA;VDDIO=1.8V
lOZH, lOZL TRI-STATE Leakage Current
COUT TRI-STATE Output Capacitance
POWER REQUIREMENTS
<1n
4
±1µ
A
pF
VA
VDDIO
IVA
Analog Supply Voltage Range
2.7
1.7
5.25
VA
1
V
V
Digital Supply Voltage Range
VA Supply Current
No load. SCLK Idle. All digital inputs at
GND or VDDIO. VA=5V
0.75
0.62
mA
mA
No load. SCLK Idle. All digital inputs at
GND or VDDIO. VA=3.3V
1
IREF
IPDVA
IPDVO
Reference Current
350
3
VA Power Down Supply Current All digital inputs at GND or VDDIO
0.5
VDDIO Power Down Supply
Current
All digital inputs at GND or VDDIO
1
µA
IPDVR
VREF Power Down Supply
Current
1
6
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: DAC161S055
DAC161S055
www.ti.com
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
DIGITAL INTERFACE TIMING CHARACTERISTICS
These specifications apply for VA = 2.7V to 5.25V, VDDIO = 1.7V to VA, CL = 200 pF. Boldface limits apply for TA = −40°C
to 105°C. All other limits apply to TA = 25°C, unless otherwise specified.
Symbol
Parameter
Conditions
VDDIO=1.7V to 2.7V
Min
0
Typ
Max
10
Units
fSCLK
MHz
SCLK Frequency
VDDIO=2.7V to 5.25V
0
20
tH
tL
SCLK High Time
SCLK Low Time
15
20
25
25
75
40
tCSB
VDDIO=1.7V to 2.7V
VDDIO=2.7V to 5.25V
CSB High Pulse width
tCSS
tCSH
CSB Set-up Time Prior to SCLK Rising
edge
10
CSB Hold Time after the 24th Falling
Edge of SCLK
0
tZSDO
CSB Falling Edge to SDO Valid
CSB Rising Edge to SDO HiZ
VDDIO=1.8V
VDDIO=3V
VDDIO=5V
VDDIO=1.8V
VDDIO=3V
VDDIO=5V
40
10
6
tSDOZ
75
40
27
5
ns
tCLRS
CSB Rising Edge to CLRB Falling
Edge
CLRB must not transition anytime CSB
is low.
tLDACS
CSB Rising Edge to LDACB Falling
Edge
LDACB must not transition anytime CSB
is low.
5
tLDAC
tCLR
tDS
LDACB Low Time
CLRB Low Time
10
10
2.5
2.5
10
SDI Data Set-up Time prior to SCLK
Rising Edge
tDH
tDO
SDI Data Hold Time after SCLK Rising
Edge
0
SDO Output Data Valid
VDDIO=1.7
VDDIO=3.3
VDDIO=5
62
25
15
TIMING DIAGRAMS
1/f
SCLK
SCLK
1
2
21
22
23
24
t
L
t
H
CS
t
CSB
SDI
PD0
D23
D0
SDO
PD23
PD0
Figure 1. DAC161S055 Input/Output Waveforms
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: DAC161S055
DAC161S055
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
www.ti.com
CSB 50%
50%
50%
SCLK
CSB
50%
50%
50%
50%
t
LDACB
t
t
t
LDAC
CSH
CSS
LDACS
50%
50%
50%
SCLK
SDO
CSB
SDO
t
DO
t
t
ZSDO
SDOZ
50%
CSB 50%
CLRB
SCLK
50%
50%
SDI
t
t
t
CLRS
t
DS
DH
CLR
Figure 2. Timing Parameter Specifics
TRANSFER CHARACTERISTICS
FSE
65535 x VA
65536
GE = FSE - ZE
FSE = GE + ZE
OUTPUT
VOLTAGE
ZE
0
0
65535
DIGITAL INPUT CODE
Figure 3. Input/Output Transfer Characteristic
8
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: DAC161S055
DAC161S055
www.ti.com
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
SPECIFICATION DEFINITIONS
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB, which is VREF / 65536.
DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital
inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus.
FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFFh) loaded
into the DAC and the value of VREF x 65535 / 65536.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and
Full-Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error.
GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register
changes. It is specified as the area of the glitch in nanovolt-seconds.
INTEGRAL NON_LINEARITY (INL) is a measure of the deviation of each individual code from a straight line
through the input to output transfer function. The deviation of any given code from this straight line is measured
from the center of that code value. The end point method is used. INL for this product is specified over a limited
range, per the Electrical Tables.
LEAST SIGNIFICANT BIT (MSB) is the bit that has the smallest value or weight of all bits in a word. This value
is LSB = VREF / 2n where VREF is the reference voltage for this product, and "n" is the DAC resolution in bits,
which is 16 for the DAC161S055.
MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output
stability maintained, although some ringing may be present.
MONOTONICITY is the condition of being monotonic, where the DAC output never decreases when the input
code increases.
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is
1/2 of VREF
.
OFFSET ERROR is the difference between zero voltage and a where a straight line fit to the actual transfer
function intersects the y axis.
SETTLING TIME is the time for the output to settle to within 1 LSB of the final value after the input code is
updated.
WAKE-UP TIME is the time for the output to recover after the device is commanded to the active mode from any
of the power down modes.
ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 0000h has been
entered.
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: DAC161S055
DAC161S055
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS
DNL at VA = 3.0V
DNL at VA = 5.0V
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
0
16,384 32,768 49,152 65,536
0
16,384 32,768 49,152 65,536
OUTPUT CODE
OUTPUT CODE
Figure 4.
Figure 5.
INL at VA = 3.0V
INL at VA = 5.0V
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
0
16,384 32,768 49,152 65,536
0
16,384 32,768 49,152 65,536
OUTPUT CODE
OUTPUT CODE
Figure 6.
Figure 7.
DNL vs. Supply
INL vs. Supply
0.8
0.7
1.0
0.5
-INL
+INL
0.4
-DNL
+DNL
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-0.5
-1.0
2.65
3.30
3.95
4.60
5.25
2.65
3.30
3.95
4.60
5.25
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 8.
Figure 9.
10
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: DAC161S055
DAC161S055
www.ti.com
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
DNL vs. VREF, VA=5V
INL vs. VREF, VA=5V
0.8
0.7
1.100
0.576
0.051
-0.475
-1.000
0.4
-INL
+INL
-DNL
+DNL
0.2
0.0
-0.2
-0.4
-0.6
-0.8
2.00 2.65 3.30 3.95 4.60 5.25
2.00 2.65 3.30 3.95 4.60 5.25
V
REF
(V)
V
REF
(V)
Figure 10.
Figure 11.
DNL vs. Temperature, VA=5V, VREF=4.096
0.8
INL vs. Temperature, VA=5V, VREF=4.096
1.00
0.7
0.75
0.4
0.50
-DNL
-DNL
+DNL
+DNL
0.25
0.2
0.0
0.00
-0.25
-0.50
-0.75
-0.2
-0.4
-0.6
-0.8
-1.00
-50 -30 -10 10 30 50 70 90 110
-50 -30 -10 10 30 50 70 90 110
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12.
Figure 13.
Zero Code Error vs. IOUT
Full Scale Error vs. IOUT
4.4
3.3
2.2
1.1
0.0
-0.08
VA=3V
VA=5V
VA=3V
VA=5V
-0.10
-0.12
-0.14
-0.16
-0.18
200
400
600
800
1,000
200
400
600
800
1,000
LOAD CURRENT (ꢀA)
LOAD CURRENT (ꢀA)
Figure 14.
Figure 15.
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: DAC161S055
DAC161S055
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
IVA vs VA
IVA vs TEMPERATURE
890
840
790
740
690
640
920
690
460
230
0
NO CLOCK, 5V
CLOCKING, 5V
NO CLOCK, 3.3V
CLOCKING, 3.3V
3
4
5
6
-50
-10
30
70
110
110
40
TEMPERATURE °C
SUPPLY VOLTAGE (V
)
A
Figure 16.
Figure 17.
IREF vs VREF
IREF vs TEMPERATURE
380
335
290
245
200
360
240
120
0
NO CLOCK, 5V
CLOCKING, 5V
NO CLOCK, 3.3V
CLOCKING, 3.3V
1.8
2.4
3.0
3.6
4.2
-50
-10
30
70
TEMPERATURE °C
SUPPLY VOLTAGE (V
)
REF
Figure 18.
Figure 19.
Settling Time
POR
3.60
2.95
2.30
1.65
1.00
3.5
5
4
3
2
1
0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VA
VOUT
VOUT
CSB
100
101
102
103
104
0
10
20
30
TIME (ꢀS)
TIME (ms)
Figure 20.
Figure 21.
12
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: DAC161S055
DAC161S055
www.ti.com
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
5V Glitch Response
1.275
1.270
1.265
1.260
1.255
1.250
1.245
1.240
Mid Scale-1 to Mid Scale
2,000
2,500
3,000
3,500
4,000
TIME (ns)
Figure 22.
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: DAC161S055
DAC161S055
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
www.ti.com
FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE OVERVIEW
The DAC161S055 uses a resistor array to convert the input code to an analog signal, which in turn is buffered by
the rail-to-rail output amplifier. The resistor array is factory trimmed to achieve 16-bit accuracy.
An SPI interface shifts the input codes into the device. The acquired input code is stored in the PREREG
register. After the input code is transferred to the DACREG register it affects the state of the resistor array and
the output level of the DAC. The transfer can be initiated by the type of write command used, by a software
LDAC command or by the state of the LDACB pin.
The user can control the power up state of the output using the MZB pin and the power down state of the output
using the CONFIG register. Additionally, there are external pins and CONFIG register bits that also control
clearing the DAC.
NOTE
Although the DAC161S055 is a single channel device, the instruction set is for
multichannel DACs. The user must address channel 0 (A2,A1,A0={000}).
OUTPUT AMPLIFIER
The output buffer amplifier is a rail to rail type which buffers the signal produced by the resistor array and drives
the external load. All amplifiers, including rail to rail amplifiers, exhibit a loss of linearity as the output nears the
power rails (in this case GND and VA). Thus the linearity of the part is specified over less than the full output
range. The user can program the CONFIG register to power down the amplifier and either place it in the high
impedance state (HiZ), or have the output terminated by an internal 10 kΩ pull-down resistor.
REFERENCE
An external reference source is required to produce an output. The reference input is not internally buffered and
presents a resistive load to the external source. Loading presented by the VREF pin varies by about 12.5%
depending on the input code. Thus a low impedance reference should be used for best results.
SERIAL INTERFACE
The 4-wire interface is compatible with SPI, QSPI and MICROWIRE, as well as most DSPs. See the TIMING
DIAGRAMS for timing information about the read and write sequences. The serial interface is the four signals
CSB, SCLK, SDI and SDO.
A bus transaction is initiated by the falling edge of the CSB. Once CSB is low, the input data is sampled at the
SDI pin by the rising edge of the SCLK. The output data is put out on the SDO pin on the falling edge of SCLK.
At least 24 SCLK cycles are required for a valid transfer to occur. If CSB is raised before 24th rising edge of the
SCLK, the transfer is aborted. If the CSB is held low after the 24th falling edge of the SCLK, the data will
continue to flow through the FIFO and out the SDO pin. Once CSB transitions high, the internal controller will
decode the most recent 24 bits that were received before the rising edge of CSB. The DAC will then change
state depending on the instruction sent and the state of the LDACB pin.
CSB
SCLK
2
3
4
23
24
1
SDI
D23 D22
D21 D20
D1 D0
HiZ
HiZ
SDO
Preceeding Transfer Data
14
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: DAC161S055
DAC161S055
www.ti.com
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
The acquired data is shifted into an internal 24 bit shift register (MSB first) which is configured as a 24 bit deep
FIFO. As the data is being shifted into the FIFO via the SDI pin, the prior contents of the register are being
shifted out through the SDO output. While CSB is high, SDO is in a high-Z state. At the falling edge of CSB, SDO
presents the MSB of the data present in the shift register. SDO is updated on every subsequent falling edge of
SCLK (note — the first SDO transition will happen on the first falling edge AFTER the first rising edge of SCLK
when CSB is low).
The 24 bits of data contained in the FIFO are interpreted as an 8 bit COMMAND word followed by 16 bits of
DATA. The general format of the 24 bit data stream is shown below. The full Instruction Set is tabulated in
Section INSTRUCTION SET.
CSB
COMMAND
8 bits
DATA
16 bits
SDI
1.4.1 SPI Write
SPI write operation is the simplest transaction available to the user. There is no handshaking between master
and the slave (DAC161S055), and the master is the source of all signals required for communication: SCLK,
CSB, SDI. The format of the data transfer is described in the section 1.4. The user instruction set is shown in
Section INSTRUCTION SET.
SPI Read
The read operation requires all 4 wires of the SPI interface: SCLK, SCB, SDI, SDO. The simplest READ
operation occurs automatically during any valid transaction on the SPI bus since SDO pin of DAC161S055
always shifts out the contents of the internal FIFO. Therefore the user can verify the data being shifted in to the
FIFO by initiating another transaction and acquiring data at SDO. This allows for verification of the FIFO contents
only.
The 3 internal registers (PREREG, DACREG, CONFIG) can be accessed by the user through the Register Read
commands: RDDO, RDIN, RDCO respectively (see Section INSTRUCTION SET). These operations require 2
SPI transaction to recover the register data. The first transaction shifts in the Register Read command; an 8 bit
command byte followed by 16 bit “dummy” data. The Register Read command will cause the transfer of contents
of the internal register into the FIFO. The second transaction will shift out the FIFO contents; an 8 bit command
byte (which is a copy of previous transaction) followed by the register data. The Register Read operation is
shown in the figure below.
CSB
Don‘t Care
16 bits
RDDO/RDCO/RDIN
8 bits
Next Data
16 bits
Next Command
8 bits
SDI
HiZ
HiZ
HiZ
RDDO/RDCO/RDIN
8 bits
REG DATA
16 bits
Prior Command
8 bits
Prior Data
16 bits
SDO
SPI Daisy Chain
It is possible to control multiple DACs or other SPI devices with a single master equipped with one SPI interface.
This is accomplished by connecting the DACs in a Daisy Chain. The scheme is depicted in the figure below. An
arbitrary length of the chain and an arbitrary number of control bits for other devices in the chain is possible since
individual DAC devices do not count the data bits shifted in. Instead, they wait to decode the contents of their
respective shift registers until CSB is raised high.
A typical bus cycle for this scheme is initiated by the falling CSB. After the 24 SCLK cycles new data starts to
appear at the SDO pin of the first device in the chain, and starts shifting into the second device. After 72 SCLK
cycles following the falling CSB edge, all three devices in this example will contain new data in their input shift
registers. Raising CSB will begin the process of decoding data in each DAC. When in the Daisy Chain the full
READ and WRITE capability of every device is maintained.
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: DAC161S055
DAC161S055
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
www.ti.com
SYNC
CLK
(1)
(2)
(3)
SPI/QSPI
MICROWIRE
CSB
CSB
CSB
MASTER
SCLK
SCLK
SCLK
MOSI
SDI SDO
SDI SDO
SDI SDO
DAC161S055
DAC161S055
DAC161S055
MISO
A sample of SPI data transfer appropriate for a 3 DAC Daisy Chain is shown in the figure below.
72 Clock Cycles
SYNC
MOSI
DATA (3)
DATA (1)
DATA (2)
POWER-UP DEFAULT OUTPUT
It is possible to power up the DAC with the output either at GND or midscale. This functionality is achieved by
connecting the MZB pin either to GND or to VA (note, the MZB pin is referenced to VA, not VDDIO). Usually this
function is hardwired in the application, but can also be controlled by a GPIO pin of the µC. To power up with
output at zero, tie the MZB pin low. To power up with output at midscale, tie MZB high. The MZB pin is level
sensitive.
CHANGING DAC OUTPUT
There are multiple different ways to affect the DAC output. The CONFIG register can be changed so that a write
to the PREREG is seen instantly at the output. The LDAC function or LDACB pin updates the output instantly.
Finally, the type of write command (WRUP, WRAL, WR) can affect if the output updates instantly or not.
Write-Through and Write-Block Modes
Using the SWB bit of the CONFIG register, the user can set the part in WRITE-BLOCK or WRITE-THROUGH
mode.
If the DAC channel is configured in the WRITE-BLOCK mode (SWB=0, default), the DAC input DATA is held in
the PREREG until the controller forces the transfer of DATA from PREREG to DACREG register. Only DATA in
DACREG register is converted to the equivalent analog output. The transfer from PREREG into DACREG can be
forced by both software and hardware LDAC commands. The Data Writing commands WRUP and WRAL update
both PREREG and DACREG at the same time regardless of the channel mode. WRITE-BLOCK mode is used in
multi device or multi channel applications. A user can preload all DAC channels with desired data, in multiple SPI
transactions, and then issue a single software LDAC command (or toggle the LDACB pin) to simultaneously
update all analog outputs.
If the DAC channel is configured in WRITE-THROUGH mode (SWB=1) the controller updates both PREREG and
DACREG registers simultaneously. Therefore in WRITE-THROUGH mode the channel output is updated as soon
as the SPI transfer is completed i.e. upon the rising edge of CSB.
LDAC Function
The LDACB (Load DAC) pin provides a easy way to synchronize several DACs and update the output without
any SPI latency. If the LDACB is asserted low, the content of the PREREG register is instantaneously moved
into the DACREG register. The LDACB pin is level sensitive. If the LDACB pin is held low continuously, the DAC
output will update as soon as the CSB pin goes high.
16
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: DAC161S055
DAC161S055
www.ti.com
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
CSB
SCLK
2
3
4
23
24
1
LDACB
LDACB must not transition here (may be
held low for whole transaction)
The DAC Configuration command LDAC (see Section INSTRUCTION SET below) will also update the DAC
output as soon as it is received. The effect of hardware LDACB or software LDAC is the same i.e. data is
transferred from the PREREG to DACREG and output of the DAC is updated.
Write Commands
There are three write commands available in the DAC command set. Issuing a WR command causes the DAC to
update either the PREREG or the DACREG depending on the setting of the SWB bit (see Section Write-Through
and Write-Block Modes). Issuing a WRUP command causes the specified channels output (for multiple channel
parts) to update immediately, regardless of the SWB bit setting. Issuing a WRAL command causes all channels
(for multiple channel parts) to update immediately with the same data, regardless of the SWB bit setting.
CLEAR FUNCTION
The CLRB pin provides a easy way to reset the DAC161S055 output. If the CLRB pin goes low, VOUT
instantaneously slews to the value indicated by the MZB pin, either zero or midscale. The CLRB pin is level
sensitive.
CSB
SCLK
CLRB
2
3
4
23
24
1
CLRB must not be asserted here
Clear function can also be accessed via the software instruction CLR, see Section INSTRUCTION SET below.
The effect of hardware CLRB or software CLR is the same.
POWER ON RESET
An on-chip power on reset circuit (POR) ensures that the DAC always powers on in the same state. The
registers will be loaded with the defaults shown in Section INSTRUCTION SET. The output state will be
controlled by the state of the MZB pin.
POWER DOWN
Power down is achieved by writing the PD instruction and setting the appropriate bit to a logic '1'. In the PD
command, it is possible to specify if the output is left in a high impedance (HIZ) state or if it is pulled to GND
through a 10K resistor. During power down, the output amplifier is disabled and the resistor ladder is
disconnected from Vref. The SPI interface remains active. To exit power down, write the PD command again,
setting the appropriate bit to a logic '0'. Note that the SPI interface and the registers are all active during power
down.
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: DAC161S055
DAC161S055
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
www.ti.com
INTERNAL REGISTERS
There are 3 registers that are accessible to the user. The data registers (PREREG and DACREG) are both
readable and writable from the command set. The CONFIG register is only readable from the command set. Bits
in the CONFIG register are set by the commands detailed in Section INSTRUCTION SET.
PREREG: DAC Preload Data Register(16Bits)
R/W
PRD15
Bit15
R/W
PRD14
Bit14
R/W
PRD13
Bit13
R/W
PRD12
Bit12
R/W
PRD11
Bit11
R/W
PRD10
Bit10
R/W
PRD9
Bit9
R/W
PRD8
Bit8
MSB
R/W
PRD7
Bit7
R/W
PRD6
Bit6
R/W
PRD5
Bit5
R/W
PRD4
Bit4
R/W
PRD3
Bit3
R/W
PRD2
Bit2
R/W
PRD1
Bit1
R/W
PRD0
Bit0
LSB
Bit15–0:
16 bit data word to be converted. Bit 15 has a weight of 1/2*Vref. Bit 0 has a weight of Vref/216
.
DACREG: DAC Output Data Register(16Bits)
R/W
IND15
Bit15
R/W
IND14
Bit14
R/W
IND13
Bit13
R/W
IND12
Bit12
R/W
IND11
Bit11
R/W
IND10
Bit10
R/W
IND9
Bit9
R/W
IND8
Bit8
MSB
R/W
IND7
Bit7
R/W
IND6
Bit6
R/W
IND5
Bit5
R/W
IND4
Bit4
R/W
IND3
Bit3
R/W
IND2
Bit2
R/W
IND1
Bit1
R/W
IND0
Bit0
LSB
Bit15–0:
16 bit data word to be converted. Bit 15 has a weight of 1/2*Vref. Bit 0 has a weight of Vref/216
.
CONFIG: DAC Configuration Reporting Register (8 Bits)
R/W
IND7
Bit7
R/W
IND6
Bit6
R/W
IND5
Bit5
R/W
IND4
Bit4
R/W
IND3
Bit3
R/W
IND2
Bit2
R/W
IND1
Bit1
R/W
IND0
Bit0
LSB
Bit7–3:
Bit2:
Reserved. Read value is undefined and should be discarded.
SWB: Set Write Block bit
0: Channel is in WRITE THROUGH mode.
1: Channel is in WRITE BLOCK mode.
0: Channel is either active or SEL_HIZ is set.
Bit1:
Bit0:
1: Channel is powered down and output is terminated by a 10K resistor to GND.
0: Channel is either active or SEL_10K is set.
1: Channel is powered down and output is in high impedance state.
18
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: DAC161S055
DAC161S055
www.ti.com
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
INSTRUCTION SET
The instruction set for the DAC161S055 is common to the family of single and multi channel devices (DAC16xS055). The DAC161S055 has only a single
channel — Channel 0.
NOTE
DATA WRITING and REGISTER READING instructions encode the channel address as a binary triplet (A2,A1,A0) as the
last three LSBs of the command byte. DAC CONFIGURATION instructions encode the channel selection by a bit set in the
data bytes. For example, when executing the LDAC instruction a payload of {0100 0001} in the least significant byte of the
instruction indicates channels 6 and 0 are targeted.
MNEMONIC
Command Byte[7:0]
DATA[15:8]
DATA [7:0]
Description
DEFAULT
DAC Configuration
NOP
CLR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
No Operation
Clear internal registers, return to Power-Up
default state
LDAC
SWB
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
xxxx xxxx
xxxx xxxx
CHANNEL[7:0]
CHANNEL[7:0]
Software LOAD DAC. A '1' causes data stored in
the specified channel's PREREG to be transferred
to DACREG and the output updated.
Set WRITE BLOCK or WRITE THROUGH for the 00FFh
selected channels.
0: WRITE THROUGH
1: WRITE BLOCK
PD
0
0
1
1
0
0
0
0
CHANNEL[7:0]
CHANNEL[7:0]
Sets SEL_10K or SEL_HIZ. Upper 8 bits PD Hi-Z; 0000h
Lower 8-bits PD 10K; if both are 1's; PD -> 10K
1: Upper 8 bits: SEL_HIZ
1: Lower 8 bits: SEL_10K
1: Both upper and lower: SEL_10K
Data Writing
WR
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
A2 A1 A0
A2 A1 A0
DACDATA[15:8]
DACDATA[15:8]
DACDATA[15:8]
DACDATA[7:0]
DACDATA[7:0]
DACDATA[7:0]
Write to specified channel. WRITE BLOCK or
WRITE TRHOUGH setting controls destination
register (PREREG or DACREG).
WRUP
WRAL
Update specified channel's DACREG and
PREREG regardless of WRITE BLOCK or WRITE
THROUGH setting.
0
0
0
Update all channel's DACREG and PREREG
regardless of WRITE BLOCK or WRITE
THROUGH setting.
Register Reading
<Reserved>
RDDO
1
1
0
0
0
0
0
0
0
1
x
x
x
<Reserved>
A2 A1 A0
DACDATA[15:8]
DACDATA[7:0]
Read PREREG register.
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: DAC161S055
DAC161S055
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
www.ti.com
DEFAULT
MNEMONIC
RDCO
Command Byte[7:0]
DATA[15:8]
0000 0000
DATA [7:0]
0000 0,swb,sel_10k, sel_hiz
DACDATA[7:0]
Description
Read CONFIG register.
Read DACREG register.
1
1
0
0
0
0
1
1
0
1
A2 A1 A0
A2 A1 A0
0004h
RDIN
DACDATA[15:8]
20
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: DAC161S055
DAC161S055
www.ti.com
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
APPLICATIONS INFORMATION
SAMPLE INSTRUCTION SEQUENCE
The following table shows an example instruction sequence to illustrate the usage of different modes of operation
of the DAC. This sequence is for a one channel DAC.
Step
Instruction
8-bit Command
16 bit Payload
Comments
1
CLR
0000 0001
0000 0000 0000 0000
Clear device - return to Power-Up Default State
Write 1/4 FS into channel 0. Since device by default is in
WRITE-BLOCK mode the data will be written into PREREG,
and DAC output will not update
2
WR
0000 1000
0100 0000 0000 0000
Issue LDAC command to channel 0. Data is transferred from
PREREG into DACREG and DAC output updates to 1/4 FS
3
4
5
6
LDAC
SWB
WR
0001 1000
0010 1000
0000 1000
0011 0000
xxxx xxxx 0000 0001
xxxx xxxx 1111 1110
1111 1111 1111 1111
0000 0001 0000 0000
Set channels 1 to 7 to WRITE-BLOCK mode, and channel 0 to
WRITE-THROUGH mode
DAC output updates immediately to FS since the channel is
set to write through mode.
Power down the device, and set the channel 0 DAC output to
the HIZ state
PD
USING REFERENCES AS POWER SUPPLIES
Although the DAC has a separate reference and analog power pin, it is still possible to use a reference to drive
both. This arrangement will avoid a separate voltage regulator for VA and will provide a more stable voltage
source. The LM4140 has an initial accuracy of 0.1%, is capable of driving 8mA and comes in a 4.096V version.
Bypassing both the input and the output will improve noise performance.
Input
Voltage
LM4120-
4.096
C3
0.022 mF
C2
0.022 mF
C1
0.1 mF
VREF VA
DAC161S055
CSB
V
OUT
= 0V to 4.095V
SDI
SCLK
SDO
Figure 23. Using the LM4120 as a power supply
A LOW NOISE EXAMPLE
A LM4050 powered off of a battery is a good choice for very low noise prototype circuits. The minimum value for
R must be chosen so that the LM4050 does not draw more than its 15mA rating. Note the largest current through
the LM4050 will occur when the DAC is shutdown. The maximum resistor value must allow the LM4050 to draw
more than its minimum current for regulation plus the maximum VREF current.
4.5V
Battery
(3 AA)
9V
Battery
R
V
Z
0.47 mF
LM4050-4.1
VREF VA
DAC161S055
CSB
V
OUT
SDI
SCLK
SDO
Figure 24. Using the LM4050 in a low noise circuit
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: DAC161S055
DAC161S055
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
www.ti.com
LAYOUT, GROUNDING AND BYPASSING
For best accuracy and minimum noise, the printed circuit board containing the DAC should have separate analog
and digital areas. These areas are defined by the locations of the analog and digital power planes. Both power
planes should be in the same board layer. There should be a single ground plane. Frequently a single ground
plane design will utilize a fencing technique to prevent the mixing of analog and digital ground currents. Separate
ground planes should only be used if the fencing technique proves inadequate. The separate ground planes
must be connected in a single place, preferably near the DAC. Special care is required to specify that digital
signals with fast edge rates do not pass over split ground planes. The fast digital signals must always have a
continuous return path below their traces.
When possible, the DAC power supply should be bypassed with a 10µF and a 0.1µF capacitor placed as close
as possible to the device with the 0.1µF closest to the supply pin. The 10µF capacitor should be a tantalum type
and the 0.1µF capacitor should be a low ESL, low ESR type. Sometime, the loading requirements of the
regulator driving the DAC do not allow such capacitance to be placed on the regulator output. In those cases,
bypass should be as large as allowed by the regulator using a low ESL, low ESR capacitance. In the LM4120
example above, the supply is bypassed with 0.022µF ceramic capacitors. The DAC should be fed with power
that is only used for analog circuits.
Avoid crossing analog and digital signals and keep the clock and data lines on the component side of the board.
The clock and data lines should have controlled impedances.
22
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: DAC161S055
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 105
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
DAC161S055CISQ/NOPB
DAC161S055CISQE/NOPB
DAC161S055CISQX/NOPB
ACTIVE
WQFN
WQFN
WQFN
RGH
16
16
16
1000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
161S055
ACTIVE
ACTIVE
RGH
RGH
250
Green (RoHS
& no Sb/Br)
-40 to 105
161S055
161S055
4500
Green (RoHS
& no Sb/Br)
-40 to 105
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC161S055CISQ/NOPB WQFN
RGH
RGH
16
16
1000
250
178.0
178.0
12.4
12.4
4.3
4.3
4.3
4.3
1.3
1.3
8.0
8.0
12.0
12.0
Q1
Q1
DAC161S055CISQE/NOP WQFN
B
DAC161S055CISQX/NOP WQFN
B
RGH
16
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC161S055CISQ/NOPB
WQFN
WQFN
RGH
RGH
16
16
1000
250
213.0
213.0
191.0
191.0
55.0
55.0
DAC161S055CISQE/NOP
B
DAC161S055CISQX/NOP
B
WQFN
RGH
16
4500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
RGH0016A
SQA16A (Rev A)
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
Video and Imaging
www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
相关型号：
DAC161S997EVM
helps designers evaluate the operation and performance of the DAC161S997 4-20mA Loop Drive with SPI control
TI
DAC1627D1G25HN/C1,
Dual 16-bit DAC, up to 1.25 Gsps; 2x 4x and 8x interpolating, SOT813-3 Package, Standard Markigg, Reel Dry Pack, SMD, 13"
IDT
DAC1653D1G0NLGA
D/A Converter, 1 Func, Serial Input Loading, 0.02us Settling Time, 8 X 8 MM, 0.85 MM HEIGHT, 0.50 MM PITCH, VFQFP-56
IDT
DAC1653D1G5NLGA
D/A Converter, 1 Func, Serial Input Loading, 0.02us Settling Time, 8 X 8 MM, 0.85 MM HEIGHT, 0.50 MM PITCH, VFQFP-56
IDT
DAC1653D2G0NLGA
D/A Converter, 1 Func, Serial Input Loading, 0.02us Settling Time, 8 X 8 MM, 0.85 MM HEIGHT, 0.50 MM PITCH, VFQFP-56
IDT
©2020 ICPDF网 联系我们和版权申明