CSD87313DMST [TI]
采用 3mm x 3mm SON 封装的双路共漏极、5.5mΩ、30V、N 沟道 NexFET™ 功率 MOSFET | DMS | 8 | -55 to 150;型号: | CSD87313DMST |
厂家: | TEXAS INSTRUMENTS |
描述: | 采用 3mm x 3mm SON 封装的双路共漏极、5.5mΩ、30V、N 沟道 NexFET™ 功率 MOSFET | DMS | 8 | -55 to 150 |
文件: | 总14页 (文件大小:831K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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CSD87313DMS
ZHCSG72 –APRIL 2017
CSD87313DMS 30V 双路 N 通道 NexFET™功率 MOSFET
1 特性
产品概要
1
•
•
•
•
•
•
•
•
•
•
低源极至源极导通电阻
TA = 25°C
VS1S2
Qg
数值
30
单位
V
双共漏极 N 通道 MOSFET
针对 5V 栅极驱动进行了优化
低 Qg 和 Qgd
源极 1 到源极 2 电压
栅极电荷总量 (4.5V)
栅极电荷(栅极到漏极)
28
nC
nC
Qgd
6.0
VGS = 2.5V
VGS = 4.5V
0.9
9.6
5.5
低热阻
RS1S2(on) 源极 1 到源极 2 最大导通电阻
VGS(th) 阈值电压
mΩ
雪崩额定值
V
无铅引脚镀层
符合 RoHS 标准
无卤素
器件信息(1)
器件
CSD87313DMS 2500 13 英寸卷带
CSD87313DMST 250 7 英寸卷带
数量
包装介质
封装
运输
小外形尺寸无引线 (SON) 3.3mm × 3.3mm 塑料封
装
SON
卷带封
装
3.30mm × 3.30mm
塑料封装
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
2 应用范围
•
•
•
USB Type-C™和电力输送 (PD) VBus 保护
绝对最大额定值
电池保护
负载开关
TA = 25°C 时测得,除非另外注明
值
30
单位
V
VS1S2 源极 1 到源极 2 电压
VGS
IS1S2 持续源极电流(2)
栅源电压(1)
±10
17
V
A
3 说明
ISM
脉冲源极电流,TA = 25°C 时测得(2)(3)
120
2.7
1
A
CSD87313DMS 是一款 30V 共漏极、双路 N 通道器
件,专为 USB Type-C/PD 和电池保护而设计。此
3.3mm × 3.3mm SON 器件具有低源极至源极导通电
阻,可最大限度地较少损耗,且具有较少的组件数量,
适用于空间受限的 应用。
功率耗散(2)
功率耗散(4)
PD
W
TJ,T 工作结温,
-55 至 150
°C
储存温度
stg
雪崩能量,单一脉冲,
ID = 100A,L = 0.1mH,RG = 25Ω
EAS
67
mJ
(1) VG1S1 不应超过 ±10V,VG2S2 不应超过 ±10V。
原理图
(2) 典型 RθJA = 45°C/W(当在 0.06 英寸 [1.52mm] 厚的 FR4
PCB 上将其安装在 1 平方英寸 [6.45cm2] 2oz [0.071mm] 厚的
铜焊盘上时)。
{1
D1
(3) 占空比 ≤ 2%,脉冲持续时间 ≤ 300µs。
(4) 典型 RθJA = 125°C/W(在 2oz 铜焊盘上)。
5
D2
{2
RS1S2(ON) 与 VGS 对比
栅极电荷
20
8
TC = 25°C, I D = 23 A
TC = 125°C, I D = 23 A
ID = 23 A
VDS = 15 V
18
7
16
14
12
10
8
6
5
4
3
2
1
0
6
4
2
0
0
1
2
3
4
5
6
7
8
9
10
0
5
10
15
20
25
30
35
40
45
50
VGS - Gate-To-Source Voltage (V)
Qg - Gate Charge (nC)
D006
D010
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLPS642
CSD87313DMS
ZHCSG72 –APRIL 2017
www.ti.com.cn
目录
6.1 接收文档更新通知 ..................................................... 8
6.2 社区资源.................................................................... 8
6.3 商标........................................................................... 8
6.4 静电放电警告............................................................. 8
6.5 Glossary.................................................................... 8
机械、封装和可订购信息 ......................................... 9
7.1 DMS 封装尺寸........................................................... 9
7.2 建议 PCB 布局 ........................................................ 10
7.3 建议模板开口........................................................... 11
1
2
3
4
5
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Specifications......................................................... 3
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information.................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
器件和文档支持........................................................ 8
7
6
4 修订历史记录
日期
修订版本
注释
2017 年 4 月
*
最初发布。
2
Copyright © 2017, Texas Instruments Incorporated
CSD87313DMS
www.ti.com.cn
ZHCSG72 –APRIL 2017
5
Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
IS1S2
IGSS
Source1-to-Source2 leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
VG1S1 = 0 V, VG2S2 = 0 V, VS1S2 = 24 V
VS1S2 = 0 V, VGS = 10 V
1
100
1.2
9.6
5.5
μA
nA
V
VGS(th)
VS1S2 = VGS, IS1S2 = 250 μA
VGS = 2.5 V, IS1S2 = 20 A
0.6
0.9
6.7
RS1S2(on)
gfs
Source1-to-Source2 on resistance
Transconductance
mΩ
VGS = 4.5 V, IS1S2 = 23 A
4.6
VS1S2 = 3 V, IS1S2 = 23 A
149
S
DYNAMIC CHARACTERISTICS(1)
CISS
COSS
CRSS
Qg
Input capacitance
3300
281
154
28
4290
365
pF
pF
pF
nC
nC
nC
nC
ns
Output capacitance
Reverse transfer capacitance
Gate charge total (4.5 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Turnon delay time
Rise time
VGS = 0 V, VS1S2 = 15 V, ƒ = 1 MHz
200
VS1S2 = 15 V, IS1S2 = 23 A
VG1S1 = 4.5 V, VG2S2 = 0 V
Qgd
Qgs
Qg(th)
td(on)
tr
6.0
6.3
3.2
9
27
ns
VS1S2 = 15 V, IS1S2 = 23 A
VGS = 4.5 V, RGEN = 0 Ω
td(off)
tf
Turnoff delay time
Fall time
41
ns
13
ns
DIODE CHARACTERISTICS
Maximum continuous Source1-to-Source2
diode forward current(2)
Ifss
VG1S1 = 0 V, VG2S2 = 4.5 V
2
A
V
Vfss
Source1-to-Source2 diode forward voltage VG1S1 = 0 V, VG2S2 = 4.5 V, Ifss = 23 A
0.8
1.0
(1) Dynamic characteristic measurements are for a single FET.
(2) Typical RθJA = 125°C/W on a minimum 2-oz Cu pad.
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-case thermal resistance(1)
Junction-to-ambient thermal resistance(1)(2)
UNIT
°C/W
°C/W
RθJA
RθJA
125
45
(1) Device mounted on minimum 2-oz (0.071-mm) thick Cu.
(2) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
GATE
Source
GATE
Source
R
θJA = 45°C/W when
RθJA = 125°C/W when
mounted on 1 in2 (6.45
cm2) of
mounted on a
minimum pad area of
2-oz (0.071-mm) thick
Cu.
2-oz (0.071-mm) thick
Cu.
DRAIN
DRAIN
M0161-02
M0161-01
Copyright © 2017, Texas Instruments Incorporated
3
CSD87313DMS
ZHCSG72 –APRIL 2017
www.ti.com.cn
5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
120
108
96
120
108
96
84
72
60
48
36
24
12
0
84
72
60
48
36
VG1S1 = 3 V
VG1S1 = 3.5 V
VG1S1 = 4 V
VGS = 3 V
VGS = 3.5 V
VGS = 4 V
24
12
0
VG1S1 = 4.5 V
VGS = 4.5 V
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VS1S2 - Source1-to-Source2 Voltage (V)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
VS1S2 - Source1-to-Source2 Voltage (V)
D001
D002
Pulse width = 250 µs, duty cycle = 0.5%
VG2S2 = 4.5 V
Pulse width = 250 µs, duty cycle = 0.5%
Figure 1. Saturation Characteristics
Figure 2. Saturation Characteristics
1.5
1.25
1
1.75
1.5
1.25
1
0.75
0.5
0.75
0.5
VG1S1 = 3 V
VG1S1 = 3.5 V
VG1S1 = 4 V
VG1S1 = 4.5 V
VGS = 3 V
VGS = 3.5 V
VGS = 4 V
VGS = 4.5 V
0
10 20 30 40 50 60 70 80 90 100 110 120
IS1S2 - Source1-to-Source2 Current (A)
0
10 20 30 40 50 60 70 80 90 100 110 120
IS1S2 - Source1-to-Source2 Current (A)
D004
D004
Pulse width = 250 µs, duty cycle = 0.5%
VG2S2 = 4.5 V
Pulse width = 250 µs, duty cycle = 0.5%
Figure 3. Saturation Characteristics
Figure 4. Saturation Characteristics
1.8
1.6
1.4
1.2
1
20
18
16
14
12
10
8
VGS = 2.5 V
VGS = 4.5 V
TC = 25°C, I D = 23 A
TC = 125°C, I D = 23 A
6
0.8
0.6
0.4
4
2
0
-75 -50 -25
0
25
50
75 100 125 150 175
0
1
2
3
4
5
6
7
8
9
10
TC - Case Temperature (°C)
VGS - Gate-To-Source Voltage (V)
D008
D006
IS1S2 = 23 A
VGS = 15 V
Figure 5. Normalized On-State Resistance vs Temperature
Figure 6. On-State Resistance vs Gate-to-Source Voltage
4
Copyright © 2017, Texas Instruments Incorporated
CSD87313DMS
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ZHCSG72 –APRIL 2017
Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
120
100
10
TC = 150°C
TC = 25°C
TC = -55°C
TC = -55èC
TC = 25èC
TC = 125èC
108
96
84
72
60
48
36
24
12
0
1
0.1
0.01
0.001
0.0001
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
0
0.2
0.4
0.6
0.8
1
1.2
VGS - Gate-to-Source Voltage (V)
Vf - Source-to-Drain Voltage (V)
SS
D007
D009
VS1S2 = 5 V
Figure 7. Transfer Characteristics
Figure 8. Typical Diode Forward Voltage
10000
1000
100
8
7
6
5
4
3
2
1
0
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
10
0
5
10
15
20
25
30
0
5
10
15
20
25
30
35
40
45
50
VS1S2 - Source1-to-Source2 Voltage (V)
Qg - Gate Charge (nC)
D010
D010
ID = 23 A
VS1S2 = 15 V
Figure 10. Capacitance
Figure 9. Gate Charge
10000
1000
100
10
200
100
10
1
0.1
DC
10 s
10 ms
1 ms
1
0.01
1 s
100 µs
100 ms
0.001
0.1
0.01
0.1
1
10
100
0.0001 0.001
0.01
0.1
1
10
100
1000
VS1S2 - Source1-to-Source2 Voltage (V)
tp - Pulse Duration (s)
D010
D013
Single pulse, RθJA = 125°C/W
RθJA = 125 °C/W, TA = 25°C
Figure 11. Maximum Safe Operating Area
Figure 12. Single Pulse Maximum Power Dissipation
Copyright © 2017, Texas Instruments Incorporated
5
CSD87313DMS
ZHCSG72 –APRIL 2017
www.ti.com.cn
Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
100
10
1
1.3
TC = 25è C
TC = 125è C
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
-75 -50 -25
0
25
50
75 100 125 150 175
0.01
0.1
1
TC - Case Temperature (èC)
TAV - Time in Avalanche (ms)
D006
D011
ID = 250 µA
Figure 13. Threshold Voltage vs Temperature
Figure 14. Single Pulse Unclamped Inductive Switching
24
20
16
12
8
4
0
-50
-25
0
25
50
75
100 125 150 175
TA - Ambient Temperature (èC)
D012
Figure 15. Maximum Source1-to-Source2 Current vs Temperature
6
Copyright © 2017, Texas Instruments Incorporated
CSD87313DMS
www.ti.com.cn
ZHCSG72 –APRIL 2017
Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
Figure 16. Transient Thermal Impedance
版权 © 2017, Texas Instruments Incorporated
7
CSD87313DMS
ZHCSG72 –APRIL 2017
www.ti.com.cn
6 器件和文档支持
6.1 接收文档更新通知
如需接收文档更新通知,请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后,即可每周定期收到已更改的产品信息。有关更改的详细信息,请查阅已修订文档中包含的修订历史记录。
6.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.3 商标
NexFET, E2E are trademarks of Texas Instruments.
USB Type-C is a trademark of USB Implementers Forum.
All other trademarks are the property of their respective owners.
6.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
6.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
8
版权 © 2017, Texas Instruments Incorporated
CSD87313DMS
www.ti.com.cn
ZHCSG72 –APRIL 2017
7 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本,请查阅左侧的导航栏
7.1 DMS 封装尺寸
3.4
3.2
A
B
PIN 1 INDEX AREA
3.4
3.2
C
0.8 MAX
SEATING PLANE
0.08 C
1.66 0.1
PKG
(0.2) TYP
1.04
4X
0.05
0.00
0.3
0.1
0.84
4X
4
5
2X
1.28 0.1
2X
1.95
SYMM
EXPOSED
THERMAL PAD
8
1
6X 0.65
0.37
8X
0.27
0.1
0.05
C A B
C
PIN 1 ID
(OPTIONAL)
2X (0.2)
2X (0.4)
4222980/A 05/2016
(1) 所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和容限值遵循 ASME Y14.5M。
(2) 本图纸如有变更,恕不通知。
(3) 必须在印刷电路板上焊接封装散热焊盘,以获得良好的散热和机械性能。
表 1. 引脚配置表
位置
名称
栅极 1
漏极
位置
名称
1
2
3
4
5
6
7
8
源极 2
源极 2
源极 1
源极 1
漏极
栅极 2
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9
CSD87313DMS
ZHCSG72 –APRIL 2017
www.ti.com.cn
7.2 建议 PCB 布局
0.05 MIN
ALL AROUND
2X (1.66)
2X (0.62)
4X (0.4)
(
0.2) TYP
4X (1.14)
8
4X (0.32)
1
(1.28)
4X (0.32)
(0.805)
(0.415)
PKG
SYMM
(1.195)
3X (0.65)
4
2X (0.65)
5
(R0.05) TYP
METAL UNDER
SOLDER MASK
TYP
SEE DETAILS
(1.28)
(0.04) TYP
(1.2) TYP
SOLDER MASK
OPENING
TYP
PKG
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
4222980/A 05/2016
(1) 此封装设计用于焊接到电路板的散热焊盘上。如需更多信息,请参见《QFN/SON PCB 连接》(SLUA271)。
(2) 根据具体应用决定是否选用通孔,请参见器件数据表。如需实施任意通孔,请参见此视图上的通孔位置。建议对焊锡膏
下方的通孔进行填充、堵塞或包覆。
10
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ZHCSG72 –APRIL 2017
7.3 建议模板开口
SOLDER MASK EDGE
TYP
2X (1.52)
PKG
4X (0.39)
4X (0.97)
8
1
4X (0.32)
2X (1.19)
4X (0.32)
PKG
SYMM
(0.805)
3X
3X (0.65)
(0.65)
4
5
(R0.05) TYP
METAL UNDER
SOLDER MASK
TYP
EXPOSED METAL
TYP
2X (0.55)
(1.37)
(1.655)
EXPOSED METAL
TYP
(1) 具有漏斗形壁和圆角的激光切割窗孔将提供更佳的焊锡膏脱离。IPC-7525 可能提供其他替代性设计建议。
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11
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
250
(1)
(2)
(3)
(4/5)
(6)
CSD87313DMS
CSD87313DMST
ACTIVE
WSON
WSON
DMS
8
8
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
CSD87313
CSD87313
ACTIVE
DMS
RoHS-Exempt
& Green
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
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