CSD23381F4T [TI]
采用 0.6mm x 1mm LGA 封装、具有栅极 ESD 保护的单路、175mΩ、-12V、P 沟道 NexFET™ 功率 MOSFET | YJC | 3 | -55 to 150;
| 型号： | CSD23381F4T |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 0.6mm x 1mm LGA 封装、具有栅极 ESD 保护的单路、175mΩ、-12V、P 沟道 NexFET™ 功率 MOSFET | YJC | 3 | -55 to 150 栅 开关 小信号场效应晶体管 栅极 |
| 文件： | 总12页 (文件大小：786K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD23381F4
SLPS450B –OCTOBER 2013–REVISED FEBRUARY 2014
CSD23381F4, 12 V P-Channel FemtoFET™ MOSFET
.
1 Features
Product Summary
Drain-to-Source Voltage
1
•
•
•
•
Ultra-Low On Resistance
VDS
Qg
–12
1140
V
Ultra-Low Qg and Qgd
Gate Charge Total (–4.5 V)
Gate Charge Gate to Drain
pC
pC
mΩ
mΩ
mΩ
V
High Operating Drain Current
Ultra-Small Footprint (0402 Case Size)
Qgd
190
VGS = –1.8 V
VGS = –2.5 V
VGS = –4.5 V
–0.95
480
250
150
RDS(on) Drain-to-Source On Resistance
–
1.0 mm × 0.6 mm
Ultra-Low Profile
0.35 mm Max Height
Integrated ESD Protection Diode
•
•
VGS(th)
Threshold Voltage
–
.
Ordering Information
–
–
Rated > 4 kV HBM
Rated > 2 kV CDM
Device
Qty
Media
Package
Ship
CSD23381F4
3000
Femto(0402)
1.0 mm x 0.6 mm
Land Grid Array (LGA)
7-Inch
Reel
Tape and
Reel
•
•
Lead and Halogen Free
RoHS Compliant
CSD23381F4T
250
.
2 Applications
Absolute Maximum Ratings
•
•
Optimized for Load Switch Applications
TA = 25°C
VALUE
UNIT
Optimized for General Purpose Switching
Applications
VDS
VGS
ID
Drain-to-Source Voltage
–12
–8
V
V
A
A
Gate-to-Source Voltage
Continuous Drain Current(1)
Pulsed Drain Current(2)
–2.3
–9
•
•
Battery Applications
IDM
Handheld and Mobile Applications
Continuous Gate Clamp Current
Pulsed Gate Clamp Current(2)
Power Dissipation(1)
–35
–350
500
4
IG
mA
3 Description
PD
mW
kV
This 150 mΩ, 12 V P-Channel FemtoFET™ MOSFET
is designed and optimized to minimize the footprint in
many handheld and mobile applications. This
technology is capable of replacing standard small
signal MOSFETs while providing at least a 60%
reduction in footprint size.
Human Body Model (HBM)
Charged Device Model (CDM)
ESD
Rating
2
kV
TJ,
TSTG
Operating Junction and
Storage Temperature Range
–55 to 150
°C
(1) Typical RθJA = 85°C/W on 1-inch2 (6.45-cm2), 2-oz. (0.071-
mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB.
.
(2) Pulse duration ≤ 300 μs, duty cycle ≤ 2%
Typical Part Dimensions
Top View
0.35 mm
D
0.60 mm
1.00 mm
G
S
.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD23381F4
SLPS450B –OCTOBER 2013–REVISED FEBRUARY 2014
www.ti.com
4 Specifications
4.1 Electrical Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static Characteristics
BVDSS
IDSS
Drain-to-Source Voltage
VGS = 0 V, IDS = –250 μA
–12
V
nA
nA
V
Drain-to-Source Leakage Current
Gate-to-Source Leakage Current
Gate-to-Source Threshold Voltage
VGS = 0 V, VDS = –16 V
VDS = 0 V, VGS = –12 V
VDS = VGS, IDS = –250 μA
VGS = –1.8 V, IDS = –0.1 A
VGS = –2.5 V, IDS = –0.5 A
VGS = –4.5 V, IDS = –0.5 A
VDS = –6 V, IDS = –0.5 A
–100
–50
IGSS
VGS(th)
–0.70
–0.95
480
250
150
2.0
–1.20
970
mΩ
mΩ
mΩ
S
RDS(on)
Drain-to-Source On Resistance
300
175
gfs
Transconductance
Dynamic Characteristics
Ciss
Coss
Crss
RG
Input Capacitance
236
98
pF
pF
pF
Ω
VGS = 0 V, VDS = –6 V,
f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
Series Gate Resistance
Gate Charge Total (4.5 V)
Gate Charge Gate to Drain
Gate Charge Gate to Source
Gate Charge at Vth
Output Charge
6.9
20
Qg
1140
190
300
145
1290
4.5
pC
pC
pC
pC
pC
ns
ns
ns
ns
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
VDS = –6 V, IDS = –0.5 A
VDS = –6 V, VGS = 0 V
Turn On Delay Time
Rise Time
3.9
VDS = 0 V, VGS = –4.5 V,
IDS = –0.5 A,RG = 2 Ω
td(off)
tf
Turn Off Delay Time
Fall Time
18.0
7.0
Diode Characteristics
VSD
Qrr
trr
Diode Forward Voltage
ISD = –0.5 A, VGS = 0 V
–0.75
1260
7.9
V
Reverse Recovery Charge
Reverse Recovery Time
pC
ns
VDS= –10 V, IF = –0.5 A, di/dt = 100 A/μs
4.2 Thermal Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
Typical Values
UNIT
°C/W
°C/W
Junction-to-Ambient Thermal Resistance(1)
Junction-to-Ambient Thermal Resistance(2)
85
RθJA
245
(1) Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
(2) Device mounted on FR4 material with minimum Cu mounting area.
2
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Product Folder Links: CSD23381F4
CSD23381F4
www.ti.com
SLPS450B –OCTOBER 2013–REVISED FEBRUARY 2014
5 Typical MOSFET Characteristics
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
5.5
5
5.5
5
VGS = −4.5V
VGS = −2.5V
VGS = −1.8V
VDS = −5V
4.5
4
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
TC = 125°C
TC = 25°C
TC = −55°C
0.5
0
0.5
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.5
1
1.5
2
2.5
3
3.5
4
−VDS - Drain-to-Source Voltage (V)
−VGS - Gate-to-Source Voltage (V)
G001
G001
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
Copyright © 2013–2014, Texas Instruments Incorporated
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3
Product Folder Links: CSD23381F4
CSD23381F4
SLPS450B –OCTOBER 2013–REVISED FEBRUARY 2014
www.ti.com
Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
4.5
300
270
240
210
180
150
120
90
ID = −0.5A
VDS = −6V
4
3.5
3
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
2.5
2
1.5
1
60
0.5
0
30
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1 1.2
0
1
2
3
4
5
6
7
8
9
10 11 12
Qg - Gate Charge (nC)
−VDS - Drain-to-Source Voltage (V)
G001
G001
Figure 4. Gate Charge
Figure 5. Capacitance
1.25
1.15
1.05
0.95
0.85
0.75
0.65
0.55
0.45
600
540
480
420
360
300
240
180
120
60
ID = −250uA
TC = 25°C,I D = −0.5A
TC = 125°C,I D = −0.5A
0
−75
−25
25
75
125
175
0
1
2
3
4
5
6
7
8
TC - Case Temperature (ºC)
−VGS - Gate-to- Source Voltage (V)
G001
G001
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
1.4
1.3
1.2
1.1
1
10
VGS = −4.5V, ID = −0.5A
TC = 25°C
TC = 125°C
1
0.1
0.01
0.9
0.8
0.7
0.001
0.0001
−75
−25
25
75
125
175
0
0.2
0.4
0.6
0.8
1
TC - Case Temperature (ºC)
−VSD − Source-to-Drain Voltage (V)
G001
G001
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
4
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Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: CSD23381F4
CSD23381F4
www.ti.com
SLPS450B –OCTOBER 2013–REVISED FEBRUARY 2014
Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
100
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1ms
10ms
100ms
1s
DC
10
1
0.1
0.01
Single Pulse
TypicalRthetaJA =245ºC/W(min Cu)
TypicalRthetaJA = 85ºC/W(max Cu)
0.01
0.1
1
10
50
−50 −25
0
25
50
75
100 125 150 175
−VDS - Drain-to-Source Voltage (V)
TA - AmbientTemperature (ºC)
G001
G001
Figure 10. Maximum Safe Operating Area
Figure 11. Maximum Drain Current vs Temperature
Copyright © 2013–2014, Texas Instruments Incorporated
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5
Product Folder Links: CSD23381F4
CSD23381F4
SLPS450B –OCTOBER 2013–REVISED FEBRUARY 2014
www.ti.com
6 Mechanical Data
6.1 0402 Mechanical Dimensions
(1) All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994).
(2) This drawing is subject to change without notice.
(3) This package is a PB-free solder land design.
Pin Configuration
Position
Designation
Pin 1
Gate
Pin 2
Source
Drain
Pin 3
6
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Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: CSD23381F4
CSD23381F4
www.ti.com
SLPS450B –OCTOBER 2013–REVISED FEBRUARY 2014
6.2 Recommended Minimum PCB Layout
(1) All dimensions are in millimeters.
6.3 Recommended Stencil Pattern
(1) All dimensions are in millimeters.
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7
Product Folder Links: CSD23381F4
CSD23381F4
SLPS450B –OCTOBER 2013–REVISED FEBRUARY 2014
www.ti.com
6.4 CSD23381F4 Embossed Carrier Tape Dimensions
(1) Pin 1 is oriented in the top-right quadrant of the tape enclosure (quadrant 2), closest to the carrier tape sprocket
holes.
8
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Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: CSD23381F4
CSD23381F4
www.ti.com
SLPS450B –OCTOBER 2013–REVISED FEBRUARY 2014
7 Trademarks
FemtoFET is a trademark of Texas Instruments.
8 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (January 2014) to Revision B
Page
•
•
•
•
Updated lead and halogen free in features ........................................................................................................................... 1
Added IG parameter ............................................................................................................................................................... 1
Lowered IDSS limit .................................................................................................................................................................. 2
Lowered IGSS limit .................................................................................................................................................................. 2
Changes from Original (October 2013) to Revision A
Page
•
•
Updated title .......................................................................................................................................................................... 1
Added small reel info ............................................................................................................................................................. 1
Copyright © 2013–2014, Texas Instruments Incorporated
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9
Product Folder Links: CSD23381F4
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jan-2014
PACKAGING INFORMATION
Orderable Device
CSD23381F4
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
PICOSTAR
YJC
3
3
3000
Green (RoHS
& no Sb/Br)
Call TI
Level-1-250C-UNLIM
DS
CSD23381F4R
PREVIEW PICOSTAR
YJC
18000
TBD
Call TI
Call TI
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jan-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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相关型号：
CSD23382F4T
采用 0.6mm x 1mm LGA 封装、具有栅极 ESD 保护的单路、76mΩ、-12V、P 沟道 NexFET™ 功率 MOSFET | YJC | 3 | -55 to 150
TI
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