CSD19503KCS [TI]
80 V N-Channel NexFET Power MOSFETs; 80伏N通道NexFET功率MOSFET
| 型号： | CSD19503KCS |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 80 V N-Channel NexFET Power MOSFETs |
| 文件： | 总10页 (文件大小：768K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD19503KCS
www.ti.com
SLPS479 –DECEMBER 2013
80 V N-Channel NexFET™ Power MOSFETs
Check for Samples: CSD19503KCS
1
FEATURES
2
•
•
•
•
•
•
•
Ultra-Low Qg and Qgd
Low Thermal Resistance
Avalanche Rated
PRODUCT SUMMARY
TA = 25°C
VDS
TYPICAL VALUE
UNIT
V
Drain-to-Source Voltage
Gate Charge Total (10 V)
Gate Charge Gate to Drain
80
28
Qg
nC
nC
mΩ
mΩ
V
Pb-Free Terminal Plating
RoHS Compliant
Qgd
5.4
VGS = 6 V
8.8
7.6
RDS(on) Drain-to-Source On Resistance
VGS(th) Threshold Voltage
Halogen Free
VGS = 10 V
TO-220 Plastic Package
2.8
APPLICATIONS
ORDERING INFORMATION
Device
CSD19503KCS
Package
Media
Qty
Ship
Tube
•
•
Secondary Side Synchronous Rectifier
Motor Control
TO-220 Plastic
Package
Tube
50
DESCRIPTION
This 80 V, 7.6 mΩ, TO-220 NexFET™ power
MOSFET is designed to minimize losses in power
conversion applications.
ABSOLUTE MAXIMUM RATINGS
TA = 25°C
VALUE
UNIT
VDS
VGS
Drain-to-Source Voltage
80
V
V
Gate-to-Source Voltage
±20
100
Continuous Drain Current (Package limited)
Pin Out Drawing
Continuous Drain Current (Silicon limited),
TC = 25°C
Drain (Pin 2)
94
66
ID
A
Continuous Drain Current (Silicon limited),
TC = 100°C
IDM
PD
TJ,
Pulsed Drain Current (1)
113
188
A
Power Dissipation
W
Operating Junction and
–55 to 175
140
°C
Gate
(Pin 1)
TSTG Storage Temperature Range
Avalanche Energy, single pulse
EAS
mJ
ID = 53 A, L = 0.1 mH, RG = 25 Ω
(1) Pulse duration ≤ 300 μs, Duty cycle ≤ 1%
Source (Pin 3)
RDS(on) vs VGS
GATE CHARGE
22
10
TC = 25°C,I D = 60A
TC = 125°C,I D = 60A
ID = 60A
VDS = 40V
9
20
8
7
6
5
4
3
2
1
0
18
16
14
12
10
8
6
4
0
2
4
6
8
10
12
14
16
18
20
0
4
8
12
16
20
24
28
Qg - Gate Charge (nC)
VGS - Gate-to- Source Voltage (V)
G001
G001
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
CSD19503KCS
SLPS479 –DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
Static Characteristics
TEST CONDITIONS
MIN
TYP
MAX UNIT
BVDSS
IDSS
Drain-to-Source Voltage
VGS = 0 V, ID = 250 μA
80
V
Drain-to-Source Leakage Current
Gate-to-Source Leakage Current
Gate-to-Source Threshold Voltage
VGS = 0 V, VDS = 64 V
VDS = 0 V, VGS = 20 V
VDS = VGS, ID = 250 μA
VGS = 6 V, ID = 60 A
VGS = 10 V, ID = 60 A
VDS = 8 V, ID = 60 A
1
100
3.4
μA
nA
V
IGSS
VGS(th)
2.2
2.8
8.8
7.6
110
10.9
9.2
mΩ
mΩ
S
RDS(on)
Drain-to-Source On Resistance
gfs
Transconductance
Dynamic Characteristics
Ciss
Coss
Crss
RG
Input Capacitance
2100
555
8.5
1.2
28
5.4
9.8
6.1
71
7
2730
721
11.1
2.4
pF
pF
pF
Ω
Output Capacitance
Reverse Transfer Capacitance
Series Gate Resistance
Gate Charge Total (10 V)
Gate Charge Gate to Drain
Gate Charge Gate to Source
Gate Charge at Vth
Output Charge
VGS = 0 V, VDS = 40 V, f = 1 MHz
Qg
36
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
VDS = 40 V, ID = 60 A
VDS = 40 V, VGS = 0 V
Turn On Delay Time
Rise Time
3
VDS = 40 V, VGS = 10 V,
IDS = 60 A, RG = 0 Ω
td(off)
tf
Turn Off Delay Time
Fall Time
11
2
Diode Characteristics
VSD
Qrr
trr
Diode Forward Voltage
ISD = 60 A, VGS = 0 V
0.9
119
72
1.1
V
Reverse Recovery Charge
Reverse Recovery Time
nC
ns
VDS= 40 V, IF = 60 A,
di/dt = 300 A/μs
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
Thermal Resistance Junction to Case
MIN
TYP
MAX
UNIT
°C/W
°C/W
RθJC
RθJA
0.8
62
Thermal Resistance Junction to Ambient
2
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Product Folder Links: CSD19503KCS
CSD19503KCS
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SLPS479 –DECEMBER 2013
TYPICAL MOSFET CHARACTERISTICS
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
200
180
160
140
120
100
80
120
100
80
60
40
20
0
VDS = 5V
60
VGS =10V
VGS =8V
VGS =6V
TC = 125°C
TC = 25°C
TC = −55°C
40
20
0
0
0.4
0.8
1.2
1.6
2
0
1
2
3
4
5
6
7
8
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
G001
G001
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
Copyright © 2013, Texas Instruments Incorporated
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3
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CSD19503KCS
SLPS479 –DECEMBER 2013
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
10
9
8
7
6
5
4
3
2
1
0
100000
10000
1000
100
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
ID = 60A
VDS = 40V
10
1
0
4
8
12
16
20
24
28
0
10
20
30
40
50
60
70
80
Qg - Gate Charge (nC)
VDS - Drain-to-Source Voltage (V)
G001
G001
Figure 4. Gate Charge
TEXT ADDED FOR SPACING
Figure 5. Capacitance
TEXT ADDED FOR SPACING
3.4
3.2
3
22
20
18
16
14
12
10
8
ID = 250uA
TC = 25°C,I D = 60A
TC = 125°C,I D = 60A
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
6
4
−75 −50 −25
0
25 50 75 100 125 150 175 200
0
2
4
6
8
10
12
14
16
18
20
TC - Case Temperature (ºC)
VGS - Gate-to- Source Voltage (V)
G001
G001
Figure 6. Threshold Voltage vs. Temperature
TEXT ADDED FOR SPACING
Figure 7. On-State Resistance vs. Gate-to-Source Voltage
TEXT ADDED FOR SPACING
2.4
2.2
2
100
VGS = 6V
VGS = 10V
TC = 25°C
TC = 125°C
10
1.8
1.6
1.4
1.2
1
1
0.1
0.01
0.8
0.6
0.4
0.001
0.0001
ID =60A
−75 −50 −25
0
25 50 75 100 125 150 175 200
0
0.2
0.4
0.6
0.8
1
TC - Case Temperature (ºC)
VSD − Source-to-Drain Voltage (V)
G001
G001
Figure 8. Normalized On-State Resistance vs. Temperature
Figure 9. Typical Diode Forward Voltage
4
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Product Folder Links: CSD19503KCS
CSD19503KCS
www.ti.com
SLPS479 –DECEMBER 2013
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
5000
1000
100
TC = 25ºC
TC = 125ºC
10us
1ms
DC
100us
10ms
100
10
1
Single Pulse
Max RthetaJC = 0.8ºC/W
0.1
0.1
10
0.01
1
10
100
1000
0.1
1
VDS - Drain-to-Source Voltage (V)
TAV - Time in Avalanche (mS)
G001
G001
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
120
100
80
60
40
20
0
−50 −25
0
25
50
75 100 125 150 175 200
TC - Case Temperature (ºC)
G001
Figure 12. Maximum Drain Current vs. Temperature
Copyright © 2013, Texas Instruments Incorporated
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5
Product Folder Links: CSD19503KCS
CSD19503KCS
SLPS479 –DECEMBER 2013
www.ti.com
MECHANICAL DATA
KCS Package Dimensions
Notes:
1. All linear dimensions are in inches.
2. This drawing is subject to change without notice.
3. Lead dimensions are not controlled within "C" area.
4. All lead dimensions apply before solder dip.
5. The center lead is in electrical contact with the mounting tab.
6. The chamfer at "F" is optional.
7. Thermal pad contour at "G" optional with these dimensions.
8. "H" falls within JEDEC TO-220 variation AB, except for minimum lead thickness, minimum exposed pad
length, and maximum body length.
Table 1. Pin Configuration
Position
Pin 1
Designation
Gate
Pin 2 / Tab
Pin 3
Drain
Source
6
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: CSD19503KCS
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2014
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
CSD19503KCS
ACTIVE
TO-220
KCS
3
50
Pb-Free (RoHS
Exempt)
CU SN
N / A for Pkg Type
-55 to 150
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2014
Addendum-Page 2
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