CSD18511KTT [TI]
采用 D2PAK 封装的单路、2.6mΩ、40V、N 沟道 NexFET™ 功率 MOSFET;
| 型号： | CSD18511KTT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 D2PAK 封装的单路、2.6mΩ、40V、N 沟道 NexFET™ 功率 MOSFET 局域网 开关 脉冲 晶体管 |
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CSD18511KTT
SLPS684 –JULY 2017
CSD18511KTT 40-V N-Channel NexFET™ Power MOSFET
1 Features
Product Summary
1
•
•
•
•
•
•
•
•
Low Qg and Qgd
TA = 25°C
TYPICAL VALUE
UNIT
V
Low RDS(ON)
VDS
Qg
Drain-to-Source Voltage
Gate Charge Total (10 V)
Gate Charge Gate-to-Drain
40
63.9
9.7
Low-Thermal Resistance
Avalanche Rated
nC
nC
Qgd
VGS = 4.5 V
VGS = 10 V
1.8
3.2
2.1
Lead-Free Terminal Plating
RoHS Compliant
RDS(on) Drain-to-Source On-Resistance
VGS(th) Threshold Voltage
mΩ
V
Halogen Free
D2PAK Plastic Package
Device Information(1)
DEVICE
QTY
MEDIA
PACKAGE
SHIP
2 Applications
CSD18511KTT
CSD18511KTTT
500
50
Tape
and
Reel
D2PAK
Plastic Package
13-Inch Reel
•
•
Secondary Side Synchronous Rectifier
Motor Control
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
This 40-V, 2.1-mΩ, D2PAK (TO-263) NexFET™
power MOSFET is designed to minimize losses in
power conversion applications.
Absolute Maximum Ratings
TA = 25°C
VALUE
UNIT
V
VDS
VGS
Drain-to-Source Voltage
40
Drain (Pin 2)
Gate-to-Source Voltage
±20
V
Continuous Drain Current (Package Limited)
110
Continuous Drain Current (Silicon Limited),
TC = 25°C
194
137
ID
A
Continuous Drain Current (Silicon Limited),
TC = 100°C
Gate
(Pin 1)
IDM
PD
Pulsed Drain Current(1)
400
188
A
Power Dissipation
W
TJ,
Tstg
Operating Junction,
Storage Temperature
–55 to 175
156
°C
Source (Pin 3)
Avalanche Energy, Single Pulse
ID = 56 A, L = 0.1 mH, RG = 25 Ω
EAS
mJ
(1) Max RθJC = 0.8°C/W, pulse duration ≤ 100 μs, duty cycle ≤
1%.
RDS(on) vs VGS
Gate Charge
10
10
ID = 100 A
VDS = 20 V
TC = 25°C, I D = 100 A
TC = 125°C, I D = 100 A
9
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
0
2
4
6
8
10
12
14
16
18
20
0
10
20
30
40
50
60
70
VGS - Gate-to-Source Voltage (V)
Qg - Gate Charge (nC)
D007
D004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD18511KTT
SLPS684 –JULY 2017
www.ti.com
Table of Contents
6.2 Community Resources.............................................. 7
6.3 Trademarks............................................................... 7
6.4 Electrostatic Discharge Caution................................ 7
6.5 Glossary.................................................................... 7
1
2
3
4
5
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Specifications......................................................... 3
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information.................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
Device and Documentation Support.................... 7
6.1 Receiving Notification of Documentation Updates.... 7
7
Mechanical, Packaging, and Orderable
Information ............................................................. 8
7.1 KTT Package Dimensions ........................................ 8
7.2 Recommended PCB Pattern..................................... 9
7.3 Recommended Stencil Opening (0.125 mm Stencil
Thickness).................................................................. 9
6
4 Revision History
DATE
REVISION
NOTES
July 2017
*
Initial release.
2
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SLPS684 –JULY 2017
5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-source voltage
VGS = 0 V, ID = 250 μA
40
V
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
VGS = 0 V, VDS = 32 V
VDS = 0 V, VGS = 20 V
VDS = VGS, ID = 250 μA
VGS = 4.5 V, ID = 100 A
VGS = 10 V, ID = 100 A
VDS = 4 V, ID = 100 A
1
100
2.4
4.2
2.6
μA
nA
V
IGSS
VGS(th)
1.5
1.8
3.2
2.1
249
RDS(on)
gfs
Drain-to-source on-resistance
Transconductance
mΩ
S
DYNAMIC CHARACTERISTICS
Ciss
Coss
Crss
RG
Input capacitance
4570
454
235
0.9
31
5940
591
306
1.8
pF
pF
pF
Ω
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge total (10 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Output charge
VGS = 0 V, VDS = 20 V, ƒ = 1 MHz
Qg
nC
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qg
64
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
VDS = 20 V, ID = 100 A
VDS = 20 V, VGS = 0 V
9.7
17.9
7.4
20.7
8
Turnon delay time
Rise time
6
VDS = 20 V, VGS = 10 V,
IDS = 100 A, RG = 0 Ω
td(off)
tf
Turnoff delay time
Fall time
17
3
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
ISD = 100 A, VGS = 0 V
0.9
62
31
1.0
V
nC
ns
VDS= 20 V, IF = 100 A,
di/dt = 300 A/μs
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-case thermal resistance
Junction-to-ambient thermal resistance
MIN
TYP
MAX
UNIT
°C/W
°C/W
RθJC
RθJA
0.8
62
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SLPS684 –JULY 2017
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5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
Figure 1. Transient Thermal Impedance
200
175
150
125
100
75
200
TC = 125°C
TC = 25°C
TC = -55°C
175
150
125
100
75
50
50
VGS = 4.5 V
VGS = 8 V
VGS = 10 V
25
0
25
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1
1.5
2
2.5
3
3.5
4
4.5
5
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
D002
D003
VDS = 5 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
4
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Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
10000
1000
100
10
9
8
7
6
5
4
3
2
1
0
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
0
10
20
30
40
0
10
20
30
40
50
60
70
VDS - Drain-to-Source Voltage (V)
Qg - Gate Charge (nC)
D005
D004
VDS = 20 V
ID = 100 A
Figure 5. Capacitance
Figure 4. Gate Charge
10
9
8
7
6
5
4
3
2
1
2.6
TC = 25°C, I D = 100 A
TC = 125°C, I D = 100 A
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0
0
2
4
6
8
10
12
14
16
18
20
-75 -50 -25
0
25 50 75 100 125 150 175 200
VGS - Gate-to-Source Voltage (V)
TC - Case Temperature (èC)
D007
D006
ID = 250 µA
Figure 7. On-State Resistance vs Gate-to-Source Voltage
Figure 6. Threshold Voltage vs Temperature
100
2.2
2
TC = 25èC
TC = 125èC
VGS = 4.5 V
VGS = 10 V
10
1.8
1.6
1.4
1.2
1
1
0.1
0.01
0.8
0.6
0.4
0.001
0.0001
-75 -50 -25
0
25 50 75 100 125 150 175 200
0
0.2
0.4
0.6
0.8
1
TC - Case Temperature (°C)
VSD - Source-to-Drain Voltage (V)
D008
D009
ID = 100 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
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SLPS684 –JULY 2017
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Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
1000
100
10
1
100
10
1
DC
10 ms
1 ms
100 µs
10 µs
TC = 25è C
TC = 125è C
0.1
0.1
1
10
100
0.01
0.1
TAV - Time in Avalanche (ms)
1
VDS - Drain-to-Source Voltage (V)
D010
D011
Single pulse, max RθJC = 0.8°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
150
125
100
75
50
25
0
-50 -25
0
25
50
75 100 125 150 175 200
TC - Case Temperature (èC)
D012
Max RθJC = 0.8°C/W
Figure 12. Maximum Drain Current vs Temperature
6
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CSD18511KTT
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SLPS684 –JULY 2017
6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.3 Trademarks
NexFET, E2E, PowerPAD are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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CSD18511KTT
SLPS684 –JULY 2017
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 KTT Package Dimensions
15.5
14.7
9.25
9.05
A
B
3
10.26
10.06
2X 5.08
2
1
1.36
1.23
2[.0]X
0.9
2[.0]X
1.75 MAX
0.77
0.25
C
A
B
1.4
1.17
0.47
0.34
4.7
4.4
8
0
C
0.25
0
1.32
1.22
2.6
2
0.25
GAGE PLANE
7.48
7.08
8°
0°
8.55
8.15
2.6
2
0.25
GAGE PLANE
OPTIONAL LEAD FORM
EXPOSED
THERMAL PAD
NOTE 3
Notes:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Features may not exist and shape may vary per different assembly sites.
Table 1. Pin Configuration
POSITION
Pin 1
DESIGNATION
Gate
Pin 2 / Tab
Pin 3
Drain
Source
8
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SLPS684 –JULY 2017
7.2 Recommended PCB Pattern
PKG
(3.4)
(6.9)
(R0.05) TYP
PKG
SYMM
(5.08)
(8.55)
2X (1.05)
2X (3.82)
(7.48)
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
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0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques
(SLPA005).
7.3 Recommended Stencil Opening (0.125 mm Stencil Thickness)
(1.17) TYP
42X (0.97)
(0.48) TYP
2X (3.82)
2X (1.05)
42X (0.95)
(R0.05) TYP
(1.15) TYP
SYMM
(5.08)
(6.9)
PKG
Notes:
1. This package is designed to be soldered to a thermal pad on the board. See PowerPAD™ Thermally
Enhanced Package (SLMA002) and PowerPAD™ Made Easy (SLMA004) for more information.
2. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
3. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
500
50
(1)
(2)
(3)
(4/5)
(6)
CSD18511KTT
CSD18511KTTT
ACTIVE
DDPAK/
TO-263
KTT
3
3
RoHS-Exempt
& Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 175
-55 to 175
CSD18511KTT
CSD18511KTT
ACTIVE
DDPAK/
TO-263
KTT
RoHS-Exempt
& Green
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD18511KTT
CSD18511KTTT
DDPAK/
TO-263
KTT
KTT
3
3
500
50
330.0
24.4
10.8
16.3
5.11
16.0
24.0
Q2
DDPAK/
TO-263
330.0
24.4
10.8
16.3
5.11
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CSD18511KTT
CSD18511KTTT
DDPAK/TO-263
DDPAK/TO-263
KTT
KTT
3
3
500
50
340.0
340.0
340.0
340.0
38.0
38.0
Pack Materials-Page 2
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Copyright © 2020, Texas Instruments Incorporated
相关型号：
CSD18531Q5A_12
The NexFET power MOSFET has been designed to minimize losses in power conversion applications.
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