COPGW888-XXX/V/NOPB [TI]
8-BIT, MROM, 10MHz, MICROCONTROLLER, PQCC68, PLASTIC, LCC-68;
| 型号： | COPGW888-XXX/V/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT, MROM, 10MHz, MICROCONTROLLER, PQCC68, PLASTIC, LCC-68 时钟 微控制器 外围集成电路 |
| 文件： | 总47页 (文件大小：561K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
August 1996
COP888GW
8-Bit Microcontroller with Pulse Train Generators and
Capture Modules
n Multi-Input Wake-Up (MIWU) with optional interrupts (8)
General Description
The COP888 family of microcontrollers uses an 8-bit single
™
n MICROWIRE/PLUS serial I/O
chip core architecture fabricated with National Semiconduc-
2
I/O Features
™
tor’s M CMOS process technology. The COP888GW is a
n Memory mapped I/O
member of this expandable 8-bit core processor family of mi-
crocontrollers. It is a fully static part, fabricated using
double-metal silicon gate microCMOS technology.
n Software selectable I/O options ( TRI-STATE® Output,
Push-Pull Output, Weak Pull-Up Input, High Impedance
Input)
Features include an 8-bit memory mapped architecture,
™
n Schmitt trigger inputs on port G
n Package: 68-pin PLCC
MICROWIRE/PLUS serial I/O, two 16-bit timer/counters
supporting three modes (Processor Independent PWM gen-
eration, External Event counter and Input Capture mode ca-
pabilities), four independent 16-bit pulse train generators
with 16-bit prescalers, two independent 16-bit input capture
modules with 8-bit prescalers, multiply and divide functions,
full duplex UART, and two power savings modes (HALT and
IDLE), both with a multi-sourced wake up/interrupt capability.
This multi-sourced interrupt capability may also be used in-
dependent of the HALT or IDLE modes.
CPU/Instruction Set Features
n 1 µs instruction cycle time
n Fourteen multi-source vectored interrupts servicing:
— External Interrupt with selectable edge
— Idle Timer T0
— Two Timers (each with 2 interrupts)
— MICROWIRE/PLUS
Each I/O pin has software selectable configurations. The de-
vices operate over a voltage range of 2.5V–6V. High
throughput is achieved with an efficient, regular instruction
set operating at a maximum of 1 µs per instruction rate. The
device has low EMI emissions. Low radiated emissions are
achieved by gradual turn-on output drivers and internal ICC
filters on the chip logic and crystal oscillator. The device is
available in 68-pin PLCC package.
— Multi-Input Wake-Up
— Software Trap
— UART (2)
— Capture Timers
— Counters (one vector for all four counters)
— Default VIS (default interrupt)
n Versatile and easy-to-use instruction set
n 8-bit Stack Pointer SP—(stack in RAM)
n Two 8-bit register indirect data memory pointers
(B and X)
Key Features
n Two 16-bit input capture modules with 8-bit prescalers
n Four Pulse Train Generators with 16-bit prescalers
n Full duplex UART
n Two 16-bit timers, each with two 16-bit registers
supporting:
— Processor independent PWM mode
— External event counter mode
— Input capture mode
Fully Static CMOS
n Two power saving modes: HALT and IDLE
n Low current drain (typically 1 µA)
n Single supply operation: 2.5V–5.5V
<
n Temperature range: −40˚C to +85˚C
n Quiet design (low radiated emissions)
n 16 kbytes on-board ROM
Development Support
n Emulation and OTP device
n 512 bytes on-board RAM
n Real time emulation and full program debug offered by
MetaLink’s Development System
Additional Peripheral Features
n Idle Timer
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
2
™
™ ™ ™ ™
CMOS , MICROWIRE/PLUS , COPS , MICROWIRE and WATCHDOG are trademarks of National Semiconductor Corporation.
M
IBM®, PC®, PC-AT® and PC/XT® are registered trademarks of International Business Machines Corporation.
™
iceMASTER is a trademark of MetaLink Corporation.
© 2000 National Semiconductor Corporation
DS012065
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Block Diagram
DS012065-1
FIGURE 1. COP888GW Block Diagram
Connection Diagram
DS012065-2
Top View
Order Number COP888GW-XXX/V
See NS Package Number V68A
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2
Absolute Maximum Ratings (Note 1)
Total Current out of GND Pin (Sink)
Storage Temperature Range
Note 1: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
110 mA
−65˚C to +150˚C
SuppIy Voltage (VCC
Voltage at Any Pin
)
7V
−0.3V to VCC +0.3V
100 mA
Total Current into VCC Pin (Source)
DC Electrical Characteristics
COP888GW: −40˚C ≤ TA ≤ 85˚C unless otherwise specified
Parameter ConditIons
Operating Voltage
Min
Typ
Max
6.0
UnIts
2.5
V
V
Power Supply Ripple (Note 2)
Supply Current (Note 3)
CKI = 10 MHz
Peak-to-Peak
0.1 VCC
VCC = 6V, tc = 1 µs
10
1.7
10
mA
mA
µA
CKI = 4 MHz
VCC = 2.5V, tc = 2.5 µs
VCC = 6V, CKI = 0 MHz
<
HALT Current (Note 4)
IDLE Current
1
CKI = 10 MHz
VCC = 6V
1.7
0.4
mA
mA
CKI = 4 MHz
VCC = 2.5V
Input Levels (VIH, VIL)
RESET , CKI
Logic High
0.8 VCC
0.7 VCC
V
V
Logic Low
0.2 VCC
All Other Inputs
Logic High
V
V
Logic Low
0.2 VCC
+2
Hi-Z Input Leakage
Input Pullup Current
G Port Input Hysteresis
Output Current Levels
D Outputs
VCC = 6V
−2
µA
µA
V
VCC = 6V, VIN = 0V
(Note 7)
−40
−250
0.05 VCC
0.35 VCC
Source
VCC = 4V, VOH = 3.3V
VCC = 2.5V, VOH = 1.8V
VCC = 4V, VOL = 1V
−0.4
−0.2
10
mA
mA
mA
mA
Sink
VCC = 2.5V, VOL = 0.4V
2.0
All Others
Source (Weak Pull-Up Mode)
VCC = 4V, VOH = 2.7V
VCC = 2.5V, VOH = 1.8V
VCC = 4V, VOH = 3.3V
VCC = 2.5V, VOH = 1.8V
VCC = 4V, VOL = 0.4V
VCC = 2.5V, VOL = 0.4V
VCC = 6.0V
−10
−2.5
−0.4
−0.2
1.6
−100
−33
µA
µA
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
mA
mA
mA
mA
µA
0.7
TRI-STATE Leakage
Allowable Sink/Source
Current per Pin
−2
+2
D Outputs (Sink)
15
3
mA
mA
mA
All others
±
Maximum Input Current
without Latchup (Notes 5, 7)
RAM Retention Voltage, VR (Note 6)
Input Capacitance
Room Temp
200
500 ns Rise and Fall Time (min)
2
V
(Note 7)
(Note 7)
7
pF
pF
Load Capacitance on D2
1000
3
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AC Electrical Characteristics
COP888GW: −40˚C ≤ TA ≤ 85˚C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (tc)
<
Crystal, Resonator
Ceramic
2.5V ≤ VCC 4V
2.5
1.0
40
DC
DC
60
5
µs
µs
%
VCC ≥ 4V
CKI Clock Duty Cycle (Note 6)
Rise Time (Note 6)
Fall Time (Note 6)
Inputs
f = Max
f = 10 MHz Ext Clock
f = 10 MHz Ext Clock
µs
µs
5
tSETUP
VCC ≥ 4V
200
500
60
ns
ns
ns
ns
<
2.5V ≤ VCC 4V
tHOLD
VCC ≥ 4V
<
2.5V ≤ VCC 4V
150
Output Propagation Delay (Note 9)
RL = 2.2k, CL = 100 pF
tPD1, tPD0
SO, SK
VCC ≥ 4V
0.7
1.8
1
µs
µs
µs
µs
ns
ns
ns
<
2.5V ≤ VCC 4V
All Others
VCC ≥ 4V
<
2.5V ≤ VCC 4V
2.5
™
MICROWIRE Setup Time (tUWS) (Note 7)
MICROWIRE Hold Time (tUWH) (Note 7)
MICROWIRE Output Propagation Delay (tUPD
Input Pulse Width (Note 8)
VCC ≥ 4V
VCC ≥ 4V
VCC ≥ 4V
20
56
)
220
Interrupt Input High Time
1
1
1
1
1
1
1
tc
tc
Interrupt Input Low Time
Timer 1, 2 Input High Time
tc
Timer 1, 2 Input Low Time
tc
Capture Timer High Time
CKI
CKI
tc
Capture Timer Low Time
Reset Pause Width
Note 2: Maximum rate of voltage change to be defined.
Note 3: Supply current is measured after running 2000 cydes with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 4: The HALT mode will stop CKI from oscillatng. Test conditions: All inputs tied to V , L, C, E, F, and G port I/O’s configured as outputs and programmed low
CC
and not driving a load; D outputs programmed low and not driving a load. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part
will pull up CKI during HALT in crystal clock mode.
Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than V
and the pins will have sink current
CC
to V when biased at voltages greater than V (the pins do not have source current when biased at a voltage below V .) The effective resistance to V is 750Ω
CC
CC
CC
CC
(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14 volts. WARNING: Voltages in excess of 14 volts will cause damage
to the pins. This warning excludes ESD transients.
Note 6: Condition and parameter valid only for part in HALT mode.
Note 7: Parameter characterized but not tested.
Note 8: t = Instruction Cycle Time
c
Note 9: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
DS012065-3
FIGURE 2. MICROWIRE/PLUS Timing
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4
AC Electrical Characteristics (Continued)
Typical Performance Characteristics
Port D Source Current
Port D Sink Current
DS012065-23
DS012065-24
DS012065-26
DS012065-28
DS012065-30
Ports C/G/L/E/F Source Current
Ports C/G/L/E/F Sink Current
Dynamic — IDD vs VCC
HALT — IDD vs VCC
DS012065-25
Ports C/G/L/E/F Weak Pull-Up Source Current
DS012065-27
Idle — IDD vs VCC
DS012065-29
5
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PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.
Pin Descriptions
VCC and GND are the power supply pins. All VCC and GND
pins must be connected.
The Port L supports Multi-Input Wake Up on all eight pins. L1
is used for the UART external clock. L2 and L3 are used for
the UART transmit and receive. L4 and L5 are used for the
timer input functions T2A and T2B. L6 and L7 are used for
the capture timer input functions CAP1 and CAP2.
CKI is the clock input. This comes from an R/C generated
oscillator, or a crystal oscillator (in conjunction with CKO).
See Oscillator Description section.
RESET is the master reset input. See Reset description sec-
tion.
The Port L has the following alternate features:
L0 MIWU
The device contains five bidirectional 8-bit I/O ports (C, E, F,
G and L), where each individual bit may be independently
configured as an input (Schmitt trigger inputs on ports L and
G), output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these
I/O ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also re-
served for the input pins of each I/O port. (See the memory
map for the various addresses associated with the I/O ports.)
Figure 3 shows the I/O port configurations. The DATA and
CONFIGURATION registers allow for each port bit to be in-
dividually configured under software control as shown below:
L1 MIWU or CKX
L2 MIWU or TDX
L3 MIWU or RDX
L4 MIWU or T2A
L5 MIWU or T2B
L6 MIWU or CAP1
L7 MIWU or CAP2
Port G is an 8-bit port with 6 I/O pins (G0–G5), an input pin
(G6), and a dedicated output pin (G7). Pins G0–G6 all have
Schmitt Triggers on their inputs. Pin G7 serves as the dedi-
cated output pin for the CKO clock output. There are two reg-
isters associated with the G Port, a data register and a con-
figuration register. Therefore, each of the 6 I/O bits (G0–G5)
can be individually configured under software control.
Configuration
Data
Register
0
Port Set-Up
Register
0
Hi-Z Input
(TRI-STATE Output)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output
0
1
1
1
0
1
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6
Pin Descriptions (Continued)
DS012065-4
FIGURE 3. I/O Port Configurations
Since G6 is an input only pin and G7 is dedicated CKO clock
output pin, the associated bits in the data and configuration
registers for G6 and G7 are used for special purpose func-
tions as outlined below. Reading the G6 and G7 data bits will
return zeros.
memory (RAM). Both ROM and RAM have their own sepa-
rate addressing space with separate address buses. The ar-
chitecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.
CPU REGISTERS
Note that the chip will be placed in the HALT mode by writing
a “1” to bit 7 of the Port G Data Register. Similarly the chip
will be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (tc) cycle time.
There are six CPU registers:
Writing a “1” to bit 6 of the Port G Configuration Register en-
ables the MICROWIRE/PLUS to operate with the alternate
phase of the SK clock.
A is the 8-bit Aocumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
Config Reg.
Not Used
Data Reg.
HALT
G7
G6
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
Alternate SK
IDLE
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
Port G has the following alternate features:
G0 INTR (ExternaI Interrupt Input)
G2 T1B (Timer T1 Capture Input)
G3 T1A (Timer T1 I/O)
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM ad-
dress 06F with reset.
G4 SO (MICROWIRE Serial Data Output)
G5 SK (MICROWIRE SeriaI Clock)
G6 SI (MICROWIRE Serial Data Input)
Port G has the following dedicated functions:
G7 CKO OsciIlator dedicated output
Ports C and F are 8-bit I/O ports.
S is the 8-bit Data Segment Address Register used to extend
the Iower haIf of the address range (00 to 7F) into 256 data
segments of 128 bytes each.
All the CPU registers are memory mapped with the excep-
tion of the AccumuIator (A) and the Program Counter (PC).
PROGRAM MEMORY
Port E is an 8-bit I/O port. It has the following alternate fea-
tures:
The program memory consists of 16384 bytes of ROM.
These bytes may hoId program instructions or constant data
(data tables for the LAID instruction, jump vectors for the JID
instruction, and interrupt vectors for the VIS instruction). The
program memory is addressed by the 15-bit program
counter (PC). All interrupts in the devices Vector to program
memory location OFF Hex.
E0 CT1 (Output for counter1, PuIse Train Generator)
E1 CT2 (Output for counter2, Pulse Train Generator)
E2 CT3 (Output for counter3, PuIse Train Generator)
E3 CT4 (Output for counter4, Pulse Train Generator)
Port I is an eight-bit Hi-Z input port.
DATA MEMORY
Port D is an 8-bit output port that is preset high when RESET
goes Iow. The user can tie two or more D port outputs (ex-
cept D2) together in order to get a higher drive.
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X, SP pointers and S register.
Functional Description
The architecture of the device is modified Harvard architec-
ture. With the Harvard architecture, the control store pro-
gram memory (ROM) is separated from the data store
7
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Figure 4 illustrates how the S register data memory exten-
sion is used in extending the lower half of the base address
range (00 to 7F hex) into 256 data segments of 128 bytes
each, with a total addressing range of 32 kbytes from XX00
to XX7F. This organization allows a total of 256 data seg-
ments of 128-bytes each with an additional upper base seg-
ment of 128 bytes. Furthermore, all addressing modes are
availabIe for all data segments. The S register must be
changed under program control to move from one data seg-
ment (128 bytes) to another. However, the upper base seg-
ment (containing the 16 memory registers, I/O registers,
controI registers, etc.) is always available regardless of the
contents of the S register, since the upper base segment
(address range 0080 to 00FF) is independent of data seg-
ment extension.
Functional Description (Continued)
The data memory consists of 512 bytes of RAM. Sixteen
bytes of RAM are mapped as “registers” at addresses 0F0 to
0FF Hex. These registers can be loaded immediately, and
also decremented and tested with the DRSZ (decrement
register and skip if zero) instruction. The memory pointer
registers X, SP, B and S are memory mapped into this space
at address locations 0FC to 0FF Hex respectively, with the
other registers being available for general usage.
Note: RAM contents are undefined upon power-up.
Data Memory Segment RAM
Extension
Data memory address 0FF is used as a memory mapped lo-
cation for the Data Segment Address Register (S).
The instructions that utilize the stack pointer (SP) always ref-
erence the stack as part of the base segment (Segment 0),
regardless of the contents of the S register. The S register is
not changed by these instructions. Consequently, the stack
(used with subroutine linkage and interrupts) is always lo-
cated in the base segment. The stack pointer will be initial-
ized to point at data memory location 006F as a result of re-
set.
The data store memory is either addressed directly by a
single-byte address within the instruction, or indirectly rela-
tive to the reference of the B, X, or SP pointers (each con-
tains a single-byte address). This single-byte address allows
an addressing range of 256 locations from 00 to FF hex. The
upper bit of this single-byte address divides the data store
memory into two separate sections as outlined previously.
With the exception of the RAM register memory from ad-
dress locations 00F0 to 00FF, all RAM memory is memory
mapped with the upper bit of the single-byte address being
equal to zero. This allows the upper bit of the single-byte ad-
dress to determine whether or not the base address range
(from 0000 to 00FF) is extended. If this upper bit equals one
(representing address range 0080 to 00FF), then address
extension does not take place. Alternatively, if this upper bit
equals zero, then the data segment extension register S is
used to extend the base address range (from 0000 to 007F)
from XX00 to XX7F, where XX represents the 8 bits from the
S register. Thus the 128-byte data segment extensions are
located from addresses 0100 to 017F for data segment 1,
0200 to 027F for data segment 2, etc., up to FF00 to FF7F
for data segment 255. The base address range from 0000 to
007F represents data segment 0.
The 128 bytes of RAM contained in the base segment are
split between the Iower and upper base segments. The first
112 bytes of RAM are resident from address 0000 to 006F in
the Iower base segment, while the remaining 16 bytes of
RAM represent the 16 data memory registers located at ad-
dresses 00F0 to 00FF of the upper base segment. No RAM
is located at the upper sixteen addresses (0070 to 007F) of
the lower base segment.
Additional RAM beyond these initial 128 bytes, however, will
always be memory mapped in groups of 128 bytes (or less)
at the data segment address extensions (XX00 to XX7F) of
the lower base segment. The additional 384 bytes of RAM in
this device are memory mapped at address locations 0100
to 017F˚ 0200 to 027F, and 0300 to 037F hex.
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8
Data Memory Segment RAM Extension (Continued)
DS012065-5
Note 10: Reads as all ones.
FIGURE 4. RAM Organization
Reset
This device enters a reset state immediately upon detecting
a logic low on the RESET pin. The RESET pin must be held
low for a minimum of one instruction cycle to guarantee a
valid reset. During power-up initialization, the user must in-
sure that the RESET pin is held low until this device is within
the specified VCC voltage. An R/C circuit on the RESET pin
with a delay 5 times (5x) greater than the power supply rise
time is recommended.
Port D: HIGH
PC: CLEARED
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
T1CNTRL: CLEARED
When the RESET input goes low, the I/O ports are initialized
immediately, with any observed delay being only propaga-
tion delay. When the RESET pin goes high, this device
comes out of the reset state synchronously. This device will
be running within two instruction cycles of the RESET pin go-
ing high.
T2CNTRL: CLEARED
TxRA, TxRB: RANDOM
CCMR1, CCMR2: CLEARED
CM1PSC, CM1CRL, CM1CRH, CM2PSC, CM2CRL, and
CM2CRH:
RESET may also be used to exit this device from the HALT
mode.
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
Some registers are reset to a known state, whereas other
registers and RAM are “unchanged” by reset. When the con-
troller goes into reset state while it is performing a write op-
eration to one of these registers or RAM that are “un-
changed” by reset, the register or RAM value will become
unknown (i.e. not unchanged). This is because the write op-
eration is terminated prematurely by reset and the results
become uncertain. These registers and RAM locations are
unchanged by reset only if they are not written to when the
controller resets.
CCR1 and CCR2: CLEARED
CxPRH, CxPRL, CxCTH, and CxCTL:
UNAFFECTED after RESET with RC clock option (power al-
ready applied)
RANDOM after RESET at power-on
PSR, ENUR and ENUI: CLEARED
ENU: CLEARED except Bit 1 (TBMT) = 1
Accumulator, Timer 1 and Timer 2:
RANDOM after RESET with crystal clock option (power al-
ready applied)
The following initializations occur with RESET :
Port L: TRI-STATE
RANDOM after RESET at power-on
MDCR: CLEARED
Port C: TRI-STATE
Port G: TRI-STATE
MDR1, MDR2, MDR3, MDR4, MDR5: RANDOM
WKEN, WKEDG: CLEARED
Port E: TRI-STATE
Port F: TRI-STATE
9
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Reset (Continued)
R1
R2
C1
C2
(pF)
CKI Freq
(MHz)
4
Conditions
(kΩ) (MΩ) (pF)
WKPND: RANDOM
0
0
1
1
30
30–36
VCC = 5V
VCC = 5V
S Register: CLEARED
200 100–150
0.455
SP (Stack Pointer): Loaded with 6F Hex
B and X Pointers:
Control Registers
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
RAM:
CNTRL Register (Address X’00EE)
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
SL1 & SL0 Select the MICROWIRE/PLUS clock divide by
(00 = 2, 01 = 4, 1x = 8)
The external RC network shown in Figure 5 should be used
to ensure that the RESET pin is held low until the power sup-
ply to the chip stabilizes.
IEDG
MSEL
T1C0
External interrupt edge polarity select (0 = Ris-
ing edge, 1 = Falling edge)
Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
Timer T1 Start/Stop control in timer modes
1 and 2
T1 Underflow Interrupt Pending Flag in timer
mode 3
T1C1
T1C2
T1C3
Timer T1 mode control bit
Timer T1 mode control bit
Timer T1 mode control bit
DS012065-6
>
RC 5 x POWER SUPPLY RISE TIME
T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1
Bit 7
SL0
FIGURE 5. Recommended Reset Circuit
Bit 0
PSW Register (Address X’00EF)
Oscillator Circuits
The PSW register contains the following select bits:
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration), The CKI input fre-
quency is divided down by 10 to produce the instruction
cycle clock (tc).
GIE
GIobaI interrupt enable (enables interrupts)
EXEN
BUSY
EnabIe externaI interrupt
MICROWIRE/PLUS busy shifting flag
EXPND ExternaI interrupt pending
T1ENA Timer T1 Interrupt Enable for Timer Underflow or
T1A Input capture edge
Figure 6 shows the Crystal diagram
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1, T1 Underflow in Mode 2, T1A capture
edge in mode 3)
C
Carry FIag
HC
Half Carry Flag
HC
Bit 7
C
T1PNDA T1ENA EXPND BUSY EXEN
GIE
Bit 0
The Half-Carry fIag is aIso affected by aII the instructions
that affect the Carry fIag. The SC (Set Carry) and RC (Reset
Carry) instructions wilI respectiveIy set or clear both the
carry flags. In addition to the SC and RC instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry fIags.
DS012065-7
FIGURE 6. Crystal Diagram
CRYSTAL OSCILLATOR
ICNTRL Register (Address X’00E8)
CKI and CKO can be connected to make a closed loop crys-
tal (or resonator) controlled oscillator.
The ICNTRL register contains the foIlowing bits:
T1ENB
Timer T1 Interrupt Enable for T1B Input capture
edge
Table 1 shows the component values required for various
standard crystal values.
T1PNDB Timer T1 Interrupt Pending Flag for T1B capture
edge
TABLE 1. CrystaI Oscillator Configuration, TA = 25˚C
µWEN
EnabIe MICROWIRE/PLUS interrupt
R1
(kΩ) (MΩ) (pF)
30
R2
C1
C2
(pF)
CKI Freq
(MHz)
10
Conditions
µWPND MICROWIRE/PLUS interrupt pending
T0EN
Timer T0 Interrupt Enable (Bit 12 toggle)
Timer T0 Interrupt pending
0
1
30–36
VCC = 5V
T0PND
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10
Each timer block consists of a 16-bit timer, Tx, and two sup-
porting 16-bit autoreload/capture registers, RxA and RxB.
Each timer block has two pins associated with it, TxA and
TxB. The pin TxA supports I/O required by the timer block,
while the pin TxB is an input to the timer block. The powerful
and flexible timer block allows the device to easily perform all
timer functions with minimal software overhead. The timer
block has three operating modes: Processor Independent
PWM mode, External Event Counter mode, and Input Cap-
ture mode.
Control Registers (Continued)
LPEN
L Port Interrupt Enable (Multi-Input Wake up/
Interrupt)
Bit 7 could be used as a flag
Unused
Bit 7
LPEN
T0PND
T0EN
WPND
WEN
T1PNDB T1ENB
Bit 0
T2CNTRL Register (Address X’00C6)
The T2CNTRL register contains the following bits:
The control bits TxC3, TxC2, and TxC1 allow selection of the
different modes of operation.
T2ENB
Timer T2 Interrupt Enable for T2B Input capture
edge
Mode 1. Processor Independent PWM Mode
T2PNDB Timer T2 Interrupt Pending Flag for T2B capture
edge
As the name suggests, this mode allows the device to gen-
erate a PWM signal with very minimal user intervention. The
user only has to define the parameters of the PWM signal
(ON time and OFF time). Once begun, the timer block will
continuously generate the PWM signal completely indepen-
dent of the microcontroller. The user software services the
timer block only when the PWM parameters require updat-
ing.
T2ENA
Timer T2 Interrupt Enable for Timer Underflow or
T2A Input capture edge
T2PNDA Timer T2 Interrupt Pending Flag (Auto reload RA
in mode 1, T2 Underflow in mode 2, T2A capture
edge in mode 3)
T2C0
Timer T2 Start/Stop control in timer modes 1 and
2 Timer T2 Underflow Interrupt Pending Flag in
timer mode 3
In this mode the timer Tx counts down at a fixed rate of tc.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from
the register RxA. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB.
T2C1
T2C2
T2C3
Timer T2 mode control bit
Timer T2 mode control bit
Timer T2 mode control bit
T2C3
Bit 7
T2C2
T2C1
T2C0
T2PNDA
T2ENA
T2PNDB T2ENB
Bit 0
The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.
Timers
Figure 7 shows a block diagram of the timer in PWM mode.
The device contains a very versatile set of timers (T0, T1,
T2). All timers and associated autoreload/capture registers
power up containing random data.
The underfIows can be programmed to toggle the TxA output
pin. The underfIows can also be programmed to generate in-
terrupts.
UnderfIows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending fIags under software control. Two control ena-
bIe fIags, TxENA and TxENB, alIow the interrupts from the
timer underflow to be enabled or disabled. Setting the timer
enable flag TxENA wilI cause an interrupt when a timer un-
derflow causes the RxA register to be reloaded into the timer.
Setting the timer enable flag TxENB will cause an interrupt
when a timer underflow causes the RxB register to be re-
loaded into the timer. Resetting the timer enable flags will
disable the associated interrupts.
TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining
reaI time and Iow power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer T0, which is a
16-bit timer. The Timer T0 runs continuously at the fixed rate
of the instruction cycle cIock, tc. The user cannot read or
write to the IDLE Timer T0, which is a count down timer.
The Timer T0 supports the following functions:
•
•
Exit out of the Idle Mode (See Idle Mode description)
Start up delay out of the HALT mode
Either or both of the timer underflow interrupts may be en-
abled. This gives the user the flexibility of interrupting once
per PWM period on either the rising or falling edge of the
PWM output. Alternatively, the user may choose to interrupt
on both edges of the PWM output.
The IDLE Timer T0 can generate an interrupt when the thir-
teenth bit toggIes. This toggle is Iatched into the T0PND
pending flag, and wiIl occur every 4 ms at the maximum
clock frequency (tc = 1 µs). A control flag T0EN allows the in-
terrupt from the thirteenth bit of Timer T0 to be enabled or
disabIed. Setting T0EN will enable the interrupt, while reset-
ting it will disable the interrupt.
Mode 2. ExternaI Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that the
timer, Tx, is cIocked by the input signal from the TxA pin. The
Tx timer control bits, TxC3, TxC2 and TxC1 allow the timer to
be clocked either on a positive or negative edge from the
TxA pin. Underflows from the timer are Iatched into the TxP-
NDA pending flag. Setting the TxENA control flag will cause
an interrupt when the timer underflows.
TIMER T1 AND TIMER T2
The device has a set of two powerful timer/counter blocks,
T1 and T2. The associated features and functioning of a
timer block are described by referring to the timer block Tx.
Since the two timer blocks, T1 and T2 are identical, all com-
ments are equally applicable to either of the two timer
blocks.
11
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Timers (Continued)
DS012065-8
FIGURE 7. Timer in PWM Mode
DS012065-9
FIGURE 8. Timer in External Event Counter Mode
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12
The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively Iatched into the
pending flags, TxPNDA and TxPNDB.
Timers (Continued)
In this mode the input pin TxB can be used as an indepen-
dent positive edge sensitive interrupt input if the TxENB con-
trol flag is set. The occurrence of a positive edge on the TxB
input pin is latched into the TxPNDB flag.
The control flag TxENA allows the interrupt on TxA to be ei-
ther enabled or disabled. Setting the TxENA flag enables in-
terrupts to be generated when the selected trigger condition
occurs on the TxA pin. Similarly, the flag TxENB controls the
interrupts from the TxB pin.
Figure 8 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is being
used as the counter input clock.
Underflows from the timer can also be programmed to gen-
erate interrupts. Underflows are latched into the timer TxC0
pending flag (the TxC0 control bit serves as the timer under-
flow interrupt pending flag in the Input Capture mode). Con-
sequently, the TxC0 control bit should be reset when enter-
ing the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
the TxPNDA and TxC0 pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.
Mode 3. Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the in-
put capture mode.
In this mode, the timer Tx is constantly running at the fixed tc
rate. The two registers, RxA and RxB, act as capture regis-
ters. Each register acts in conjunction with a pin. The register
RxA acts in conjunction with the TxA pin and the register RxB
acts in conjunction with the TxB pin.
Figure 9 shows a block diagram of the timer in Input Capture
mode.
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
TxC3, TxC2 and TxC1, allow the trigger events to be speci-
fied either as a positive or a negative edge. The trigger con-
dition for each input pin can be specified independently.
DS012065-10
FIGURE 9. Timer in Input Capture Mode
TIMER CONTROL FLAGS
The timer mode controI bits (TxC3, TxC2 and TxC1) are de-
tailed beIow:
The timers T1 and T2 have identical control structures. The
control bits and their functions are summarized below.
Capture Timer
TxC0
Timer Start/Stop controI in Modes 1 and 2 (Pro-
cessor Independent PWM and External Event
Counter), where 1 = Start, 0 = Stop Timer Under-
fIow Interrupt Pending Flag in Mode 3 (Input Cap-
ture)
This device contains two independent capture timers, Cap-
ture Timer 1 and Capture Timer 2. Each capture timer con-
tains an 8-bit programmable prescaler register, a 16-bit
down counter, a 16-bit input capture register, and capture
edge select Iogic. The 16-bit down counter is clocked at a
specific frequency determined by the value loaded into the
prnscaler register. A selected positive or negative edge tran-
sition on the capture input causes the contents of the down
counter to be latched into the capture register. The values
captured in the registers reflect the eIapsed time between
two positive or two negative transitions on the capture input.
The time between a positive and negative edge (a pulse
width) may be measured if the selected capture edge is
switched after the first edge is captured. Each capture timer
TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag
TxENA
TxENB
Timer Interrupt Enable FIag
Timer Interrupt Enable Flag
1 = Timer Interrupt EnabIed
0 = Timer Interrupt Disabled
Timer mode controI
TxC3
TxC2
TxC1
Timer mode control
Timer mode controI
13
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Figure 10 shows the capture timer 1 block diagram.
Capture Timer (Continued)
may be stopped/started under software control, and each
capture timer may be configured to interrupt the microcon-
troller on an underflow or input capture.
TABLE 2. Timer Mode Control
TxC3 TxC2 TxC1
Timer Mode
Interrupt A
Interrupt B
Source
Timer
Source
Timer Underflow
Timer Underflow
Counts On
0
0
0
0
0
1
MODE 2 (External Event Counter)
MODE 2 (External Event Counter)
Positive TxB Edge
Positive TxB Edge
TxA Positive Edge
TxA Negative
Edge
1
1
0
0
0
1
1
0
0
MODE 1 (PWM) TxA Toggle
MODE 1 (PWM) No TxA Toggle
MODE 3 (Capture) Captures:
TxA Positive Edge
Autoreload RA
Autoreload RB
Autoreload RB
Positive TxB Edge
tc
tc
tc
Autoreload RA
Positive TxA Edge or
Timer Underflow
TxB Positive Edge
1
0
1
1
1
1
0
1
1
MODE 3 (Capture) Captures:
TxA Positive Edge
Positive TxA Edge or
Timer Underflow
Negative TxB
Edge
tc
tc
tc
TxB Negative Edge
MODE 3 (Capture) Captures:
TxA Negative Edge
Negative TxA Edge or
Timer Underflow
Positive TxB Edge
TxB Positive Edge
MODE 3 (Capture) Captures:
TxA Negative Edge
Negative TxA Edge or
Timer Underflow
Negative TxB
Edge
TxB Negative Edge
DS012065-11
FIGURE 10. Capture Timer 1 Block Diagram
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14
FUNCTIONAL DESCRIPTION
Capture Timer (Continued)
The capture timer is used to determine the time between
events, where an event is simply a selected edge transition
on the capture input. The resolution of the time measure-
ment is dependent on the frequency at which the down
counter is clocked. The vaIue Ioaded into the prescaler con-
trols this frequency.
The registers shown in the block diagram include those for
Capture Timer 1 (CM1), as well as, the capture timer 1 con-
trol register. These registers are read/writable (with the ex-
ception of the capture registers, which are read-only) and
may be accessed through the data memory address/data
bus. The registers are designated as:
The prescaIer is clocked by CKI, while the down counter is
clocked on every underfIow of the prescaler. This means the
prescaIer simpIy divides the CKI cIock before it is fed into the
down counter. The prescaler register must be Ioaded with a
vaIue corresponding to the CKI divisor needed to produce
the desired down counter clock. The appropriate prescaler
vaIue can be determined using the following equation:
CM1PSC Capture Timer 1 Prescaler (8-bit)
CM1CRL Capture Timer 1 Capture Register (Low-byte),
read-only
CM1CRH Capture Timer 1 Capture Register (High-byte),
read-only
CM2PSC Capture Timer 2 Prescaler (8-bit)
Down Counter Clock Frequency = CKI/(CMxPSC + 1)
CM2CRL Capture Timer 2 Capture Register (Low-byte),
read-only
The capture input signaI is set up by configuring the port pin
associated with the capture timer as an input. The edge
seIect bit for the capture input is then set or reset according
to the desired transition. If the pin is configured as an input,
the appropriate externaI transition will cause a capture. If the
pin is configured as an output, toggling the data register bit
wiIl cause a capture. If interrupts are used, the capture timer
interrupt pending bits are cIeared and the capture timer inter-
rupt enable bit is set. Both interrupt sources, down counter
underflow and input capture edge, are enabled/disabled with
the same CMxIEN bit. The GIE bit must also be set to enable
interrupts. The interrupt signals from the two capture timers
are gated to a single 16-bit interrupt vector located at ad-
dresses 0xE6 and 0xE7.
CM2CRH Capture Timer 2 Capture Register (High-byte),
read-only
CCMR1 Control Register for Capture Timer 1
CCMR2 Control Register for Capture Timer 2
CONTROL REGISTER BITS
The control bits for Capture Timer 1 (CM1) and Capture
Timer 2 (CM2) are contained in CCMR1 and CCMR2.
The CCMR1 Register Bits are:
CM1RUN CM1 start/stop control bit (1 = start; 0 = stop)
CM1IEN CM1 interrupt enable control bit (1 = enable IRQ)
CM1IP1
CM1 interrupt pending bit 1 (1 = CM1 under-
flowed)
The capture timer is started by writing a “1” to the capture
timer start/stop bit. Setting this bit also enables the port pin to
be the capture input to the capture timer. The internal pres-
caler is loaded with the contents of the prescaler register,
and begins counting down. Setting the start/stop bit also
loads the down counter with 0FFFF Hex. The prescaler is
clocked by CKI. An underflow of the prescaler decrements
the 16-bit down counter, and reloads the value from the pres-
caler register into the prescaler. Each additional underflow of
the prescaler decrements the down counter, and reloads the
prescaler from the prescaler register.
CM1IP2
CM1EC
CM1 interrupt pending bit 2 (1 = CM1 captured)
Select the active edge for capture on CM1 (0 =
rising, 1 = falling)
CM1TM
CM1 test mode control bit (1 = special test path
in test mode. This bit is reserved during normal
operation, and must never be set to one.)
CM1
TM
un-
un- CM1 CM1 CM1 CM1 CM1
used used EC
IP2
IP1 IEN
RUN
Bit 0
If a selected edge transition on the input capture pin occurs,
the contents of the down counter are immediately latched
into the capture register, the down counter is re-initialized to
0FFFF Hex, and the capture input pending flag is set. The
prescaler counter is not loaded. (In order for an input transi-
tion to be guaranteed recognized, the signal on the capture
input pin must have a low pulse width and a high pulse width
of at least one CKI period.) If interrupts are enabled, the cap-
ture timer generates an interrupt. The prescaler and down
counter continue to operate until a reset condition occurs or
the capture timer start/stop bit is reset. The user must pro-
cess capture interrupts faster than the capture input fre-
quency, otherwise input captures may be lost or erroneous
values may be read.
Bit 7
All interrupt pending bits must be reset by software.
The CCMR2 Register Bits are:
CM2RUN CM2 start/stop control bit (1 start; 0=stop)
CM2IEN CM2 interrupt enable control bit (1= enable IRQ)
CM2IP1
CM2 interrupt pending bit 1 (1=CM2 under-
flowed)
CM2IP2
CM2EC
CM2 interrupt pending bit 2 (1=CM2 captured)
Select the active edge for capture on CM2 (0 =
rising, 1 = falling)
CM2TM
CM2 test mode control bit (1 = speciaI test path
in test mode. This bit is reserved during normal
operation, and must never be set to one.)
If the down counter underflows (changes state from 0000 to
FFFF) before a capture input is detected, the underflow in-
terrupt pending flag is set. If interrupts are enabled, the cap-
ture timer generates an interrupt.
CM2
TM
un-
un- CM2 CM2 CM2 CM2
IP2 IP1 IEN
CM
RUN
Bit 0
used used EC
The capture timer may be stopped at any time under soft-
ware control by resetting the capture timer start/stop bit. A
capture may occur before the start/stop bit is physically
cIeared, due to the fully asynchronous nature of the input
capture signal. The user must ensure that the software
handles this situation correctly. If the user wishes to process
this capture and interrupts are being used, the capture timer
Bit 7
AII interrupt pending bits must be reset by software.
15
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2. Configure the corresponding Port bits as inputs
3. Set the edge control bits CMxEC
4. Reset CMxIP1 (CMxIP1 = 0)
Capture Timer (Continued)
interrupts should not be disabIed prior to stopping the timer.
If interrupts are not being used, the user should poll the cap-
ture timer pending bits after stopping the timer. If the user
wishes to ignore this capture and interrupts are being used,
the capture timer interrupt service routine should check that
the timer is still running prior to processing capture inter-
rupts. If the user is polling the pending flags, these flags
should be cleared after the timer is stopped. The contents of
the prescaler and down counter remain unchanged while the
capture timer is stopped. The capture edge detect logic is
disabled, and no capture takes place even if an external cap-
ture signal occurs. The capture timer may be restarted under
software control by writing a “1” to the start/stop bit. This
causes the prescaler and down counter to be re-initialized.
The prescaler is loaded from the prescaler register, and the
down counter is loaded with 0FFFF Hex.
5. Reset CMxIP2 (CMxIP2 = 0)
6. Load the 8-bit prescaler register CMxPSC with the de-
sired value (from 0 to 255)
7. Set CMxIEN (if interrupts are to be used)
8. Set the Global Interrupt Enable (GIE) bit (if interrupts are
to be used)
9. Set CMxRUN bit to start the capture timer
WARNING
In order to avoid erroneous interrupts, the capture timer in-
terrupts must be disabled prior to setting/resetting the cap-
ture edge control bits (CMxEC). In addition, after selecting
the interrupt edge, the pending flags must be reset before
the capture interrupts are enabled or re-enabled. If the initial-
ization sequence outlined above is followed each time the
user aIters the edge control bits, the user is guaranteed to
avoid erroneous interrupts.
RESET STATE
A reset signal applied to the counter block during normal op-
eration has the following effects:
•
•
•
Clear CCMR1 register
Clear CCMR2 register
Pulse Train Generators
This device contains four independent pulse train genera-
tors. Each individual generator is controlled by a correspond-
ing 16-bit counter. Each counter has a 16-bit prescaler and a
16-bit count register. Each counter may be configured to out-
put a selected number of 50% duty cycle pulses. The con-
tents of the prescaler determine the width of the output
pulses, and the value of the count register determines the
number of pulses. Each counter may be stopped/started un-
der software control, and each counter may be configured to
interrupt the microcontroller on an underflow.
CM1PSC, CMICRL, CM1CRH, CM2PSC, CM2CRL and
CM2CRH are unaffected. (At power-on, the contents of
these registers are undefined.)
The bi-directional port pins are initialized during reset as
HI-Z inputs. Setting the start/stop bits connects the pins to
the capture timers.
INITIALIZATION
The user should perform the following initialization prior to
starting the capture timer:
Figure 11 shows the pulse train generator 1 block diagram.
1. Reset the CMxRUN bit
DS012065-12
FIGURE 11. Pulse Train Generator 1 Block Diagram
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16
Pulse Train Generators (Continued)
C4TM
Bit 7
C4
C4
C4
C3TM
C3
C3
C3
IPND
IEN RUN
IPND
IEN
RUN
Bit 0
The four 8-bit registers shown in each individual counter in
the block diagram constitute a 16-bit prescaler and a 16-bit
count register. These registers are all read/writable and may
be accessed through the data memory address/data bus.
The registers are designated as:
All interrupt pending bits must be reset by software.
FUNCTIONAL DESCRIPTION
CxPRL Low-byte of the Prescaler
CxPRH High-byte of the Prescaler
CxCTL Low-byte of the Count Register
CxCTH High-byte of the Count Register
The pulse train generator may be used to produce a series of
output pulses of a given width. The high/low time of a pulse
is determined by the contents of the prescaler. The number
of pulses in a series is determined by the contents of the
count register.
The prescaler is loaded with a value corresponding to the
desired width of the output pulse (tw). The high time and low
time of the output signal are each equal to tw, therefore the
output signal produced has a 50% duty cycle and a period
CONTROL REGISTER BITS
The control bits for Counter 1 and Counter 2 are contained in
the CCR1 register. The CCR1 Register bits are:
C1RUN COUNTER1 start/stop control bit (1 = start; 0 =
stop)
*
equal to 2 tw. The appropriate prescaler value can be de-
termined using the following equation:
C1IEN
COUNTER1 interrupt enable control bit (1 = en-
able IRQ)
*
*
tw = [(PRH 256) + PRL + 1] tc
Since PRH and PRL are both 8-bit registers, this equation al-
lows a maximum tw of 65536 tc and a minimum tw of one tc.
The internal prescaler is automatically loaded from PRH and
PRL when the counter start/stop bit is set.
C1IPND COUNTER1 interrupt pending bit (1 counter 1 un-
derflowed)
C1TM
COUNTER1 test mode control bit (1=special test
path in test mode. This bit is reserved during nor-
mal operation, and must never be set to one.)
The count register is loaded with a value corresponding to
the desired number of output pulses. The appropriate count
value is calculated with the following equation:
C2RUN COUNTER2 start/stop control bit (1 = start; 0 =
stop)
*
Number of Pulses = CTH 256 + CTL + 1
C2IEN
COUNTER2 interrupt enable control bit (1= en-
able IRQ)
The port pin associated with the counter OUT signal is con-
figured in software as an output, and preset to the desired
start logic level. lf interrupts are to be used, the counter inter-
rupt pending bit is cleared and the interrupt enable bit is set.
The GIE bit must also be set to enable interrupts. The inter-
rupt signals from the four counters are gated to a single inter-
rupt vector located at addresses 0xF0–0xF1.
C2IPND COUNTER2 interrupt pending bit (1 =counter 2
underflowed)
C2TM
COUNTER2 test mode control bit (1=special test
path. This bit is reserved during normal operation,
and must never be set to one.)
The counter is started by writing a “1” to the counter start/
stop bit. This resets the divide-by-2 counter which produces
the clock signal for the counter register from the prescaler
underflow (See Figure 11). It also reloads the internal pres-
caler and starts the prescaler counting down on the next ris-
ing edge of tc. The prescaler is clocked on the rising edge of
tc to ensure synchronization. Each subsequent rising edge of
tc causes the prescaler to be decremented. When the pres-
caler underflows, UFL1 is generated (see Figure 12). This
signal causes the port pin to toggle. In addition, the internal
prescaler is reloaded with the value from the PRH and PRL
registers. Each additional underflow of the prescaler causes
the port pin to toggle and reloads the internal prescaler.
All interrupt pending bits must be reset by software.
C2TM
C2
C2
C2
C1TM
C1
C1
C1
IPND
IEN RUN
IPND
IEN
RUN
Bit 0
Bit 7
The control bits for Counter 3 and Counter 4 are contained in
the CCR2 register. The CCR2 Register bits are:
C3RUN COUNTER3 start stop control bit (1 =start; 0 =
stop)
C3IEN
COUNTER3 interrupt enable control bit (1 = en-
able IRQ)
C3IPND COUNTER3 interrupt pending Bit (1=counter 3
underflowed)
Every second underflow of the prescaler generates the sig-
nal UFL2. (UFL2 occurs at half the frequency of UFL1, or
once per output pulse.) This signal, UFL2, decrements the
count register. Therefore, the count registers are decre-
mented once per output pulse.
C3TM
COUNTER3 test mode control bit (1=special test
path. This bit is reserved during normal operation,
and must never be set to one.)
C4RUN COUNTER4 start/stop control bit (1 = start; 0 =
stop)
The underflow of the counter register produces the signal
UFL3. This signal stops the counter by resetting the counter
start/stop bit, and sets the counter interrupt pending flag. If
the counter interrupt is enabled, an interrupt occurs.
C4IEN
COUNTER4 interrupt enable control bit (1 = en-
able IRQ)
C4IPND COUNTER4 interrupt pending bit (1 =counter 4
underflowed
The counter may be stopped at any time under software con-
trol by resetting the counter start/stop bit. The contents of the
count register and the output on the associated port pin are
frozen. The counter may be restarted under software control
by setting the start/stop bit. The internal prescaler is auto-
matically reloaded from PRH and PRL when the counter
start/stop bit is set, therefore a full width pulse will be gener-
ated before the output is toggled. The user may also choose
C4TM
COUNTER4 test mode control bit (1 =special test
path. This bit is reserved during normal operation,
and must never be set to one.)
17
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•
•
Divide-by-2 counter is reset
Pulse Train Generators (Continued)
The bi-directional port pins are initialized during reset as
HI-Z inputs. The appropriate bits must be initialized as
outputs, in order to route the Counter OUT signals to the
port pins.
to alter the logic level on the port pin before restarting. This
is done by initializing the associated port pin data register bit.
A counter underflow may occur before the start/stop bit is
physically cleared by software. The user must ensure that
the software handles this situation correctly. If the user
wishes to process this underflow and interrupts are being
used, the counter interrupts should not be disabled prior to
stopping the timer. If interrupts are not being used, the user
should poll the counter pending bits after stopping the timer.
If the user wishes to ignore this underflow and interrupts are
being used, the counter interrupt should be disabled prior to
stopping the timer. If the user is polling the pending flags,
these flags should be cleared after the timer is stopped.
INITIALIZATION
The user should perform the following initialization prior to
starting the counter:
1. Load PRL register
2. Load PRH register
3. Load CTL register
4. Load CTH register
5. Reset CxIPND bit
If the default level of the output pin is high (associated port
data register bit is set to “1”) and the counter is stopped dur-
ing a low level, the low level becomes the default level. The
software must reinitialize the port pin to a high level before
restarting if necessary. The programmer may also have to
adjust the counter value (See Figure 12).
6. Set CxIEN (if interrupt is to be used)
7. Configure the associated port bit as an output (if OUT is
to be used)
8. Set the Global Interrupt Enable (GIE) bit (if interrupt is to
be used)
9. Set CxRUN bit to start counter
RESET STATE
A reset signal applied to the pulse train generator block dur-
ing normal operation has the following effects:
Multiply/Divide
This device contains a multiply/divide block. This block sup-
ports a 1 byte x 2 bytes (3 bytes result) multiply or a 3 bytes/
2 bytes (2 bytes result) divide operation. The multiply or di-
vide operation is executed by setting control bits located in
the multiply/divide control register. The multiply or divide op-
erands must be placed into the appropriate memory mapped
locations before the operation is initiated.
•
•
•
•
•
•
Counting stops immediately
Interrupt enable bit is reset to zero
Counter start/stop bit is reset to zero
Interrupt pending bit is reset to zero
Test mode controI bit is reset to zero
PRL, PRH, CTL and CTH are unaffected (At power-on re-
set, the contents of the prescaler and count register are
undefined.)
DS012065-13
FIGURE 12. Timing Diagram for PRL=1, PRH=0, CTL=3, CTH=0
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18
Multiply/Divide (Continued)
TABLE 3. Multiply/Divide Registers
Multiplication Assignment
Register Name
(Address)
Division Assignment
Before Operation After Operation
Before Operation
Unused
After Operation
Unchanged
MDR1 (xx98)
MDR2 (xx99)
MDR3 (xx9A)
MDR4 (xx9B)
MDR5 (xx9C)
Low byte of dividend
Middle byte of dividend
High byte of dividend
Low byte of divisor
Low byte of result
High byte of result
Undefined
Multiplier
Low byte of result
Middle byte of result
High byte of result
Unchanged
Low byte of multiplicand
High byte of multiplicand
Low byte of divisor
High byte of divisor
High byte of divisor
CONTROL REGISTER BITS
bit is set in the multiply/divide control register. The dividend
and the divisor are left unchanged. The divide operation al-
ways causes the DIVOVF flag to be set or reset as appropri-
ate. The DIVOVF flag is cleared following a multiply opera-
tion.
The Multiply/Divide control register (MDCR) is located at ad-
dress xx9D. It has the following bit assignments:
MULT
DIV
Start Multiplication Operation (1 = start)
Start Division Operation (1 = start)
DIVOVF Division Overflow (if the result of a division is
greater than 16 bits or the user attempted to divide
by zero; 1 = error)
RESET STATE
A reset signal applied to the device during normal operation
has the following affects:
MDCR is cleared, and any operation in progress is stopped.
MDR1 through MDR5 are undefined.
Rsvd Rsvd Rsvd Rsvd Rsvd DIV DIV MULT
OVF
Bit 7
Bit 0
Power Save Modes
After the appropriate MDR registers are loaded, the MULT
and DIV start bits are set by the user to start a multiply or di-
vide operation. The division operation has priority, if both bits
are set simultaneously. The MULT and DIV bits are BOTH
automatically cleared by hardware at the end of a divide or
multiply operation. Each division operation causes the DI-
VOVF flag to be set/reset as appropriate. The DIVOVF flag
is cleared following a multiplication operation. DIVOVF is a
read-only bit. The MULT and DIV bits are read/writable. Bits
3-7 in MDCR should not be used, as the MULT and DIV op-
erations will change their values.
The device offers the user two power save modes of opera-
tion: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscil-
lator circuitry and timer T0 are active but all other microcon-
troller activities are stopped. In either mode, all on-board
RAM, registers, I/O states, and timers (with the exception of
T0) are unaltered.
HALT MODE
The device can be placed in the HALT mode by writing a “1”
to the HALT flag (G7 data bit). All microcontroller activities,
including the clock and timers, are stopped. In the HALT
mode, the power requirements of the device are minimal and
the applied voltage (VCC) may be decreased to Vr (Vr
2.0V) without altering the state of lhe machine.
MULTIPLY/DIVIDE OPERATION
For the multiply operation, the muItiplicand is placed at ad-
dresses xx9B and xx9C. The multiplier is placed at address
xx99. For the divide operation, the dividend is placed at ad-
dresses xx98 to xx9A and the divisor is placed at addresses
xx9B to xx9C. In both operations, all operands are inter-
preted as unsigned values. The divide or multiply operation
is started by setting the appropriate MDCR bit. If both the
MULT and DIV bits are set, the microcontroller performs a di-
vide operation. (The user is not required to read or clear the
DIVOVF error bit prior to beginning a new multiply/divide op-
eration. This bit is ignored during subsequent operations.
However, the next divide operation will overwrite the error
flag as appropriate, and the next multiply operation will clear
it.)
=
The device supports two different ways of exiting the HALT
mode. The first method of exiting the HALT mode is with the
Multi-Input Wakeup feature on the L port. The second
method of exiting the HALT mode is by pulling the RESET
pin low.
Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full ampli-
tude and frequency stability. The IDLE timer is used to gen-
erate a fixed deIay to ensure that the oscilIator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wakeup signal, only the oscillator cir-
cuitry is enabled. The IDLE timer is loaded with a value of
256 and is clocked with the tc instruction cycle clock. The tc
clock is derived by dividing the oscillator clock down by a fac-
tor of 10. The Schmitt trigger following the CKI inverter on
the chip ensures that the IDLE timer is clocked only when the
oscillator has a sufficiently large amplitude to meet the
Schmitt trigger specifications. This Schmitt trigger is not part
of the oscillator closed loop. The startup timeout from the
IDLE timer enables the clock signals to be routed to the rest
of the chip.
The multiply operation requires 1 instruction cycle to com-
plete. The divide operation requires 2 instruction cycles to
complete. A divide by zero or a division which produces an
overflow requires only 1 instruction cycle to execute. The
MDR1 through MDR5 registers and the MDCR register can
not be read from or written to during a multiply or divide op-
eration. Any attempt to write into these registers will be ig-
nored. Any attempt to read these registers will return unde-
fined data.
The result of a multiply is placed in addresses xx99-xx9B.
The result of a divide is placed in addresses xx98-xx99. If a
division by zero is attempted or if the resulting quotient of a
divide operation is more than 16 bits long, then the DIVOVF
19
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The user can enter the IDLE mode with the Timer T0 inter-
rupt enabled. In this case, when the T0PND bit gets set, the
device will first execute the Timer T0 interrupt service routine
and then return to the instruction following the “Enter Idle
Mode” instruction.
Power Save Modes (Continued)
The devices have two mask options associated with the
HALT mode. The first mask option enables the HALT mode
feature, while the second mask option disables the HALT
mode. With the HALT mode enable mask option, the device
will enter and exit the HALT mode as described above. With
the HALT disable mask option, the device cannot be placed
in the HALT mode (writing a “1” to the HALT flag will have no
effect, the HALT flag will remain “0”).
Alternatively, the user can enter the IDLE mode with the
IDLE Timer T0 interrupt disabled. In this case, the device will
resume normal operation with the instruction immediately
following the “Enter IDLE Mode” instruction.
Note: It is necessary to program two NOP instructions following both the set
HALT mode and set IDLE mode instructions. These NOP instructions
are necessary to allow clock resynchronization following the HALT or
IDLE modes.
IDLE MODE
The device is placed in the IDLE mode by writing a “1” to the
IDLE flag (G6 data bit). In this mode, all activities, except the
associated on-board oscillator circuitry and the IDLE Timer
T0, are stopped.
Multi-Input Wakeup
The Multi-Input Wake Up feature is used to return (wake up)
the device from either the HALT or IDLE modes. Alternately
Multi-Input Wake Up/Interrupt feature may also be used to
generate up to 8 edge selectable external interrupts.
As with the HALT mode, the device can be returned to nor-
mal operation with a reset, or with a Multi-Input Wake up
from the L Port. Alternately, the microcontroller resumes nor-
mal operation from the IDLE mode when the thirteenth bit
(representing 4.096 ms at internal clock frequency of
10 MHz, tc = 1 µs) of the IDLE Timer toggles.
Figure 13 shows the Multi-Input Wake Up logic.
This toggle condition of the thirteenth bit of the IDLE Timer
T0 is latched into the T0PND pending flag.
The user has the option of being interrupted with a transition
on the thirteenth bit of the IDLE Timer T0. The interrupt can
be enabled or disabled via the T0EN control bit. Setting the
T0EN flag enables the interrupt and vice versa.
DS012065-15
FIGURE 13. Multi-Input Wake Up Logic
The Multi-Input Wake Up feature utilizes the L Port. The user
selects which particular L port bit (or combination of L Port
bits) will cause the device to exit the HALT or IDLE modes.
The selection is done through the register WKEN. The regis-
ter WKEN is an 8-bit read/write register, which contains a
control bit for every L port bit. Setting a particular WKEN bit
enables a Wake Up from the associated L port pin.
The user can select whether the trigger condition on the se-
lected L Port pin is going to be either a positive edge (low to
high transition) or a negative edge (high to low transition).
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20
The interrupt from Port L shares logic with the wake up cir-
cuitry. The register WKEN allows interrupts from Port L to be
individually enabled or disabled. The register WKEDG speci-
fies the trigger condition to be either a positive or a negative
edge. Finally, the register WKPND latches in the pending
trigger conditions.
Multi-Input Wakeup (Continued)
This selection is made via the register WKEDG, which is an
8-bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a Wake
Up condition as a result of the edge change. First, the asso-
ciated WKEN bit should be reset, followed by the edge select
change in WKEDG. Next, the associated WKPND bit should
be cleared, followed by the associated WKEN bit being reen-
abled.
The GIE (Global Interrupt Enable) bit enables the interrupt
function.
A control flag, LPEN, functions as a global interrupt enable
for Port L interrupts. Setting the LPEN flag will enable inter-
rupts and vice versa. A separate global pending flag is not
needed since the register WKPND is adequate.
Since Port L is also used for waking the device out of the
HALT or lDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If he
elects to disable the interrupt, then the device will restart ex-
ecution from the instruction immediately following the in-
struction that placed the microcontroller in the HALT or IDLE
modes. In the other case, the device will first execute the in-
terrupt service routine and then revert to normal operation.
(See HALT MODE for clock option wake up information.)
An example may serve to clarify this procedure. Suppose we
wish to change the edge select from positive (low going high)
to negative (high going low) for L Port bit 5, where bit 5 has
previously been enabled for an input interrupt. The program
would be as follows:
RBIT 5, WKEN
SBIT 5, WKEDG
RBIT 5, WKPND
SB1T 5, WKEN
If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wake Up/lnterrupt, a
safety procedure should also be followed to avoid wakeup
conditions. After the selected L port bits have been changed
from output to input but before the associated WKEN bits are
enabled, the associated edge select bits in WKEDG should
be set or reset for the desired edge selects, followed by the
associated WKPND bits being cleared,
UART
The device contains a full-duplex software programmable
UART. The UART (Figure 14) consists of a transmit shift reg-
ister, a receive shift register and seven addressable regis-
ters, as follows: a transmit buffer register (TBUF), a receiver
buffer register (RBUF), a UART control and status register
(ENU), a UART receive control and status register (ENUR),
a UART interrupt and clock source register (ENUI), a pres-
caler select register (PSR) and baud (BAUD) register. The
ENU register contains flags for transmit and receive func-
tions; this register also determines the length of the data
frame (7, 8 or 9 bits), the value of the ninth bit in transmis-
sion, and parity selection bits. The ENUR register flags fram-
ing, data overrun and parity errors while the UART is receiv-
ing.
This same procedure should be used following reset, since
the L port inputs are left floating as a result of reset.
The occurrence of the selected trigger condition for
Multi-Input Wake Up is latched into a pending register called
WKPND. The respective bits of the WKPND register will be
set on the occurrence of the selected trigger edge on the cor-
responding Port L pin. The user has the responsibility of
clearing these pending flags. Since WKPND is a pending
register for the occurrence of selected wake up conditions,
the device will not enter the HALT mode if any Wake Up bit
is both enabled and pending. Consequently, the user must
clear the pending flags before attempting to enter the HALT
mode.
Other functions of the ENUR register include saving the
ninth bit received in the data frame, enabling or disabling the
UART’s attention mode of operation and providing additional
receiver/transmitter status information via RCVG and XMTG
bits. The determination of an internal or external clock
source is done by the ENUI register, as well as selecting the
number of stop bits and enabling or disabling transmit and
receive interrupts. A control flag in this register can also se-
lect the UART mode of operation: asynchronous or
synchronous.
WKEN, WKPND and WKEDG are all read/write registers,
and are cleared at reset.
PORT L INTERRUPTS
Port L provides the user with an additional eight fully select-
able, edge sensitive interrupts which are all vectored into the
same service subroutine.
21
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UART (Continued)
DS012065-16
FIGURE 14. UART Block Diagram
UART CONTROL AND STATUS REGISTERS
DESCRIPTION OF UART REGISTER BITS
The operation of the UART is programmed through three
registers: ENU, ENUR and ENUI. The function of the indi-
vidual bits in these registers is as follows:
ENU—UART CONTROL AND STATUS REGISTER
TBMT: This bit is set when the UART transfers a byte of data
from the TBUF register into the TSFT register for transmis-
sion. It is automatically reset when software writes into the
TBUF register.
ENU-UART Control and Status Register (Address at 0BA)
PEN
PSEL1
0RW
XBIT9/
PSEL0
0RW
CHL1
0RW
CHL0
0RW
ERR
0R
RBFL
0R
TBMT
RBFL: This bit is set when the UART has received a com-
plete character and has copied it into the RBUF register. It is
automatically reset when software reads the character from
RBUF.
0RW
Bit 7
IR
Bit 0
ENUR-UART Receive Control and Status Register (Address
at 0BB)
ERR: This bit is a global UART error flag which gets set if
any or a combination of the errors (DOE, FE, PE) occur.
DOE
0RD
Bit 7
FE
PE
SPARE
RBlT9
0R
ATTN
0RW
XMTG
0R
RCVG
0R
CHL1, CHL0: These bits select the character frame format.
Parity is not included and is generated/verified by hardware.
*
0RW
0RD
0RD
Bit 0
CHL1 = 0, CHL0 = 0 The frame contains eight data bits.
ENUI-UART Interrupt and Clock Source Register (Address
at 0BC)
CHL1 = 0, CHL0 = 1 The frame continues seven data
bits.
STP2
0RW
Bit 7
STP78
0RW
ETDX
0RW
SSEL
0RW
XRCLK
0RW
XTCLK
0RW
ERI
ETI
0RW
Bit 0
CHL1 = 1, CHL0 = 0 The frame continues nine data bits.
0RW
CHL1 = 1, CHL0 = 1 Loopback Mode selected. Transmit-
ter output internally looped back to
receiver input. Nine bit framing for-
mat is used.
*
Bit is not used.
Bit is cleared on reset.
Bit is set to one on reset.
Bit is read-only; it cannot be written by software.
0
1
R
XBIT9/PSEL0: Programs the ninth bit for transmission when
the UART is operating with nine data bits per frame. For
seven or eight data bits per frame, this bit in conjunction with
PSEL1 selects parity.
RW Bit is read/write.
Bit is cleared on read; when read by software as a one,
D
PSEL1, PSEL0: Parity select bits.
it is cleared automatically. Writing to the bit does not af-
fect its state.
PSEL1 = 0, PSEL0 = 0 Odd Parity (if Parity enabled)
PSEL1 = 0, PSEL1 = 1 Odd Parity (if Parity enabled)
PSEL1 = 1, PSEL0 = 0 Mark(1) (if Parity enabled)
PSEL1 = 1, PSEL1 = 1 Space(0) (if Parity enabled)
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22
To simulate line break generation, software should reset
ETDX bit and output logic zero to TDX pin through Port L
data and configuration registers.
UART (Continued)
PEN: This bit enables/disables Parity (7- and 8-bit modes
only).
STP78: This bit is set to program the last Stop bit to be 7/8th
PEN = 0 Parity disabled.
PEN = 1 Parity enabled.
of a bit in length.
STP2: This bit programs the number of Stop bits to be trans-
mitted.
ENUR—UART RECEIVE CONTROL AND STATUS
REGISTER
STP2 = 0 One Stop bit transmitted.
STP2 = 1 Two Stop bits transmitted.
RCVG: This bit is set high whenever a framing error occurs
and goes low when RDX goes high.
Associated I/O Pins
XMTG: This bit is set to indicate that the UART is transmit-
ting. It gets reset at the end of the last frame (end of last Stop
bit).
Data is transmitted on the TDX pin and received on the RDX
pin. TDX is the alternate function assigned to Port L pin L2;
it is selected by setting ETDX (in the ENUI register) to one.
RDX is an inherent function of Port L pin L3, requiring no
setup.
ATTN: ATTENTION Mode is enabled while this bit is set.
This bit is cleared automatically on receiving a character with
data bit nine set.
The baud rate clock for the UART can be generated on-chip,
or can be taken from an external source. Port L pin L1 (CKX)
is the external clock I/O pin. The CKX pin can be either an in-
put or an output, as determined by Port L Configuration and
Data registers (Bit 1). As an input, it accepts a clock signal
which may be selected to drive the transmitter and/or re-
ceiver. As an output, it presents the internal Baud Rate Gen-
erator output.
RBIT9: Contains the ninth data bit received when the UART
is operating with nine data bits per frame.
SPARE: Reserved for future use.
PE: Flags a Parity Error.
PE = 0 Indicates no Parity Error has been detected since
the last time the ENUR register was read.
PE = 1 Indicates the occurrence of a Parity Error.
FE: Flags a Framing Error.
UART Operation
The UART has two modes of operation: asynchronous mode
and synchronous mode.
FE = 0 Indicates no Framing Error has been detected
since the last time the ENUR register was read.
FE = 1 Indicates the occurrence of a Framing Error.
DOE: Flags a Data Overrun Error.
ASYNCHRONOUS MODE
DOE = 0 Indicates no Data Overrun Error has been de-
tected since the last time the ENUR register was
read.
This mode is selected by resetting the SSEL (in the ENUI
register) bit to zero. The input frequency to the UART is 16
times the baud rate.
DOE = 1 Indicates the occurrence of a Data Overrun Er-
ror.
The TSFT and TBUF registers double-buffer data for trans-
mission. While TSFT is shifting out the current character on
the TDX pin, the TBUF register may be loaded by software
with the next byte to be transmitted. When TSFT finishes
transmitting the current character the contents of TBUF are
transferred to the TSFT register and the Transmit Buffer
Empty Flag (TBMT in the ENU register) is set. The TBMT
flag is automatically reset by the UART when software loads
a new character into the TBUF register. There is also the
XMTG bit which is set to indicate that the UART is transmit-
ting. This bit gets reset at the end of the last frame (end of
last Stop bit). TBUF is a read/write register.
ENUI—UART INTERRUPT AND CLOCK SOURCE
REGISTER
ETI: This bit enables/disables interrupt from the transmitter
section.
ETI = 0 Interrupt from the transmitter is disabled.
ETI = 1 Interrupt from the transmitter is enabled.
ERI: This bit enables/disables interrupt from the receiver
section.
ERI = 0 Interrupt from the receiver is disabled.
ERI = 1 Interrupt from the receiver is enabled.
The RSFT and RBUF registers double-buffer data being re-
ceived. The UART receiver continually monitors the signal
on the RDX pin for a low level to detect the beginning of a
Start bit. Upon sensing this low level, it waits for half a bit
time and samples again. If the RDX pin is still low, the re-
ceiver considers this to be a valid Start bit, and the remaining
bits in the character frame are each sampled a single time, at
the mid-bit position. Serial data input on the RDX pin is
shifted into the RSFT register. Upon receiving the complete
character, the contents of the RSFT register are copied into
the RBUF register and the Received Buffer Full Flag (RBFL)
is set. RBFL is automatically reset when software reads the
character from the RBUF register. RBUF is a read only reg-
ister. There is also the RCVG bit which is set high when a
framing error occurs and goes low once RDX goes high.
TBMT, XMTG, RBFL and RCVG are read only bits.
XTCLK: This bit selects the clock source for the transmitter
section.
XTCLK = 0 The clock source is selected through the PSR
and BAUD registers.
XTCLK = 1 Signal on CKX (L1) pin is used as the clock.
XRCLK: This bit selects the clock source for the receiver
section.
XRCLK = 0 The clock source is selected through the PSR
and BAUD registers.
XRCLK = 1 Signal on CKX (L1) pin is used as the clock.
SSEL: UART mode select.
SSEL = 0 Asynchronous Mode.
SSEL = 1 Synchronous Mode.
ETDX: TDX (UART Transmit Pin) is the alternate function
assigned to Port L pin L2; it is selected by setting ETDX bit.
23
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The first format (1,1a, 1b, 1c) for data transmission (CHL0 =
1, CHL1 = 0) consists of Start bit, seven Data bits (excluding
parity) and 7/8, one or two Stop bits. In applications using
parity, the parity bit is generated and verified by hardware.
UART Operation (Continued)
SYNCHRONOUS MODE
In this mode data is transferred synchronously with the
clock. Data is transmitted on the rising edge and received on
the falling edge of the synchronous clock.
The second format (CHL0 = 0, CHL1 = 0) consists of one
Start bit, eight Data bits (excluding parity) and 7/8, one or
two Stop bits. Parity bit is generated and verified by hard-
ware.
This mode is selected by setting SSEL bit in the ENUI regis-
ter. The input frequency to the UART is the same as the
baud rate.
The third format for transmission (CHL0 = 0, CHL1 = 1) con-
sists of one Start bit, nine Data bits and 7/8, one or two Stop
bits. This format also supports the UART “ATTENTION” fea-
ture. When operating in this format, all eight bits of TBUF
and RBUF are used for data. The ninth data bit is transmitted
and received using two bits in the ENU and ENUR registers,
called XBIT9 and RBIT9. RBIT9 is a read only bit. Parity is
not generated or verified in this mode.
When an external clock input is selected at the CKX pin, data
transmit and receive are performed synchronously with this
clock through TDX/RDX pins.
If data transmit and receive are selected with the CKX pin as
clock output, the device generates the synchronous clock
output at the CKX pin. The internal baud rate generator is
used to produce the synchronous clock. Data transmit and
receive are performed synchronously with this clock.
FRAMING FORMATS
The UART supports several serial framing formats (Figure
15). The format is selected using control bits in the ENU,
ENUR and ENUI registers.
DS012065-17
FIGURE 15. Framing Formats
For any of the above framing formats, the last Stop bit can
be programmed to be 7/8th of a bit in length. If two Stop bits
are selected and the 7/8th bit is set (selected), the second
Stop bit will be 7/8th of a bit in length.
ity is enabled (PEN = 1), the parity selection is then per-
formed by PSEL0 and PSEL1 bits located in the ENU regis-
ter.
Note that the XBIT9/PSEL0 bit located in the ENU register
serves two mutually exclusive functions. This bit programs
the ninth bit for transmission when the UART is operating
The parity is enabled/disabled by PEN bit located in the ENU
register. Parity is selected for 7- and 8-bit modes only. If par-
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24
The interrupt from the Transmitter is set pending, and re-
mains pending, as long as both the TBMT and ETl bits are
set. To remove this interrupt, software must either clear the
ETI bit or write to the TBUF register (thus clearing the TBMT
bit).
UART Operation (Continued)
with nine data bits per frame. There is no parity selection in
this framing format. For other framing formats XBIT9 is not
needed and the bit is PSEL0 used in conjunction with PSEL1
to select parity.
The interrupt from the receiver is set pending, and remains
pending, as long as both the RBFL and ERI bits are set. To
remove this interrupt, software must either clear the ERl bit
or read from the RBUF register (thus clearing the RBFL bit).
The frame formats for the receiver differ from the transmitter
in the number of Stop bits required. The receiver only re-
quires one Stop bit in a frame, regardless of the setting of the
Stop bit selection bits in the control register. Note that an im-
plicit assumption is made for full duplex UART operation that
the framing formats are the same for the transmitter and re-
ceiver.
Baud Clock Generation
The clock inputs to the transmitter and receiver sections of
the UART can be individually selected to come either from
an external source at the CKX pin (port L, pin L1) or from a
source selected in the PSR and BAUD registers. Internally,
the basic baud clock is created from the oscillator frequency
through a two-stage divider chain consisting of a 1–16 (in-
crements of 0.5) prescaler and an 11-bit binary counter
(Figure 16). The divide factors are specified through two
read/write registers shown in Figure 17. Note that the 11-bit
Baud Rate Divisor spills over into the Prescaler Select Reg-
ister (PSR). PSR is cleared upon reset.
UART INTERRUPTS
The UART is capable of generating interrupts. Interrupts are
generated on Receive Buffer Full and Transmit Buffer Empty.
Both interrupts have individual interrupt vectors. Two bytes
of program memory space are reserved for each interrupt
vector. The two vectors are located at addresses 0xEC to
0xEF Hex in the program memory space. The interrupts can
be individually enabled or disabled using Enable Transmit In-
terrupt (ETl) and Enable Receive Interrupt (ERl) bits in the
ENUI register.
DS012065-18
FIGURE 16. UART BAUD Clock Generation
DS012065-19
FIGURE 17. UART BAUD Clock Divisor Registers
25
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TABLE 5. Prescaler Factors
Baud Clock Generation (Continued)
Prescaler
Select
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Prescaler
As shown in Table 5, a Prescaler Factor of 0 corresponds to
NO CLOCK. This condition is the UART power down mode
where the UART clock is turned off for power saving pur-
pose. The user must also turn the UART clock off when a dif-
ferent baud rate is chosen.
Factor
NO CLOCK
1
1.5
2
The correspondences between the 5-bit Prescaler Select
and Prescaler factors are shown in Table 5. There are many
ways to calculate the two divisor factors, but one particularly
effective method would be to achieve a 1.8432 MHz fre-
quency coming out of the first stage. The 1.8432 MHz pres-
caler output is then used to drive the software programmable
baud rate counter to create a 16x clock for the following baud
rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400, 3600,
4800, 7200, 9600, 19200 and 38400 (Table 4). Other baud
rates may be created by using appropriate divisors. The 16x
clock is then divided by 16 to provide the rate for the serial
shift registers of the transmitter and receivers.
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
TABLE 4. Baud Rate Divisors
(1.8432 MHz PrescaIer Output)
7.5
8
Baud
Rate
Baud Rate
Divisor − 1 (N-1)
8.5
9
110 (110.03)
134.5 (134.58)
150
1046
855
767
383
191
95
9.5
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
15
15.5
16
300
600
1200
1800
63
2400
47
3600
31
4800
23
7200
15
9600
11
19200
38400
5
2
Note 11: The entries in Table 4 assume a prescaIer output of 1.8432 MHz. In
asynchronous mode the baud rate could be as high as 625k.
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26
The idle timer (T0) generates a fixed (256 tc) delay to ensure
that the oscillator has indeed stabilized before allowing the
device to execute code. The user has to consider this delay
when data transfer is expected immediately after exiting the
HALT mode.
Baud Clock Generation (Continued)
As an example, considering Asynchronous Mode and a CKI
clock of 4.608 MHz, the prescaler factor selected is:
4.608/1.8432 = 2.5
The 2.5 entry is available in Table 5. The 1.8432 MHz pres-
caler output is then used with proper Baud Rate Divisor
(Table V) to obtain different baud rates. For a baud rate of
19200 e.g., the entry in Table IV is 5.
Diagnostic
Bits CHARL0 and CHARL1 in the ENU register provide a
Ioopback feature for diagnostic testing of the UART. When
these bits are set to one, the following occur: The receiver in-
put pin (RDX) is internally connected to the transmitter out-
put pin (TDX); the output of the Transmitter Shift Register is
“looped back” into the Receive Shift Register input. In this
mode, data that is transmitted is immediately received. This
feature allows the processor to verify the transmit and re-
ceive data paths of the UART.
N − 1 = 5 (N − 1 is the value from Table 4)
N = 6 (N is the Baud Rate Divisor)
Baud Rate = 1.8432 MHz/(16 x 6) = 19200
The divide by 16 is performed because in the asynchronous
mode, the input frequency to the UART is 16 times the baud
rate. The equation to calculate baud rates is given below.
The actual Baud Rate may be found from:
BR = Fc/(16 x N x P)
Note that the framing format for this mode is the nine bit for-
mat; one Start bit, nine data bits, and 7/8, one or two Stop
bits. Parity is not generated or verified in this mode.
Where:
BR is the Baud Rate
Attention Mode
Fc is the CKI frequency
N is the Baud Rate Divisor (Table 4).
The UART Receiver section supports an alternate mode of
operation, referred to as ATTENTION Mode. This mode of
operation is selected by the ATTN bit in the ENUR register.
The data format for transmission must also be selected as
having nine Data bits and either 7/8, one or two Stop bits.
P is the Prescaler Divide Factor selected by the value in the
Prescaler Select Register (Table 5)
Note: In the Synchronous Mode, the divisor 16 is replaced by two.
Example:
The ATTENTION mode of operation is intended for use in
networking the device with other processors. Typically in
such environments the messages consists of device ad-
dresses, indicating which of several destinations should re-
ceive them, and the actual data. This Mode supports a
scheme in which addresses are flagged by having the ninth
bit of the data field set to a 1. If the ninth bit is reset to a zero
the byte is a Data byte.
Asynchronous Mode:
Crystal Frequency = 5 MHz
Desired baud rate = 9600
Using the above equation N x P can be calculated first.
N x P = (5 x 106)/(16 x 9600) = 32.552
Now 32.552 is divided by each Prescaler Factor (Table 5) to
obtain a value closest to an integer. This factor happens to
be 6.5 (P = 6.5).
While in ATTENTION mode, the UART monitors the commu-
nication flow, but ignores all characters until an address
character is received. Upon receiving an address character,
the UART signals that the character is ready by setting the
RBFL flag, which in turn interrupts the processor if UART Re-
ceiver interrupts are enabled. The ATTN bit is also cleared
automatically at this point, so that data characters as well as
address characters are recognized. Software examines the
contents of the RBUF and responds by deciding either to ac-
cept the subsequent data stream (by leaving the ATTN bit re-
set) or to wait until the next address character is seen (by
setting the ATTN bit again).
N = 32.552/6.5 = 5.008 (N = 5)
The programmed value (from Table 4) should be 4 (N − 1).
Using the above values calculated for N and P:
BR = (5 x 106)/(16 x 5 x 6.5) = 9615.384
% error = (9615.385 − 9600)/9600 = 0.16
Effect of HALT/IDLE
The UART logic is reinitialized when either the HALT or IDLE
modes are entered. This reinitialization sets the TBMT flag
and resets all read only bits in the UART control and status
registers. Read/Write bits remain unchanged. The Transmit
Buffer (TBUF) is not affected, but the Transmit Shift register
(TSFT) bits are set to one. The receiver registers RBUF and
RSFT are not affected.
Operation of the UART Transmitter is not affected by selec-
tion of this Mode. The value of the ninth bit to be transmitted
is programmed by setting XBIT9 appropriately. The value of
the ninth bit received is obtained by reading RBIT9. Since
this bit is located in ENUR register where the error flags re-
side, a bit operation on it will reset the error flags.
The device will exit from the HALT/IDLE modes when the
Start bit of a character is detected at the RDX (L3) pin. This
feature is obtained by using the Multi-Input Wakeup scheme
provided on the device.
Interrupts
The devices supports a vectored interrupt scheme. It sup-
ports a total of fourteen interrupt sources. Table 6 lists all the
possible device interrupt sources, their arbitration rankings
and the memory locations reserved for the interrupt vector
for each source.
Before entering the HALT or IDLE modes the user program
must select the Wakeup source to be on the RDX pin. This
selection is done by setting bit 3 of WKEN (Wakeup Enable)
register. The Wakeup trigger condition is then selected to be
high to low transition. This is done via the WKEDG register
(Bit 3 is “one”).
Two bytes of program memory space are reserved for each
interrupt source. All interrupt sources except the software in-
terrupt are maskable. Each of the maskable interrupts have
an Enable bit and one or more Pending bits. A maskable in-
terrupt is active it its associated enable and pending bits are
If the device is halted and crystal oscillator is used, the Wake
Up signal will not start the chip running immediately because
of the finite start up time requirement of the crystal oscillator.
27
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Thus, if an interrupt with a higher rank than the one which
caused the interruption becomes active before the decision
of which interrupt to service is made by the VIS, then the in-
terrupt with the higher rank will override any lower ones and
will be acknowledged. The lower priority interrupt(s) are still
pending, however, and will cause another interrupt immedi-
ately following the completion of the interrupt service routine
associated with the higher priority interrupt just serviced.
This lower priority interrupt will occur immediately following
the RETI (Return from Interrupt) instruction at the end of the
interrupt service routine just completed.
Interrupts (Continued)
set. If GlE = 1 and an interrupt is active, then the processor
will be interrupted as soon as it is ready to start executing an
instruction except if the above conditions happen during the
Software Trap service routine. This exception is described in
the Software Trap sub-section.
The interruption process is accomplished with the INTR in-
struction (opcode 00), which is jammed inside the Instruction
Register and replaces the opcode about to be executed. The
following steps are performed for every interrupt:
Inside the interrupt service routine, the associated pending
bit has to be cleared by software. The RETI (Return from In-
terrupt) instruction at the end of the interrupt service routine
will set the GIE (Global Interrupt Enable) bit, allowing the
processor to be interrupted again if another interrupt is active
and pending.
1. The GIE (Global Interrupt Enable) bit is reset.
2. The address of the instruction about to be executed is
pushed into the stack.
3. The PC (Program Counter) branches to address 00FF.
This procedure takes 7 tc cycles to execute.
At this time, since GIE = 0, other maskable interrupts are
disabled. The user is now free to do whatever context
switching is required by saving the context of the machine in
the stack with PUSH instructions. The user would then pro-
gram a VIS (Vector Interrupt Select) instruction in order to
branch to the interrupt service routine of the highest priority
interrupt enabled and pending at the time of the VIS. Note
that this is not necessarily the interrupt that caused the
branch to address location 00FF Hex prior to the context
switching.
The VIS instruction looks at all the active interrupts at the
time it is executed and performs an indirect jump to the be-
ginning of the service routine of the one with the highest
rank.
The addresses of the different interrupt service routines,
called vectors, are chosen by the user and stored in ROM in
a table starting at 01E0 (assuming that VIS is located be-
tween 00FF and 01DF). The vectors are 15-bit wide and
therefore occupy 2 ROM locations.
TABLE 6. Interrupt Vector Table
ARBITRATION
RANKING
SOURCE
DESCRIPTION
VECTOR (Note 12)
ADDRESS
(Hi-Low Byte)
(1) Highest
Software
0yFE–0yFF
(2)
Reserved
External
0yFC–0yFD
0yFA-0yFB
0yF8–0yF9
0yF6–0yF7
0yF4-0yF5
0yF2–0yF3
0yF0–0yF1
0yEE–0yEF
0yEC–0yED
0yEA–0yEB
0yE8–0yE9
0yE6–0yE7
0yE4–0yE5
0yE2–0yE3
0yE0–0yE1
(3)
G0
(4)
Timer T0
Underflow
T1A/Underflow
T1B
(5)
Timer T1
(6)
Timer T1
(7)
Microwire/PIus
Counters
Busy Low
(8)
(9)
UART
Receive
(10)
(11)
(12)
(13)
(14)
(15)
(16) Lowest
UART
Transmit
T2A/Underflow
T2B
Timer T2
Timer T2
Capture Timer 1 and 2
Unused
Port L/Wakeup
Default VIS
Reserved
Note 12: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last ad-
dress of a block, In this case, the table must be in the next block.
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28
to reset the interrupt enable bit, the interrupt enable bit will be reset but
an interrupt may still occur. This is because interrupt processing is
started at the same time as the interrupt bit is being reset. To avoid this
scenario, the user should always use a two-, three- or four-cycle in-
struction to reset interrupt enable bits.
Interrupts (Continued)
VIS and the vector table must be located in the same
256-byte block (0y00 to 0yFF) except if VIS is located at the
last address of a block. In this case, the table must be in the
next block. The vector table cannot be inserted in the first
Figure 18 shows the Interrupt block diagram.
≠
256-byte block (y 0).
SOFTWARE TRAP
The vector of the maskable interrupt with the lowest rank is
located at 0yE0 (Hi-Order byte) and 0yE1 (Lo-Order byte)
and so forth in increasing rank number. The vector of the
maskable interrupt with the highest rank is located at 0yFA
(Hi-Order byte) and 0yFB (Lo-Order byte).
The Software Trap (ST) is a special kind of non-maskable in-
terrupt which occurs when the INTR instruction (used to ac-
knowledge interrupts) is fetched from ROM and placed in-
side the instruction register. This may happen when the PC
is pointing beyond the available ROM address space or
when the stack is over-popped.
The Software Trap has the highest rank and its vector is lo-
cated at 0yFE and 0yFF.
When an ST occurs, the user can re-initialize the stack
pointer and do a recovery procedure (similar to reset, but not
necessarily containing all of the same initialization proce-
dures) before restarting.
If, by accident, a VIS gets executed and no interrupt is ac-
tive, then the PC (Program Counter) will branch to a vector
located at 0yE0–0yE1.
The occurrence of an ST is latched into the ST pending bit.
The GIE bit is not affected and the ST pending bit (not ac-
cessible by the user) is used to inhibit other interrupts and
to direct the program to the ST service routine with the VIS
instruction. The RPND instruction is used to clear the soft-
ware interrupt pending bit. This pending bit is also cleared on
reset.
Warning:
A Default VIS interrupt handler routine must be present. As a
minimum, this handler should confirm that the GIE bit is
cleared (this indicates that the interrupt sequence has been
taken), take care of any required housekeeping, restore con-
text and return. Some sort of Warm Restart procedure
should be implemented. These events can occur without any
error on the part of the system designer or programmer.
The ST has the highest rank among all interrupts.
Nothing (except another ST) can interrupt an ST being
serviced.
Note: There is always the possibility of an interrupt occurring during an in-
struction which is attempting to reset the GIE bit or any other interrupt
enable bit. If this occurs when a single cycle instruction is being used
DS012065-20
FIGURE 18. Interrupt Block Diagram
29
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vice to interface with any of National Semiconductor’s MI-
CROWIRE peripherals (i.e., A/D converters, display drivers,
E2PROMs etc.) and with other microcontrollers which sup-
port the MICROWIRE interface. It consists of an 8-bit serial
shift register (SIO) with serial data input (SI), serial data out-
put (SO) and serial shift clock (SK). Figure 19 shows a block
diagram of the MICROWIRE/PLUS logic.
Detection of Illegal Conditions
The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc.
Reading of undefined ROM gets zeroes. The opcode for
software interrupt is 00. If the program fetches instructions
from undefined ROM, this will force a software interrupt, thus
signaling that an illegal condition has occurred.
The shift clock can be selected from either an internal source
or an external source. Operating the MlCROWIRE/PLUS ar-
rangement with the internal clock source is called the Master
mode of operation. Similarly, operating the MICROWIRE/
PLUS arrangement with an external shift clock is called the
Slave mode of operation.
The subroutine stack grows down for each call (jump to sub-
routine), interrupt, or PUSH, and grows up for each return or
POP. The stack pointer is initialized to RAM location 06F Hex
during reset. Consequently, if there are more returns than
calls, the stack pointer will point to addresses 070 and 071
Hex (which are undefined RAM). Undefined RAM from ad-
dresses 070 to 07F (Segment 0), 140 to 17F (Segment 1),
and all other segments (i.e., Segments 3... etc.) is read as all
1’s, which in turn will cause the program to return to address
7FFF Hex. This is an undefined ROM location and the in-
struction fetched (all 0’s) from this location will generate a
software interrupt signaling an illegal condition.
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
the MSEL bit in the CNTRL register is set to one. In the mas-
ter mode, the SK clock rate is selected by the two bits, SL0
and SL1, in the CNTRL register. Table VII details the different
clock rates that may be selected.
TABLE 7. MICROWIRE/PLUS
Master Mode Clock Select
Thus, the chip can detect the following illegal conditions:
1. Executing from undefined ROM
SL1
0
SL0
SK Period
2 x tc
2. Over “POP”ing the stack by having more returns than
calls.
0
1
x
When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restart-
ing (this recovery program is probably similar to that follow-
ing reset, but might not contain the same program initializa-
tion procedures). The recovery program should reset the
software interrupt pending bit using the RPND instruction.
0
4 x tc
1
8 x tc
Where tc is the instruction cycle clock
MICROWIRE/PLUS
MICROWIRE/PLUS is a serial synchronous communications
interface. The MICROWIRE/PLUS capability enables the de-
DS012065-21
FIGURE 19. MICROWIRE/PLUS Block Diagram
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30
TABLE 8. MICROWIRE Mode Settings
MICROWIRE/PLUS (Continued)
G4 (SO)
Config. Bit
1
G5 (SK)
Config. Bit
1
G4
G5
Fun.
Int.
Operation
MICROWIRE/PLUS OPERATION
Fun.
Setting the BUSY bit in the PSW register causes the
MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 20 shows how
two devices, microcontrollers and several peripherals may
be interconnected using the MICROWIRE/PLUS arrange-
ments.
SO
MICROWIRE/PLUS
Master
SK
0
1
0
1
0
0
TRI-
Int.
MICROWlRE/PLUS
Master
STATE SK
SO
Ext.
SK
MlCROWlRE/PLUS
Slave
TRl-
Ext.
MICROWlRE/PLUS
Slave
STATE SK
This table assumes that the control flag MSEL is set.
Warning:
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by the
Master will be shifted properly. After eight clock pulses the
BUSY flag will be cleared and the sequence may be re-
peated.
The SIO register should only be loaded when the SK clock is
low. Loading the SIO register while the SK clock is high will
resuIt in undefined data in the SIO register. SK clock is nor-
mally low when not shifting.
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PLUS slave mode may cause the current SK
clock for the SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is low.
Alternate SK Phase Operation
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register. in
both the modes the SK is normally low. In the normal mode
data is shifted in on the rising edge of the SK clock and the
data is shifted out on the falling edge of the SK clock. The
SIO register is shifted on each falling edge of the SK clock.
In the alternate SK phase operation, data is shifted in on the
falling edge of the SK clock and shifted out on the rising edge
of the SK clock.
MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally by the device. The MI-
CROWIRE Master always initiates all data exchanges. The
MSEL bit in the CNTRL register must be set to enable the
SO and SK functions onto the G Port. The SO and SK pins
must also be selected as outputs by setting appropriate bits
in the Port G configuration register. Table VIII summarizes
the bit settings required for Master mode of operation.
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alter-
nate SK clock. The SKSEL is mapped into the G6 configura-
tion bit. The SKSEL flag will power up in the reset condition,
selecting the normal SK signal.
MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and re-
setting the appropriate bits in the Port G configuration regis-
ter. Table VIII summarizes the settings required to enter the
Slave mode of operation.
DS012065-22
FIGURE 20. MICROWIRE/PLUS Application
31
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Memory Map
All RAM, ports and registers (except A and PC) are mapped into data memory address space.
ADDRESS
CONTENTS
S/ADD REG
0000 to 006F
112 On-Chip RAM Bytes
0070 to 007F
xx80 to xx8F
Unused RAM Address Space
(reads as all 1’s)
Unused RAM Address Space
(reads undefined data)
xx90
xx91
xx92
xx93
xx94
xx95
xx96
xx97
xx98
xx99
xx9A
xx9B
xx9C
xx9D
xx9E
xx9F
xxA0
xxA1
xxA2
xxA3
xxA4
xxA5
xxA6
xxA7
xxA8
xxA9
xxAA
xxAB
xxAC
xxAD
xxAE
xxAF
xxB0
xxB1
xxB2
xxB3
xxB4
xxB5
xxB6
xxB7
xxB8
xxB9
Port E Data Register
Port E Configuration Register
Port E Input Pins (read only)
Reserved
Port F Data Register
Port F Configuration Register
Port F Input Pins (read only)
Reserved
Dividend or Result Byte (MDR1)
Dividend/Multiplier or Result Byte (MDR2)
Dividend/Result Byte or Undefined (MDR3)
Divisor/Multiplicand or Result Byte (MDR4)
Divisor or Multiplicand Byte(MDR5)
MuItiply/Divide Control Register (MDCR)
Counter Control 1 Register (CCR1)
Counter Control 2 Register (CCR2)
Counter 1 Prescaler Lower Byte (C1PRL)
Counter 1 Prescaler Upper Byte (C1PRH)
Counter 1 Count Register Lower Byte (C1CTL)
Counter 1 Count Register Upper Byte (C1CTH)
Counter 2 Prescaler Lower Byte (C2PRL)
Counter 2 Prescaler Upper Byte (C2PRH)
Counter 2 Count Register Lower Byte (C2CTL)
Counter 2 Count Register Upper Byte (C2CTH)
Counter 3 Prescaler Lower Byte (C3PRL)
Counter 3 Prescaler Upper Byte (C3PRH)
Counter 3 Count Register Lower Byte (C3CTL)
Counter 3 Count Register Upper Byte (C3CTH)
Counter 4 Prescaler Lower Byte (C4PRL)
Counter 4 Prescaler Upper Byte (C4PRH)
Counter 4 Count Register Lower Byte (C4CTL)
Counter 4 Count Register Upper Byte (C4CTH)
Capture Timer 1 Prescaler Register (CM1 PSC)
Capture Timer 1 Lower Byte (CM1CRL) Read-Only
Capture Timer 1 Upper Byte (CM1CRH) Read-Only
Capture Timer 2 Prescaler Register (CM2PSC)
Capture Timer 2 Lower Byte (CM2CRL) Read-Only
Capture Timer 2 Upper Byte (CM2CRH) Read-Only
Capture Timer 1 Control Register (CCMR1)
Capture Timer 2 Control Register (CCMR2)
UART Transmit Buffer (TBUF)
UART Receive Buffer (RBUF)
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32
Memory Map (Continued)
ADDRESS
S/ADD REG
xxBA
CONTENTS
UART Control and Status Register (ENU)
UART Receive Control and Status Register (ENUR)
UART Interrupt and Clock Source Register (ENUI)
UART Baud Register (BAUD)
UART Prescaler Select Register (PSR)
Reserved for UART
xxBB
xxBC
xxBD
xxBE
xxBF
xxC0
Timer T2 Lower Byte
xxC1
Timer T2 Upper Byte
xxC2
Timer T2 Autoload Register T2RA Lower Byte
Timer T2 Autoload Register T2RA Upper Byte
Timer T2 Autoload Register T2RB Lower Byte
Timer T2 Autoload Register T2RB Upper Byte
Timer T2 Control Register
Reserved
xxC3
xxC4
xxC5
xxC6
xxC7
xxC8
MIWU Edge Select Register (WKEDG)
MlWU Enable Register (WKEN)
MlWU Pending Register (WKPND)
Reserved
xxC9
xxCA
xxCB
xxCC
Reserved
xxCD to xxCF
xxD0
Reserved
Port L Data Register
xxD1
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
xxD2
xxD3
xxD4
Port G Data Register
xxD5
Port G Configuration Register
Port G Input Pins (Read Only)
Port l Input Pins (Read Only)
Port C Data Register
xxD6
xxD7
xxD8
xxD9
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
xxDA
xxDB
xxDC
Port D
xxDD to xxDF
xxE0 to xxE5
xxE6
Reserved for Port D
Reserved for EE Control Registers
Timer T1 Autoload Register T1RB Lower Byte
Timer T1 Autoload Register T1RB Upper Byte
ICNTRL Register
xxE7
xxE8
xxE9
MICROWIRE Shift Register
Timer T1 Lower Byte
xxEA
xxEB
Timer T1 Upper Byte
xxEC
Timer T1 Autoload Register T1RA Lower Byte
Timer T1 Autoload Register T1RA Upper Byte
CNTRL Control Register
xxED
xxEE
xxEF
PSW Register
xxF0 to xxFB
xxFC
On-chip RAM Mapped as Registers
X Register
xxFD
SP Register
33
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Memory Map (Continued)
ADDRESS
S/ADD REG
xxFE
CONTENTS
B Register
S Register
xxFF
0100 to 017F
0200 to 027F
0300 to 037F
On Chip RAM Bytes (384 Bytes)
Reading memory locations 0070H-007FH (Segment 0) will return all ones. Reading unused memory locations between 0080H-00F0 Hex (Segment
0) will return undefined data. Reading memory locations from other segments (i.e., segment 4, segment 5, etc.) will return all ones.
ADDRESSING MODES
Absolute Long
There are ten addressing modes, six for operand addressing
and four for transfer of control.
This mode is used with the JMPL and JSRL instructions, with
the instruction field of 15 bits replacing the entire 15 bits of
the program counter (PC). This allows jumping to any loca-
tion up to 32k in the program memory space.
OPERAND ADDRESSING MODES
Register Indirect
Indirect
This is the “normal” addressing mode. The operand is the
data memory addressed by the B pointer or X pointer.
This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits of
PC) for accessing a location in the program memory. The
contents of this program memory location serve as a partial
address (lower 8 bits of PC) for the jump to the next instruc-
tion.
Note: The VIS is a special case of the Indirect Transfer of Control addressing
mode, where the double byte vector associated with the interrupt is
transferred from adjacent addresses in the program memory into the
program counter (PC) in order to jump to the associated interrupt ser-
vice routine.
Register Indirect (with auto post Increment or
decrement of pointer)
This addressing mode is used with the LD and X instruc-
tions. The operand is the data memory addressed by the B
pointer or X pointer. This is a register indirect mode that au-
tomatically post increments or decrements the B or X regis-
ter after executing the instruction.
Direct
Instruction Set
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
Register and Symbol Definition
ImmedIate
Registers
The instruction contains an 8-bit immediate field as the oper-
and.
A
8-Bit Accumulator Register
8-Bit Address Register
B
X
8-Bit Address Register
Short Immediate
SP
PC
PU
PL
C
8-Bit Stack Pointer Register
15-Bit Program Counter Register
Upper 7 Bits of PC
This addressing mode is used with the Load B Immediate in-
struction. The instruction contains a 4-bit immediate field as
the operand.
Lower 8 Bits of PC
Indirect
1 Bit of PSW Register for Carry
1 Bit of PSW Register for Half Carry
This addressing mode is used with the LAID instruction. The
contents of the accumuiator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
HC
GIE
1 Bit of PSW Register for Global Interrupt
Enable
VU
VL
Interrupt Vector Upper Byte
Interrupt Vector Lower Byte
TRANSFER OF CONTROL ADDRESSING MODES
Relative
This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new pro-
gram location. JP has a range from −31 to +32 to allow a
1-byte relative jump (JP + 1 is implemented by a NOP in-
struction). There are no “pages” when using JP, since all 15
bits of PC are used.
Absolute
This mode is used with the JMP and JSR instructions, with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any loca-
tion in the current 4k program memory segment.
www.national.com
34
Instruction Set (Continued)
Symbols
Imm
Reg
8-Bit Immediate Data
Symbols
Register Memory: Addresses F0 to FF
(Includes B, X and SP)
[B]
Memory Indirectly Addressed by B Register
[X]
Memory Indirectly Addressed by X Register
Direct Addressed Memory
Bit
←
↔
Bit Number (0 to 7)
Loaded with
MD
Mem
Meml
Direct Addressed Memory or [B]
Exchanged with
Direct Addressed Memory or [B] or
Immediate Data
INSTRUCTION SET
←
←
←
←
ADD
ADC
SUBC
AND
A,MemI
A,Meml
A,Meml
A,Meml
ADD
A
A
A
A
A + MemI
A + MemI + C, C Carry, HC Half Carry
←
←
ADD with Carry
←
←
Subtract with Carry
Logical AND
A − MemI + C, C Carry, HC Half Carry
A and MemI
ANDSZ A,lmm
Logical AND lmmed., Skip if Zero
Logical OR
Skip next if (A and Imm) = 0
←
←
OR
A,Meml
A,Meml
MD,lmm
A,Meml
A,Meml
A,Meml
#
A
A
A or MemI
XOR
IFEQ
IFEQ
IFNE
IFGT
lFBNE
DRSZ
SBIT
RBIT
lFBIT
RPND
X
Logical EXclusive OR
IF EQual
A xor MemI
Compare MD and lmm, Do next if MD = lmm
Compare A and Meml, Do next if A = Meml
IF EQual
≠
Compare A and Meml, Do next if A Meml
IF Not Equal
>
IF Greater Than
IF B Not Equal
Compare A and Meml, Do next if A Meml
≠
Do next if lower 4 bits of B Imm
←
Reg
Decrement Reg., Skip if Zero
Set BIT
Reg Reg − 1, Skip if Reg = 0
#
#
#
,Mem
,Mem
,Mem
1 to bit, Mem (bit = 0 to 7 immediate)
0 to bit, Mem
Reset BIT
#
IF BIT
If bit , A or Mem is true do next instruction
Reset PeNDing Flag
EXchange A with Memory
EXchange A with Memory [X]
LoaD A with Memory
LoaD A with Memory [X]
LoaD B with Immed.
LoaD Memory Immed.
Reset Software Interrupt Pending Flag
↔
↔
←
←
←
A,Mem
A,[X]
A
A
A
A
B
Mem
[X]
X
LD
A,Meml
A,[X]
MemI
[X]
LD
LD
B, Imm
Imm
←
Mem Imm
LD
Mem,
Imm
←
Reg Imm
LD
Reg, Imm
LoaD Register Memory Immed.
EXchange A with Memory [B]
EXchange A with Memory [X]
LoaD A with Memory [B]
LoaD A with Memory [X]
LoaD Memory [B] lmmed.
CLeaR A
↔
↔
←
←
±
±
±
±
±
X
A, [B ]
A
A
A
A
[B], (B
[X], (X
B
X
B
X
1)
1)
1)
1)
±
←
±
A, [X ]
X
←
←
±
LD
A, [B ]
[B], (B
←
[X], (X
±
LD
A, [X ]
←
←
B
±
LD
[B ],lmm
[B] Imm, (B
1)
←
←
←
←
←
→
←
CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
A
A
A
A
A
A
A
A
C
C
0
INCrement A
A + 1
A − 1
DECrement A
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
Set C
ROM (PU, A)
BCD correction of A (follows ADC, SUBC)
A
A
A
A
→
←
→
←
→
A0 C
A7
A7
…
…
←
A0
C
↔
A7…A4 A3…A0
←
←
←
←
C
C
1, HC
0, HC
1
0
RC
Reset C
IFC
IF C
If C is true, do next instruction
35
www.national.com
Instruction Set (Continued)
IFNC
POP
PUSH
VIS
IF Not C
If C is not true, do next instruction
← ←
SP SP + 1, A [SP]
A
A
POP the stack into A
PUSH A onto the stack
Vector to Interrupt Service Routine
Jump absolute Long
Jump absolute
←
←
[SP] A, SP SP − 1
←
←
PU [VU], PL
[VL]
←
JMPL
JMP
JP
Addr.
Addr.
Disp.
Addr.
Addr
PC ii (ii = 15 bits, 0 to 32k)
←
PC9…0 i (i = 12 bits)
←
PC PC + r (r is −31 to +32, except 1)
Jump relative short
Jump SubRoutine Long
Jump SubRoutine
← ← ←
[SP] PL, [SP − 1] PU, SP − 2, PC ii
JSRL
JSR
←
←
←
PU, SP − 2, PC9…0 i
[SP] PL, [SP − 1]
←
PL ROM (PU, A)
JID
Jump InDirect
←
←
[SP − 1]
RET
RETSK
RETI
INTR
NOP
RETurn from subroutine
RETurn and SKip
SP + 2, PL [SP], PU
←
←
SP + 2, PL [SP], PU [SP − 1], skip next instruction
←
←
←
[SP − 1], GIE 1
RETurn from Interrupt
Generate an Interrupt
No OPeration
SP + 2, PL [SP], PU
←
←
←
PU, SP − 2, PC 0FF
[SP] PL, [SP − 1]
←
PC PC + 1
Instruction Execution Time
Most instructions are single byte (with immediate addressing mode instructions taking two bytes).
Most single byte instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be skipped, where x equals the number of bytes in the skipped instruction op-
code.
See the BYTES and CYCLES per INSTRUCTION table for details.
Bytes and Cycles per InstructIon
The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle.
Arithmetic and Logic Instructions
Instructions Using A & C
[B]
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
Direct
3/4
Immed.
2/2
CLRA
INCA
DECA
LAID
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2
ADD
ADC
SUBC
AND
OR
3/4
2/2
3/4
2/2
3/4
2/2
DCORA
RRCA
RLCA
SWAPA
SC
3/4
2/2
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
RBIT
lFBIT
3/4
2/2
3/4
2/2
3/4
2/2
RC
1/3
3/4
3/4
3/4
IFC
1/1
1/1
1/1
IFNC
PUSHA
POPA
ANDSZ
RPND
1/1
www.national.com
36
Instruction Execution Time (Continued)
Transfer of Control Instructions
JMPL
JMP
JP
3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5
1/7
1/1
JSRL
JSR
JID
VIS
RET
RETSK
RETI
INTR
NOP
Memory Transfer Instructions
Register
Indirect
Direct
Immed.
Register Indirect
Auto Incr. and Decr.
[B]
[X]
1/3
1/3
[B+, B−]
1/2
[X+, X−]
1/3
X A, (Note 13)
LD A, (Note 13)
LD B, Imm
1/1
1/1
2/3
2/3
2/2
1/1
2/2
1/2
1/3
<
(IF B 16)
>
(IF B 15)
LD B, Imm
LD Mem, Imm
LD Reg, Imm
IFEQ MD, Imm
2/2
3/3
2/3
3/3
2/2
>
Memory location addressed by B or X or directly.
*
Note 13:
=
Mask Options
The mask programmable options are shown below. The op-
tions are programmed at the same time as the ROM pattern
submission.
OPTION 3: BONDING OPTIONS
= 1 68 Pins PLCC
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (if clock option = 1 has been selected).
The CKI input frequency is divided down by 10 to produce
the instruction cycle clock (1/tc).
OPTION 1: CLOCK CONFIGURATION
= 1 Crystal Oscillator (CKI/10)
G7 (CKO) is clock generator output to crystal/resonator
with CKI being the clock input
OPTION 2: HALT
= 1 Enable HALT mode
= 2 Disable HALT mode
37
www.national.com
N i b b l e L o w e r
Note: The opcode 60 Hex is also the opcode for IFBIT,#iA.
www.national.com
38
•
Full 4k frame synchronous trace memory. Address, in-
struction, and 8 unspecified, circuit connectable trace
lines. Display can be HLL source (e.g., C source), as-
sembly or mixed.
Development Support
SUMMARY
™
•
iceMASTER
: IM-COP8/400—Full feature in-circuit
•
•
A full 64k hardware configurable break, trace on, trace oft
control, and pass count increment events.
emulation for all COP8 products. A full set of COP8 Basic
and Feature Family device and package specific probes
are available.
Tool
set
integrated
interactive
symbolic
debugger—supports both assembler (COFF) and C
Compiler (.COD) linked object formats.
•
•
COP8 Debug Module: Moderate cost in-circuit emulation
and development programming unit.
•
•
•
•
Real time peformance profiling analysis; selectable
bucket definition.
COP8
Evaluation
and
Programming
Unit:
EPU-COP888GG—low cost In-circuit simulation and de-
velopment programming unit.
Watch windows, content updated automatically at each
execution break.
•
Assembler: COP8-DEV-IBMA. A DOS installable cross
development Assembler, Linker, Librarian and Utility Soft-
ware Development Tool Kit.
Instruction by instruction memory/register changes dis-
played on source window when in single step operation.
Single base unit and debugger software reconfigurable to
support the entire COP8 family; only the probe personal-
ity needs to change. Debugger software is processor
customized, and reconfigured from a master model file.
•
•
C Compiler: COP8C. A DOS installable cross develop-
ment Software Tool Kit.
OTP/EPROM Programmer Support: Covering needs
from engineering prototype, pilot production to full pro-
duction environments.
•
Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
iceMASTER (IM) IN-CIRCUIT EMULATION
•
•
Halt/Idle mode notification.
The iceMASTER IM-COP8/400 is a full feature, PC based,
in-circuit emulation tool developed and marketed by Met-
aLink Corporation to support the whole COP8 family of prod-
ucts. National is a resale vendor for these products.
On-line HELP customized to specific processor using
master model file.
•
Includes a copy of COP8-DEV-IBMA assembler and
linker SDK.
See Figure 21 for configuration.
IM Order Information
The iceMASTER IM-COP8/400 with its device specific
COP8 Probe provides a rich feature set for developing, test-
ing and maintaining product:
Base Unit
IM-COP8/400-1
iceMASTER base unit, 110V
power supply
•
Real-time in-circuit emulation; full 2.4V–5.5V operation
range, full DC-10 MHz clock. Chip options are program-
mable or jumper selectable.
IM-COP8/400-2
iceMASTER base unit, 220V
power supply
•
•
Direct connection to application board by package com-
patible socket or surface mount assembly.
iceMASTER Probe
Full 32 kbytes of loadable programming space that over-
lays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated on the
probe as necessary.
MHW-888GW68PWPC
68 PLCC
DS012065-31
FIGURE 21. COP8 iceMASTER Environment
39
www.national.com
•
•
•
Instruction by instruction memory/register changes dis-
played when in single step operation.
Development Support (Continued)
iceMASTER DEBUG MODULE (DM)
Debugger software is processor customized, and recon-
figured from a master model file.
The iceMASTER Debug Module is a PC based, combination
in-circuit emulation tool and COP8 based OTP/EPROM pro-
gramming tool developed and marketed by MetaLink Corpo-
ration to support the whole COP8 family of products. Na-
tional is a resale vendor for these products.
Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
•
•
Halt/Idle mode notification.
Programming menu supports full product line of program-
mable OTP and EPROM COP8 products. Program data
is taken directly from the overlay RAM.
See Figure 22 for configuration.
The iceMASTER Debug Module is a moderate cost develop-
ment tool. It has the capability of in-circuit emulation for a
specific COP8 microcontroller and in addition serves as a
programming tool for COP8 OTP and EPROM product fami-
lies. Summary of features is as follows:
•
Programming of 44 PLCC and 68 PLCC parts requires
external programming adapters.
•
•
Includes wallmount power supply.
On-board VPP generator from 5V input or connection to
external supply supported. Requires VPPlevel adjustment
per the family programming specification (correct level is
provided on an on-screen pop-down display).
•
Real-time in-circuit emulation; full operating voltage
range operation, full DC-10 MHz clock.
•
All processor I/O pins can be cabled to an application de-
velopment board with package compatible cable to
socket and surface mount assembly.
•
•
On-line HELP customized to specific processor using
master model file.
•
•
•
Full 32 kbytes of loadable programming space that over-
lays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated as
necessary.
Includes a copy of COP8-DEV-IBMA assembler and
linker SDK.
DM Order Information
100 frames of synchronous trace memory. The display
can be HLL source (C source), assembly or mixed. The
most recent history prior to a break is available in the
trace memory.
Debug Module Unit
COP8-DM/888GW
Cable Adapters
DM-COP8/68P
Configured break points; uses INTR instruction which is
modestly intrusive.
68 PLCC
•
•
Software—only supported features are selectable.
Tool
set
integrated
interactive
symbolic
debugger—supports both assembler (COFF) and C
Compiler (.COD) SDK linked object formats.
DS012065-32
FIGURE 22. COP8-DM Environment
www.national.com
40
#
•
BITS data type extension. Register declaration pragma
with direct bit level definitions.
Development Support (Continued)
COP8 ASSEMBLER/LINKER SOFTWARE
DEVELOPMENT TOOL KIT
•
•
C language support for interrupt routines.
Expert system, rule based code generation and optimiza-
tion.
National Semiconductor offers a relocateable COP8 macro
cross assembler, linker, librarian and utility software develop-
ment tool kit. Features are summarized as follows:
•
Performs consistency checks against the architectural
definitions of the target COP8 device.
•
•
•
•
•
•
•
•
Basic and Feature Family instruction set by “device” type.
Nested macro capability.
•
•
Generates program memory code.
Supports linking of compiled object or COP8 assembled
object formats.
Extensive set of assembler directives.
Supported on PC/DOS platform.
•
•
Global optimization of linked code.
Generates National standard COFF output files.
Integrated Linker and Librarian.
Symbolic debug load format fully source level supported
by the MetaLink debugger.
Integrated utilities to generate ROM code file outputs.
DUMPCOFF utility.
SINGLE CHIP OTP/EMULATOR SUPPORT
The COP8 family is supported by single chip OTP emulators.
For detailed information refer to the emulator specific
datasheet and the emulator selection table below:
This product is integrated as a part of MetaLink tools as a de-
velopment kit, fully supported by the MetaLink debugger. It
may be ordered separately or it is bundled with the MetaLink
products at no additional cost.
OTP Emulator Ordering Information
Order-Information
Assembler SDK
Device Number
Clock
Package
Emulates
Option
COP8-DEV-IBMA Assembler SDK on installable 3.5"
PC/DOS Floppy Disk Drive format.
Periodic upgrades and most recent
version is available on National’s
BBS and Internet.
COP87L88GWV-XE Crystal/
68
COP888GW
HALT
En
PLCC
INDUSTRY WIDE OTP/EPROM PROGRAMMING
SUPPORT
COP8 C COMPILER
Programming support, in addition to the MetaLink develop-
ment tools, is provided by a full range of independent ap-
proved vendors to meet the needs from the engineering
laboratory to full production.
A C Compiler is developed and marketed by Byte Craft Lim-
ited. The COP8C compiler is a fully integrated development
tool specifically designed to support the compact embedded
configuration of the COP8 family of products. Features are
summarized as follows:
•
ANSI C with some restrictions and extensions that opti-
mize development for the COP8 embedded application.
Approved List
Manufacturer
North
America
Europe
Asia
BP
(800) 225-2102
(713) 688-4600
Fax: (713) 688-0920
(800) 426-1045
(206) 881-6444
Fax: (206) 882-1043
(510) 623-8860
+49-8152-4183
+852-234-16611
+852-2710-8121
Microsystems
+49-8856-932616
Data I/O
HI–LO
+44-0734-440011
Call Asia
Call
North America
+886-2-764-0215
Fax: +886-2-756-6403
ICE
(800) 624-8949
(919) 430-7915
(800) 638-2423
(602) 926-0797
Fax: (602) 693-0681
(408) 263-6667
+44-1226-767404
Fax: 0-1226-370-434
+49-80 9156 96-0
Fax: +49-80 9123 86
Technology
MetaLink
+852-737-1800
Systems
General
+41-1-9450300
+886-2-917-3005
Fax: +886-2-911-1283
Needhams
(916) 924-8037
Fax: (916) 924-8065
41
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DIAL-A-HELPER BBS via a Standard Modem
Modem:
Development Support (Continued)
AVAILABLE LITERATURE
CANADA/U.S.: (800) NSC-MICRO
(800) 672-6427
For more information, please see the COP8 Basic Family
User’s Manual, Literature Number 620895, COP8 Feature
Family User’s Manual, Literature Number 620897 and Na-
tional’s Family of 8-bit Microcontrollers COP8 Selection
Guide, Literature Number 630009.
EUROPE:
Baud:
(+49) 0-8141-351332
14.4k
Set-Up:
Length: 8-Bit
Parity: None
DIAL-A-HELPER SERVICE
Stop Bit:
1
Dial-A-Helper is a service provided by the Microcontroller
Applications group. The Dial-A-Helper is an Electronic Infor-
mation System that may be accessed as a Bulletin Board
System (BBS) via data modem, as an FTP site on the Inter-
net via standard FTP client application or as an FTP site on
the Internet using a standard Internet browser such as
Netscape or Mosaic.
Operation:
24 Hours, 7 Days
DIAL-A-HELPER via FTP
ftp nscmicro.nsc.com
user:
anonymous
@
username yourhost.site.domain
password:
The Dial-A-Helper system provides access to an automated
information storage and retrieval system. The system capa-
bilities include a MESSAGE SECTION (electronic mail,
when accessed as a BBS) for communications to and from
the Microcontroller Applications Group and a FILE SECTION
which consists of several file areas where valuable applica-
tion software and utilities could be found.
www.national.com
42
CUSTOMER RESPONSE CENTER
Development Support (Continued)
Complete product information and technical support is avail-
able from National’s customer response centers.
DIAL-A-HELPER via a WorldWide Web Browser
ftp://nscmicro.nsc.com
CANADA/
U.S.:
Tel:
(800) 272-9959
@
support tevm2.nsc.com
email:
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Physical Dimensions inches (millimeters) unless otherwise noted
68-Lead Molded Plastic Chip Carrier
Order Number COP888GW-XXX/V
NS Package Number V68A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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Products > Microcontrollers > 8-Bit COP8 Family > Mask ROM > COP888GW
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COP888GW
8-Bit Microcontroller with Pulse Train Generators and Capture Modules
Generic P/N 888GW
Contents
Parametric Table
Code Memory
RAM
16 K
512
l
l
l
General Description
Datasheet
Package Availability, Models, Samples
& Pricing
I/O Pins
56
Halt/Idle
yes/yes
Yes
l
Application Notes
MIWU
TO Timer
Voltage Range
Interrupts
Yes
2.5 to 6.0V
14
Watchdog/Clock Monitor N/A
Microwire Plus
Yes
Yes
USART Interface
General Description
The COP888 family of microcontrollers uses an 8-bit single chip core architecture fabricated
2
with National Semiconductor's M CMOS™ process technology. The COP888GW is a
member of this expandable 8-bit core processor family of microcontrollers. It is a fully static
part, fabricated using double-metal silicon gate microCMOS technology.
Features include an 8-bit memory mapped architecture, MICROWIRE/PLUS™ serial I/O,
two 16-bit timer/counters supporting three modes (Processor Independent PWM generation,
External Event counter and Input Capture mode capabilities), four independent 16-bit pulse
train generators with 16-bit prescalers, two independent 16-bit input capture modules with
8-bit prescalers, multiply and divide functions, full duplex UART, and two power savings
modes (HALT and IDLE), both with a multi-sourced wake up/interrupt capability. This
multi-sourced interrupt capability may also be used independent of the HALT or IDLE
modes.
Each I/O pin has software selectable configurations. The devices operate over a voltage
range of 2.5V-6V. High throughput is achieved with an efficient, regular instruction set
operating at a maximum of 1 µs per instruction rate. The device has low EMI emissions.
Low radiated emissions are achieved by gradual turn-on output drivers and internal I
CC
filters on the chip logic and crystal oscillator. The device is available in 68-pin PLCC
package.
Datasheet
Size
Title
(in
Kbytes)
Date
Receive via
Email
View
Online
Download
COP888GW 8-Bit Microcontroller with Pulse Train Generators and Capture
Modules
29-Aug-
00
509 Kbytes
View Online Download Receive via Email
Please use Adobe Acrobat to view PDF file(s).
If you have trouble printing, see Printing Problems.
Package Availability, Models, Samples & Pricing
Samples
&
Electronic
Orders
Package
Models
Budgetary Pricing
Quantity $US each
Std
Package
Pack
Part Number
Status
Marking
Size
Type
wafer
# pins
SPICE IBIS
COPGW888XXX/DWF
COPGW888-XXX/V
Preliminary N/A N/A
.
N/A
tube
-
[logo]¢U¢Z¢3¢T
COP888GW-XXX/V
PLCC(MCM) 68 Production N/A N/A
.
10000+ $6.3000 of
18
Application Notes
Size
(in
Kbytes)
Title
Date
Receive via
Email
View
Online
Download
Download
Download
View
Online
Receive via
Email
AN-982: Application Note 982 COP888GW Features and Applications
409 Kbytes 8-Dec-98
AN-1099: Application Note 1099 Creating a Multitasking Kernel for the COP8
26-Feb- View
99
Receive via
Email
168 Kbytes
Microcontroller
Online
Please use Adobe Acrobat to view PDF file(s).
If you have trouble printing, see Printing Problems.
[Information as of 30-Aug-2000]
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