CDCVF2310MPWREP [TI]
增强型产品 2.5V 至 3.3V 高性能时钟缓冲器 | PW | 24 | -55 to 125;
| 型号： | CDCVF2310MPWREP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 增强型产品 2.5V 至 3.3V 高性能时钟缓冲器 | PW | 24 | -55 to 125 时钟 驱动 CD 光电二极管 逻辑集成电路 |
| 文件： | 总15页 (文件大小：522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCVF2310-EP
www.ti.com.cn
ZHCSAL8 –DECEMBER 2012
2.5V 至 3.3V 高性能时钟缓冲器
查询样品: CDCVF2310-EP
1
特性
PW PACKAGE
(TOP VIEW)
•
•
•
•
•
•
•
•
高性能 1:10 时钟驱动器
在 VDD为 3.3V 时，运行频率高达 200MHz
1
24
在 VDD为 3.3V 时，引脚到引脚偏斜小于 100ps
GND
VDD
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VDD
1G
CLK
2
23
22
21
20
19
18
17
16
15
14
13
VDD
VDD
2Y0
2Y1
GND
GND
2Y2
2Y3
VDD
VDD
2G
VDD范围：2.3V 至 3.6V
3
输出使能毛刺脉冲抑制
4
将一个时钟输入分频至五个输出的两个组
25Ω 片载串联阻尼电阻器
5
6
7
采用 24 引脚薄型小尺寸封装 (TSSOP)
8
9
应用范围
10
11
12
•
通用应用
2Y4
支持国防、航空航天、和医疗应用
•
•
•
•
•
•
•
受控基线
一个组装和测试场所
一个制造场所
(1)
支持军用（-55°C 至 125°C）温度范围
延长的产品生命周期
延长的产品变更通知
产品可追溯性
(1) 可定制工作温度范围
说明
CDCVF2310 是一款运行频率高达 200MHz 的高性能、低偏斜时钟缓冲器。 五个输出的两个组中的每一个组提供
CLK 的低偏斜副本。 加电后，无论控制引脚的状态如何，输出的缺省状态为低电平。 对于正常运行，当控制引
脚（分别为 1G 或 2G）被保持在低电平并且在 CLK 输入上检测到一个负时钟边沿时，组 1Y[0:4] 或 2Y[0:4] 的输
出可被置于低电平状态。 当控制引脚（1G 和 2G）被保持在高电平并且在 CLK 输入上检测到一个负时钟边沿时，
组 1Y[0:4] 或 2Y[0:4] 的输出可被切换至缓冲器模式。 此器件运行在一个
2.5V 和 3.3V 环境中。 内置的输出使能毛刺脉冲抑制可确保一个已同步的输出使能序列以分配完全周期时钟信号。
CDCVF2310 运行温度范围为 -55°C 至 125°C。
Table 1. ORDERING INFORMATION(1)
TJ
PACKAGE
ORDERABLE PART NUMBER
CDCVF2310MPWREP
TOP-SIDE MARKING
CKV2310EP
VID NUMBER
V62/13603-01XE
V62/13603-01XE-T
–55°C to 125°C
TSSOP - PW
CDCVF2310MPWEP
CKV2310EP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
English Data Sheet: SCAS934
CDCVF2310-EP
ZHCSAL8 –DECEMBER 2012
www.ti.com.cn
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
3
1Y0
25 Ω
4
1Y1
25 Ω
5
1Y2
25 Ω
8
1Y3
25 Ω
9
1Y4
25 Ω
11
Logic Control
Logic Control
1G
2G
13
24
21
20
17
16
12
2Y0
2Y1
2Y2
2Y3
2Y4
25 Ω
25 Ω
25 Ω
25 Ω
CLK
25 Ω
2
Copyright © 2012, Texas Instruments Incorporated
CDCVF2310-EP
www.ti.com.cn
ZHCSAL8 –DECEMBER 2012
Table 2. FUNCTION TABLE
INPUT
2G
OUTPUT
1G
L
CLK
1Y[0:4]
L
CLK(1)
2Y[0:4]
L
L
L
↓
↓
↓
↓
H
L
L
H
H
L
CLK(1)
CLK(1)
H
CLK(1)
(1) After detecting one negative edge on the CLK input, the output
follows the input CLK if the control pin is held high.
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
1G
11
I
Output enable control for 1Y[0:4] outputs. This output enable is active-high, meaning the
1Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high.
2G
13
I
Output enable control for 2Y[0:4] outputs. This output enable is active-high, meaning the
2Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high.
1Y[0:4]
2Y[0:4]
CLK
3, 4, 5, 8, 9
21, 20, 17, 16, 12
24
O
O
I
Buffered output clocks
Buffered output clocks
Input reference frequency
Ground
GND
1, 6, 7, 18, 19
2, 10, 14, 15, 22, 23
VDD
DC power supply, 2.3 V – 3.6 V
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range (unless otherwise noted)
(1)
Supply voltage range, VDD
–0.5 V to 4.6 V
–0.5 V to VDD + 0.5 V
–0.5 V to VDD + 0.5 V
±50 mA
(2) (3)
Input voltage range, VI
(2) (3)
Output voltage range, VO
Input clamp current, IIK (VI < 0 or VI> VDD
)
Output clamp current, IOK (VO < 0 or VO > VDD
)
±50 mA
Continuous total output current, IO (VO = 0 to VDD
)
±50 mA
Storage temperature range Tstg
–65°C to 150°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This value is limited to 4.6 V maximum.
Copyright © 2012, Texas Instruments Incorporated
3
CDCVF2310-EP
ZHCSAL8 –DECEMBER 2012
www.ti.com.cn
THERMAL INFORMATION
CDCVF2310
PW
THERMAL METRIC(1)
UNITS
24 PINS
91.7
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
θJCtop
θJB
31.2
46.4
°C/W
ψJT
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
1.5
ψJB
45.8
θJCbot
N/A
(1) 有关传统和新的热 度量的更多信息，请参阅IC 封装热度量应用报告， SPRA953。
(2) 在 JESD51-2a 描述的环境中，按照 JESD51-7 的指定，在一个 JEDEC 标准高 K 电路板上进行仿真，从而获得自然 对流条件下的结至环
境热阻。
(3) 通过在封装顶部模拟一个冷板测试来获得结至芯片外壳（顶部）的热阻。 不存在特定的 JEDEC 标准测试，但 可在 ANSI SEMI 标准 G30-
88 中能找到内容接近的说明。
(4) 按照 JESD51-8 中的说明，通过 在配有用于控制 PCB 温度的环形冷板夹具的环境中进行仿真，以获得结板热阻。
(5) 结至顶部特征参数， ψJT，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中 描述的程序从仿真数据中 提取出该参
数以便获得 θJA
(6) 结至电路板特征参数， ψJB，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中 描述的程序从仿真数据中 提取出该
参数以便获得 θJA
。
。
(7) 通过在外露（电源）焊盘上进行冷板测试仿真来获得 结至芯片外壳（底部）热阻。 不存在特定的 JEDEC 标准 测试，但可在 ANSI SEMI
标准 G30-88 中能找到内容接近的说明。
空白
(1)
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
2.3
2.5
3.3
Supply voltage, VDD
V
3.6
VDD = 3 V to 3.6 V
VDD = 2.3 V to 2.7 V
VDD = 3 V to 3.6 V
VDD = 2.3 V to 2.7 V
0.8
V
Low-level input voltage, VIL
0.7
2
1.7
0
High-level input voltage, VIH
Input voltage, VI
V
VDD
12
6
V
VDD = 3 V to 3.6 V
VDD = 2.3 V to 2.7 V
VDD = 3 V to 3.6 V
VDD = 2.3 V to 2.7 V
High-level output current, IOH
mA
12
6
Low-level output current, IOL
mA
°C
Operating junction temperature, TJ
–55
125
(1) Unused inputs must be held high or low to prevent them from floating.
4
Copyright © 2012, Texas Instruments Incorporated
CDCVF2310-EP
www.ti.com.cn
ZHCSAL8 –DECEMBER 2012
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range (unless otherwise noted)
PARAMETER
Input voltage
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
VIK
II
VDD = 3 V,
II = –18 mA
–1.2
±5
V
Input current
VI = 0 V or VDD
μA
μA
pF
pF
(2)
IDD
CI
Static device current
Input capacitance
Output capacitance
CLK = 0 V or VDD
,
IO = 0 mA
100
VDD = 2.3 V to 3.6 V,
VDD = 2.3 V to 3.6 V,
VI = 0 V or VDD
VI = 0 V or VDD
2.5
2.8
CO
VDD = 3.3 V ±0.3 V
VDD = min to max,
VDD = 3 V
IOH = –100 μA
IOH = –12 mA
IOH = –6 mA
IOL = –100 μA
IOL = 12 mA
IOL = 6 mA
VDD – 0.2
2.1
VOH
VOL
IOH
IOL
High-level output voltage
V
V
2.4
VDD = min to max,
VDD = 3 V
0.2
0.8
Low-level output voltage
High-level output current
Low-level output current
0.55
VDD = 3 V,
VO = 1 V
–28
28
VDD = 3.3 V,
VDD = 3.6 V,
VDD = 3 V,
VO = 1.65 V
VO = 3.135 V
VO = 1.95 V
VO = 1.65 V
VO = 0.4 V
–36
36
mA
mA
–14
14
VDD = 3.3 V,
VDD = 3.6 V,
VDD = 2.5 V ±0.2 V
VOH High-level output voltage
VDD = min to max,
VDD = 2.3 V
IOH = –100 μA
IOH = –6 mA
IOL = 100 μA
IOL = 6 mA
VO = 1 V
VDD – 0.2
1.8
V
V
VDD = min to max,
VDD = 2.3 V
0.2
VOL
Low-level output voltage
High-level output current
0.55
VDD = 2.3 V,
VDD = 2.5 V,
VDD = 2.7 V,
VDD = 2.3 V,
VDD = 2.5 V,
VDD = 2.7 V,
–15
15
IOH
VO = 1.25 V
VO = 2.375 V
VO = 1.2 V
VO = 1.25 V
VO = 0.3 V
–25
25
mA
mA
–10
10
IOL
Low-level output current
(1) All typical values are at respective nominal VDD
.
(2) For ICC over frequency, see Figure 6.
Copyright © 2012, Texas Instruments Incorporated
5
CDCVF2310-EP
ZHCSAL8 –DECEMBER 2012
www.ti.com.cn
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating junction temperature
MIN NOM
MAX
UNIT
VDD = 3 V to 3.6 V
0
0
200
170
fclk
Clock frequency
MHz
VDD = 2.3 V to 2.7 V
JITTER CHARACTERISTICS
Characterized using CDCVF2310 Performance EVM when VDD=3.3 V. Outputs not under test are terminated to 50 Ω.
PARAMETER
TEST CONDITIONS
12 kHz to 5 MHz, fout = 30.72 MHz
12 kHz to 20 MHz, fout = 125 MHz
MIN
TYP
52
MAX
UNIT
tjitter
Additive phase jitter from input to output 1Y0
fs rms
45
SWITCHING CHARACTERISTICS
over recommended operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VDD = 3.3 V ±0.3 V (see Figure 2)
tPLH
f = 0 MHz to 200 MHz
For circuit load, see Figure 2.
CLK to Yn
tPHL
1.3
3.3
ns
tsk(o)
tsk(p)
tsk(pp)
tr
Output skew (Ym to Yn) (1) (see Figure 4)
100
570
500
2.2
ps
ps
Pulse skew (see Figure 5)
Part-to-part skew
ps
Rise time (see Figure 3)
VO = 0.4 V to 2 V
VO = 2 V to 0.4 V
0.7
0.7
0.1
0.1
0.4
0.4
V/ns
V/ns
ns
tf
Fall time (see Figure 3)
2.2
tsu(en)
tsu(dis)
th(en)
th(dis)
Enable setup time, G_high before CLK ↓
Disable setup time, G_low before CLK ↓
Enable hold time, G_high after CLK ↓
Disable hold time, G_low after CLK ↓
ns
ns
ns
VDD = 2.5 V ±0.2 V (see Figure 2)
tPLH
f = 0 MHz to 170 MHz
For circuit load, see Figure 2.
CLK to Yn
tPHL
1.5
4
ns
tsk(o)
tsk(p)
tsk(pp)
tr
Output skew (Ym to Yn) (1) (see Figure 4 )
170
680
600
1.4
ps
ps
Pulse skew (see Figure 5)
Part-to-part skew
ps
Rise time (see Figure 3)
VO = 0.4 V to 1.7 V
VO = 1.7 V to 0.4 V
0.5
0.5
0.1
0.1
0.4
0.4
V/ns
V/ns
ns
tf
Fall time (see Figure 3)
1.4
tsu(en)
tsu(dis)
th(en)
th(dis)
Enable setup time, G_high before CLK ↓
Disable setup time, G_low before CLK ↓
Enable hold time, G_high after CLK ↓
Disable hold time, G_low after CLK ↓
ns
ns
ns
(1) The tsk(o) specification is only valid for equal loading of all outputs.
6
Copyright © 2012, Texas Instruments Incorporated
CDCVF2310-EP
www.ti.com.cn
ZHCSAL8 –DECEMBER 2012
DETAILED DESCRIPTION
Output Enable Glitch Suppression Circuit
The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the
clock input such that the output buffer is enabled or disabled on the next full period of the input clock (negative
edge triggered by the input clock) (see Figure 1).
The G input must fulfill the timing requirements (tsu, th) according to the Switching Characteristics table for
predictable operation.
CLK
G
n
n
Y
t
t
h(en)
su(en)
a) Enable Mode
CLK
G
n
n
Y
t
t
h(dis)
su(dis)
b) Disable Mode
Figure 1. Enable and Disable Mode Relative to CLK↓
Copyright © 2012, Texas Instruments Incorporated
7
CDCVF2310-EP
ZHCSAL8 –DECEMBER 2012
www.ti.com.cn
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
C
L
= 25 pF on Y
500 Ω
n
A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 200 MHz, ZO = 50 Ω,
tr < 1.2 ns, tf < 1.2 ns.
Figure 2. Test Load Circuit
V
DD
CLK
50% V
0 V
DD
t
t
PHL
PLH
V
OH
1.7 V or 2 V
Y
n
50% V
DD
0.4 V
0.4 V
V
OL
t
r
t
f
Figure 3. Voltage Waveforms Propagation Delay Times
V
DD
CLK
0 V
V
OH
50% V
Any Y
DD
V
V
OL
OH
50% V
DD
Any Y
V
OL
t
t
sk(o)
sk(o)
Figure 4. Output Skew
V
DD
50% V
CLK
DD
0 V
t
t
PHL
PLH
V
OH
V
OL
Y
n
50% V
DD
NOTE: t
= | t
− t
PHL
|
sk(p)
PLH
Figure 5. Pulse Skew
8
Copyright © 2012, Texas Instruments Incorporated
CDCVF2310-EP
www.ti.com.cn
ZHCSAL8 –DECEMBER 2012
PARAMETER MEASUREMENT INFORMATION (continued)
SUPPLY CURRENT
vs
FREQUENCY
220
200
180
160
140
120
100
80
V
= 2.3 V to 3.6 V
DD
V
T
A
= 3.6 V
= –40°C
DD
C (Y ) = 25 pF || 500 Ω
L
n
All Outputs Switching
= –40°C to 85°C
V
T
= 3.6 V
= 85°C
DD
T
A
A
V
DD
= 2.3 V
60
T
A
= 85°C
V
T
A
= 2.3 V
= –40°C
DD
40
20
0
0
20
40
60
80
100
120
140
160
180
200
f – Frequency – MHz
Figure 6.
Copyright © 2012, Texas Instruments Incorporated
9
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CDCVF2310MPWEP
CDCVF2310MPWREP
V62/13603-01XE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
24
24
24
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
-55 to 125
-55 to 125
CKV2310EP
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
CKV2310EP
CKV2310EP
CKV2310EP
V62/13603-01XE-T
60
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
B
13
0.30
24X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
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