CDCLVC1102PWR [TI]
3.3 V and 2.5 V LVCMOS High-Performance Clock Buffer Family; 3.3 V和2.5 V LVCMOS高性能时钟缓冲器系列
| 型号： | CDCLVC1102PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3 V and 2.5 V LVCMOS High-Performance Clock Buffer Family |
| 文件： | 总14页 (文件大小：418K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCLVC11xx
www.ti.com
SCAS895 –MAY 2010
3.3 V and 2.5 V LVCMOS High-Performance Clock Buffer Family
Check for Samples: CDCLVC11xx
1
FEATURES
•
•
Operating Temperature Range: –40°C to 85°C
•
High-Performance 1:2, 1:3, 1:4, 1:6, 1:8, 1:10,
1:12 LVCMOS Clock Buffer Family
Available in 8-, 14-, 16-, 20-, 24-Pin TSSOP
Package (all pin compatible)
•
•
•
•
Very Low Pin-to-Pin Skew < 50 ps
Very Low Additive Jitter < 100 fs
Supply Voltage: 3.3 V or 2.5 V
fmax = 250 MHz for 3.3 V
APPLICATIONS
•
General Purpose Communication, Industrial
and Consumer Applications
fmax = 180 MHz for 2.5 V
CLKIN
1G
1
2
3
4
5
6
7
8
9
24 Y1
23 Y3
22 VDD
21 Y2
20 GND
19 Y5
18 VDD
17 Y7
16 Y8
15 GND
14 Y10
13 VDD
LV
CMOS
LV
CMOS
Y0
Y1
Y2
Y3
CLKIN
CDCLVC 1102
CDCLVC 1103
CDCLVC 1104
Y0
LV
CMOS
GND
VDD
Y4
LV
CMOS
CDCLVC 1106
CDCLVC 1108
GND
Y6
LV
CMOS
VDD
CDCLVC 1110
CDCLVC 1112
Y9 10
GND 11
Y11 12
•
•
•
LV
CMOS
Yn
1G
DESCRIPTION
The CDCLVC11xx is a modular, high-performance, low-skew, general purpose clock buffer family from Texas
Instruments.
The whole family is designed with a modular approach in mind. It is intended to round up TI's series of LVCMOS
clock generators.
There are 7 different fan-out variations, 1:2 to 1:12, available. All of the devices are pin compatible to each other
for easy handling.
All family members share the same high performing characteristics like low additive jitter, low skew, and wide
operating temperature range.
The CDCLVC11xx supports an asynchronous output enable control (1G) which switches the outputs into a low
state when 1G is low. Also, versions with synchronized enable control for glitch free switching and three-state
outputs are planned in future device options.
The CDCLVC11xx operate in a 2.5 V and 3.3 V environment and are characterized for operation from –40°C to
85°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CDCLVC11xx
SCAS895 –MAY 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE OPTIONS
CLKIN
1G
1
2
3
4
8
7
6
5
Y 1
CLKIN
1G
1
2
3
4
5
6
14 Y 1
13 Y 3
12 VDD
11 Y 2
10 GND
CLKIN
1G
1
2
3
4
5
6
20 Y1
19 Y3
18 VDD
17 Y2
16 GND
15 Y5
NC
CDCLVC1102
Y 0
VDD
NC
Y 0
Y 0
CDCLVC1106
GND
GND
VDD
Y 4
GND
VDD
Y 4
CDCLVC 1110
9
8
Y 5
CLKIN
1G
1
2
3
4
8
7
6
5
Y 1
GND
7
VDD
GND
Y 6
7
8
9
14 VDD
13 Y7
NC
CDCLVC1103
Y 0
VDD
Y 2
VDD
12 Y8
GND
CLKIN
1G
1
2
16 Y 1
15 Y 3
Y 9 10
11 GND
Y 0
GND
VDD
Y 4
3
4
5
6
7
8
14 VDD
13 Y 2
CLKIN
1G
1
2
3
4
8
7
6
5
Y 1
CLKIN
1
2
3
4
5
6
7
8
9
24 Y1
CDCLVC1108
Y 3
1G
Y 0
23 Y3
CDCLVC1104
12 GND
11 Y 5
Y 0
VDD
Y 2
22 VDD
21 Y2
GND
GND
VDD
Y 4
GND
Y 6
10 VDD
20 GND
19 Y5
9
Y 7
CDCLVC 1112
GND
Y 6
18 VDD
17 Y7
VDD
16 Y8
Y 9 10
GND 11
Y11 12
15 GND
14 Y10
13 VDD
PIN FUNCTIONS
LVCMOS
CLOCK INPUT
CLOCK OUTPUT
ENABLE
SUPPLY
VOLTAGE
LVCMOS CLOCK OUTPUT
GROUND
DEVICES
CLKIN
1G
2
Y0, Y1, … Y11
3, 8
VDD
GND
CDCLVC1102
CDCLVC1103
CDCLVC1104
CDCLVC1106
CDCLVC1108
CDCLVC1110
CDCLVC1112
1
1
1
1
1
1
1
6
6
4
4
2
3, 8, 5
2
3, 8, 5, 7
6
4
2
3, 14, 11, 13, 6, 9
5, 8, 12
5, 10, 14
5, 9, 14, 18
5, 9, 13, 18, 22
4, 7, 10
4, 7, 12
4, 7, 11, 16
4, 7, 11, 15, 20
2
3, 16, 13, 15, 6, 11, 8, 9
3, 20, 17, 19, 6, 15, 8, 13, 10
3, 24, 21, 23, 6, 19, 8, 17, 16, 10, 14, 12
2
2
OUTPUT LOGIC TABLE
INPUTS
OUTPUTS
CLKIN
1G
L
Yn
L
X
L
H
L
H
H
H
2
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CDCLVC11xx
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SCAS895 –MAY 2010
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE / UNIT
VDD
VIN
VO
IIN
Supply voltage range
–0.5 V to 4.6 V
–0.5 V to VDD + 0.5 V
–0.5 V to VDD + 0.5 V
±20 mA
(2)
Input voltage range
Output voltage range
Input current
(2)
IO
Continuous output current
Maximum junction temperature
Storage temperature range
±50 mA
TJ
125°C
TST
–65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) This value is limited to 4.6 V maximum.
THERMAL INFORMATION
DCDLVC1102/03/04
CDCLVC1106
PW
CDCLVC1108 CDCLVC11010 CDCLVC1112
THERMAL METRIC(1)
PW
8 PINS
149.4
69.4
PW
16 PINS
108.4
33.6
PW
20 PINS
83.0
PW
24 PINS
87.9
UNITS
14 PINS
112.6
qJA
Junction-to-ambient thermal resistance(2)
°C/W
(3)
qJC(top) Junction-to-case(top) thermal resistance
48.0
32.3
26.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
3.0
NOM
3.3
MAX
3.6
UNIT
3.3 V supply
VDD
Supply voltage range
Low-level input voltage
High-level input voltage
V
2.5 V supply
2.3
2.5
2.7
VDD = 3.0 V to 3.6 V
VDD = 2.3 V to 2.7 V
VDD = 3.0 V to 3.6 V
VDD = 2.3 V to 2.7 V
VDD = 2.3 V to 3.6 V
VDD/2 – 600
VDD/2 – 400
VIL
mV
mV
VDD/2 + 600
VDD/2 + 400
VIH
Vth
Input threshold voltage
Input slew rate
VDD/2
mV
tr / tf
1
1.8
4
V/ns
VDD = 3.0 V to 3.6 V
VDD = 2.3 V to 2.7 V
VDD = 3.0 V to 3.6 V
VDD = 2.3 V to 2.7 V
Minimum pulse width at
CLKIN
tw
ns
2.75
DC
250
180
85
LVCMOS clock Input
Frequency
fCLK
TA
MHz
°C
DC
Operating free-air temperature
–40
Copyright © 2010, Texas Instruments Incorporated
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SCAS895 –MAY 2010
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DEVICE CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
CONDITION
MIN TYP(1)
MAX UNIT
OVERALL PARAMETERS FOR ALL VERSIONS
1G = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 3.6 V
1G = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 2.7 V
1G = 0 V; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 3.6 V or 2.7 V
VDD = 3.3 V; f = 10 MHz
6
3
10 mA
IDD
IPD
Static device current(2)
Power down current
6
mA
µA
pF
pF
60
6
Power dissipation capacitance
per output(3)
CPD
VDD = 2.5 V; f = 10 MHz
4.5
Input leakage current at 1G
± 8
II
VI = 0 V or VDD, VDD = 3.6 V or 2.7 V
µA
Input leakage current at CLKIN
± 25
VDD = 3.3 V
45
Ω
Ω
ROUT Output impedance
fOUT Output frequency
VDD = 2.5 V
60
VDD = 3.0 V to 3.6 V
VDD = 2.3 V to 2.7 V
DC
DC
250 MHz
180 MHz
OUTPUT PARAMETERS FOR VDD = 3.3 V ± 0.3 V
VDD = 3 V, IOH = –0.1 mA
2.9
2.5
2.2
VOH High-level output voltage
VDD = 3 V, IOH = –8 mA
VDD = 3 V, IOH = –12 mA
VDD = 3 V, IOL = 0.1 mA
VDD = 3 V, IOL = 8 mA
VDD = 3 V, IOL = 12 mA
V
0.1
VOL Low-level output voltage
0.5
0.8
V
tPLH
tPHL
,
Propagation delay
CLKIN to Yn
0.8
0.3
2.0
ns
tsk(o) Output skew
Equal load of each output
50
0.8
6
ps
ns
ns
ns
tr/tf
tDIS
tEN
Rise and fall time
20%–80% (VOH - VOL
)
Output disable time
Output enable time
Pulse skew ;
1G to Yn
1G to Yn
6
tsk(p)
To be measured with input duty cycle of 50%
180
ps
(4)
tPLH(Yn) – tPHL(Yn)
tsk(pp) Part-to-part skew
tjitter Additive jitter rms
Under equal operating conditions for two parts
12kHz…20 MHz, fOUT = 250 MHz
0.5
ns
fs
100
(1) All typical values are at respective nominal VDD. For switching characteristics, outputs are terminated to 50 Ω to VDD/2 (see Figure 1).
(2) For dynamic IDD over frequency see Figure 8 and Figure 9.
(3) This is the formula for the power dissipation calculation (see Figure 8 and the Power Consideration section).
Ptot = Pstat + Pdyn + PCload [W]
Pstat = VDD × IDD [W]
Pdyn = CPD × VDD2 × ƒ [W]
PCload = Cload × VDD2 × ƒ × n [W]
n = Number of switching output pins
(4) tsk(p) depends on output rise- and fall-time (tr/tf). The output duty-cycle can be calculated: odc = (tw(OUT) ± tsk(p))/tperiod; tw(OUT) is
pulse-width of output waveform and tperiod is 1/fOUT
.
4
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CDCLVC11xx
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SCAS895 –MAY 2010
DEVICE CHARACTERISTICS (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
CONDITION
MIN TYP(1)
MAX UNIT
OUTPUT PARAMETERS FOR VDD = 2.5 V ± 0.2 V
VDD = 2.3 V, IOH = –0.1 mA
2.2
1.7
VOH High-level output voltage
VOL Low-level output voltage
V
VDD = 2.3 V, IOH = –8 mA
VDD = 2.3 V, IOL = 0.1 mA
VDD = 2.3 V, IOL = 8 mA
0.1
V
0.5
tPLH
tPHL
,
Propagation delay
CLKIN to Yn
1.0
0.3
2.6
ns
tsk(o) Output skew
Equal load of each output
20%–80% reference point
1G to Yn
50
1.2
10
ps
ns
ns
ns
tr/tf
tDIS
tEN
Rise and fall time
Output disable time
Output enable time
Pulse skew ;
1G to Yn
10
tsk(p)
To be measured with input duty cycle of 50%
220
ps
(5)
tPLH(Yn) – tPHL(Yn)
tsk(pp) Part-to-part skew
tjitter Additive jitter rms
Under equal operating conditions for two parts
12kHz…20 MHz, fOUT = 180 MHz
1.2
ns
fs
350
(5) tsk(p) depends on output rise- and fall-time (tr/tf). The output duty-cycle can be calculated: odc = (tw(OUT) ± tsk(p))/tperiod; tw(OUT) is
pulse-width of output waveform and tperiod is 1/fOUT
.
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PARAMETERS MEASUREMENT INFORMATION
V
= 3.3 V or 2.5 V
DD
LVCMOS
Output
Z
= 50 W
O
R=50 W
C = 2 pF
from Measurement Equipment
parasitic capasitance
V
/2
DD
Figure 1. Test Load Circuit
V
DD
V
= 3.3 V or 2.5 V
DD
R=100 W
LVCMOS
Output
Z
= 50 W
O
parasitic input capacitance
R= 100 W
Figure 2. Application Load With 50 Ω Line Termination
V
= 3.3 V or 2.5 V
DD
RS = 10 W (V = 3.3 V)
DD
RS = 0 W (V = 2.5 V)
DD
LVCMOS
Output
Z
= 50 W
O
parasitic input capacitance
Figure 3. Application Load With Series Line Termination
VDD / 2
VIN / 2
Y
n
1 G
VIN / 2
VDD / 2
Yn
Y
n+1
tsk(o)
tDIS
tEN
tsk(o)
Figure 4. tDIS and tEN for Disable Low
Figure 5. Output Skew tsk(o)
6
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SCAS895 –MAY 2010
PARAMETERS MEASUREMENT INFORMATION (continued)
V
/ 2
DD
CLKIN
CLKIN
V
OH
80 % V
20 % V
-V
OH OL
Y
n
V
/ 2
DD
-V
OH OL
Y
n
V
OL
t
t
f
r
t
PLH
t
PHL
Note: t
= | t
– t
|
PHL
sk(p)
PLH
Figure 6. Pulse Skew tsk(p) and Propagation Delay
tPLH/tPHL
Figure 7. Rise/Fall Times tr/tf
TYPICAL CHARACTERISTICS
Power Consideration
The following power consideration refers to the device-consumed power consumption only. The device power
consumption is the sum of static power and dynamic power. The dynamic power usage consists of two
components:
1. Power used by the device as it switches states.
2. Power required to charge any output load.
The output load can be capacitive only or capacitive and resistive. The following formula and the power graphs in
Figure 8 and Figure 9 can be used to obtain the power consumption of the device:
Pdev = Pstat + n (Pdyn + PCload
)
Pstat = VDD x IDD
Pdyn + PCload = see Figure 8 and Figure 9
where:
VDD = Supply voltage (3.3 V or 2.5 V)
IDD = Static device current (typ 6 mA for VDD = 3.3 V; typ 3 mA for VDD = 2.5 V)
n = Number of switching output pins
Example for Device Power Consumption for CDCLVC1104: 4 outputs are switching, f = 120 MHz, VDD = 3.3 V
and Cload = 2 pF per output:
Pdev = Pstat + n (Pdyn + PCload) = 19.8 mW + 40 mW = 59.8 mW
Pstat = VDD x IDD = 6 mA x 3.3 V = 19.8 mW
n (Pdyn + PCload) = 4 x 10 mW = 40 mW
NOTE
For dimensioning the power supply, the total power consumption needs to be considered.
The total power consumption is the sum of the device power consumption and the power
consumption of the load.
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TYPICAL CHARACTERISTICS (continued)
40
15
V
= 3.3 V
P
+ P
Cload8pF
DD
V
= 2.5 V
DD
dyn
P
+ P
Cload8pF
dyn
P
+ P
Cload50/2
30
dyn
10
P
+ P
Cload50/2
dyn
20
10
0
5
0
P
+ P
Cload2pF
P
+ P
Cload2pF
dyn
dyn
0
20
40
60 80 100 120 140 160 180
f - Clock Frequency - MHz
0
20 40 60 80 100 120 140 160 180 200 220 240
f - Clock Frequency - MHz
Figure 8. Device Power Consumption vs Clock Frequency
Figure 9. Device Power Consumption vs Clock Frequency
(Load 50Ω into VDD/2. 2pF, 8pF; Per Output)
(Load 50Ω into VDD/2. 2pF, 8pF; Per Output)
5
3
V
= 2.5 V
DD
V
= 3.3 V
DD
4
3
2
I
= C * V
* f
dyn
PD
DD
2
1
0
I
= C * V
* f
dyn
PD
DD
1
0
0
20
40
60
f - Clock Frequency - MHz
80 100 120 140 160 180
0
20 40 60 80 100 120 140 160 180 200 220 240
f - Clock Frequency - MHz
Figure 10. Dynamic Supply Current vs Clock Frequency
(CPD = 6pF, No Load; Per Output)
Figure 11. Dynamic Supply Current vs Clock Frequency
(CPD = 4.5pF, No Load; Per Output)
8
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PACKAGE OPTION ADDENDUM
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26-Jun-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
CDCLVC1102PW
CDCLVC1102PWR
CDCLVC1103PW
CDCLVC1103PWR
CDCLVC1104PW
CDCLVC1104PWR
CDCLVC1106PW
CDCLVC1106PWR
CDCLVC1108PW
CDCLVC1108PWR
CDCLVC1110PW
CDCLVC1110PWR
CDCLVC1112PW
CDCLVC1112PWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
8
8
150
2000
150
2000
150
2000
90
Green (RoHS
& no Sb/Br)
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CU NIPDAU Level-1-260C-UNLIM
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Purchase Samples
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& no Sb/Br)
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14
16
16
20
20
24
24
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& no Sb/Br)
2000
90
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& no Sb/Br)
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2000
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2000
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2000
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(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCLVC1102PWR
CDCLVC1103PWR
CDCLVC1104PWR
CDCLVC1106PWR
CDCLVC1108PWR
CDCLVC1110PWR
CDCLVC1112PWR
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
PW
8
8
2000
2000
2000
2000
2000
2000
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
16.4
16.4
7.0
7.0
3.6
3.6
3.6
5.6
5.6
7.1
8.3
1.6
1.6
1.6
1.6
1.6
1.6
1.6
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
8
7.0
14
16
20
24
6.9
6.9
6.95
6.95
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CDCLVC1102PWR
CDCLVC1103PWR
CDCLVC1104PWR
CDCLVC1106PWR
CDCLVC1108PWR
CDCLVC1110PWR
CDCLVC1112PWR
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
PW
8
8
2000
2000
2000
2000
2000
2000
2000
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
29.0
29.0
29.0
29.0
29.0
33.0
33.0
8
14
16
20
24
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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