CDCEL824PWR [TI]

具有展频功能的可编程 2-PLL 时钟合成器 | PW | 16 | -40 to 85;


型号：	CDCEL824PWR
厂家：	TEXAS INSTRUMENTS
描述：	具有展频功能的可编程 2-PLL 时钟合成器 \| PW \| 16 \| -40 to 85 时钟
文件：	总33页 (文件大小：2205K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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CDCEL824

ZHCSEA7A –JUNE 2015–REVISED SEPTEMBER 2015

CDCEL824 可编程 2 PLL 时钟合成器

1 特性

2 应用

激光测距应用

•

灵活的时钟驱动器

–

3 个用户定义的控制输入 [S0/S1/S2]：例如，开

关频率、输出使能或断电

3 说明

CDCEL824 是一款基于锁相环 (PLL) 的模块化、低成

本、高性能可编程时钟合成器/乘法器/除法器。该器件

最多可从单输入频率中生成四个输出时钟。在系统内

最多可使用两个独立可配置 PLL 在任何时钟频率下

（最高可达 201MHz）对各输出进行编程。

–

启用 0-PPM 时钟生成

•

系统内可编程性和 EEPROM

–

串行可编程易失性寄存器

非易失性 EEPROM 以存储客户设置

灵活的输入计时理念

–

外部晶振：20MHz 至 30MHz

CDCEL824 具备一个独立的输出电源引脚 V_DDOUT，其

电压为 1.8V。

单端低电压互补金属氧化物半导体 (LVCMOS)

高达 130MHz

此输入接受一个外部晶振或 LVCMOS 时钟信号。对

于晶振输入，片上负载电容足以满足大多数应用的要

求。负载电容值可在 0pF 至 20pF 的范围内设定。

•

高达 201MHz 的可选输出频率

低噪声 PLL 内核

–

集成了 PLL 环路滤波器组件

低周期抖动（典型值为 80ps）

器件信息⁽¹⁾

•

1.8V 器件电源

部件号

CDCEL824

封装

封装尺寸（标称值）

TSSOP (16)

5.00mm x 4.40mm

温度范围：–40°C 至 85°C

采用薄型小外形尺寸 (TSSOP) 封装

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

典型电路原理图

Ethernet PHY

CDCEL824

WiFi

25 MHz

USB Controller

FPGA

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SCAS945

CDCEL824

ZHCSEA7A –JUNE 2015–REVISED SEPTEMBER 2015

www.ti.com.cn

9.2 Functional Block Diagram ......................................... 9

9.3 Feature Description................................................. 10

9.4 Device Functional Modes........................................ 12

9.5 Programming........................................................... 13

9.6 Register Maps......................................................... 15

10 Application and Implementation........................ 22

10.1 Application Information.......................................... 22

10.2 Typical Application ............................................... 22

11 Power Supply Recommendations ..................... 24

12 Layout................................................................... 24

12.1 Layout Guidelines ................................................. 24

12.2 Layout Example .................................................... 25

13 器件和文档支持 ..................................................... 26

13.1 文档支持 ............................................................... 26

13.2 社区资源................................................................ 26

13.3 商标....................................................................... 26

13.4 静电放电警告......................................................... 26

13.5 Glossary................................................................ 26

14 机械、封装和可订购信息....................................... 26

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）............................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Conditions....................... 4

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics .......................................... 6

7.6 CLK_IN Timing Requirements .................................. 7

7.7 SDA/SCL Timing Requirements .............................. 7

7.8 EEPROM Specification ............................................. 7

7.9 Typical Characteristics.............................................. 7

Parameter Measurement Information .................. 8

Detailed Description .............................................. 9

9.1 Overview ................................................................... 9

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (June 2015) to Revision A

Page

•

已更改 “产品定制”至“产品目录数据表”.................................................................................................................................... 1

Changed order of pin function rows to be by number per format rules ................................................................................. 3

Changed Thermal Information table format; move EEPROM Spec table per format rules ................................................... 5

5 说明（续）

例如，深 M/N 分频比可从 27MHz 基准输入频率中生成零 ppm 音频/视频、网络互联（无线局域网 (WLAN)、

Bluetooth、以太网、全球定位系统 (GPS)）或接口（通用串行总线 (USB)、IEEE1394、记忆棒）时钟。

该器件会根据 PLL 频率和分频器设置自动调整内部环路滤波器组件，从而使各 PLL 具备较高稳定性和优化的抖动

传输特性。

为了轻松实现器件自定义来满足应用需要，该器件支持使用非易失性 EEPROM 进行编程。该器件预设为采用默认

出厂配置，允许在安装于印刷电路板 (PCB) 前按照另一种应用配置重新编程，或者通过系统内部编程进行重新编

程。所有器件设置均可通过串行数据/串行时钟 (SDA/SCL) 总线（一种二线制串行接口）进行编程。

三个可自由编程的控制输入（S0、S1 和 S2）可用于选择不同频率或其他控制功能，包括将输出禁用为低电平、在

高阻抗状态下输出、断电以及 PLL 旁路等。

CDCx824 可在 1.8V 电压的作用下运行，其运行温度范围为 –40°C 至 85°C。

CDCEL824

www.ti.com.cn

ZHCSEA7A –JUNE 2015–REVISED SEPTEMBER 2015

6 Pin Configuration and Functions

PW Package

20-Pin TSSOP

Top View

Xin/Clk 1

S0 2

16 Xout

15 S1/SDA

14 S2/SCL

13 DNC

12 GND

11 Y1

Vdd 3

Vctr 4

GND 5

Vddout 6

Y3 7

10 Y2

Y4 8

9 Vddout

Pin Functions

I/O

DESCRIPTION

NUMBER

NAME

Xin/CLK

Crystal oscillator input or LVCMOS clock Input (selectable via SDA/SCL bus).

User-programmable control input S0; LVCMOS inputs; internal pullup.

1.8-V power supply for the device

VCXO control voltage (leave open or pull up when not used).

Ground

V_DD

Power

V_Ctrl

5, 12

6, 9

GND

V_DDOUT

Ground

Power

1.8-V supply for all outputs

LVCMOS outputs

DNC

Reserved pin, do not connect

SCL: Serial clock input (default configuration), LVCMOS; internal pullup.

S2: User-programmable control input; LVCMOS inputs; internal pullup.

SCL/S2

SDA: Bidirectional serial data input/output (default configuration), LVCMOS; internal pullup

S1: User-programmable control input; LVCMOS inputs; internal pullup.

SDA/S1

Xout

I/O or I

Crystal oscillator output (leave open or pull up when not used).

CDCEL824

ZHCSEA7A –JUNE 2015–REVISED SEPTEMBER 2015

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

MAX

2.5

UNIT

V_DD

V_I

Supply voltage range

Input voltage range^{(2) (3)}

Output voltage range⁽²⁾

Input current (V_I< 0, V_I> V_DD

Continuous output current

V_DD+ 0.5

V_O

I_I

)

°C

I_O

T_J

Maximum junction temperature

Storage temperature range

125

T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3) SDA and SCL can go up to 3.6V as stated in the Recommended Operating Conditions table.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification JESD22-C101, all

pins⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN

1.7

NOM

MAX

1.9

UNIT

V_DD

Device supply voltage

1.8

V_DDOUT

V_IL

Output Yx supply voltage for CDCEL824

Low-level input voltage LVCMOS

High-level input voltage LVCMOS

Input voltage threshold LVCMOS

Input voltage range S0

1.7

1.9

0.3 V_DD

V_IH

0.7 V_DD

V_I(thresh)

0.5 V_DD

1.9

3.6

1.9

±8

V_I(S)

Input voltage range S1, S2, SDA, SCL; V_(Ithresh)= 0.5 V_DD

Input voltage range CLK

V_I(CLK)

I_OH/I_OL

C_L

Output current (V_DDOUT= 1.8 V)

Output load LVCMOS

°C

T_A

Operating free-air temperature

–40

RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS⁽¹⁾

f_Xtal

Crystal input frequency range (fundamental mode)

Effective series resistance

Pulling range (0 V ≤ V_Ctrl≤ 1.8 V)⁽²⁾

MHz

Ω

ESR

f_PR

100

±120

±150

ppm

V_Ctrl

C₀/C₁

C_L

Frequency control voltage

V_DD

220

Pullability ratio

On-chip load capacitance at Xin and Xout

(1) For more information about VCXO configuration, and crystal recommendation, see application report (SCAA085).

(2) Pulling range depends on crystal-type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm

applies for crystal listed in the application report (SCAA085).

CDCEL824

www.ti.com.cn

ZHCSEA7A –JUNE 2015–REVISED SEPTEMBER 2015

7.4 Thermal Information

CDCEL824

AIRFLOW

(lfm)

THERMAL METRIC⁽¹⁾⁽²⁾

PW (TSSOP)

UNIT

30 PINS

101

°C/W

150

200

250

500

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

ψ_JB

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

R_θJC(bot)

1.0

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

CDCEL824

ZHCSEA7A –JUNE 2015–REVISED SEPTEMBER 2015

www.ti.com.cn

7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

UNIT

OVERALL PARAMETER

All PLLS on

All outputs off, f_CLK= 27 MHz,

f_VCO= 135 MHz; f_OUT= 27 MHz

I_DD

Supply current (see Figure 1)

Supply current (see Figure 2)

Per PLL

No load, all outputs on,

f_OUT= 27 MHz

I_DDOUT

I_DDPD

V_PUC

V_DDOUT= 1.8 V

μA

Power-down current. Every circuit

powered down except SDA/SCL

f_IN= 0 MHz,

V_DD= 1.9 V

Supply voltage V_DDthreshold for power-

up control circuit

0.85

1.45

201

f_VCO

f_OUT

VCO frequency range of PLL

LVCMOS output frequency

MHz

V_DDOUT= 1.8 V

201

LVCMOS PARAMETER

V_IK

I_I

LVCMOS input voltage

V_DD= 1.7 V; I_S= –18 mA

V_I= 0 V or V_DD; V_DD= 1.9 V

V_I= V_DD; V_DD= 1.9 V

V_I= 0 V; V_DD= 1.9 V

V_IClk= 0 V or V_DD

–1.2

±5

LVCMOS input current

μA

I_IH

I_IL

LVCMOS input current for S0/S1/S2

LVCMOS Input current for S0/S1/S2

Input capacitance at Xin/Clk

Input capacitance at Xout

–4

C_I

V_IXout= 0 V or V_DD

Input capacitance at S0/S1/S2

V_IS= 0 V or V_DD

LVCMOS PARAMETER for V_DDOUT= 1.8 V – MODE

V_DDOUT= 1.7 V, I_OH= –0.1 mA

V_DDOUT= 1.7 V, I_OH= –4 mA

V_DDOUT= 1.7 V, I_OH= –8 mA

V_DDOUT= 1.7 V, I_OL= 0.1 mA

V_DDOUT= 1.7 V, I_OL= 4 mA

V_DDOUT= 1.7 V, I_OL= 8 mA

All PLL bypass

1.6

1.4

1.1

V_OH

LVCMOS high-level output voltage

LVCMOS low-level output voltage

0.1

0.3

0.6

V_OL

t_PLH, t_PHLPropagation delay

2.6

0.7

t_r/t_f

Rise and fall time

V_DDOUT= 1.8 V (20%–80%)

1 PLL switching, Y1-to-Y2

2 PLL switching, Y1-to-Y4

1 PLL switching, Y1-to-Y2

2 PLL switching, Y1-to-Y4

f_OUT= 50 MHz; Y1-to-Y2

f_OUT= 50 MHz; Y1-to-Y4

f_VCO= 100 MHz; Pdiv = 1

110

200

130

220

(2) (3)

t_jit(cc)

Cycle-to-cycle jitter

130

100

150

(3)

t_jit(per)

Peak-to-peak period jitter

t_sk(o)

odc

Output skew⁽⁴⁾

110

55%

Output duty cycle⁽⁵⁾

45%

SDA/SCL PARAMETER

V_IK

I_IH

SCL and SDA input clamp voltage

SCL and SDA input current

SDA/SCL input high voltage⁽⁶⁾

SDA/SCL input low voltage⁽⁶⁾

SDA low-level output voltage

SCL/SDA Input capacitance

V_DD= 1.7 V; I_I= –18 mA

V_I= V_DD; V_DD= 1.9 V

–1.2

±10

μA

V_IH

V_IL

V_OL

C_I

0.7 V_DD

0.3 V_DD

0.2 V_DD

I_OL= 3 mA V_DD= 1.7 V

V_I= 0 V or V_DD

(1) All typical values are at respective nominal V_DD

(2) 10,000 cycles

(3) Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, f_VCO= 135 MHz, f_OUT= 27 MHz. f_OUT= 3.072 MHz or input

frequency = 27 MHz, f_VCO= 108 MHz, f_OUT= 27 MHz. f_OUT= 16.384 MHz, f_OUT= 25 MHz, f_OUT= 74.25 MHz, f_OUT= 48 MHz

(4) The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider,

data sampled on rising edge (t_r).

(5) odc depends on output rise- and fall time (t_r/t_f).

(6) SDA and SCL pins are 3.3-V tolerant.

CDCEL824

www.ti.com.cn

ZHCSEA7A –JUNE 2015–REVISED SEPTEMBER 2015

7.6 CLK_IN Timing Requirements

over recommended ranges of supply voltage, load, and operating free-air temperature

MIN

NOM

MAX

130

UNIT

MHz

PLL bypass mode

f_CLK

LVCMOS clock input frequency

PLL mode

t_r/ t_f

Rise and fall time CLK signal (20% to 80%)

Duty cycle CLK at V_DD/ 2

duty_CLK

40%

60%

7.7 SDA/SCL Timing Requirements

STANDARD MODE

FAST MODE

(SeeFigure 5)

UNIT

MIN

MAX

MIN

MAX

f_SCL

SCL clock frequency

100

400

kHz

μs

t_su(START)

t_h(START)

t_w(SCLL)

t_w(SCLH)

t_h(SDA)

t_su(SDA)

t_r

START setup time (SCL high before SDA low)

START hold time (SCL low after SDA low)

SCL low-pulse duration

4.7

0.6

1.3

0.6

4.7

SCL high-pulse duration

SDA hold time (SDA valid after SCL low)

SDA setup time

3.45

0.9

250

100

SCL/SDA input rise time

1000

300

t_f

SCL/SDA input fall time

t_su(STOP)

t_BUS

STOP setup time

0.6

1.3

Bus free time between a STOP and START condition

4.7

7.8 EEPROM Specification

MIN

100

TYP

MAX

UNIT

cycles

years

EEcyc

EEret

Programming cycles of EEPROM

Data retention

1000

7.9 Typical Characteristics

All PLL Off

1 PLL On

2 PLL On

All Outputs Off

1 Output On

3 Outputs On

130

170

200

130

170

200

f - Frequency (MHz)

f_OUT- Output Frequency (MHz)

D001

D002

Figure 1. Supply Current vs PLL Frequency

Figure 2. Output Current vs Output Frequency

CDCEL824

ZHCSEA7A –JUNE 2015–REVISED SEPTEMBER 2015

www.ti.com.cn

8 Parameter Measurement Information

CDCEL824

1 kW

LVCMOS

10 pF

Figure 3. Test Load

CDCEL824

LVCMOS

Series

Termination

~ 18 W

Line Impedance

Zo = 50 W

Typical Driver

Impedance

~ 32 W

Figure 4. Test Load for 50-Ω Board Environment

CDCEL824

www.ti.com.cn

ZHCSEA7A –JUNE 2015–REVISED SEPTEMBER 2015

9 Detailed Description

9.1 Overview

The CDCEL824 is a modular PLL-based low-cost, high-performance, programmable clock synthesizer, multiplier,

and divider. It generates up to four output clocks from a single input frequency. Each output can be programmed

in-system for any clock frequency up to 201 MHz, using up to two independent configurable PLLs.

The CDCEL824 has a separate output supply pins, V_DDOUT, which are 1.8 V.

The input accepts an external crystal or LVCMOS clock signal. In case of a crystal input, an on-chip load

capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 pF to 20 pF.

The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, Bluetooth,

Ethernet, GPS) or interface (USB, IEEE1394, memory stick) clocks from a 27-MHz reference input frequency, for

example.

Based on the PLL frequency and the divider settings, the internal loop filter components are automatically

adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL.

The device supports nonvolatile EEPROM programming for easy customization of the device in the application. It

is preset to a factory default configuration and can be reprogrammed to a different application configuration

before it goes onto the PCB or reprogrammed by in-system programming. All device settings are programmable

through the SDA/SCL bus, a 2-wire serial interface.

Three, free programmable control inputs, S0, S1, and S2, can be used to select different frequencies, or other

control features like outputs disable to low, outputs in high-impedance state, power down, PLL bypass, and so

forth.

The CDCx824 operates in a 1.8-V environment. It operates in a temperature range of –40°C to 85°C.

9.2 Functional Block Diagram

GND

DDOUT

Vctr

Xin/CLK

VCXO

CMOS

Pdiv2

7-Bit

LVCMOS

PLL 1

Xout

CMOS

Pdiv3

7-Bit

PLL Bypass

EEPROM

Programming

and

SDA/SCL

S1/SDA

S2/SCL

CMOS

Pdiv4

7-Bit

PLL 2

CMOS

Pdiv5

7-Bit

PLL Bypass

CDCEL824

ZHCSEA7A –JUNE 2015–REVISED SEPTEMBER 2015

www.ti.com.cn

9.3 Feature Description

9.3.1 Control Pins Settings

The CDCEL824 has three user-definable control pins (S0, S1, and S2) which allow external control of device

settings. They can be programmed to any of the following settings:

•

Frequency selection → switching between any of two user-defined frequencies

Output state selection → output configuration and power-down control

The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.

Table 1. Control Pin Definition

EXTERNAL

CONTROL

BITS

PLL1 SETTING

PLL2 SETTING

RSVD SETTING

Control

function

PLL frequency

selection

Output Y1/Y2

selection

PLL frequency

selection

Output Y3/Y4

selection

Reserved

Table 2. PLL Setting (Can Be Selected for Each PLL Individual)⁽¹⁾

FREQUENCY SELECTION⁽²⁾

FSx

FUNCTION

Frequency0

Frequency1

OUTPUT SELECTION⁽³⁾(Y1 ... Y4)

YxYx

FUNCTION

State0

State1

(1) Center/down-spread, Frequency0/1 and State0/1 are user-definable in the PLLx configuration register.

(2) Frequency0 and Frequency1 can be any frequency within the specified f_VCOrange.

(3) State0/1 selection is valid for both outputs of the corresponding PLL module and can be power down,

high-impedance state, low, or active

SDA/S1 and SCL/S2 pins of the CDCEL824 are dual-function pins. In the default configuration, they are

predefined as the SDA/SCL serial programming interface. They can be programmed to control pins (S1/S2) by

setting the relevant bits in the EEPROM. Note that the changes of the bits in the control register (bit [6] of byte

02h) have no effect until they are written into the EEPROM.

Once they are set as control pins, the serial programming interface is no longer available. However, if V_DDOUTis

forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL).

S0 is not a multi-use pin; it is a control pin only.

CDCEL824

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ZHCSEA7A –JUNE 2015–REVISED SEPTEMBER 2015

9.3.2 SDA/SCL Serial Interface

This section describes the SDA/SCL interface of the CDCEL824 device. The CDCEL824 operates as a slave

device of the 2-wire serial SDA/SCL bus, compatible with the popular SMBus or I²C specification. It operates in

the standard-mode transfer (up to 100 kbit/s) and fast-mode transfer (up to 400 kbit/s) and supports 7-bit

addressing.

The SDA/S1 and SCL/S2 pins of the CDCEL824 are dual-function pins. In the default configuration they are used

as SDA/SCL serial programming interface. They can be reprogrammed as general-purpose control pins, S1 and

S2, by changing the corresponding EEPROM setting, byte 02h, bit [6].

Bit 7 (MSB)

Bit 6

Bit 0 (LSB)

w(SCLL)

w(SCLH)

SCL

su(START)

h(START)

su(SDA)

h(SDA)

su(STOP)

(BUS)

SDA

Figure 5. Timing Diagram for SDA/SCL Serial Control Interface

9.3.3 SDA/SCL Hardware Interface

Figure 6 shows how the CDCEL824 clock synthesizer is connected to the SDA/SCL serial interface bus. Multiple

devices can be connected to the bus, but the speed may need to be reduced (400 kHz is the maximum) if many

devices are connected.

Note that the pullup resistors (R_P) depend on the supply voltage, bus capacitance, and number of connected

devices. The recommended pullup value is 4.7 kΩ. It must meet the minimum sink current of 3 mA at V_OLmax

0.4 V for the output stages (for more details see the SMBus or I²C Bus specification).

CDCEL824

Master

SDA

Slave

SCL

BUS

Figure 6. SDA/SCL Hardware Interface

CDCEL824

ZHCSEA7A –JUNE 2015–REVISED SEPTEMBER 2015

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9.4 Device Functional Modes

9.4.1 Default Device Setting

The internal EEPROM of CDCEL824 is preconfigured as shown in Figure 7. The input frequency is passed

through the output as a default. This allows the device to operate in default mode without the extra production

step of programming it. The default setting appears after power is supplied or after a power-down/up sequence

until it is reprogrammed by the user to a different application configuration. A new register setting is programmed

via the serial SDA/SCL interface.

DDOUT

GND

Xin

27-MHz

Crystal

Xtal

CMOS

Y1 = 27 MHz

Y2 = 27 MHz

PLL1

Power Down

Pdiv2 = 1

Pdiv3 = 1

Xout

CMOS

PLL Bypass

EEPROM

1 = Outputs Enabled

Programming

and

SDA/SCL

0 = Outputs Disabled

(High-Impedance)

SDA

SCL

CMOS

Y3 = 27 MHz

PLL2

Programming Bus

Pdiv4 = 1

Pdiv5 = 1

Power Down

CMOS

Y4 = 27 MHz

PLL Bypass

Figure 7. Preconfiguration of CDCEL824 Internal EEPROM

Table 3 shows the factory default setting for the control terminal register (external control pins). Note that even

though eight different register settings are possible, in default configuration, only the first two settings (0 and 1)

can be selected with S0, as S1 and S2 are configured as programming pins in the default mode.

Table 3. Factory Default Settings for Control Terminal Register⁽¹⁾

PLL1 SETTINGS

PLL2 SETTINGS

FREQUENCY

SELECTION

OUTPUT

SELECTION

FREQUENCY

SELECTION

OUTPUT

SELECTION

EXTERNAL CONTROL PINS

FS1

Y1Y2

FS2

Y2Y3

High-impedance

state

High-impedance

state

SDA (I²C)

SCL (I2C)

f_{VCO1_0}

f_{VCO2_0}

Enabled

(1) S1 is SDA and S2 is SCL in default mode or when programmed (SPICON bit 6 of register 2 set to 0). They do not have any control-pin

function but they are internally interpreted as if S1 = 0 and S2 = 0. S0, however, is a control pin which in the default mode switches all

outputs ON or OFF (as previously predefined).

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9.5 Programming

9.5.1 Data Protocol

The device supports Byte Write and Byte Read and Block Write and Block Read operations.

For Byte Write/Read operations, the system controller can individually access addressed bytes.

For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with

most-significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of

bytes read out are defined by byte count in the generic configuration register. At the Block Read instruction, all

bytes defined in the byte count must be read out to finish the read cycle correctly.

Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to

each transferred byte regardless of whether this is a Byte Write or a Block Write sequence.

If the EEPROM write cycle is initiated, the internal SDA registers are written into the EEPROM. During this write

cycle, data is not accepted at the SDA/SCL bus until the write cycle is completed. However, data can be read out

during the programming sequence (Byte Read or Block Read). The programming status can be monitored by

EEPIP, byte 01h–bit 6.

The offset of the indexed byte is encoded in the command code, as described in Table 4.

Table 4. Slave Receiver Address (7 Bits)

DEVICE

A1⁽¹⁾

A0⁽¹⁾

R/W

1/0

CDCEL824

(1) Address bits A0 and A1 are programmable via the SDA/SCL bus (byte 01, bit [1:0]. This allows addressing up to four devices connected

to the same SDA/SCL bus. The least-significant bit of the address byte designates a write or read operation.

9.5.2 Command Code Definition

Table 5. Command Code Definition

BIT

DESCRIPTION

0 = Block Read or Block Write operation

1 = Byte Read or Byte Write operation

(6:0)

Byte offset for Byte Read, Block Read, Byte Write and Block Write operations.

9.5.3 Generic Programming Sequence

Slave Address

Data Byte

R/W

MSB

LSB

MSB

LSB

Start Condition

Sr Repeated Start Condition

1 = Read (Rd) From CDCE9xx Device; 0 = Write (Wr) to CDCE9xxx

Acknowledge (ACK = 0 and NACK =1)

Stop Condition

R/W

Master-to-Slave Transmission

Slave-to-Master Transmission

Figure 8. Generic Programming Sequence

9.5.4 Byte Write Programming Sequence

Slave Address

CommandCode

Data Byte

Figure 9. Byte Write Protocol

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9.5.5 Byte Read Programming Sequence

Slave Address

CommandCode

Slave Address

Data Byte

Figure 10. Byte Read Protocol

9.5.6 Block Write Programming Sequence

Slave Address

CommandCode

Byte Count = N

Data Byte 0

Data Byte 1

…

Data Byte N-1

(1) Data byte 0 bits [7:0] is reserved for Revision Code and Vendor Identification. Also, it is used for internal test purpose

and should not be overwritten.

Figure 11. Block Write Protocol

9.5.7 Block Read Programming Sequence

Slave Address

CommandCode

Slave Address

Byte Count N

Data Byte 0

…

Data Byte N-1

Figure 12. Block Read Protocol

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9.6 Register Maps

9.6.1 SDA/SCL Configuration Registers

The clock input, control pins, PLLs, and output stages are user configurable. The following tables and

explanations describe the programmable functions of the CDCEL824. All settings can be manually written into

the device via the SDA/SCL bus or easily programmed by using the TI Pro-Clock™ software.

Table 6. SDA/SCL Registers

ADDRESS OFFSET

Generic configuration register

PLL1 configuration register

PLL2 configuration register

TABLE

Table 8

Table 9

Table 10

00h

10h

20h

The grey-highlighted bits, described in the Configuration Registers tables in the following pages, belong to the

Control Terminal Register. The user can predefine up to eight different control settings. These settings then can

be selected by the external control pins, S0, S1, and S2. Table 7 explains the corresponding bit assignment

between the Control Terminal Register and the Configuration Registers.

Table 7. Configuration Register, External Control Terminals

PLL1 SETTINGS

PLL2 SETTINGS

FREQUENCY

OUTPUT

SELECTION

FREQUENCY

OUTPUT

SELECTION

EXTERNAL CONTROL PINS

SELECTION

FS1

SELECTION

FS2

Y1Y2

Y3Y4

Y3Y4_0

Y3Y4_1

Y3Y4_2

Reserved

Y3Y4_5

Y3Y4_6

Y3Y4_7

25h

FS1_0

FS1_1

FS1_2

FS1_3

FS1_4

FS1_5

FS1_6

FS1_7

13h

Y1Y2_0

Y1Y2_1

Y1Y2_2

Y1Y2_3

Y1Y2_4

Y1Y2_5

Y1Y2_6

Y1Y2_7

15h

FS2_0

FS2_1

FS2_2

FS2_3Reserved

FS2_4Reserved

FS2_5

FS2_6

FS2_7

Address offset⁽¹⁾

23h

(1) Address offset refers to the byte address in the configuration register in Table 8, Table 9, and Table 10.

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Table 8. Generic Configuration Register

OFFSET⁽¹⁾

BIT⁽²⁾

ACRONYM

DEFAULT⁽³⁾

DESCRIPTION

E_EL

RID

VID

–

Device identification (read-only): 0 is CDCEL824 (1.8 V out)

Revision identification number (read-only)

Vendor identification number (read-only)

Reserved – always write 0

00h

6:4

3:0

EEPROM programming Status4:⁽⁴⁾(read-only)

0 – EEPROM programming is completed

1 – EEPROM is in programming mode

EEPIP

Permanently lock EEPROM data⁽⁵⁾

0 – EEPROM is not locked

1 – EEPROM is permanently locked

EELOCK

01h

Device power down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)

Note: PWDN cannot be set to 1 in the EEPROM.

0 – Device active (all PLLs and all outputs are enabled)

PWDN

1 – Device power down (all PLLs in power down and all outputs in high-impedance state)

3:2

1:0

INCLK

SLAVE_ADR

00b

Input clock selection:

00 – Xtal 01 – VCXO

10 – LVCMOS 1 – Reserved

Address bits A0 and A1 of the slave receiver address

RSVD

0 – Input clock

1 – PLL1 clock

Operation mode selection for pins 14/15⁽⁶⁾

SPICON

0 – Serial programming interface SDA (pin 15) and SCL (pin 14)

1 – Control pins S1 (pin 15) and S2 (pin 14)

02h

03h

5:4

3:2

1:0

7:0

RSVD

01b

RSVD

Reserved

RSVD

001h

RSVD

Reserved

04h

RSVD

Reserved

(1) Writing data beyond 30h may affect device function.

(2) All data transferred with the MSB first

(3) Unless customer-specific setting

(4) During EEPROM programming, no data is allowed to be sent to the device via the SDA/SCL bus until the programming sequence is completed. Data, however, can be read out during the

programming sequence (Byte Read or Block Read).

(5) If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. No further programming is possible. Data, however can still be written via the SDA/SCL bus

to the internal register to change device function on the fly. But new data can no longer be saved to the EEPROM. EELOCK is effective only if written into the EEPROM.

(6) Selection of control pins is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are no longer available. However, if V_DDOUTis forced to

GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL), and the two slave receiver address bits are reset to A0 = 0 and A1 = 0.

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Table 8. Generic Configuration Register (continued)

OFFSET⁽¹⁾

BIT⁽²⁾

ACRONYM

DEFAULT⁽³⁾

DESCRIPTION

05h

Crystal load-capacitor selection⁽⁷⁾

00h – 0 pF

01h – 1 pF

02h – 2 pF

7:3

XCSEL

0Ah

14h to 1Fh – 20 pF

2:0

7:1

Reserved – do not write other than 0.

06h

7-bit byte count (defines the number of bytes which will be sent from this device at the next Block Read transfer); all bytes must be read out to correctly finish the read

cycle.

BCOUNT

30h

0 – No EEPROM write cycle

Initiate EEPROM write cycle⁽⁸⁾

EEWRITE

—

1 – Start EEPROM write cycle (internal registers are saved to the EEPROM)

07h-0Fh

Reserved – do not write other than 0

(7) The internal load capacitor (C1, C2) must be used to achieve the best clock performance. External capacitors should be used only to finely adjust C_Lby a few picofarads. The value of C_L

can be programmed with a resolution of 1 pF for a crystal load range of 0 pF to 20 pF. For CL > 20 pF, use additional external capacitors. Also, the value of the device input capacitance

has to be considered which always adds 1.5 pF (6 pF/2 pF) to the selected C_L. For more information about VCXO configuration and crystal recommendation, see application report

SCAA085.

(8) Note: The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The EEWRITE cycle is initiated with the rising edge of

the EEWRITE bit. A static level-high does not trigger an EEPROM WRITE cycle. The EEWRITE bit must be reset to low after the programming is completed. The programming status can

be monitored by reading out EEPIP. If EELOCK is set to high, no EEPROM programming is possible.

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Table 9. PLL1 Configuration Register

OFFSET⁽¹⁾

10h

BIT⁽²⁾

ACRONYM

Reserved

FS1_7

DEFAULT⁽³⁾

DESCRIPTION

7:0

00000000b

Reserved

11h

00000000b

Reserved

12h

00000000b

Reserved

FS1_x: PLL1 frequency selection⁽⁴⁾

FS1_6

0 – f_{VCO1_0}(predefined by PLL1_0 – multiplier/divider value)

1 – f_{VCO1_1}(predefined by PLL1_1 – multiplier/divider value)

FS1_5

FS1_4

13h

FS1_3

FS1_2

FS1_1

FS1_0

0 – PLL1

MUX1

PLL1 multiplexer:

1 – PLL1 bypass (PLL1 is in power down)

0 – bypass

1 – Pdiv2

Output Y1 multiplexer:

Output Y2 multiplexer:

00 – bypass

01 – Pdiv2-divider

10 – Pdiv3-divider

11 – Reserved

14h

5:4

10b

3:2

1:0

Y1Y2_ST1

Y1Y2_ST0

11b

01b

00 – Y1/Y2 disabled to high-impedance state (PLL1 is in power down)

01 – Y1/Y2 disabled to high-impedance state (PLL1 on)

10 – Y1/Y2 disabled to low (PLL1 on)

Y1, Y2-state0/1definition:

11 – Y1/Y2 enabled (normal operation, PLL1 on)

(1) Writing data beyond 30h may adversely affect device function.

(2) All data is transferred MSB-first.

(3) Unless a custom setting is used

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Table 9. PLL1 Configuration Register (continued)

BIT⁽²⁾

ACRONYM

Y1Y2_7

Y1Y2_6

Y1Y2_5

Y1Y2_4

Y1Y2_3

Y1Y2_2

Y1Y2_1

Y1Y2_0

Reserved

DEFAULT⁽³⁾

DESCRIPTION

Y1Y2_x output state selection⁽⁴⁾

0 – state0 (predefined by Y1Y2_ST0)

1 – state1 (predefined by Y1Y2_ST1)

15h

RSVD Reserved

16h

17h

7-bit Y1-output-divider Pdiv2:

0 – Reset and in standby

1 to 127 – Divider value

6:0

Pdiv2

—

01h

Reserved – do not write others than 0

7-bit Y2-output-divider Pdiv3:

0 – Reset and in standby

1 to 127 – Divider value

6:0

Pdiv3

01h

18h

19h

7:0

7:4

3:0

7:3

2:0

7:5

4:2

PLL1_0N [11:4

PLL1_0N [3:0]

PLL1_0R [8:5]

PLL1_0R[4:0]

PLL1_0Q [5:3]

PLL1_0Q [2:0]

PLL1_0P [2:0]

004h

000h

PLL1_0⁽⁴⁾: 30-bit multiplier/divider value for frequency f_{VCO1_0}

(for more information, see the PLL Multiplier/Divider Definition paragraph).

1Ah

10h

010b

1Bh

00 – f_{VCO1_0}< 125 MHz

01 – 125 MHz ≤ f_{VCO1_0}< 150 MHz

10 – 150 MHz ≤ f_{VCO1_0}< 175 MHz

11 – f_{VCO1_0}≥ 175 MHz

1:0

VCO1_0_RANGE

00b

f_{VCO1_0}range selection:

1Ch

1Dh

7:0

7:4

3:0

7:3

2:0

7:5

4:2

PLL1_1N [11:4]

PLL1_1N [3:0]

PLL1_1R [8:5]

PLL1_1R[4:0]

PLL1_1Q [5:3]

PLL1_1Q [2:0]

PLL1_1P [2:0]

PLL1_1⁽⁴⁾: 30-bit multiplier/divider value for frequency f_{VCO1_1}

(for more information see the PLL Multiplier/Divider Definition paragraph)

004h

000h

1Eh

10h

010b

1Fh

00 – f_{VCO1_1}< 125 MHz

01 – 125 MHz ≤ f_{VCO1_1}< 150 MHz

10 – 150 MHz ≤ f_{VCO1_1}< 175 MHz

11 – f_{VCO1_1}≥ 175 MHz

1:0

VCO1_1_RANGE

00b

f_{VCO1_1}range selection:

(4) PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096

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Table 10. PLL2 Configuration Register

OFFSET⁽¹⁾

20h

BIT⁽²⁾

ACRONYM

Reserved

FS2_7

DEFAULT⁽³⁾

DESCRIPTION

7:0

0000000b

Reserved

21h

0000000b

Reserved

22h

0000000b

Reserved

FS2_x: PLL2 frequency selection⁽⁴⁾

23h

FS2_6

0 – f_{VCO2_0}(predefined by PLL2_0 – multiplier/divider value)

1 – f_{VCO2_1}(predefined by PLL2_1 – multiplier/divider value)

FS2_5

FS2_4

FS2_3

FS2_2

FS2_1

FS2_0

24h

PLL2 multiplexer:

0 – PLL2

MUX2

1 – PLL2 bypass (PLL2 is in power down)

Output Y3 multiplexer:

Output Y4 multiplexer:

0 – Pdiv2

1 – Pdiv4

00 – Pdiv2-divider

01 – Pdiv4-divider

10 – Pdiv5-divider

11 – Reserved

5:4

10b

3:2

1:0

Y3Y4_ST1

Y3Y4_ST0

11b

01b

Y3, Y4-State0/1definition:

00 – Y3/Y4 disabled to high-impedance state (PLL2 is in power down)

01 – Y3/Y4 disabled to high-impedance state (PLL2 on)

10–Y3/Y4 disabled to low (PLL2 on)

11 – Y3/Y4 enabled (normal operation, PLL2 on)

(1) Writing data beyond 30h may adversely affect device function.

(2) All data is transferred MSB-first.

(3) Unless a custom setting is used

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Table 10. PLL2 Configuration Register (continued)

OFFSET⁽¹⁾

BIT⁽²⁾

ACRONYM

Y3Y4_7

Y3Y4_6

Y3Y4_5

Y3Y4_4

Y3Y4_3

Y3Y4_2

Y3Y4_1

Y3Y4_0

DEFAULT⁽³⁾

DESCRIPTION

Y3Y4_x output state selection⁽⁴⁾

0 – state0 (predefined by Y3Y4_ST0)

25h

1 – state1 (predefined by Y3Y4_ST1)

26h

27h

Reserved

0 – Down

1 – Center

Reserved

7-Bit Y3-output-divider Pdiv4:

0 – Reset and in standby

1 to 127 – Divider value

6:0

Pdiv4

—

01h

Reserved – do not write others than 0

7-bit Y4-output-divider Pdiv5:

0 – Reset and in standby

1 to 127 – Divider value

6:0

Pdiv5

01h

28h

29h

7:0

7:4

3:0

7:3

2:0

7:5

4:2

PLL2_0N [11:4

PLL2_0N [3:0]

PLL2_0R [8:5]

PLL2_0R[4:0]

PLL2_0Q [5:3]

PLL2_0Q [2:0]

PLL2_0P [2:0]

PLL2_0⁽⁴⁾: 30-Bit Multiplier/Divider value for frequency f_{VCO2_0}

(for more information see the PLL Multiplier/Divider Definition paragraph)

004h

000h

2Ah

2Bh

10h

010b

f_{VCO2_0}range selection:

00 – f_{VCO2_0}< 125 MHz

01 – 125 MHz ≤ f_{VCO2_0}< 150 MHz

10 – 150 MHz ≤ f_{VCO2_0}< 175 MHz

11 – f_{VCO2_0}≥ 175 MHz

1:0

VCO2_0_RANGE

00b

2Ch

2Dh

7:0

7:4

3:0

7:3

2:0

7:5

4:2

PLL2_1N [11:4]

PLL2_1N [3:0]

PLL2_1R [8:5]

PLL2_1R[4:0]

PLL2_1Q [5:3]

PLL2_1Q [2:0]

PLL2_1P [2:0]

PLL2_1⁽⁴⁾: 30-bit multiplier/divider value for frequency f_{VCO2_1}

(for more information see the PLL Multiplier/Divider Definition paragraph)

004h

000h

2Eh

2Fh

10h

010b

f_{VCO2_1}range selection:

00 – f_{VCO2_1}< 125 MHz

01 – 125 MHz ≤ f_{VCO2_1}< 150 MHz

10 – 150 MHz ≤ f_{VCO2_1}< 175 MHz

11 – f_{VCO2_1}≥ 175 MHz

1:0

VCO2_1_RANGE

00b

(4) PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

CDCEL824 is an easy to use low-cost, programmable CMOS clock synthesizer. it can be used as a crystal

buffer, clock synthesizer with separate output supply pin. CDCEL824 features on-chip loop filter. Programming

can be done through SPI, pin-mode, or using on-chip EEPROM. This section shows some examples of using

CDCEL824 in various applications.

10.2 Typical Application

CDCEL824 is ideal clock generator for medium-range phase-shift laser distance meter. Having two separate

PLLs allows for achieving as low intermediate frequency as required as well as high maximum modulation

frequency, hence increasing the accuracy of the measurement device. Moreover, a fast settling PLL supports

faster switching between multiple modulation frequencies required by a single measurement. this results in

higher measurement rates for the device. Low power consumption and low cost position CDCEL824 as an ideal

device for commercial laser distance metering equipment.

Figure 13 shows a typical application concept for the CDCEL824, where the outputs of the PLL1, Y1 and Y2 are

used to generate the modulation and the counter frequency respectively. Y3 coming out of the PLL2 is carrying

the shifted modulation frequency for down mixing. all three frequencies are programmable and dynamically

switchable.

Example:

f_{0 :}modulation freq. 200 MHz

f_{I :}intermediate freq. 10 kHz

f_{C :}counter frequency. 2 MHz

Laser

Diode

APD

Mixer

f_I

f₀

CDCEL824

f₀-f_I

Digital

Processor

f_I

f_C

Figure 13. Heterodyne Phase-Shift Laser Distance Meter Concept

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Typical Application (continued)

10.2.1 Design Requirements

For Laser distance meter applications, if heterodyne technique is used as mentioned in Typical Application , it is

shown that:

R =

2 f

Maximum Measurement Range equals:

(1)

(2)

Dd =

And best error achievable in measurement:

That means lower RF frequency allows for longer range, while lower ratio ^o( higher RF frequency and lower IF

frequency) gives lower error.

The values of intermediate, RF, and counter frequency should be chosen according to design targets of the

maximum range and maximum tolerable error. Typically multiple consecutive measurements with multiple RF

frequencies are carried on to resolve the trade-off between the accuracy and the maximum range.

10.2.2 Detailed Design Procedure

10.2.2.1 PLL Multiplier/Divider Definition

At a given input frequency (ƒ_IN), the output frequency (ƒ_OUT) of the CDCEL824 can be calculated:

OUT

Pdiv

where

•

M (1 to 511) and N (1 to 4095) are the multiplier/divide values of the PLL

Pdiv (1 to 127) is the output divider.

(3)

(4)

The target VCO frequency (ƒ_VCO) of each PLL can be calculated:

+ ƒ

VCO

The PLL internally operates as fractional divider and needs the following multiplier/divider settings:

NȀ

ǒ_logǓ_{[if P t 0 then P + 0]}

ǒ Ǔ

²M

NP = 4 – int

Q = int

R = N′ – M × Q

where

N′ = N × 2^P

N ≥ M

80 MHz ≤ ƒ_VCO≤ 200 MHz

16 ≤ q ≤ 63

0 ≤ p ≤ 4

0 ≤ r ≤ 511

Example:

for ƒ_IN= 27 MHz; M = 1; N = 4; Pdiv = 2;

→ f_OUT= 54 MHz

for ƒ_IN= 27 MHz; M = 2; N = 11; Pdiv = 2;

→ f_OUT= 74.25 MHz

→ f_VCO= 108 MHz

→ f_VCO= 148.50 MHz

→ P = 4 – int(log₂4) = 4 – 2 = 2

→ N′’ = 4 × 2²= 16

→ P = 4 – int(log₂5.5) = 4 – 2 = 2

→ N′’ = 11 × 2²= 44

→ Q = int(16) = 16

→ Q = int(22) = 22

→ R = 16 – 16 = 0

→ R = 44 – 44 = 0

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Typical Application (continued)

The values for P, Q, R, and N’ are automatically calculated when using TI Pro-Clock™ software.

10.2.3 Application Curves

1.625 MHz to 3.25 MHz

1.5 MHz to 2.5 MHz

Figure 15. Phase Noise and RMS Jitter

Figure 14. Phase Noise and RMS Jitter

11 Power Supply Recommendations

There is no restriction on the power-up sequence. In case VDDOUT is applied first, it is recommended to ground

VDD. In case VDDOUT is powered while VDD is floating, there is a risk of high current flowing on the VDDOUT.

The device has a power-up control that is connected to the 1.8-V supply. This keeps the whole device disabled

until the 1.8-V supply reaches a sufficient voltage level. Then the device switches on all internal components,

including the outputs. If there is a VDDOUT available before the V_DDsupply, the outputs will stay disabled until

the VDD supply has reached a certain level.

12 Layout

12.1 Layout Guidelines

When the CDCEL824 is used as a crystal buffer, any parasitics across the crystal affects the pulling range of the

VCXO. Therefore, care must be taken in placing the crystal units on the board. Crystals should be placed as

close to the device as possible, ensuring that the routing lines from the crystal terminals to X_INand X_OUThave the

same length.

If possible, cut out both ground plane and power plane under the area where the crystal and the routing to the

device are placed. In this area, always avoid routing any other signal line, as it could be a source of noise

coupling.

Additional discrete capacitors can be required to meet the load capacitance specification of certain crystal. For

example, a 10.7-pF load capacitor is not fully programmable on the chip, because the internal capacitor can

range from 0 pF to 20 pF with steps of 1 pF. The 0.7-pF capacitor therefore can be discretely added on top of an

internal 10 pF.

To minimize the inductive influence of the trace, it is recommended to place this small capacitor as close to the

device as possible and symmetrically with respect to XIN and XOUT.

Figure 16 shows a conceptual layout detailing recommended placement of power supply bypass capacitors. For

component side mounting, use 0402 body size capacitors to facilitate signal routing. Keep the connections

between the bypass capacitors and the power supply on the device as short as possible. Ground the other side

of the capacitor using a low-impedance connection to the ground plane.

CDCEL824

www.ti.com.cn

ZHCSEA7A –JUNE 2015–REVISED SEPTEMBER 2015

12.2 Layout Example

Figure 16. Board Layout

CDCEL824

ZHCSEA7A –JUNE 2015–REVISED SEPTEMBER 2015

www.ti.com.cn

13 器件和文档支持

13.1 文档支持

13.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

13.3 商标

Pro-Clock, E2E are trademarks of Texas Instruments.

13.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

13.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不

对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

CDCEL824PWR

ACTIVE

TSSOP

2000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 85

CKEL824

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Feb-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CDCEL824PWR

TSSOP

2000

330.0

12.4

6.9

5.6

1.6

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Feb-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TSSOP PW 16

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

CDCEL824PWR

2000

Pack Materials-Page 2

PACKAGE OUTLINE

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SEATING

PLANE

6.6

6.2

TYP

0.1 C

PIN 1 INDEX AREA

14X 0.65

5.1

4.9

4.55

NOTE 3

0.30

16X

4.5

4.3

NOTE 4

1.2 MAX

0.19

0.1

C A B

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

0 -8

DETAIL A

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

www.ti.com

EXAMPLE BOARD LAYOUT

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SYMM

16X (1.5)

(R0.05) TYP

16X (0.45)

SYMM

14X (0.65)

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4220204/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

16X (1.5)

SYMM

(R0.05) TYP

16X (0.45)

SYMM

14X (0.65)

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

4220204/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

CDCEL824PWR [TI]

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