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CDCE913-Q1, CDCEL913-Q1

SCAS918C –JUNE 2013–REVISED NOVEMBER 2016

CDCEx913-Q1 Programmable 1-PLL VCXO Clock Synthesizer

With 1.8-V, 2.5-V, and 3.3-V Outputs

1 Features

2 Applications

1

•

Qualified for Automotive Applications

•

Clusters

AEC-Q100 Qualified With the Following Results:

Head Units

Navigation Systems

–

Device Temperature Grades

Advanced Driver Assistance Systems (ADAS)

–

Grade 1 For CDCE913-Q1: –40°C to

+125°C Ambient Operating Temperature

3 Description

The CDCE913-Q1 and CDCEL913-Q1 devices are

–

Grade 3 For CDCEL913-Q1: –40°C to

+85°C Ambient Operating Temperature

modular,

phase-locked

loop

(PLL)

based

–

Device HBM ESD Classification Level H2

Device CDM ESD Classification Level C6

programmable clock synthesizers. These devices

provide flexible and programmable options, such as

output clocks, input signals, and control pins, so that

the user can configure the CDCEx913-Q1 for their

own specifications.

•

In-System Programmability and EEPROM

–

Serial Programmable Volatile Register

Nonvolatile EEPROM to Store Customer

Settings

The CDCEx913-Q1 generates up to three output

clocks from a single input frequency to enable both

board space and cost savings. Additionally, with

multiple outputs, the clock generator can replace

multiple crystals with one clock generator. This

makes the device well-suited for head unit and

telematics applications in infotainment and camera

systems in ADAS as these platforms are evolving into

smaller and more cost effective systems.

Flexible Input Clocking Concept

–

External Crystal: 8 MHz to 32 MHz

On-Chip VCXO: Pull Range ±150 ppm

Single-Ended LVCMOS up to 160 MHz

•

Free Selectable Output Frequency up to 230 MHz

Low-Noise PLL Core

–

PLL Loop Filter Components Integrated

Low Period Jitter (Typical 50 ps)

Device Information⁽¹⁾

PART NUMBER

CDCE913-Q1

PACKAGE

BODY SIZE (NOM)

•

Separate Output Supply Pins

TSSOP (14)

5.00 mm × 4.40 mm

–

CDCE913-Q1: 3.3 V and 2.5 V

CDCEL913-Q1: 1.8 V

CDCEL913-Q1

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Flexible Clock Driver

–

Three User-Definable Control Inputs [S0, S1,

S2], for Example, SSC Selection, Frequency

Switching, Output Enable, or Power Down

Simplified Schematic

Digital Radio

Interface

Generates Highly Accurate Clocks for Video,

Audio, USB, IEEE1394, RFID, Bluetooth^®,

WLAN, Ethernet, and GPS

Codec

Generates Common Clock Frequencies Used

With TI-DaVinci™, OMAP™, DSPs

CDCE913-Q1

–

Programmable SSC Modulation

Enables 0-PPM Clock Generation

Graphics

Processor

25 MHZ

XTAL

•

1.8-V Device Power Supply

Packaged in TSSOP

Development and Programming Kit for Easy PLL

Design and Programming (TI Pro-Clock™)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

CDCE913-Q1, CDCEL913-Q1

SCAS918C –JUNE 2013–REVISED NOVEMBER 2016

www.ti.com

Table of Contents

10.4 Device Functional Modes...................................... 15

10.5 Programming......................................................... 16

10.6 Register Maps....................................................... 17

11 Application and Implementation........................ 21

11.1 Application Information.......................................... 21

11.2 Typical Application ............................................... 21

12 Power Supply Recommendations ..................... 26

13 Layout................................................................... 27

13.1 Layout Guidelines ................................................. 27

13.2 Layout Example .................................................... 27

14 Device and Documentation Support ................. 28

14.1 Documentation Support ........................................ 28

14.2 Related Links ........................................................ 28

14.3 Receiving Notification of Documentation Updates 28

14.4 Community Resources.......................................... 28

14.5 Trademarks........................................................... 28

14.6 Electrostatic Discharge Caution............................ 28

14.7 Glossary................................................................ 29

1

2

3

4

5

6

7

8

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Description (Continued)........................................ 4

Device Comparison Table..................................... 4

Pin Configuration and Functions......................... 5

Specifications......................................................... 6

8.1 Absolute Maximum Ratings ...................................... 6

8.2 ESD Ratings.............................................................. 6

8.3 Recommended Operating Conditions....................... 6

8.4 Thermal Information.................................................. 7

8.5 Electrical Characteristics .......................................... 7

8.6 Timing Requirements................................................ 9

8.7 Typical Characteristics............................................ 10

Parameter Measurement Information ................ 11

9

10 Detailed Description ........................................... 12

10.1 Overview ............................................................... 12

10.2 Functional Block Diagram ..................................... 12

10.3 Feature Description............................................... 13

15 Mechanical, Packaging, and Orderable

Information ........................................................... 30

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (September 2016) to Revision C

Page

•

Clarified different temperature range for the CDCEL913-Q1 device...................................................................................... 1

Deleted old table notes from the Thermal Information table ................................................................................................. 7

Changes from Revision A (June 2013) to Revision B

Page

•

Added Feature Description section, Device Functional Modes, Application and Implementation section, Power

Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,

Packaging, and Orderable Information section ...................................................................................................................... 1

•

Changed ESD Ratings: Human-body model (HBM) from 2500 V to 2000 V and Charged-device model (CDM) from

500 V to 1000 V...................................................................................................................................................................... 6

Changed second S to Sr in Byte Read Protocol .................................................................................................................. 16

Changes from Original (June 2013) to Revision A

Page

•

Changed CDM ESD classification level.................................................................................................................................. 1

Added ESD ratings ................................................................................................................................................................. 6

Changed I_DDPDtypical From: 20 To: 30 .................................................................................................................................. 7

Changed I_ILVCMOS input current value from typical to maximum ....................................................................................... 7

Changed I_IHLVCMOS input current for S0, S1, and S2 value from typical to maximum....................................................... 7

Changed I_ILLVCMOS input current for S0, S1, and S2 value from typical to maximum....................................................... 7

Changed Test Load for 50-Ω Board Environment................................................................................................................ 11

Changed Output Selection From: (Y2, Y9) To: (Y2, Y3)...................................................................................................... 13

Changed text note for Block Write Protocol ......................................................................................................................... 17

Changed 01h, Bit 7 From: For internal use – always write 1 To: Reserved – always write 0.............................................. 18

2

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SCAS918C –JUNE 2013–REVISED NOVEMBER 2016

•

Changed 06h, 7:1 From: 30h To: 20h .................................................................................................................................. 19

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SCAS918C –JUNE 2013–REVISED NOVEMBER 2016

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5 Description (Continued)

Furthermore, each output can be programmed in-system for any clock frequency up to 230 MHz through the

integrated, configurable PLL. The PLL also supports spread-spectrum clocking (SSC) with programmable down

and center spread. This provides better electromagnetic interference (EMI) performance to enable customers to

pass industry standards such as CISPR-25.

Customization of frequency programming and SSC are accessed using three, user-defined control pins. This

eliminates the need to use an additional interface to control the clock. Specific power-up and power-down

sequences can also be defined to the user’s needs.

6 Device Comparison Table

DEVICE

SUPPLY (V)

2.5 to 3.3

1.8

PLL

1

OUTPUT

CDCE913-Q1

CDCEL913-Q1

CDCE937-Q1

CDCEL937-Q1

CDCE949-Q1

CDCEL949-Q1

3

7

9

1

2.5 to 3.3

1.8

3

2.5 to 3.3

1.8

4

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SCAS918C –JUNE 2013–REVISED NOVEMBER 2016

7 Pin Configuration and Functions

PW Package

14-Pin TSSOP

Top View

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

GND

5, 10

G

I

Ground

SCL: serial clock input LVCMOS (default configuration), 500 kΩ internal pullup; or

S2: user-programmable control input, LVCMOS input, 500-kΩ internal pullup

SCL/S2

SDA/S1

12

13

SDA: bidirectional serial data input/output (default configuration), LVCMOS internal pullup; or

S1: user-programmable control input, LVCMOS input, 500-kΩ internal pullup

I/O or I

S0

2

4

3

I

User-programmable control input S0, LVCMOS input, 500-kΩ internal pullup

VCXO control voltage (leave open or pull up when not used)

1.8-V power supply for the device

V_ctr

V_DD

P

CDCE913-Q1: 3.3-V or 2.5-V supply for all outputs

CDCEL913-Q1: 1.8-V supply for all outputs

Crystal oscillator input or LVCMOS clock input (selectable through the I²C bus)

Crystal oscillator output (leave open or pull up when not used)

LVCMOS output

V_DDOUT

6, 7

P

Xin/CLK

Xout

Y1

1

14

11

9

I

O

Y2

LVCMOS output

Y3

8

LVCMOS output

(1) G = Ground, I = Input, O = Output, P = Power

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Product Folder Links: CDCE913-Q1 CDCEL913-Q1

CDCE913-Q1, CDCEL913-Q1

SCAS918C –JUNE 2013–REVISED NOVEMBER 2016

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8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

MAX

2.5

UNIT

V_DD

Supply voltage

V

CDCEL913-Q1

CDCE913-Q1

V_DD

V_DDOUT

Output clocks supply voltage

V

3.6 + 0.5

V_DD+ 0.5

V_DDOUT+ 0.5

20

V_I

Input voltage⁽²⁾⁽³⁾

Output voltage⁽²⁾

V

V_O

I_I

Input current (V_I< 0, V_I> V_DD

)

mA

I_O

Continuous output current

50

T_J

T_stg

Maximum junction temperature

Storage temperature

125

°C

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3) SDA and SCL can go up to 3.6 V as stated in the Recommended Operating Conditions table.

8.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) Charged-device model ESD rating for corner pins is 750 V.

8.3 Recommended Operating Conditions

MIN

1.7

2.3

1.7

NOM

MAX

1.9

UNIT

V_DD

V_O

Device supply voltage

1.8

V

CDCE913-Q1

CDCEL913-Q1

3.6

Output Yx supply voltage, V_DDOUT

V

1.9

V_IL

Low-level input voltage, LVCMOS

High-level input voltage, LVCMOS

Input voltage threshold, LVCMOS

0.3 × V_DD

V

V_IH

0.7 × V_DD

V_I(thresh)

0.5 × V_DD

S0

0

1.9

3.6

V_I(S)

Input voltage

V

S1, S2, SDA, SCL (V_I(thresh)

0.5 V_DD

=

)

V_I(CLK)

Input voltage range CLK

1.9

±12

±10

±8

V_DDOUT= 3.3 V

V_DDOUT= 2.5 V

V_DDOUT= 1.8 V

I_OH, I_OL

Output current

mA

C_L

T_A

Output load, LVCMOS

15

pF

°C

CDCE913-Q1

CDCEL913-Q1

–40

125

85

Operating ambient temperature

6

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SCAS918C –JUNE 2013–REVISED NOVEMBER 2016

Recommended Operating Conditions (continued)

MIN

NOM

27

MAX

UNIT

CRYSTAL AND VCXO SPECIFICATIONS⁽¹⁾

f_Xtal

Crystal input frequency (fundamental mode)

Effective series resistance

Pulling range (0 V ≤ V_ctr≤ 1.8 V)⁽²⁾

8

32

MHz

Ω

ESR

f_PR

100

±120

0

±150

ppm

V

V_ctr

Frequency control voltage

V_DD

220

20

C₀/ C₁

C_L

Pullability ratio

On-chip load capacitance at Xin and Xout

0

pF

(1) For more information about VCXO configuration, and crystal recommendation, see VCXO Application Guideline for CDCE(L)9xx Family

(SCAA085).

(2) Pulling range depends on crystal type, on-chip crystal load capacitance, and PCB stray capacitance; pulling range of minimum ±120

ppm applies for crystal listed in VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).

8.4 Thermal Information

CDCE913-Q1,

CDCEL913-Q1

THERMAL METRIC⁽¹⁾⁽²⁾

UNIT

PW (TSSOP)

14 PINS

110.6

35.4

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

53.6

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

2.1

ψ_JB

52.8

R_θJC(bot)

—

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

(2) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-K board).

8.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX UNIT

OVERALL PARAMETER

All outputs off,

f_CLK= 27 MHz,

f_VCO= 135 MHz,

f_OUT= 27 MHz

All PLLS on

Per PLL

11

9

I_DD

Supply current (see Figure 1)

mA

V_DDOUT= 3.3 V

V_DDOUT= 1.8 V

1.3

0.7

No load, all outputs on,

f_OUT= 27 MHz

I_DD(OUT)

Supply current (see Figure 2 and Figure 3)

mA

µA

Power-down current. Every circuit powered

down except I²C

I_DD(PD)

V_(PUC)

f_VCO

f_IN= 0 MHz, V_DD= 1.9 V

30

Supply voltage V_DDthreshold for power-up

control circuit

0.85

80

1.45

V

VCO frequency range of PLL

230

MHz

V_DDOUT= 3.3 V

V_DDOUT= 1.8 V

f_OUT

LVCMOS output frequency

MHz

LVCMOS PARAMETER

V_IK

I_I

LVCMOS input voltage

V_DD= 1.7 V, I_I= –18 mA

V_I= 0 V or V_DD, V_DD= 1.9 V

V_I= V_DD, V_DD= 1.9 V

–1.2

±5

5

V

LVCMOS input current

µA

I_IH

I_IL

LVCMOS input current for S0, S1, and S2

V_I= 0 V, V_DD= 1.9 V

–4

(1) All typical values are at respective nominal V_DD

.

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SCAS918C –JUNE 2013–REVISED NOVEMBER 2016

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Electrical Characteristics (continued)

over recommended operating free-air temperature range (unless otherwise noted)

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX UNIT

Input capacitance at Xin/CLK

Input capacitance at Xout

V_IClk= 0 V or V_DD

V_IXout= 0 V or V_DD

V_IS= 0 V or V_DD

6

2

3

C_I

pF

Input capacitance at S0, S1, and S2

CDCE913-Q1, LVCMOS PARAMETER FOR V_DDOUT= 3.3-V MODE

V_DDOUT= 3 V, I_OH= –0.1 mA

2.9

2.4

2.2

V_OH

LVCMOS high-level output voltage

V_DDOUT= 3 V, I_OH= –8 mA

V_DDOUT= 3 V, I_OH= –12 mA

V_DDOUT= 3 V, I_OL= 0.1 mA

V_DDOUT= 3 V, I_OL= 8 mA

V_DDOUT= 3 V, I_OL= 12 mA

PLL bypass

V

0.1

V_OL

LVCMOS low-level output voltage

0.5

0.8

V

t_PLH, t_PHL

t_r, t_f

Propagation delay

3.2

0.6

50

ns

ps

Rise and fall time

V_DDOUT= 3.3 V (20%–80%)

1 PLL switching, Y2-to-Y3, 10,000 cycles

1 PLL switching, Y2-to-Y3

f_OUT= 50 MHz, Y1-to-Y3

f_VCO= 100 MHz, Pdiv = 1

t_jit(cc)

Cycle-to-cycle jitter⁽²⁾

Peak-to-peak period jitter⁽²⁾

Output skew (see Table 2)⁽³⁾

200

440

55%

t_jit(per)

t_sk(o)

60

(4)

odc

Output duty cycle

45%

CDCE913-Q1, LVCMOS PARAMETER FOR V_DDOUT= 2.5-V MODE

V_DDOUT= 2.3 V, I_OH= –0.1 mA

2.2

1.7

1.6

V_OH

LVCMOS high-level output voltage

LVCMOS low-level output voltage

V_DDOUT= 2.3 V, I_OH= –6 mA

V_DDOUT= 2.3 V, I_OH= –10 mA

V_DDOUT= 2.3 V, I_OL= 0.1 mA

V_DDOUT= 2.3 V, I_OL= 6 mA

V_DDOUT= 2.3 V, I_OL= 10 mA

PLL bypass

V

0.1

0.5

0.7

V_OL

t_PLH, t_PHL

t_r, t_f

Propagation delay

3.6

0.8

50

ns

ps

Rise and fall time

V_DDOUT= 2.5 V (20%–80%)

1 PLL switching, Y2-to-Y3, 10,000 cycles

1 PLL switching, Y2-to-Y3

f_OUT= 50 MHz, Y1-to-Y3

t_jit(cc)

Cycle-to-cycle jitter⁽²⁾

Peak-to-peak period jitter⁽²⁾

Output skew (see Table 2)⁽³⁾

Output duty cycle⁽⁴⁾

200

440

55%

t_jit(per)

t_sk(o)

60

odc

f_VCO= 100 MHz, Pdiv = 1

45%

CDCEL913-Q1, LVCMOS PARAMETER FOR V_DDOUT= 1.8-V MODE

V_DDOUT= 1.7 V, I_OH= –0.1 mA

1.6

1.4

1.1

V_OH

LVCMOS high-level output voltage

LVCMOS low-level output voltage

V_DDOUT= 1.7 V, I_OH= –4 mA

V_DDOUT= 1.7 V, I_OH= –8 mA

V_DDOUT= 1.7 V, I_OL= 0.1 mA

V_DDOUT= 1.7 V, I_OL= 4 mA

V_DDOUT= 1.7 V, I_OL= 8 mA

PLL bypass

V

0.1

0.3

0.6

V_OL

t_PLH, t_PHL

t_r, t_f

Propagation delay

2.6

0.7

80

ns

ps

Rise and fall time

V_DDOUT= 1.8 V (20%–80%)

1 PLL switching, Y2-to-Y3, 10,000 cycles

1 PLL switching, Y2-to-Y3

f_OUT= 50 MHz, Y1-to-Y3

f_VCO= 100 MHz, Pdiv = 1

t_jit(cc)

Cycle-to-cycle jitter⁽²⁾

Peak-to-peak period jitter⁽²⁾

Output skew (see Table 2)⁽³⁾

Output duty cycle⁽⁴⁾

110

130

50

t_jit(per)

t_sk(o)

100

odc

45%

55%

I²C PARAMETER

V_IK

I_IH

SCL and SDA input clamp voltage

V_DD= 1.7 V, I_I= –18 mA

V_I= V_DD, V_DD= 1.9 V

–1.2

±10

V

µA

V

SCL and SDA input current

I²C input high voltage⁽⁵⁾

V_IH

0.7 × V_DD

(2) Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, f_VCO= 108 MHz, f_OUT= 27 MHz (measured at Y2).

(3) The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider.

(4) odc depends on the output rise and fall time (t_rand t_f); data sampled on the rising edge (t_r)

(5) SDA and SCL pins are 3.3-V tolerant.

8

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SCAS918C –JUNE 2013–REVISED NOVEMBER 2016

Electrical Characteristics (continued)

over recommended operating free-air temperature range (unless otherwise noted)

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX UNIT

I²C input low voltage⁽⁵⁾

V_IL

0.3 × V_DD

V

V_OL

C_I

SDA low-level output voltage

SCL-SDA input capacitance

I_OL= 3 mA, V_DD= 1.7 V

V_I= 0 V or V_DD

0.2 × V_DD

10

3

pF

EEPROM SPECIFICATION

EEcyc

EEret

Programming cycles of EEPROM

Data retention

100

10

1000

cycles

years

8.6 Timing Requirements

over recommended ranges of supply voltage, load, and operating free-air temperature

MIN

NOM

MAX

UNIT

CLK_IN

PLL bypass mode

0

8

160

3

f_CLK

LVCMOS clock input frequency

MHz

ns

PLL mode

t_rand t_f

Rise and fall time, CLK signal (20% to 80%)

Duty cycle of CLK at V_DD/ 2

40%

60%

I²C (SEE Figure 13)

Standard mode

Fast mode

0

100

400

f_SCL

SCL clock frequency

kHz

µs

ns

Standard mode

Fast mode

4.7

0.6

4

t_su(START)START setup time (SCL high before SDA low)

t_h(START)START hold time (SCL low after SDA low)

Standard mode

Fast mode

0.6

4.7

1.3

4

Standard mode

Fast mode

t_w(SCLL)

t_w(SCLH)

t_h(SDA)

SCL low-pulse duration

Standard mode

Fast mode

SCL high-pulse duration

SDA hold time (SDA valid after SCL low)

SDA setup time

0.6

0

Standard mode

Fast mode

3.45

0.9

0

Standard mode

Fast mode

250

100

t_su(SDA)

Standard mode

Fast mode

1000

300

t_r

SCL-SDA input rise time

SCL-SDA input fall time

STOP setup time

ns

µs

t_f

300

Standard mode

Fast mode

4

0.6

4.7

1.3

t_su(STOP)

Standard mode

Fast mode

t_BUS

Bus free time between a STOP and START condition

µs

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8.7 Typical Characteristics

30

16

14

12

10

8

V

= 1.8 V

V

= 1.8 V,

DD

= 3.3 V,

DDOUT

25

20

15

10

5

no load

3 Outputs on

1 PLL on

1 Output on

6

4

all PLL off

2

0

all Outputs off

0

10 30 50 70 90 110 130 150 170 190 210 230

- Output Frequency - MHz

10

60

f

110

160

210

f

- Frequency - MHz

OUT

VCO

Figure 2. CDCE913-Q1 Output Current

vs Output Frequency

Figure 1. CDCEx913-Q1 Supply Current

vs PLL Frequency

4.5

V

= 1.8 V,

DD

4

3.5

3

= 1.8 V,

DDOUT

no load

3 Outputs on

2.5

2

1 Output on

1.5

1

all Outputs off

0.5

0

10 30 50 70 90 110 130 150 170 190 210 230

f

- Output Frequency - MHz

OUT

Figure 3. CDCEL913-Q1 Output Current vs Output Frequency

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9 Parameter Measurement Information

CDCE913-Q1

CDCEL913-Q1

1 kW

LVCMOS

10 pF

1 kW

Figure 4. Test Load

CDCE913-Q1

CDCEL913-Q1

LVCMOS

Series

Termination

Approx. 18 W

Line Impedance

Zo = 50 W

Typical Driver

Impedance

Approx. 32 W

Figure 5. Test Load for 50-Ω Board Environment

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10 Detailed Description

10.1 Overview

The CDCE913-Q1 and CDCEL913-Q1 devices are modular PLL-based, low-cost, high-performance,

programmable clock synthesizers, multipliers, and dividers. They generate up to three output clocks from a single

input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using the

integrated configurable PLL.

The CDCEx913-Q1 device has separate output supply pins, V_DDOUT, with output of 1.8 V for the CDCEL913-Q1

device and 2.5 V to 3.3 V for the CDCE913-Q1 device. Additionally, each device requires a 1.8-V supply applied

to its VDD pin in order for it to operate.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load

capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 pF to 20 pF.

Additionally, a selectable on-chip VCXO allows synchronization of the output frequency to an external control

signal, that is, the PWM signal.

The deep M / N divider ratio allows the generation of zero-ppm audio-video, networking (WLAN, Bluetooth,

Ethernet, GPS) or interface (USB, IEEE1394, memory stick) clocks from, for example, a 27-MHz reference input

frequency.

The PLL supports spread-spectrum clocking (SSC). SSC can be center-spread or down-spread clocking, which

is a common technique to reduce electromagnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop filter components are automatically

adjusted to achieve high stability and optimized jitter transfer characteristics.

The device supports nonvolatile EEPROM programming for easy customization of the device to the application. It

is preset to a factory default configuration (see Default Device Configuration). It can be reprogrammed to a

different application configuration before PCB assembly, or reprogrammed by in-system programming. All device

settings are programmable through the SDA-SCL bus, a 2-wire serial interface.

Three programmable control inputs, S0, S1, and S2, can be used to select different frequencies, change SSC

setting for lowering EMI, or control other features like outputs disable to low, outputs in Hi-Z state, power down,

PLL bypass, and so forth).

The CDCE913-Q1 device operates in a temperature range of –40°C to +125°C and the CDCEL913-Q1 device

operates in a temperature range of –40°C to 85°C.

10.2 Functional Block Diagram

GND

V

DD

V

DDOUT

Input Clock

V

ctr

LV

Pdiv1

10-Bit

Y1

CMOS

Xin/CLK

VCXO

XO

LV

CMOS

Pdiv2

Y2

Y3

PLL 1

LVCMOS

7-Bit

with SSC

Xout

LV

Pdiv3

7-Bit

CMOS

PLL Bypass

EEPROM

Programming

and I2C

Register

S0

S1/SDA

S2/SCL

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10.3 Feature Description

10.3.1 Control Terminal Configuration

The CDCE913-Q1 and CDCEL913-Q1 devices have three user-definable control terminals (S0, S1, and S2),

which allow external control of device settings. They can be programmed to any of the following functions:

•

Spread-spectrum clocking selection → spread type and spread amount selection

Frequency selection → switching between any of two user-defined frequencies

Output state selection → output configuration and power-down control

The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.

Table 1. Control Terminal Definition

EXTERNAL CONTROL

PLL1 SETTING

Y1 SETTING

BITS

PLL frequency

selection

Output Y2 and Y3

selection

Control function

SSC selection

Output Y1 and power-down selection

Table 2. PLLx Setting

(Can Be Selected for Each PLL Individually)⁽¹⁾

SSCx [3 Bits]

SSC SELECTION (CENTER AND DOWN)

CENTER

DOWN

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0% (off)

±0.25%

±0.5%

0% (off)

–0.25%

–0.5%

±0.75%

±1.0%

–0.75%

–1.0%

±1.25%

±1.5%

–1.25%

–1.5%

±2.0%

–2.0%

(1) Center and down-spread, Frequency0, Frequency1, State0, and State1 are user-definable in PLLx

configuration register.

Table 3. PLLx Setting, Frequency Selection (Can Be

Selected for Each PLL Individually)⁽¹⁾

FSx

0

FUNCTION

Frequency0

Frequency1

1

(1) Frequency0 and Frequency1 can be any frequency within the

specified f_VCOrange.

Table 4. PLLx Setting, Output Selection (Y2, Y3)⁽¹⁾

Y2, Y3

FUNCTION

State0

0

1

State1

(1) State0 or State1 selection is valid for both outputs of the

corresponding PLL module and can be power down, Hi-Z state, low,

or active.

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Table 5. Y1 Setting⁽¹⁾

Y1

0

FUNCTION

State 0

State 1

1

(1) State0 and State1 are user definable in the generic configuration

register and can be power down, Hi-Z state, low, or active.

The S1/SDA and S2/SCL pins of the CDCE913-Q1 and CDCEL913-Q1 devices are dual-function pins. In the

default configuration, they are defined as SDA and SCL for the serial programming interface. They can be

programmed as control pins (S1 and S2) by setting the appropriate bits in the EEPROM. Note that changes to

the control register (Bit [6] of byte 02h) have no effect until they are written into the EEPROM.

Once they are set as control pins, the serial programming interface is no longer available. However, if V_DDOUTis

forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA and SCL).

S0 is not a multi-use pin; it is a control pin only.

10.3.2 Default Device Configuration

The internal EEPROM of the CDCE913-Q1 and CDCEL913-Q1 devices is preconfigured with a factory default

configuration as shown in Figure 6 (The input frequency is passed through the output as a default), thus allowing

the device to operate in default mode without the extra production step of programming it. The default setting

appears after power is supplied or after a power-down–power-up sequence until it is reprogrammed by the user

to a different application configuration. A new register setting is programmed through the serial I²C interface.

V

GND

DD

DDOUT

Input Clock

LV

CMOS

Pdiv1 =1

Y1 = 27 MHz

Xin

27 MHz

Crystal

X-tal

LV

CMOS

Y2 = 27 MHz

Y3 = 27 MHz

PLL1

Pdiv 2 = 1

power down

Xout

LV

CMOS

Pdiv 3 = 1

PLL Bypass

EEPROM

1 = Output Enabled

0 = Output 3-State

S0

Programming

and I2C

Register

SDA

SCL

Programming Bus

Figure 6. Default Configuration

Table 6 shows the factory default setting for the Control Terminal Register. Note that even though eight different

register settings are possible, in the default configuration, only the first two settings (0 and 1) can be selected

with S0, as S1, and S2 are configured as programming pins in default mode.

Table 6. Factory Default Setting for Control Terminal Register⁽¹⁾

Y1

PLL1 SETTINGS

OUTPUT

SELECTION

FREQUENCY

SELECTION

SSC

SELECTION

OUTPUT

SELECTION

EXTERNAL CONTROL PINS

S2

S1

S0

0

Y1

FS1

SSC1

Off

Y2Y3

SCL (I²C)

SDA (I²C)

3-state

Enabled

f_{VCO1_0}

Hi-Z state

Enabled

1

Off

(1) In default mode or when programmed respectively, S1 and S2 act as serial programming interface, I²C. They do not have any control-

pin function but they are internally interpreted as if S1 = 0 and S2 = 0. However, S0 is a control pin, which in the default mode switches

all outputs ON or OFF (as previously predefined).

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10.3.3 I²C Serial Interface

The CDCE913-Q1 and CDCEL913-Q1 devices operate as a slave device on the 2-wire serial I²C bus,

compatible with the popular SMBus or I²C specification. It operates in the standard-mode transfer (up to

100 kbit/s) and fast-mode transfer (up to 400 kbit/s) and supports 7-bit addressing.

The S1/SDA and S2/SCL pins of the CDCE913-Q1 and CDCEL913-Q1 devices are dual-function pins. In the

default configuration, they are used as the I²C serial programming interface. They can be reprogrammed as

general-purpose control pins, S1 and S2, by changing the corresponding EEPROM setting, byte 02h, bit [6].

10.3.4 Data Protocol

The device supports Byte Write and Byte Read and Block Write and Block Read operations.

For Byte Write/Read operations, the system controller can individually access addressed bytes.

For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with

most-significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of

bytes read out are defined by Byte Count in the generic configuration register. At the Block Read instruction, all

bytes defined in Byte Count must be read out to finish the read cycle correctly.

Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to

each transferred byte, regardless of whether this is a Byte Write or a Block Write sequence.

If the EEPROM write cycle is initiated, the internal SDA registers are written into the EEPROM. During this write

cycle, data is not accepted at the I²C bus until the write cycle is completed. However, data can be read out

during the programming sequence (Byte Read or Block Read). The programming status can be monitored by

EEPIP, byte 01h–bit 6.

The offset of the indexed byte is encoded in the command code, as described in Table 7.

Table 7. Slave Receiver Address (7 Bits)

DEVICE

A6

1

A5

1

A4

0

A3

0

A2

1

A1⁽¹⁾

A0⁽¹⁾

R/W

1/0

CDCEx913-Q1

CDCEx925

CDCEx937

CDCEx949

0

1

0

1

0

1

0

1

0

1

0

1

(1) Address bits A0 and A1 are programmable through the I²C bus (byte 01, bits [1:0]. This allows addressing up to 4 devices connected to

the same I²C bus. The least-significant bit of the address byte designates a write or read operation.

10.4 Device Functional Modes

10.4.1 SDA and SCL Hardware Interface

Figure 7 shows how the CDCE913-Q1 and CDCEL913-Q1 clock synthesizer is connected to the I²C serial

interface bus. Multiple devices can be connected to the bus, but it may be necessary to reduce the speed

(400 kHz is the maximum) if many devices are connected.

Note that the pullup resistors (R_P) depend on the supply voltage, bus capacitance, and number of connected

devices. The recommended pullup value is 4.7 kΩ. The resistor must meet the minimum sink current of 3 mA at

V_OLmax = 0.4 V for the output stages (for more details see the SMBus or I²C Bus specification).

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Device Functional Modes (continued)

CDCE913-Q1

CDCEL913-Q1

R

P

R

P

Master

SDA

Slave

SCL

C

BUS

Figure 7. I²C Hardware Interface

10.5 Programming

Table 8. Command Code Definition

BIT

DESCRIPTION

0 = Block Read or Block Write operation

1 = Byte Read or Byte Write operation

Byte offset for Byte Read, Block Read, Byte Write, and Block Write operations

7

(6:0)

1

7

1

8

1

S

Slave Address

A

Data Byte

A

P

R/W

MSB

LSB

MSB

LSB

S

Start Condition

Sr Repeated Start Condition

1 = Read (Rd) From CDCE9xx Device; 0 = Write (Wr) to CDCE9xxx

Acknowledge (ACK = 0 and NACK =1)

Stop Condition

R/W

A

P

Master-to-Slave Transmission

Slave-to-Master Transmission

Figure 8. Generic Programming Sequence

1

7

1

8

1

8

1

S

Slave Address

Wr

A

CommandCode

A

Data Byte

A

P

Figure 9. Byte Write Protocol

1

7

1

8

1

7

1

S

Slave Address

Wr

A

CommandCode

A

Sr

Slave Address

Rd

A

8

1

Data Byte

A

P

Figure 10. Byte Read Protocol

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1

7

1

8

1

8

1

S

Slave Address

Wr

A

CommandCode

A

Byte Count = N

A

8

1

8

1

8

1

Data Byte 0

A

Data Byte 1

A

…

Data Byte N-1

A

P

(1) Data byte 0 bits [7:0] is reserved for Revision Code and Vendor Identification. Also, it is used for internal test purpose

and must not be overwritten.

Figure 11. Block Write Protocol

1

7

1

8

1

7

1

S

Slave Address

Wr

A

CommandCode

A

Sr

Slave Address

Rd

A

8

1

8

1

8

1

Byte Count N

A

Data Byte 0

A

…

Data Byte N-1

A

P

Figure 12. Block Read Protocol

Bit 7 (MSB)

Bit 6

Bit 0 (LSB)

P

S

t

A

P

w(SCLL)

t

w(SCLH)

t

r

t

f

V

IH

SCL

V

IL

t

su(START)

h(START)

su(SDA)

t

h(SDA)

su(STOP)

t

f

t

r

(BUS)

V

IH

SDA

V

IL

Figure 13. Timing Diagram for I²C Serial Control Interface

10.6 Register Maps

10.6.1 I²C Configuration Registers

The clock input, control pins, PLLs, and output stages are user configurable. The following tables and

explanations describe the programmable functions of the CDCE913-Q1 and CDCEL913-Q1 devices. All settings

can be manually written into the device through the I²C bus or easily programmed by using the TI Pro-Clock™

software. TI Pro-Clock™ software allows the user to make all settings quickly, and automatically calculates the

values for optimized performance at lowest jitter.

Table 9. I²C Registers

ADDRESS OFFSET

REGISTER DESCRIPTION

Generic configuration register

PLL1 configuration register

TABLE

Table 11

Table 12

00h

10h

The grey-highlighted bits, described in the configuration register tables in the following pages, belong to the

control terminal register. The user can predefine up to eight different control settings. These settings then can be

selected by the external control pins, S0, S1, and S2. See the Control Terminal Configuration section.

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Table 10. Configuration Register, External Control Terminals

Y1

PLL1 Settings

EXTERNAL

CONTROL PINS

OUTPUT

SELECTION

OUTPUT SELECTION

FREQUENCY SELECTION

SSC SELECTION

S2

0

S1

0

S0

0

Y1

FS1

SSC1

Y2Y3

0

1

2

3

4

5

6

7

Y1_0

Y1_1

Y1_2

Y1_3

Y1_4

Y1_5

Y1_6

Y1_7

04h

FS1_0

FS1_1

FS1_2

FS1_3

FS1_4

FS1_5

FS1_6

FS1_7

13h

SSC1_0

SSC1_1

SSC1_2

SSC1_3

SSC1_4

SSC1_5

SSC1_6

SSC1_7

10h–12h

Y2Y3_0

Y2Y3_1

Y2Y3_2

Y2Y3_3

Y2Y3_4

Y2Y3_5

Y2Y3_6

Y2Y3_7

15h

0

1

0

1

0

1

0

1

0

1

0

1

Address offset⁽¹⁾

(1) Address offset refers to the byte address in the configuration register in Table 11 and Table 12.

Table 11. Generic Configuration Register

OFFSET⁽¹⁾BIT⁽²⁾

ACRONYM

E_EL

RID

DEFAULT⁽³⁾

DESCRIPTION

Device identification (read-only): 1 is CDCE913-Q1 (3.3 V out), 0 is CDCEL913-Q1 (1.8 V out)

Revision identification number (read-only)

7

Xb

1h

0b

00h

6:4

3:0

7

VID

Vendor identification number (read-only)

—

Reserved – always write 0

0 – EEPROM programming is completed.

EEPROM programming Status:⁽⁴⁾(read-only)

6

5

EEPIP

0b

1 – EEPROM is in programming mode.

0 – EEPROM is not locked.

Permanently lock EEPROM data⁽⁵⁾

EELOCK

1 – EEPROM is permanently locked.

Device power down (overwrites S0, S1, and S2 settings; configuration register settings are unchanged)

Note: PWDN cannot be set to 1 in the EEPROM.

01h

4

PWDN

0b

0 – Device active (PLL1 and all outputs are enabled)

1 – Device power down (PLL1 in power down and all outputs in Hi-Z state)

00 – Xtal

10 – LVCMOS

11 – Reserved

3:2

INCLK

00b

Input clock selection:

01 – VCXO

1:0

7

SLAVE_ADR

M1

01b

1b

Address bits A0 and A1 of the slave receiver address

Clock source selection for output Y1:

0 – Input clock

1 – PLL1 clock

Operation mode selection for pins 12 and 13⁽⁶⁾

6

SPICON

0b

0 – Serial programming interface SDA (pin 13) and SCL (pin 12)

1 – Control pins S1 (pin 13) and S2 (pin 12)

02h

03h

5:4

3:2

Y1_ST1

Y1_ST0

11b

01b

Y1-State0/1 definition

00 – Device power down (all PLLs in power down and all

outputs in Hi-Z state)

01 – Y1 disabled to Hi-Z state

10 – Y1 disabled to low

11 – Y1 enabled

1:0

7:0

Pdiv1 [9:8]

Pdiv1 [7:0]

0 – Divider reset and stand-by

1 to 1023 – Divider value

001h

10-bit Y1-output-divider Pdiv1:

(1) Writing data beyond 20h may affect device function.

(2) All data transferred with the MSB first

(3) Unless customer-specific setting

(4) During EEPROM programming, no data is allowed to be sent to the device through the I²C bus until the programming sequence is

completed. However, data can be read out during the programming sequence (Byte Read or Block Read).

(5) If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. No further programming is possible.

However, data can still be written through the I²C bus to the internal register to change device function on the fly, but new data can no

longer be saved to the EEPROM. EELOCK is effective only if written into the EEPROM.

(6) Selection of control pins is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are no

longer available. However, if V_DDOUTis forced to GND, the two control pins, S1 and S2, temporarily act as serial programming pins

(SDA-SCL), and the two slave receiver address bits are reset to A0 = 0 and A1 = 0.

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Table 11. Generic Configuration Register (continued)

OFFSET⁽¹⁾BIT⁽²⁾

ACRONYM

Y1_7

DEFAULT⁽³⁾

DESCRIPTION

7

6

5

0b

1b

0b

Y1_6

Y1_5

4

Y1_4

0 – State0 (predefined by Y1_ST0)

1 – State1 (predefined by Y1_ST1)

04h

Y1_x State selection⁽⁷⁾

3

Y1_3

2

1

0

Y1_2

Y1_1

Y1_0

Crystal load capacitor selection⁽⁸⁾

00h – 0 pF

01h – 1 pF

02h – 2 pF

7:3

XCSEL

0Ah

05h

:14h to 1Fh – 20 pF

2:0

0b

Reserved – do not write other than 0

7-bit byte count (defines the number of bytes which will be sent from this device at the next Block Read transfer); all bytes

must be read out to finish the read cycle correctly.

7:1

BCOUNT

20h

06h

0– No EEPROM write cycle

1 – Start EEPROM write cycle (internal registers are saved to the EEPROM)

(4)(9)

0

EEWRITE

—

0b

0h

Initiate EEPROM write cycle

07h-0Fh

Unused address range

(7) These are the bits of the control terminal register (see Table 10 ). The user can predefine up to eight different control settings. These

settings then can be selected by the external control pins, S0, S1, and S2.

(8) The internal load capacitor (C1, C2) must be used to achieve the best clock performance. External capacitors should be used only to

finely adjust C_Lby a few picofarads. The value of C_Lcan be programmed with a resolution of 1 pF for a crystal load range of 0 pF to

20 pF. For C_L> 20 pF, use additional external capacitors. The device input capacitance value must be considered, which always adds

1.5 pF (6 pF//2 pF) to the selected C_L. For more about VCXO config. and crystal recommendation, see VCXO Application Guideline for

CDCE(L)9xx Family (SCAA085).

(9) The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The

EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level-high does not trigger an EEPROM WRITE cycle. The

EEWRITE bit must be reset to low after the programming is completed. The programming status can be monitored by reading out

EEPIP. If EELOCK is set to high, no EEPROM programming is possible.

Table 12. PLL1 Configuration Register

OFFSET⁽¹⁾

BIT⁽²⁾

7:5

4:2

1:0

7

ACRONYM

SSC1_7 [2:0]

SSC1_6 [2:0]

SSC1_5 [2:1]

SSC1_5 [0]

SSC1_4 [2:0]

SSC1_3 [2:0]

SSC1_2 [2]

SSC1_2 [1:0]

SSC1_1 [2:0]

SSC1_0 [2:0]

FS1_7

DEFAULT⁽³⁾

DESCRIPTION

(4)

000b

SSC1: PLL1 SSC selection (modulation amount).

10h

000b

Down

000 (off)

Center

000 (off)

001 – 0.25%

010 – 0.5%

011 – 0.75%

100 – 1.0%

101 – 1.25%

110 – 1.5%

111 – 2.0%

001 ± 0.25%

010 ± 0.5%

011 ± 0.75%

100 ± 1.0%

101 ± 1.25%

110 ± 1.5%

111 ± 2.0%

000b

6:4

3:1

0

000b

11h

12h

000b

7:6

5:3

2:0

7

000b

0b

(4)

FS1_x: PLL1 frequency selection

6

FS1_6

0b

5

FS1_5

0b

4

FS1_4

0b

13h

0 – f_{VCO1_0}(predefined by PLL1_0 – multiplier/divider value)

1 – f_{VCO1_1}(predefined by PLL1_1 – multiplier/divider value)

3

FS1_3

0b

2

FS1_2

0b

1

FS1_1

0b

0

FS1_0

0b

(1) Writing data beyond 20h may adversely affect device function.

(2) All data is transferred MSB-first.

(3) Unless a custom setting is used

(4) The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external

control pins, S0, S1, and S2.

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Table 12. PLL1 Configuration Register (continued)

OFFSET⁽¹⁾

BIT⁽²⁾

ACRONYM

DEFAULT⁽³⁾

DESCRIPTION

0 – PLL1

7

MUX1

1b

PLL1 multiplexer:

1 – PLL1 bypass (PLL1 is in power down)

0 – Pdiv1

1 – Pdiv2

6

M2

M3

1b

Output Y2 multiplexer:

00 – Pdiv1-divider

01 – Pdiv2-divider

10 – Pdiv3-divider

11 – Reserved

14h

5:4

10b

Output Y3 Multiplexer:

3:2

1:0

Y2Y3_ST1

Y2Y3_ST0

11b

01b

00 – Y2 and Y3 disabled to Hi-Z state (PLL1 is in power down)

01 – Y2 and Y3 disabled to Hi-Z state

10–Y2 and Y3 disabled to low

Y2, Y3-

State0/1definition:

11 – Y2 and Y3 enabled

(4)

7

6

5

4

3

2

1

0

Y2Y3_7

Y2Y3_6

Y2Y3_5

Y2Y3_4

Y2Y3_3

Y2Y3_2

Y2Y3_1

Y2Y3_0

0b

1b

0b

Y2Y3_x output state selection.

15h

0 – State0 (predefined by Y2Y3_ST0)

1 – State1 (predefined by Y2Y3_ST1)

PLL1 SSC down or center

selection:

0 – Down

1 – Center

7

SSC1DC

0b

16h

17h

0 – Reset and standby

1 to 127 – Divider value

6:0

7

Pdiv2

—

01h

0b

7-bit Y2-output-divider Pdiv2:

Reserved – do not write other than 0

7-bit Y3-output-divider Pdiv3:

0 – Reset and standby

1 to 127 – Divider value

6:0

Pdiv3

01h

18h

19h

7:0

7:4

3:0

7:3

2:0

7:5

4:2

PLL1_0N [11:4]

PLL1_0N [3:0]

PLL1_0R [8:5]

PLL1_0R[4:0]

PLL1_0Q [5:3]

PLL1_0Q [2:0]

PLL1_0P [2:0]

004h

000h

PLL1_0⁽⁵⁾: 30-bit multiplier or divider value for frequency f_{VCO1_0}

(for more information, see PLL Frequency Planning).

1Ah

10h

010b

1Bh

00 – f_{VCO1_0}< 125 MHz

01 – 125 MHz ≤ f_{VCO1_0}< 150 MHz

10 – 150 MHz ≤ f_{VCO1_0}< 175 MHz

1:0

VCO1_0_RANGE

00b

f_{VCO1_0}range selection:

11 – f_{VCO1_0}≥ 175 MHz

1Ch

1Dh

7:0

7:4

3:0

7:3

2:0

7:5

4:2

PLL1_1N [11:4]

PLL1_1N [3:0]

PLL1_1R [8:5]

PLL1_1R[4:0]

PLL1_1Q [5:3]

PLL1_1Q [2:0]

PLL1_1P [2:0]

004h

000h

PLL1_1⁽⁵⁾: 30-bit multiplier or divider value for frequency f_{VCO1_1}

(for more information, see PLL Frequency Planning).

1Eh

10h

010b

1Fh

00 – f_{VCO1_1}< 125 MHz

01 – 125 MHz ≤ f_{VCO1_1}< 150 MHz

10 – 150 MHz ≤ f_{VCO1_1}< 175 MHz

1:0

VCO1_1_RANGE

00b

f_{VCO1_1}range selection:

11 – f_{VCO1_1}≥ 175 MHz

(5) PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096

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11 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

11.1 Application Information

The CDCE913-Q1 device is an easy-to-use, high-performance, programmable CMOS clock synthesizer which

can be used as a crystal buffer, clock synthesizer with separate output supply pin. The CDCE913-Q1 device

features an on-chip loop filter and spread-spectrum modulation. Programming can be done through the I²C

interface, or previously saved settings can be loaded from on-chip EEPROM. The pins S0, S1, and S2 can be

programmed as control pins to select various output settings. This section shows some examples of using the

CDCE913-Q1 device in various applications.

11.2 Typical Application

Figure 14 shows the use of the CDCEL913-Q1 device in an infotainment system, such as in head unit or

telematics applications, using a 1.8-V single supply.

Figure 14. Single-Chip Solution Using a CDCE913-Q1 Device for Generating Clocking Frequencies

for Infotainment Application

11.2.1 Design Requirements

The CDCE913-Q1 device supports spread-spectrum clocking (SSC) with multiple control parameters:

•

Modulation amount (%)

Modulation frequency (>20 kHz)

Modulation shape (triangular, hershey, and others)

Center spread or down spread (± or –)

Consider the following sample design requirements:

•

EMI ≤ 55 dBmV

CLK1 frequency = 27 MHz

CLK2 frequency = 54 MHz

CLK3 frequency = 108 MHz

For sample calculations of PLL constants, see PLL Frequency Planning.

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Typical Application (continued)

Figure 15. Modulation Frequency (fm) and Modulation Amount

Figure 16. Spread Spectrum Modulation Shapes

11.2.2 Detailed Design Procedure

11.2.2.1 Spread-Spectrum Clock (SSC)

Spread-spectrum modulation is a method to spread emitted energy over a larger bandwidth. In clocking, spread

spectrum can reduce electromagnetic interference (EMI) by reducing the level of emission from clock distribution

network.

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Typical Application (continued)

CDCS502 with a 25-MHz Crystal, FS = 1, f_OUT= 100 MHz, and 0%, ±0.5, ±1%, and ±2% SSC

Figure 17. Comparison Between Typical Clock Power Spectrum and Spread-Spectrum Clock

Spread spectrum clocking can be used to help reduce EMI in order to meet design specifications. For example, a

specified EMI threshold of 55 dB/mV would require ±1% spread spectrum clocking to meet this requirement.

11.2.2.2 PLL Frequency Planning

At a given input frequency (f_IN), the output frequency (f_OUT) of the CDCE913-Q1 or CDCEL913-Q1 device is

calculated with Equation 1.

ƒ_IN

´

N

ƒ_OUT

=

Pdiv

M

where

M (1 to 511) and N (1 to 4095) are the multiplier or divider values of the PLL; Pdiv (1 to 127) is the output

divider.

(1)

The target VCO frequency (ƒ_VCO) of each PLL is calculated with Equation 2.

N

ƒ_VCO= ƒ_IN

´

M

(2)

The PLL internally operates as fractional divider and needs the following multiplier or divider settings:

•

N

P = 4 – int(log₂N / M); if P < 0 then P = 0

Q = int(N' / M)

R = N′ – M × Q

where

•

int(X) = integer portion of X

N′ = N × 2^P

N ≥ M

80 MHz ≤ ƒ_VCO≤ 230 MHz

16 ≤ Q ≤ 63 µs

0 ≤ P ≤ 4 µs

0 ≤ R ≤ 51 µs

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Typical Application (continued)

Example:

for ƒ_IN= 27 MHz; M = 1; N = 4; Pdiv = 2

→ f_OUT= 54 MHz

for ƒ_IN= 27 MHz; M = 2; N = 11; Pdiv = 2

→ f_OUT= 74.25 MHz

→ f_VCO= 108 MHz

→ f_VCO= 148.50 MHz

→ P = 4 – int(log₂4) = 4 – 2 = 2

→ N' = 4 × 2²= 16

→ P = 4 – int(log₂5.5) = 4 – 2 = 2

→ N' = 11 × 2²= 44

→ Q = int(16) = 16

→ Q = int(22) = 22

→ R = 16 – 16 = 0

→ R = 44 – 44 = 0

The values for P, Q, R, and N' are automatically calculated when using TI Pro-Clock™ software.

The frequency of CLK1 shown in the application diagram can be obtained by passing the input frequency of the

VCXO directly to output 1. The CLK2 frequency can be achieved by using the PLL constants derived in the first

example. The value of CLK3 requires the same PLL constants as CLK2, but Pdiv3 is set to 1 instead of 2 to yield

a frequency of 108 MHz.

11.2.2.3 Crystal Oscillator Start-Up

When the CDCE913-Q1 or CDCEL913-Q1 device is used as a crystal buffer, crystal oscillator start-up dominates

the start-up time compared to the internal PLL lock time. The following diagram shows the oscillator start-up

sequence for a 27-MHz crystal input with an 8-pF load. The start-up time for the crystal is on the order of

approximately 250 µs compared to approximately 10 µs of lock time. In general, lock time is an order of

magnitude less compared to the crystal start-up time.

Figure 18. Crystal Oscillator Start-Up vs PLL Lock Time

11.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling

The frequency for the CDCE913-Q1 or CDCEL913-Q1 device is adjusted for media and other applications with

the VCXO control input V_ctr. If a PWM-modulated signal is used as a control signal for the VCXO, an external

filter is needed.

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Typical Application (continued)

LP

CDCE(L)913-Q1

V_ctr

PWM

Control

Signal

Xin/CLK

Xout

Figure 19. Frequency Adjustment Using PWM Input to the VCXO Control

11.2.2.5 Unused Inputs and Outputs

If VCXO-pulling functionality is not required, V_ctrshould be left floating. All other unused inputs should be set to

GND. Unused outputs should be left floating.

If one output block is not used, TI recommends disabling it. However, TI recommends providing a supply for all

output blocks, even if they are disabled.

11.2.2.6 Switching Between XO and VCXO Mode

When the CDCE(L)913-Q1 device is in the crystal-oscillator or VCXO configuration, the internal capacitors

require different internal capacitance. The following steps are recommended to switch to VCXO mode when the

configuration for the on-chip capacitor is still set for XO mode. To center the output frequency to 0 ppm:

1. While in XO mode, put V_ctr= V_DD/ 2

2. Switch from XO mode to VCXO mode

3. Program the internal capacitors in order to obtain 0 ppm at the output.

11.2.3 Application Curves

Figure 20, Figure 21, Figure 22, and Figure 23 show CDCE913-Q1 measurements with the SSC feature enabled.

Device configuration: 27-MHz input, 27-MHz output.

Figure 20. f_OUT= 27 MHz,

Figure 21. f_OUT= 27 MHz,

VCO frequency < 125 MHz, SSC (2% Center)

VCO frequency > 175 MHz, SSC (1%, Center)

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Typical Application (continued)

Figure 23. Output Spectrum With SSC On,

2% Center

Figure 22. Output Spectrum With SSC Off

12 Power Supply Recommendations

There is no restriction on the power-up sequence. In case V_DDOUTis applied first, TI recommends grounding

V_DD–. In case V_DDOUTis powered while V_DDis floating, there is a risk of high current flowing on the V_DDOUTpins.

The device has a power-up control that is connected to the 1.8-V supply. This keeps the whole device disabled

until the 1.8-V supply reaches a sufficient voltage level. Then the device switches on all internal components,

including the outputs. If a 3.3-V V_DDOUTis available before the 1.8-V, the outputs stay disabled until the 1.8-V

supply has reached a certain level.

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13 Layout

13.1 Layout Guidelines

When the CDCE913-Q1 device is used as a crystal buffer, any parasitics across the crystal affect the pulling

range of the VCXO. Therefore, take care in placing the crystal units on the board. Crystals should be placed as

close to the device as possible, ensuring that the routing lines from the crystal terminals to Xin and Xout have the

same length.

If possible, cut out both ground plane and power plane under the area where the crystal and the routing to the

device are placed. In this area, always avoid routing any other signal line, as it could be a source of noise

coupling.

Additional discrete capacitors can be required to meet the load capacitance specification of certain crystals. For

example, a 10.7-pF load capacitor is not fully programmable on the chip, because the internal capacitor can

range from 0 pF to 20 pF with steps of 1 pF. Therefore, the 0.7-pF capacitor can be discretely added on top of

an internal 10 pF.

To minimize the inductive influence of the trace, TI recommends placing this small capacitor as close to the

device as possible and symmetrically with respect to Xin and Xout.

Figure 24 shows a conceptual layout detailing recommended placement of power-supply bypass capacitors. For

component-side mounting, use 0402 body-size capacitors to facilitate signal routing. Keep the connections

between the bypass capacitors and the power supply on the device as short as possible. Ground the other side

of the capacitor using a low-impedance connection to the ground plane.

13.2 Layout Example

ꢂlace tꢃe crystal ꢄitꢃ

associated load caps as close

to tꢃe cꢃip as possiꢅle

Ço ëLh

óin/ꢀ[Y

óhÜÇ

Ço 1.8ë

{5!

{1/{5!

{2/{ꢀ[

ò1

{0

ë55

{ꢀ[

Üse ferrite ꢅeads to isolate

tꢃe deꢆice supply pins from

ꢅoard noise sources

ò1 hutput

ëꢀÇw[

Db5

ò2

ë55hÜÇ

ò2 hutput

ò3 hutput

Ço 3.3ë

ꢀ5ꢀ9ꢁ13-v1

ò3

ꢂlace ꢅypass caps close to

tꢃe deꢆice pins, ensure ꢄide

frequency range

ꢂlace series termination

resistors at clock outputs to

improꢆe signal integrity

ëia

ꢀopper trace/pour

Figure 24. Annotated Layout

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14 Device and Documentation Support

14.1 Documentation Support

14.1.1 Related Documentation

For related documentation see the following:

•

Crystal Or Crystal Oscillator Replacement with Silicon Devices (SNAA217)

!~

•

CDCE(L)9xx and CDCEx06 Programming Evaluation Module (SCAU026)

CDCE(L)9xx Performance Evaluation Module (SCAU022)

General I2C/EEPROM Usage for the CDCE(L)9xx Family (SCAA104)

Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency Word Clock (SCAA088)

Practical Consideration on Choosing a Crystal for CDCE(L)9xx Family (SLEA071)

Usage of I²C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 (SCAA105)

VCXO Application Guideline for CDCE(L)9xx Family (SCAA085)

14.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 13. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

CDCE913-Q1

CDCEL913-Q1

Click here

14.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

14.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

14.5 Trademarks

DaVinci, OMAP, Pro-Clock, E2E are trademarks of Texas Instruments.

Bluetooth is a registered trademark of Bluetooth SIG, Inc.

All other trademarks are the property of their respective owners.

14.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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14.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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15 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

30

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IMPORTANT NOTICE AND DISCLAIMER

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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	CDCE913QPWRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有 2.5V 或 3.3V LVCMOS 输出的汽车类可编程 1-PLL VCXO 时钟合成器 \| PW \| 14 \| -40 to 125 时钟石英晶振压控振荡器
文件：	总37页 (文件大小：1138K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CDCE913QPWRQ1 [TI]

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