CDCDB803 概述
用于 PCIe® 第 1 代至第 5 代的 8 输出时钟缓冲器,具有可选的 SMBus 地址
CDCDB803 数据手册
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ZHCSMV0A – AUGUST 2021 – REVISED MAY 2022
CDCDB803 适用于第 1 代到第 6 代 PCIe、符合 DB800ZL 标准的 8 输出时钟缓冲
器
1 特性
2 应用
•
•
•
•
•
微服务器和塔式服务器
•
具有可编程集成 85Ω(默认值)或 100Ω 差分输出
存储区域网络和主机总线适配器卡
网络连接存储
终端的 8 个 LP-HCSL 输出
8 硬件输出使能端 (OE#) 控制装置
使用第 6 代 PCIE 滤波器之后的附加相位抖动:
20fs RMS(最大值)
•
•
硬件加速器
机架式服务器
•
•
•
使用第 5 代 PCIE 滤波器之后的附加相位抖动:
25fs RMS(最大值)
3 说明
CDCDB803 是一款符合 DB800ZL 标准的 8 输出 LP-
HCSL 时钟缓冲器,能够为第 1 代到第 6 代 PCIe、
QuickPath Interconnect (QPI)、UPI、SAS 和 SATA 接
口分配基准时钟。使用 SMBus 接口和 8 输出使能引
脚,可以单独配置和控制所有 8 个输出。CDCDB803
是一款 DB800ZL 衍生缓冲器,符合或超过 DB800ZL
中的系统参数规格。它还符合或超过了 DB2000Q 的
参数规格。CDCDB803 采用 6mm × 6mm 48 引脚
VQFN 封装。
使用 DB2000Q 滤波器之后的附加相位抖动:38fs
RMS(最大值)
支持公共时钟 (CC) 和单独基准 (IR) 架构
– 与扩频兼容
•
•
•
•
•
•
•
•
•
输出到输出偏斜:< 50ps
输入到输出延迟:< 3ns
失效防护输入
可编程输出转换率控制
9 个可选 SMBus 地址
器件信息
3.3V 内核和 IO 电源电压
器件型号
CDCDB803
封装(1)
封装尺寸(标称值)
硬件控制的低功耗模式 (PD#)
电流消耗:72mA(最大值)
6mm × 6mm 48 引脚 VQFN 封装
VQFN (48)
6.00mm × 6.00mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
PCIe Gen 4-5
Clock
Generator
8
LP-HCSL
CDCDB803
8x LP-HSCL Output Buffer
PCIe Device
LP-HCSL
OE#
Control
SMBus
Control
Control Interface
CDCDB803 系统图
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNAS820
CDCDB803
ZHCSMV0A – AUGUST 2021 – REVISED MAY 2022
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Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings ....................................... 6
6.2 ESD Ratings .............................................................. 6
6.3 Recommended Operating Conditions ........................6
6.4 Thermal Information ...................................................6
6.5 Electrical Characteristics ............................................7
6.6 Timing Requirements .................................................9
6.7 Typical Characteristics..............................................10
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................12
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................13
8.5 Programming............................................................ 14
8.6 Register Maps...........................................................16
9 Application and Implementation..................................20
9.1 Application Information............................................. 20
9.2 Typical Application.................................................... 20
10 Power Supply Recommendations..............................22
11 Layout...........................................................................23
11.1 Layout Guidelines................................................... 23
11.2 Layout Examples.....................................................23
12 Device and Documentation Support..........................25
12.1 Device Support....................................................... 25
12.2 接收文档更新通知................................................... 25
12.3 支持资源..................................................................25
12.4 Trademarks.............................................................25
12.5 Electrostatic Discharge Caution..............................25
12.6 术语表..................................................................... 25
13 Mechanical, Packaging, and Orderable
Information.................................................................... 25
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision * (August 2021) to Revision A (May 2022)
Page
•
•
•
更改了数据表标题...............................................................................................................................................1
在数据表中添加了 PCIe 第 6 代..........................................................................................................................1
Changed the pin descriptions for pins 5, 8 and 46............................................................................................. 3
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5 Pin Configuration and Functions
CKPWRGD_PD#
VDDR
1
36
35
34
33
32
31
30
29
28
27
26
25
CK6_N
CK6_P
VDD
2
CLKIN_P
CLKIN_N
SADR0
SMBDAT
SMBCLK
SADR1
NC
3
4
CK5_N
CK5_P
OE5#
5
6
GND
7
OE4#
8
CK4_N
CK4_P
VDD
9
NC
10
11
12
VDD
CK3_N
CK3_P
OE0#
Not to scale
图 5-1. CDCDB803 RSL Package 48-Pin VQFN Top View
表 5-1. Pin Functions
PIN
TYPE(2)
DESCRIPTION
NAME
NO.
INPUT CLOCK
CLKIN_P
CLKIN_N
OUTPUT CLOCKS
CK0_P
3
4
I
I
LP-HCSL differential clock input. Typically connected directly to the differential
output of clock source.
13
14
16
17
O
O
O
O
LP-HCSL differential clock output of channel 0. Typically connected directly to PCIe
differential clock input. If unused, the pins can be left no connect.
CK0_N
CK1_P
LP-HCSL differential clock output of channel 1. Typically connected directly to PCIe
differential clock input. If unused, the pins can be left no connect.
CK1_N
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表 5-1. Pin Functions (continued)
PIN
TYPE(2)
DESCRIPTION
NAME
CK2_P
NO.
21
22
25
26
28
29
32
33
35
36
39
40
O
O
O
O
O
O
O
O
O
O
O
O
LP-HCSL differential clock output of channel 2. Typically connected directly to PCIe
differential clock input. If unused, the pins can be left no connect.
CK2_N
CK3_P
CK3_N
CK4_P
CK4_N
CK5_P
CK5_N
CK6_P
CK6_N
CK7_P
CK7_N
LP-HCSL differential clock output of channel 3. Typically connected directly to PCIe
differential clock input. If unused, the pins can be left no connect.
LP-HCSL differential clock output of channel 4. Typically connected directly to PCIe
differential clock input. If unused, the pins can be left no connect.
LP-HCSL differential clock output of channel 5. Typically connected directly to PCIe
differential clock input. If unused, the pins can be left no connect.
LP-HCSL differential clock output of channel 6. Typically connected directly to PCIe
differential clock input. If unused, the pins can be left no connect.
LP-HCSL differential clock output of channel 7. Typically connected directly to PCIe
differential clock input. If unused, the pins can be left no connect.
MANAGEMENT AND CONTROL (1)
Clock Power Good and Power Down multi-function input pin with internal 180-kΩ
pulldown. Typically connected to GPIO of microcontroller. If unused, the pin can
be left no connect. After PWRGD has been asserted high for the first time, the pin
becomes a PD# pin and it controls power-down mode:
CKPWRGD_PD#
1
I, S, PD
LOW: Power-down mode, all output channels tri-stated.
HIGH: Normal operation mode.
Output Enable for channel 0 with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 0.
OE0#
OE1#
OE2#
OE3#
OE4#
OE5#
OE6#
OE7#
12
18
23
24
30
31
37
41
I, S, PD
I, S, PD
I, S, PD
I, S, PD
I, S, PD
I, S, PD
I, S, PD
I, S, PD
HIGH: disable output channel 0.
Output Enable for channel 1 with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 1.
HIGH: disable output channel 1.
Output Enable for channel 2 with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 2.
HIGH: disable output channel 2.
Output Enable for channel 3, with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 3.
HIGH: disable output channel 3.
Output Enable for channel 4, with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 4.
HIGH: disable output channel 4.
Output Enable for channel 5, with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 5.
HIGH: disable output channel 5.
Output Enable for channel 6 with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 6.
HIGH: disable output channel 6.
Output Enable for channel 7 with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 7.
HIGH: disable output channel 7.
SMBUS AND SMBUS ADDRESS
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表 5-1. Pin Functions (continued)
PIN
TYPE(2)
DESCRIPTION
NO.
SMBus address strap bit[0]. This is a 3-level input that is decoded in conjunction
with pin 8 to set SMBus address. It has internal 180-kΩ pullup / pulldown network
biasing to GND when no connect.
For a high-level input configuration, the pin should be pulled up to 3.3-V VDD
SADR0
5
I, S, PU / PD through an external pullup resistor from 1k to 5k with 5% tolerance.
For a low-level input configuration input, the pin should be pulled down to ground
through an external pulldown resistor from 1k to 5k with 5% tolerance.
For a mid-level input configuration, the pin should be left floating and not
connected to VDD or ground.
Data pin of SMBus interface. Typically pulled up to 3.3-V VDD using external pullup
resistor. The recommended pullup resistor value is > 8.5k.
SMBDAT
SMBCLK
6
7
I / O
Clock pin of SMBus interface. Typically pulled up to 3.3-V VDD using external
pullup resistor. The recommended pullup resistor value is > 8.5k.
I
SMBus address strap bit[1]. This is a 3-level input that is decoded in conjunction
with pin B4 to set SMBus address. It has internal 180-kΩ pullup / pulldown network
biasing to GND when no connect.
For a high-level input configuration, the pin should be pulled up to 3.3-V VDD
I, S, PU / PD through an external pullup resistor from 1k to 5k with 5% tolerance.
For a low-level input configuration, the pin should be pulled down to ground
through an external pulldown resistor from 1k to 5k with 5% tolerance.
For a mid-level input configuration, the pin should be left floating and not
connected to VDD or ground.
SADR1
8
SMBWRTLOCK: Disables write commands on SMBus. All writes will be ignored
when SMBWRTLOCK is asserted (reads are not affected). Internal 180-kΩ
SMBWRTLOCK
46
I, PD
pulldown, active high.
0 = SMBus write enabled.
1 = SMBus write disabled.
SUPPLY VOLTAGE AND GROUND
Power supply input for input clock receiver. Connect to 3.3-V power supply rail with
decoupling capacitor to GND. Place a 0.1-µF capacitor close to each supply pin
between power supply and ground.
VDDR
VDD
2
P
11, 15, 19, 27, 34,
38, 42, 44
P
3.3-V power supply for output channels and core voltage.
Ground. Connect ground pad to system ground.
GND
DAP
G
NO CONNECT
NC
9, 10, 20, 43, 45
47, 48
—
—
Do not connect to GND or VDD.
No connect. Pins may be connected to GND, VDD, or otherwise tied to any
potential within the Supply Voltage range stated in the Absolute Maximum Ratings.
NC
(1) The “#” symbol at the end of a pin name indicates that the active state occurs when the signal is at a low voltage level. When “#” is not
present, the signal is active high.
(2) The definitions below define the I/O type for each pin.
•
•
•
•
•
•
•
•
I = Input
O = Output
I / O = Input / Output
PU / PD = Internal 180-kΩ Pullup / Pulldown network biasing to VDD/2
PD = Internal 180-kΩ Pulldown
S = Hardware Configuration Pin
P = Power Supply
G = Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
−0.3
−0.3
MAX
3.6
UNIT
V
VDD, VDD_R
Power supply voltage
IO input voltage
VIN
TJ
3.6
V
Junction temperature
Storage temperature
125
150
°C
°C
Tstg
−65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001, all pins(1)
±3500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
3.3
MAX
3.6
UNIT
V
VDD
VDD_R
TA
IO, Core supply voltage
Input supply voltage
Ambient temperature
3
3.3
3.6
V
−40
105
°C
6.4 Thermal Information
Device Package
THERMAL METRIC(1)
RSL (QFN)
48 PINS
32.2
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
22.3
14.3
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
ΨJB
14.2
RθJC(bot)
6.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
VDD, VDD_R = 3.3 V ± 5 %, −40°C ≤ TA ≤ 105°C. Typical values are at VDD = VDD_R = 3.3 V, 25°C (unless otherwise
noted)
PARAMETER
CURRENT CONSUMPTION
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mA
Active mode. CKPWRGD_PD# = 1
Power-down mode. CKPWRGD_PD# = 0
All outputs disabled
9
2.2
18
IDD_R
Core supply current
IDD
IO supply current
All outputs active, 100MHz (Per output)
Power-down mode. CKPWRGD_PD# = 0
7.8
1.5
mA
CLOCK INPUT
fIN
Input frequency
50
200
0.7
100
250
MHz
Differential voltage between CLKIN_P and
CLKIN_N(1)
mVDiff-
VIN
Input voltage swing
2300
peak
dV/dt
Input voltage edge rate
Total variation of VCROSS
Input duty cycle
20% - 80% of input swing
V/ns
mV
%
DVCROSS
DCIN
Total variation across VCROSS
140
2.2
40
60
Differential capacitance between CLKIN_P
and CLKIN_N pins
CIN
Input capacitance(2)
pF
CLOCK OUTPUT
fOUT
Output frequency
50
100
4
250
MHz
pF
Differential capacitance between CKx_P
and CKx_N pins
COUT
Output capacitance(1)
VOH
VOL
Output high voltage
Output low voltage
225
10
270
150
Single-ended(2) (3)
Measured into an AC load as defined in
DB800ZL
VHIGH
VLOW
Output high voltage
Output low voltage
660
850
150
Measured into an AC load as defined in
DB800ZL
–150
Measured into an AC load as defined in
DB800ZL
VMAX
Output Max voltage
1150
200
550
mV
(3) (4)
VCROSS
Crossing point voltage
130
250
Measured into an AC load as defined in
DB800ZL
VCROSSAC Crossing point voltage (AC load)
(3) (4)
DVCROSS
Vovs
Total variation of VCROSS
Overshoot voltage
Variation of VCROSS
35
140
(3)
VOH+75
Measured into an AC load as defined in
DB800ZL
VHIGH+30
0
Vovs(AC)
Vuds
Overshoot voltage (AC load)
Undershoot voltage
(3)
VOL–75
Measured into an AC load as defined in
DB800ZL
VLOW–
Vuds(AC)
Undershoot voltage
mV
V
300
Measured into an AC load as defined in
DB800ZL and taken from Single Ended
Vrb
Ringback Voltage
-0.2
0.2
waveform (relative to VHIGH and VLOW
)
Differential impedance (Default
setting, 85 Ω)
Measured at VOL/VOH
81
95
68
80
85
100
85
89
105
102
120
ZDIFF
Differential impedance (Output
impedance selection bit =1, 100 Ω)
Measured at VOL/VOH
Measured at VCROSS
Measured at VCROSS
Ω
Differential impedance (Default
setting, 85 Ω)
ZDIFF_CROS
S
Differential impedance (Output
impedance selection bit = 1, 100 Ω)
100
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VDD, VDD_R = 3.3 V ± 5 %, −40°C ≤ TA ≤ 105°C. Typical values are at VDD = VDD_R = 3.3 V, 25°C (unless otherwise
noted)
PARAMETER
Differential edge rate
Edge rate matching
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V/ns
%
(7)
tEDGE
Measured (+-150 mV) around VCROSS
2
4
(7)
DtEDGE
Measured (+-75 mV) VCROSS
20
Measured
when
positive
output
reaches
0.2V
CKPWRGD_PD# pin
transitions from 0 to 1, fIN
100 MHz
Power good assertion to stable clock
output
tSTABLE
=
=
1.8
ms
µs
Measured
when
positive
output
reaches
0.2V
CKPWRGD_PD# pin
transitions from 0 to 1, fIN
100 MHz
Power good assertion to outputs
driven high
tDRIVE_PD#
300
Output enable assertion to stable
clock output
tOE
tOD
tPD
OEx# pin transitions from 1 to 0
OEx# pin transitions from 0 to 1
10
10
3
Output enable de-assertion to no
clock output
CLKIN
Periods
Power-down assertion to no clock
output
CKPWRGD_PD# pin transitions from 1 to 0
tDCD
tDLY
Duty cycle distortion
Propagation delay
Differential; fIN = 100MHz, fIN_DC = 50%
–1
1
3
%
ns
ps
(5)
0.5
(6)
tSKEW
Skew between outputs
50
tDELAY(IN-
Input-to-output delay variation at 100 MHz
across voltage and temperature
Input to output delay variation
Additive jitter for DB2000Q
–250
250
ps
OUT)
JCKx_DB2000
DB2000Q filter, for input of 200 mV
differential swing @ 1.5 V/ns
0.038 ps, RMS
(7)
Q
Input clock
slew rate =
2 V/ns
PLL BW: 0.5 - 1 MHz; CDR =
10 MHz
Additive jitter for PCIe6.0
Additive jitter for PCIe5.0
Additive jitter for PCIe4.0
0.02
PCIe5.0 filter
0.025
JCKx_PCIE
Input clock
slew rate ≥
ps, RMS
0.06
(7)
1.8 V/ns
PLL BW = 2 - 5 MHz; CDR =
10 MHz
Input clock
slew rate ≥
0.6 V/ns
Additive jitter for PCIe3.0
Additive jitter
0.1
fIN = 100 MHz; slew rate ≥ 3 V/ns; 12 kHz to
20 MHz integration bandwidth.
JCKx
NF
100
160 fs, RMS
-155 dBc/Hz
Input clock
fIN = 100 MHz; fOffset ≥ 10 MHz slew rate ≥
3 V/ns
Noise floor
–160
SMBUS INTERFACE, OEx#, CKPWRGD_PD#
VIH
VIL
High level input voltage
Low level input voltage
2.0
V
0.8
GND ≤ VIN
With internal pull-up/pull-down
≤ VDD
IIH
IIL
IIH
IIL
Input leakage current
Input leakage current
Input leakage current
Input leakage current
–30
–30
−5
30
30
5
µA
µA
µA
µA
GND ≤ VIN
With internal pull-up/pull-down
≤ VDD
Without internal pull-up/pull-
down
GND ≤ VIN
≤ VDD
Without internal pull-up/pull-
down
GND ≤ VIN
≤ VDD
−5
5
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VDD, VDD_R = 3.3 V ± 5 %, −40°C ≤ TA ≤ 105°C. Typical values are at VDD = VDD_R = 3.3 V, 25°C (unless otherwise
noted)
PARAMETER
Input capacitance
Output capacitance
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CIN
4.5
pF
COUT
4.5
pF
3-LEVEL DIGITAL INTERFACE (SADR0, SADR1)
VIH
VIM
VIL
IIH
High level input voltage
Mid level input voltage
Low level input voltage
Input leakage current
Input leakage current
Input capacitance(1)
2.3
1.25
VDD/2
1.725
0.85
30
V
With internal pull-up/pull-down VIN = VDD
With internal pull-up/pull-down VIN = GND
–30
–30
µA
µA
pF
IIL
30
CIN
4.5
(1) Voltage swing includes overshoot.
(2) Not tested in production. Ensured by design and characterization.
(3) Measured into DC test load.
(4) VCROSS is single-ended voltage when CKx_P = CKx_N with respect to system ground. Only valid on rising edge of CKx, when CKx_P
is rising.
(5) Measured from rising edge of CLK_IN to any CKx output.
(6) Measured from rising edge of any CKx output to any other CKx output.
(7) Measured into AC test load.
6.6 Timing Requirements
VDD, VDD_R = 3.3 V ± 5 %, −40°C ≤ TA ≤ 105°C. Typical values are at VDD = VDD_A = 3.3 V, 25°C (unless otherwise
noted)
MIN
NOM
MAX
UNIT
SMBUS-COMPATIBLE INTERFACE TIMING
fSMB
SMBus operating frequency
Bus free time between STOP and START
START condition hold time
START condition setup time
STOP condition setup time
SMBDAT hold time
10
4.7
4
400
kHz
tBUF
tHD_STA
tSU_STA
tSU_STO
tHD_DAT
tSU_DAT
SMBCLK low after SMBDAT low
SMBCLK high before SMBDAT low
µs
4.7
4
300
250
1e6
4.7
4
ns
cycles
µs
SMBDAT setup time
tTIMEOUT Detect SMBCLK low timeout
In terms of device input clock frequency
tLOW
tHIGH
tF
SMBCLK low period
SMBCLK high period
50
300
SMBCLK/SMBDAT fall time(1)
SMBCLK/SMBDAT rise time(2)
ns
tR
1000
(1) TF = (VIHMIN + 0.15) to (VILMAX - 0.15)
(2) TR = (VILMAX - 0.15) to (VIHMIN + 0.15)
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6.7 Typical Characteristics
图 6-1 shows both the phase noise of the source as well as the output of the DUT (CDCDB803). It can be seen from the
phase noise plot that the DUT has a very low phase noise profile with total jitter of 71 fs, rms. If we rms subtract the clock
reference noise, the additive jitter of CDCDB803 under typical conditions would be lower than 71 fs, rms.
图 6-1. CDCDB803 Clock Out (CK0:8) Phase Noise
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7 Parameter Measurement Information
10 inches/ 25.4 cm
< 1 pF
GND
CK+
CK-
DUT
Differential impedance 85
>100 k
High
Impedance
< 1 pF
2 pF
2 pF
Probe
GND
图 7-1. AC Test Load (Referencing Intel DB2000QL Document)
0.75 V
SMA
R1
R1
CK+
CK-
0.75 V
DUT
GND
GND
SMA
50
42.5
85
R1 = 47 Ω and R2 = 147 Ω.
图 7-2. DC Simulation Load (Referencing Intel DB2000QL Document)
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8 Detailed Description
8.1 Overview
The CDCDB803 is a low additive-jitter, low propagation delay clock buffer designed to meet the strict
performance requirements for PCIe Gen 1-6, QPI, UPI, SAS, and SATA reference clocks. The CDCDB803
allows buffering and replication of a single clock source to up to eight individual outputs in the LP-HCSL format.
The CDCDB803 also includes status and control registers accessible by an SMBus version 2.0 compliant
interface. The device integrates a large amount of external passive components to reduce overall system cost.
8.2 Functional Block Diagram
CK0_P
CK0_N
CLKIN_P
CLKIN_N
CK1_P
CK1_N
CK2_P
CK2_N
CK3_P
CK3_N
Glitch
Free
OE[7:0]#
Output
Control
Logic
CK7_P
CK7_N
SMBDAT
SMBCLK
SMBWRTLOCK
SADR0
Control
Logic
SADR1
CKPWRGD_PD#
8.3 Feature Description
8.3.1 Fail-Safe Input
The CDCDB803 is designed to support fail-safe input operation feature. This feature allows the user to drive the
device inputs before VDD is applied without damaging the device. Refer to the Absolute Maximum Ratings table
for more information on the maximum input supported by the device.
8.3.2 Output Enable Control
The CDCDB803 uses SMBus and OE# to control the state of the output channels. The OE# pins control the
state of the output with the same number. For example, the OE5# pin controls the state of the CK5 output driver.
The SMBus registers may enable or disable the output when the corresponding OE# pin is held low.
8.3.3 SMBus
The CDCDB803 has an SMBus interface that is active only when CKPWRGD_PD# = 1. The SMBus allows
individual enable/disable of each output.
When CKPWRGD_PD# = 0, the SMBus pins are placed in a Hi-Z state, but all register settings are retained. The
SMBus register values are only retained while VDD remains inside of the recommended operating voltage.
8.3.3.1 SMBus Address Assignment
The SMBus address is assigned by configuration of two pins (SADR1 and SADR0) that each support three
levels. This configuration allows the CDCDB803 to assume nine different SMBus addresses.
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The SMBus address pins are sampled when PWRGD is set to 1. See 表 8-1 for address pin configuration. The
address can only be changed by power cycling the device.
表 8-1. SMBus Address Assignment
SMBus ADDRESS : WRITE
SMBus ADDRESS : READ
SADR1
SADR0
OPERATION (READ/WRITE=0) OPERATION (READ/WRITE=1)
L
L
0xD8
0xDA
0xDE
0xC2
0xC4
0xC6
0xCA
0xCC
0xCE
0xD9
0xDB
0xDF
0xC3
0xC5
0xC7
0xCB
0xCD
0xCF
L
M
H
L
L
M
M
M
H
H
H
M
H
L
M
H
8.4 Device Functional Modes
8.4.1 CKPWRGD_PD# Function
The CKPWRGD_PD# pin is used to set two state variables inside of the device: PWRGD and PD#. The PWRGD
and PD# variables control which functions of the device are active at any time, as well as the state of the input
and output pins.
The PWRGD and PD# states are multiplexed on the CKPWRGD_PD# pin. CKPWRGD_PD# must remain below
VOL and not exceed VDDR + 0.3 V until VDD and VDDR are present and within the recommended operating
conditions. After CKPWRGD_PD# is set high, a valid CLKIN must be present to use PD#.
The first rising edge of the CKPWRGD_PD# pin sets PWRGD = 1. After PWRGD is set to 1, the
CKPWRGD_PD# pin is used to assert PD# mode only. PWRGD variable will only be cleared to 0 with the
removal of VDD and VDDR
.
VDD/VDDR
CKPWRGD_PD#
PWRGD
PD#
图 8-1. PWRGD and PD# State Changes
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8.4.2 OE[7:0]# and SMBus Output Enables
Each output channel, 0 to 7, can be individually enabled or disabled by a SMBus control register bit, called
SMB enable bits. Additionally, each output channel has a dedicated, corresponding, OE[7:0]# hardware pin. The
OE[7:0]# pins are asynchronously asserted-low signals that may enable or disable the output.
Refer to 表 8-2 for enabling and disabling outputs through the hardware and software. Note that both the SMB
enable bit must be a 1 and the OEx# pin must be an input low voltage 0 for the output channel to be active.
表 8-2. OE[7:0]# Functionality
Power State Variables
(Internal)
OE[7:0]# HARDWARE PINS AND SMBus
CONTROL REGISTER BITS
Control Inputs
CK[7:0]_P/
CK[7:0]_N
CLKIN
CKPWRGD_P
D#
OUT_EN_CLK[ DRIVE_OP_ST
OE[7:0]#
PWRGD
PD#
7:0]
ATE_CTRL
0
1
0
0
X
X
X
X
X
LOW/LOW
LOW/LOW
0
0
1
0
1
X
0
1
TRI-STATE
LOW/LOW
TRI-STATE
Running
X(1)
1
1
0
X
X
1
1
Running(1)
X(2)
LOW/LOW
TRI-STATE
0
0
X
(1) To enter the power-down state, CLKIN must remain active for at least 3 clock cycles after CKPWRGD_PD# transitions from 1 to 0.
(2) To enter the powered-up state with active clock outputs, CLKIN must be active before CKPWRGD_PD# transitions from 0 to 1.
8.4.3 Output Slew Rate Control
The CDCDB803 provides output slew rate control feature which customer can use to compensate for increased
output trace length based on their board design. The slew rate of a bank of 4 outputs 0 to 3 and 4 to 7, can
be changed within a given range by a SMBus control register called CAPTRIM. Refer to 表 8-16 for more
information.
8.4.4 Output Impedance Control
The integrated termination on the CDCDB803 can be programmed either for 85 Ω or 100 Ω. This flexibility
ensures that the customer can use the same device across various applications irrespective of the characteristic
board impedance which is typically either 85 Ω or 100 Ω. This termination resistor can be changed for all the
outputs as whole using bit 5 of a register called OUTSET. Refer to 表 8-14 for more information.
8.5 Programming
The CDCDB803 uses SMBus to program the states of its eight output drivers. See SMBus for more information
on the SMBus programming, and Register Maps for information on the registers.
表 8-3. Command Code Definition
BIT
7
DESCRIPTION
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
(6:0)
Register address for Byte operations, or starting register address for Block, operations
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1
7
1
1
8
1
1
S
Peripheral Address
A
Data Byte
A
P
R/W
MSB
LSB
MSB
LSB
S
Start Condition
Sr Repeated Start Condition
1 = Read (Rd); 0 = Write (Wr)
R/W
A
Acknowledge (ACK = 0 and NACK =1)
Stop Condition
P
Controller-to-Peripheral Transmission
Peripheral-to-Controller Transmission
图 8-2. Generic Programming Sequence
1
7
1
1
8
1
8
1
1
S
Peripheral Address
Wr
A
CommandCode
A
Data Byte
A
P
图 8-3. Byte Write Protocol
1
1
1
7
1
1
8
7
1
1
A
S
S
Peripheral Address
Wr
A
CommandCode
Peripheral Address
Rd
A
1
1
8
Data Byte
A
P
1
图 8-4. Byte Read Protocol
1
7
1
1
8
1
8
1
S
Peripheral Address
Wr
A
CommandCode
A
Byte Count = N
A
8
1
8
1
8
1
1
Data Byte 0
A
Data Byte 1
A
…
Data Byte N-1
A
P
图 8-5. Block Write Protocol
1
1
1
7
1
1
8
7
1
1
A
S
S
Peripheral Address
Wr
A
CommandCode
Peripheral Address
Rd
A
1
1
8
1
1
8
8
Data Byte N-1
A
P
Data Byte N
A
A
Data Byte 0
1
1
1
图 8-6. Block Read Protocol
tLOW
tR
tF
VIH
VIL
SMBCLK
SMBDAT
tSU_STO
tHD_STA
tHIGH
tSU_STA
ttBUFt
tHD_DAT
tSU_DAT
VIH
VIL
P
S
P
图 8-7. SMBus Timing Diagram
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8.6 Register Maps
8.6.1 CDCDB803 Registers
表 8-4 lists the CDCDB803 registers. All register locations not listed in 表 8-4 should be considered as reserved
locations and the register contents should not be modified.
表 8-4. CDCDB803 Registers
Address
0h
Acronym
RCR1
Register Name
Section
Go
Reserved Control Register 1
Output Enable Control 1
Output Enable Control 2
Output Enable# Pin Read Back
Reserved Control Register 2
Vendor/Revision Identification
Device Identification
1h
OECR1
Go
2h
OECR2
Go
3h
OERDBK
RCR2
Go
4h
Go
5h
VDRREVID
DEVID
Go
6h
Go
7h
BTRDCNT
OUTSET
CAPTRIM
Byte Read Count Control
Output Setting Control
Go
8h
Go
4Ch
Slew Rate Capacitor Cluster 1 & 2
Go
Complex bit access types are encoded to fit into small table cells. 表 8-5 shows the codes that are used for
access types in this section.
表 8-5. CDCDB803 Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
8.6.1.1 RCR1 Register (Address = 0h) [reset = 47h]
RCR1 is shown in 表 8-6.
Return to the Summary Table.
The RCR1 register contains reserved bits.
表 8-6. RCR1 Register Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
Reserved
Reserved
R
4h
Reserved.
R/W
7h
Writing to these bits will not affect the functionality of the device.
8.6.1.2 OECR1 Register (Address = 1h) [reset = FFh]
OECR1 is shown in OECR1 Register Field Descriptions.
Return to the Summary Table.
The OECR1 register contains bits that enable or disable individual output clock channels [5:0].
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表 8-7. OECR1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
OUT_EN_CLK5
OUT_EN_CLK4
OUT_EN_CLK3
OUT_EN_CLK2
R/W
1h
This bit controls the output enable signal for output channel CK5_P/
CK5_N.
0h = Output Disabled
1h = Output Enabled
6
5
4
R/W
R/W
R/W
1h
1h
1h
This bit controls the output enable signal for output channel CK4_P/
CK4_N.
0h = Output Disabled
1h = Output Enabled
This bit controls the output enable signal for output channel CK3_P/
CK3_N.
0h = Output Disabled
1h = Output Enabled
This bit controls the output enable signal for output channel CK2_P/
CK2_N.
0h = Output Disabled
1h = Output Enabled
3
2
Reserved
R/W
R/W
1h
1h
Writing to this bit will not affect the functionality of the device.
OUT_EN_CLK1
This bit controls the output enable signal for output channel CK1_P/
CK1_N.
0h = Output Disabled
1h = Output Enabled
1
0
OUT_EN_CLK0
Reserved
R/W
R/W
1h
1h
This bit controls the output enable signal for output channel CK0_P/
CK0_N.
0h = Output Disabled
1h = Output Enabled
Writing to this bit will not affect the functionality of the device.
8.6.1.3 OECR2 Register (Address = 2h) [reset = 0Fh]
OECR2 is shown in OECR2 Register Field Descriptions.
Return to the Summary Table.
The OECR2 register contains bits that enable or disable individual output clock channels [7:6].
表 8-8. OECR2 Register Field Descriptions
Bit
7-3
2
Field
Type
R/W
R/W
Reset
Description
Reserved
OUT_EN_CLK7
1h
Writing to these bits will not affect the functionality of the device.
1h
This bit controls the output enable signal for output channel CK7_P/
CK7_N.
0h = Output Disabled
1h = Output Enabled
1
0
Reserved
R/W
R/W
1h
1h
Writing to this bit will not affect the functionality of the device.
OUT_EN_CLK6
This bit controls the output enable signal for output channel CK6_P/
CK6_N.
0h = Output Disabled
1h = Output Enabled
8.6.1.4 OERDBK Register (Address = 3h) [reset = 0h]
OERDBK is shown in 表 8-9.
Return to the Summary Table.
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The OERDBK register contains bits that report the current state of the OE[7:0]# input pins.
表 8-9. OERDBK Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RB_OE7
RB_OE6
RB_OE5
RB_OE4
RB_OE3
RB_OE2
RB_OE1
RB_OE0
R
0h
This bit reports the logic level present on the OE7# pin.
This bit reports the logic level present on the OE6# pin.
This bit reports the logic level present on the OE5# pin.
This bit reports the logic level present on the OE4# pin.
This bit reports the logic level present on the OE3# pin.
This bit reports the logic level present on the OE2# pin.
This bit reports the logic level present on the OE1# pin.
This bit reports the logic level present on the OE0# pin.
6
R
0h
5
R
0h
4
R
0h
3
R
0h
2
R
0h
1
R
0h
0
R
0h
8.6.1.5 RCR2 Register (Address = 4h) [reset = 0h]
RCR2 is shown in RCR2 Register Field Descriptions.
Return to the Summary Table.
The RCR2 register contains reserved bits.
表 8-10. RCR2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Reserved
R
0h
Reserved.
8.6.1.6 VDRREVID Register (Address = 5h) [reset = 0Ah]
VDRREVID is shown in 表 8-11.
Return to the Summary Table.
The VDRREVID register contains a vendor identification code and silicon revision code.
表 8-11. VDRREVID Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
REV_ID
R
0h
Silicon revision code.
Silicon revision code bits
[3:0] map to register bits
[7:4] directly.
3-0
VENDOR_ID
R
Ah
Vendor identification code.
Vendor ID bits
[3:0] map to register bits
[3:0] directly.
8.6.1.7 DEVID Register (Address = 6h) [reset = E7h]
DEVID is shown in 表 8-12.
Return to the Summary Table.
The DEVID register contains a device identification code.
表 8-12. DEVID Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DEV_ID
R
E7h
Device ID code.
Device ID bits[7:0] map to register bits[7:0] directly.
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8.6.1.8 BTRDCNT Register (Address = 7h) [reset = 8h]
BTRDCNT is shown in 表 8-13.
Return to the Summary Table.
The BTRDCNT register contains bits [4:0] which configure the number of bytes which will be read back.
表 8-13. BTRDCNT Register Field Descriptions
Bit
7-5
4
Field
Type
R/W
R/W
R/W
Reset
Description
Reserved
0h
Writing to these bits will not affect the functionality of the device.
BYTE_COUNTER
BYTE_COUNTER
0h
Writing to this register configures how many bytes will be read back.
3-0
8h
8.6.1.9 OUTSET Register (Address = 8h) [reset = 0h]
OUTSET is shown in 表 8-14.
Return to the Summary Table.
Bit5 of the OUTSET register sets the termination for all the outputs while bit4 can be used to set the power-down
state for all outputs. The remaining bits for this register are reserved.
表 8-14. OUTSET Register Field Descriptions
Bit
7-6
5
Field
Type
Reset
Description
Reserved
R
0h
Reserved.
CH_ZOUT_SEL
d_DRIVE_OP_STATE_CTRL
R/W
R/W
0h
Select between 85 Ω (0) and 100 Ω (1) Output impedance
4
0h
Power-down state of all output clocks.
0: LOW/LOW
1: TRI_STATE
3-0
Reserved
R/W
0h
Register bits can be written to 0. Writing a different value than 0
will affect device functionality.
8.6.1.10 CAPTRIM Register (Address = 4Ch) [reset = 66h]
CAPTRIM is shown in 表 8-16.
Return to the Summary Table.
Bits [7:4] of the CAPTRIM register is used to control the slew rate for output channel cluster 2. Bits [3:0] control
the slew rate for output channel cluster 1. Refer below for cluster identification.
表 8-15. Cluster Identification
Cluster
Outputs
1
2
CK3, CK2, CK1, CK0
CK7, CK6, CK5, CK4
表 8-16. CAPTRIM Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
CLUSTER2_CAP_TRIM
R/W
6h
Slew Rate Reduction Cap Trim for Cluster 2. Default value of 6h.
0: minimum
F: maximum
3-0
CLUSTER1_CAP_TRIM
R/W
6h
Slew Rate Reduction Cap Trim for Cluster 1. Default value of 6h.
0: minimum
F: maximum
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9 Application and Implementation
备注
以下应用部分中的信息不属于 TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
9.1 Application Information
The CDCDB803 is a fanout buffer that supports PCIe generation 4 and PCIe generation 5 REFCLK distribution.
The device is used to distribute up to eight copies of a typically 100-MHz clock.
9.2 Typical Application
图 9-1 shows a CDCDB803 typical application. In this application, a clock generator provides a 100-MHz
reference to the CDCDB803 which then distributes that clock to PCIe endpoints. The clock generator may be
a discrete clock generator like the CDCI6214 or it may be integrated in a larger component such as a Platform
Controller Hub (PCH) or application processor.
PCIe Gen 4-5
Clock
Generator
8
LP-HCSL
PCIe Device
CDCDB803
8x LP-HSCL Output Buffer
LP-HCSL
OE#
Control
SMBus
Control
Control Interface
图 9-1. Typical Application
9.2.1 Design Requirements
Consider a typical server motherboard application which must distribute a 100-MHz PCIe reference clock from
the PCH of a processor chipset to multiple endpoints. An example of clock input and output requirements is:
•
Clock Input:
– 100-MHz LP-HCSL
•
Clock Output:
– 2x 100-MHz to processors, LP-HCSL
– 3x 100-MHz to riser/retimer, LP-HCSL
– 3x 100-MHz to DDR memory controller, LP-HCSL
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9.2.2 Detailed Design Procedure
The following items must be determined before starting design of a CDCDB803 socket:
•
•
Output Enable Control Method
SMBus address
9.2.2.1 Output Enable Control Method
The device provides an option to either use SMBus programmed registers (software) to control the outputs or by
using the hardware OE# pins. In case of using software to control the outputs, the hardware OE# pins can be left
floating as each of these pins have a pulldown to ground. Refer to 表 8-2 and the Register Maps section for more
information on programming the register.
When the user wants to control the outputs with the hardware OE# pins, they can do so for example by
connecting these pins to a GPIO controller and follow the Pin Configuration and Functions section to set the
outputs to HIGH/LOW. The bits OUT_EN_CLK7 to OUT_EN_CLK0 used to control the outputs are shown in
registers OECR1 (表 8-7) and OECR2 (表 8-8). These register bits are set to 1 by default to ensure that the
outputs are "software enabled" and their state is therefore set by hardware OE# pins.
9.2.2.2 SMBus Address
An SMBus address should be selected from the listed potential addresses in 表 8-1. The appropriate pullup or
pulldown resistor should be placed on the SADRx pins as indicated in the table. Ensure the SMBus address is
not already in use to avoid conflict.
9.2.3 Application Curves
图 6-1 in the Typical Characteristics section can be used as both an application curve and a typical
characteristics plot in this example.
The 图 9-2 and 图 9-3 show characterization data for the Output slew rate for various CAPTRIM codes and
across temperature. Customers can use these plots as reference for choosing the appropriate output slew rate
based on their system requirement.
7
6
5
4
3
2
0 - 3.3 V
1 - 3.3 V
2 - 3.3 V
3 - 3.3 V
4 - 3.3 V
5 - 3.3 V
6 - 3.3 V
7 - 3.3 V
8 - 3.3 V
9 - 3.3 V
10 - 3.3 V
11 - 3.3 V
12 - 3.3 V
13 - 3.3 V
1
0
120 100
80
60
40
20
0
-20
-40
-60
Temperature (èC)
D002
.
.
图 9-3. Slew Rate Variation Across Temperature for
图 9-2. Output Slew Rate vs. CAPTRIM Code
Different CAPTRIM Code
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10 Power Supply Recommendations
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
the jitter and phase noise is critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guards the power-supply system
against induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by
the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, place
the capacitors very close to the power-supply terminals and lay out with short loops to minimize inductance. TI
recommends to insert a ferrite bead between the board power supply and the chip power supply that isolates the
high-frequency switching noises generated by the clock buffer. These beads prevent the switching noise from
leaking into the board supply. It is imperative to choose an appropriate ferrite bead with very low DC resistance
to provide adequate isolation between the board supply and the chip supply, as well as to maintain a voltage at
the supply terminals that is greater than the minimum voltage required for proper operation.
图 10-1 shows the recommended power supply filtering and decoupling method.
3.3 V
VDD
10 ꢀF
0.1 ꢀF 0.1 ꢀF 0.1 ꢀF 0.1 ꢀF 0.1 ꢀF
3.3 V
VDDR
2.2 ꢁ
10 ꢀF
0.1 ꢀF
图 10-1. Power Supply Decoupling
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22
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11 Layout
11.1 Layout Guidelines
The following section provides the layout guidelines to ensure good thermal performance and power supply
connections for the CDCDB803.
In Layout Examples, the CDCDB803 has 85-Ω differential output impedance LP-HCSL format drivers as per
register default settings. All transmission lines connected to CKx pins should be 85-Ω differential impedance,
42.5-Ω single-ended impedance to avoid reflections and increased radiated emissions. If 100-Ω output
impedance is enabled, the transmission lines connected to CKx pins should be 100-Ω differential impedance,
50-Ω single-ended impedance. Take care to eliminate or reduce stubs on the transmission lines.
11.2 Layout Examples
图 11-1 through 图 11-3 are printed circuit board (PCB) layout examples that show the application of thermal
design practices and a low-inductance ground connection between the device DAP and the PCB.
图 11-1. PCB Layout Example for CDCDB803, Top layer
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图 11-2. PCB Layout Example for CDCDB803, GND Layer
图 11-3. PCB Layout Example for CDCDB803, Bottom Layer
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12 Device and Documentation Support
12.1 Device Support
12.1.1 TICS Pro
TICS Pro is an offline software tool for EVM programming and also for register map generation to program a
device configuration for a specific application. For TICS Pro, go to https://www.ti.com/tool/TICSPRO-SW.
12.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅 TI
的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CDCDB803RSLR
CDCDB803RSLT
ACTIVE
ACTIVE
VQFN
VQFN
RSL
RSL
48
48
4000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 105
-40 to 105
CDCB803
CDCB803
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Apr-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCDB803RSLR
CDCDB803RSLT
VQFN
VQFN
RSL
RSL
48
48
4000
250
330.0
180.0
16.4
16.4
6.3
6.3
6.3
6.3
1.1
1.1
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CDCDB803RSLR
CDCDB803RSLT
VQFN
VQFN
RSL
RSL
48
48
4000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
VQFN - 1 mm max height
RSL0048B
PLASTIC QUAD FLATPACK- NO LEAD
A
6.1
5.9
B
PIN 1 INDEX AREA
6.1
5.9
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
4.4
13
24
44X 0.4
12
23
SYMM
49
4.5
4.3
4.4
1
36
0.25
0.15
48X
PIN 1 IDENTIFICATION
(OPTIONAL)
37
48
0.1
C A B
C
SYMM
0.5
0.3
0.05
48X
4219205/A 02/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RSL0048B
PLASTIC QUAD FLATPACK- NO LEAD
(5.8)
(
4.4)
SYMM
48
37
48X (0.6)
48X (0.2)
1
36
44X (0.4)
SYMM
(5.8)
10X (1.12)
49
6X (0.83)
(R0.05) TYP
12
25
13
6X (0.83)
24
(Ø0.2) VIA
10X (1.12)
TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 12X
0.05 MAX
0.05 MIN
ALL AROUND
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219205/A 02/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RSL0048B
PLASTIC QUAD FLATPACK- NO LEAD
(5.8)
SYMM
48
37
48X (0.6)
48X (0.2)
1
49
36
44X (0.4)
16X
(
0.92)
SYMM
8X (0.56)
(5.8)
8X (1.12)
(R0.05) TYP
12
25
13
8X (1.12)
24
METAL TYP
8X (0.56)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
70% PRINTED COVERAGE BY AREA
SCALE: 12X
4219205/A 02/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023,德州仪器 (TI) 公司
CDCDB803 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
CDCDB803RSLR | TI | 用于 PCIe® 第 1 代至第 5 代的 8 输出时钟缓冲器,具有可选的 SMBus 地址 | RSL | 48 | -40 to 105 | 获取价格 | |
CDCDB803RSLT | TI | 用于 PCIe® 第 1 代至第 5 代的 8 输出时钟缓冲器,具有可选的 SMBus 地址 | RSL | 48 | -40 to 105 | 获取价格 | |
CDCDLP223 | TI | 3.3 V Clock Synthesizer for DLP TM Systems | 获取价格 | |
CDCDLP223PW | TI | 用于 DLP 系统的 3.3V 时钟合成器 | PW | 20 | -40 to 85 | 获取价格 | |
CDCDLP223PWR | TI | 3.3 V Clock Synthesizer for DLP Systems | 获取价格 | |
CDCDLP223_07 | TI | 3.3 V Clock Synthesizer for DLP Systems | 获取价格 | |
CDCE18005 | TI | Five/Ten Output Clock Generator/Buffer | 获取价格 | |
CDCE18005RGZR | TI | Five/Ten Output Clock Generator/Buffer | 获取价格 | |
CDCE18005RGZT | TI | Five/Ten Output Clock Generator/Buffer | 获取价格 | |
CDCE401 | TI | OSCILLATOR IC WITH ELECTRONIC CALIBRATION | 获取价格 |
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